Halogen-free etching of silicon nitride

Abstract

A semiconductor processing method may include providing a hydrogen-containing precursor to a processing area in a semiconductor processing chamber. A substrate may be placed on a substrate support within the processing area. A layer of a material containing silicon and nitrogen may be placed on the substrate. The method may include forming a plasma emission of the hydrogen-containing precursor. The method may include bringing the layer of the silicon and nitrogen-containing material into contact with the plasma emission of the hydrogen-containing precursor. This contact may etch a portion of the layer of the silicon and nitrogen-containing material.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 203,404, entitled "HALOGEN - FREE ETCHING OF SILICON NITRIDE", filed on May 30, 2023, the entire disclosure of which is incorporated herein by reference.

[0002]

[0002] This technology relates to semiconductor systems and processes. More specifically, this technology relates to halogen - free etching of silicon nitride. Background Art

Background Art

[0003]

[0003] Integrated circuits can be realized by a process of fabricating a complexly patterned material layer on a substrate surface. To create a patterned material on the substrate, a controlled method for removing the exposed material is required. Chemical etching is used for various purposes, including transferring a photoresist pattern to a lower layer, thinning a layer, or narrowing the lateral dimension of a feature already present on the surface. In many cases, it is desirable to perform an etching process that etches one substance faster than other materials, for example, to facilitate a pattern transfer process. Such an etching process is said to be selective to the first material. Due to the diversity in materials, circuits, and processes, etching processes having selectivity to various materials have been developed.

[0004]

[0004] Etching processes may be called wet or dry, depending on the materials used in the process. For example, wet etching can preferentially remove some oxide dielectrics over other dielectrics and materials. However, wet etching may not be able to penetrate some constrained trenches, causing deformation of the remaining material. Dry etching is performed in a localized plasma formed within the processing area of ​​the substrate, but it can penetrate more constrained trenches and causes less deformation of the remaining fragile structure. However, the electric arc generated when the localized plasma discharges can damage the substrate.

[0005]

[0005] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high-quality devices and structures. This technology addresses these and other needs. [Overview of the project]

[0006]

[0006] The semiconductor processing method may include providing a hydrogen-containing precursor to a processing area in a semiconductor processing chamber. A substrate may be placed on a substrate support within the processing area. A layer of material containing silicon and nitrogen may be placed on the substrate. The method may include forming a plasma emission of the hydrogen-containing precursor. The method may include bringing the layer of material containing silicon and nitrogen into contact with the plasma emission of the hydrogen-containing precursor. This contact may etch a portion of the layer of material containing silicon and nitrogen.

[0007]

[0007] In some embodiments, the hydrogen-containing precursor may be or contain diatomic hydrogen (H2). The processing area may be kept halogen-free. A layer of silicon- and oxygen-containing material, a layer of silicon-containing material, or both may be placed on the substrate. The method may include providing an inert precursor to the processing area together with the hydrogen-containing precursor. The flow rate of the inert precursor may be greater than the flow rate of the hydrogen-containing precursor. Plasma emissions may be formed with a plasma output of about 800 W or more. Plasma emissions may be formed with a plasma output of about 2,000 W or more. Contact may form silane (SiH4), ammonia (NH3), or both. The substrate may be characterized by a temperature of about 50°C or less. The substrate may be characterized by a temperature of about -25°C or less. The pressure in the semiconductor processing chamber may be maintained at about 100 mTorr or less. This contact may etch the layer of silicon- and nitrogen-containing material at an etching rate of about 1 Å / min or more.

[0008]

[0008] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed on a substrate support within the processing area. A layer of a material containing silicon and oxygen may be placed on the substrate. A layer of a material containing silicon and nitrogen may be placed on the layer of the material containing silicon and oxygen. The method may include forming a plasma emission of the hydrogen-containing precursor. The plasma emission may be formed with a plasma output of about 1,000 W or more. The method may include bringing the layer of the material containing silicon and nitrogen into contact with the plasma emission of the hydrogen-containing precursor. The contact may selectively etch a portion of the layer of the material containing silicon and nitrogen with respect to the layer of the material containing silicon and oxygen.

[0009]

[0009] In some embodiments, the processing area can be kept halogen-free. The substrate can be characterized by a temperature of about 50°C or less.

[0010]

[0010] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a hydrogen-containing precursor to a processing area in a semiconductor processing chamber. A substrate may be placed on a substrate support within the processing area. A layer of a material containing silicon and oxygen may be placed on the substrate. A layer of a material containing silicon and nitrogen may be placed on the layer of the material containing silicon and oxygen. The method may include forming a plasma emission of the hydrogen-containing precursor. The method may include bringing the layer of the material containing silicon and nitrogen into contact with the plasma emission of the hydrogen-containing precursor. The contact may selectively etch a portion of the layer of the material containing silicon and nitrogen with respect to the layer of the material containing silicon and oxygen. The substrate may be characterized by a temperature of about -50°C or lower.

[0011]

[0011] In some embodiments, the method may include providing helium having a hydrogen-containing precursor to the processing area. The processing area may be kept halogen-free. Plasma emissions may be formed with a plasma output of about 1,000 W or more.

[0012]

[0012] Such technologies can offer numerous advantages over conventional systems and techniques. For example, the process may offer high selectivity for silicon and / or silicon oxide etching for silicon nitride etching. Furthermore, the process may be carried out without the use of halogen materials. These and other embodiments, along with many of their advantages and features, will be described in more detail in conjunction with the following description and accompanying figures.

[0013]

[0013] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0014] [Figure 1] A schematic top view of an exemplary processing system according to several embodiments of this technology is shown. [Figure 2]A schematic cross-sectional view of an exemplary processing system according to several embodiments of this technology is shown. [Figure 3] Selected operations in a semiconductor processing method according to several embodiments of this technology are shown. [Figure 4A-4B] Schematic cross-sectional views of etched materials according to several embodiments of this technology are shown. [Modes for carrying out the invention]

[0015]

[0018] Some drawings are included as schematic diagrams. It should be understood that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0016]

[0019] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0017]

[0020] Selective etching of silicon nitride materials is beneficial in various device process flows, including the formation of dynamic random access memory, FinFETs, and many other devices. Silicon nitride can be used as a liner or barrier material, functioning as a barrier material, etching stop material, or dielectric material, to form insulating film stacks between device circuits. To pattern or remove silicon nitride materials, conventional processes can utilize halogen precursors or plasma products to etch the silicon nitride. However, these conventional processes have been limited by their low selectivity for silicon nitride materials compared to other materials on the substrate. Conventional processes have also suffered from downstream problems due to the presence of halogen precursor residues. This technology overcomes these limitations by performing a halogen-free etching process that selectively removes silicon nitride materials using one or more hydrogen precursors. The etching process may include providing hydrogen using one or more inert precursors to soften the material. In addition, this technology may utilize cryogenic temperatures to achieve ultra-high etching selectivity. Furthermore, this technology can provide a single-step process for removing silicon nitride materials, compared to conventional two-step processes such as atomic layer etching (ALE) required to remove silicon nitride materials.

[0018]

[0021] The following disclosures, while normally identifying specific etching processes utilizing the disclosed technology, will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may be carried out in the described chambers. Therefore, this technology should not be considered limited to use in the etching processes described. Before describing the systems and methods or processes of exemplary process sequences in several embodiments of the technology, this disclosure describes one possible system and chamber that may be used in the technology. It should be understood that the technology is not limited to the described apparatus, and the processes discussed can be carried out in any number of processing chambers and systems.

[0019]

[0022] Figure 1 shows a top view of one embodiment of a processing system 10 comprising a deposition chamber, etching chamber, baking chamber, and / or curing chamber. The tool or processing system 10 shown in Figure 1 may include a plurality of processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated measurement chamber 28, and a pair of load lock chambers 16a-b. The processing chamber may include any number of structures or components, and any number of combinations of processing or processing chambers.

[0020]

[0023] To transport substrates between chambers, the transport chamber 20 may include a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a, each attached to the distal end of an extendable arm 22b. The blades 22a may be used to transport individual substrates to and from the processing chambers. During operation, one of the substrate transport blades, such as the blades 22a of the transport mechanism 22, may take a substrate W from one of the load-lock chambers, such as chambers 16a-b, and transport the substrate W in chambers 24a-d to the first stage of processing, such as the processing process described later. Chambers may be included to perform individual or combined operations of the described technology. For example, one or more chambers may be configured to perform deposition or etching, while one or more other chambers may be configured to perform the described pre-processing and / or one or more post-processing. Any number of configurations are included in this technology, and any number of additional manufacturing processes commonly performed in semiconductor processes may also be performed.

[0021]

[0024] If a chamber is occupied, the robot can wait until processing is complete before removing the processed substrate from the chamber with one blade 22a and inserting a new substrate with a second blade. Once the substrate is processed, it can be moved to the second stage of processing. With each movement, the transport mechanism 22 can generally transport the substrate with one blade and the other blade may be empty in order to replace the substrate. The transport mechanism 22 may wait in each chamber until the replacement is complete.

[0022]

[0025] When the processing in the processing chamber is completed, the transfer mechanism 22 can move the substrate W from the last processing chamber and transfer the substrate W to the cassettes in the load lock chambers 16a - b. From the load lock chambers 16a - 16b, the substrate can move into the factory interface 12. The factory interface 12 can generally operate to transfer the substrate between the pod loaders 14a - d in the atmospheric pressure cleaning environment and the load lock chambers 16a - b. The cleaning environment in the factory interface 12 can generally be provided through an air filtering process such as filtering by a HEPA filter, for example. The factory interface 12 can also include a substrate aligner / orienter that can be used to properly align the substrate prior to processing. At least one substrate robot, such as robots 18a - b, can be positioned within the factory interface 12 to transfer the substrate between various positions and locations within the factory interface 12 and to other locations in communication with them. The robots 18a - 18b can be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0023]

[0026] The processing system 10 can further include an integrated measurement chamber 28 to obtain control signals that can provide adaptive control for any processing performed within the processing chamber. The integrated measurement chamber 28 can include any of a variety of measurement devices for measuring various film properties such as thickness, roughness, composition, etc., and the measurement devices can further be capable of characterizing lattice parameters such as critical dimensions, sidewall angles, and feature heights by an automated method under vacuum.

[0024] ]>

[0027] Each of the processing chambers 24a - d may be configured to perform one or more processing steps in the manufacture of semiconductor structures, and any number of processing chambers and combinations of processing chambers can be used in the multi - chamber processing system 10. For example, any of the processing chambers can be configured to perform a number of substrate processings, including any number of deposition processes such as periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other processes such as etching, pre - cleaning, pre - treatment, post - treatment, annealing, plasma treatment, degassing, orientation, and other substrate treatments. Some specific processes that can be implemented in any chamber or combination of chambers can be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. As will be readily understood by those skilled in the art, any other arbitrary process can be similarly implemented in a particular chamber incorporated in the multi - chamber processing system 10, including any of the processes described below.

[0025]

[0028] Figure 2 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer placed on a substrate 302 within the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that embodiments of the art may be performed in any number of chambers, and the substrate support according to the art may be contained in an etching chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber space 101 in which the substrate can be processed. The chamber body 105 may have side walls 112 and a bottom 118, which are connected to ground 126. The side walls 112 have liners 115 to protect the side walls 112, which may extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limiting and may generally be larger in proportion to the size of the substrate 302 processed therein. Examples of substrate sizes include, in particular, those with diameters of 200 mm, 250 mm, 300 mm, and 450 mm, such as those used for displays or solar cell substrates.

[0026]

[0029] The chamber body 105 may support the chamber lid assembly 110 so as to surround the chamber space 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 is formed through the side wall 112 of the chamber body 105, which facilitates the transfer of substrates 302 into and out of the plasma processing chamber 100. The access port 113 may be connected to the transfer chamber and / or other chambers of the substrate processing system as described above. A pumping port 145 may be formed through the side wall 112 of the chamber body 105 and connected to the chamber space 101. A pumping device may be connected to the chamber space 101 through the pumping port 145 to exhaust the processing space and control the pressure. The pumping device may include one or more pumps and throttle valves.

[0027]

[0030] The gas panel 160 may be connected to the chamber body 105 by a gas line 167 to supply a process gas into the chamber space 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include inert gases, non-reactive gases, and reactive gases that can be used in any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon-containing gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, and oxygen gas. In addition, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases among any number of additional precursors. For example, BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2.

[0028]

[0031] Valve 166 controls the flow of processing gas from sources 161, 162, 163, and 164 of the gas panel 160 and can be managed by controller 165. The flow of gas supplied from the gas panel 160 to the chamber body 105 may include a combination of gases from one or more sources. The lid assembly 110 may include nozzles 114. Nozzles 114 may be one or more ports for introducing processing gas from sources 161, 162, 164, and 163 of the gas panel 160 into the chamber space 101. After the processing gas is introduced into the plasma processing chamber 100, the gas may be activated to form a plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 may supply power to the antenna 148 via a matching circuit 141, inductively coupling energy (e.g., RF energy) to the processing gas and maintaining the plasma formed from the processing gas within the chamber space 101 of the plasma processing chamber 100. In place of, or in addition to, the antenna power supply 142, processing electrodes located below and / or above the substrate 302 can be used to capacitively couple RF power to the processing gas and maintain the plasma within the chamber space 101. The operation of the power supply 142 may be controlled by a controller (e.g., controller 165) that also controls the operation of other components within the plasma processing chamber 100.

[0029]

[0032] A substrate support pedestal 135 may be positioned within the chamber space 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 may hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include an electrode 121 embedded in a dielectric. The electrode 121 is coupled to the RF power supply 125 and may provide a bias that attracts plasma ions formed by the processing gas in the chamber space 101 to the ESC 122 and the substrate 302 fixed on the pedestal. The RF power supply 125 may repeatedly turn on and off or pulse during processing of the substrate 302. The ESC122 may have an insulating section 128 to prevent the sidewalls of the ESC122 from being attracted to the plasma, thereby extending the maintenance life of the ESC122. In addition, the substrate support pedestal 135 may have a cathode dryer 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gas and extend the maintenance interval of the plasma processing chamber 100.

[0030]

[0033] Electrode 121 may be connected to a power supply 150. The power supply 150 may provide electrode 121 with a chucking voltage of approximately 200 volts to approximately 2000 volts. The power supply 150 may also include a system controller for controlling the operation of electrode 121 by supplying DC current to electrode 121 for chucking and dechucking the substrate 302. ESC 122 may include a heater located within a pedestal and connected to the power supply for heating the substrate. Meanwhile, the cooling base 129 supporting ESC 122 may include conduits for circulating a thermal conductive fluid to maintain the temperature of ESC 122 and the substrate 302 placed on top of it. ESC 122 may be configured to operate within the temperature range required by the thermal balance of the device manufactured on the substrate 302. For example, ESC 122 may be configured to maintain the substrate 302 at a temperature from approximately -150°C or below to approximately 500°C or above, depending on the process being performed.

[0031]

[0034] A cooling base 129 may be provided to assist in temperature control of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be kept substantially constant by the cooling base 129 while the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained at a temperature between approximately -150°C and approximately 500°C throughout the subsequent cleaning process, although any temperature may be available. A covering 130 may be positioned on the ESC 122 and along the outer periphery of the substrate support pedestal 135. The covering 130 may be configured to shield the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100 while containing etching gases in desired portions of the exposed upper surface of the substrate 302. As previously stated, lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism.

[0032]

[0035] The controller 165 may be used to control the processing sequence and adjust the gas flow from the gas panel 160 to the plasma processing chamber 100 and other process parameters. When executed by the CPU, the software routines translate the CPU into a purpose-specific computer (such as a controller) capable of controlling the plasma processing chamber 100, and as a result, the process is executed in accordance with this disclosure. The software routines may also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0033]

[0036] The chamber described above may be used when performing exemplary methods, including etching methods. Figure 3 shows exemplary operation of Method 300 according to an embodiment of the Art. Method 300 may include one or more steps before the commencement of the Method. These one or more steps may include front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the described steps. Method 300 may include a number of optional operations that may or may not be specifically associated with some embodiments of the Method according to embodiments of the Art. For example, many of the steps are described to provide a broader range of processes to be performed, but are not important to the Art, or can be performed by alternative methods, as will be further described below. Method 300 can describe the processes schematically shown in Figures 4A-4B, which will be described in conjunction with the processes of Method 300. The figures show only partial schematics, and it should be understood that the substrate may include any number of additional materials and features having various properties and characteristics as shown in the figures.

[0034]

[0037] Method 300 may or may not include optional operations to develop the semiconductor structure into a specific manufacturing operation. It should be understood that Method 300 can be performed on any number of semiconductor structures 400 or substrates 405, including exemplary structures in which a silicon and nitrogen-containing material removal step can be performed, as shown in Figure 4A. The exemplary semiconductor structures may include trenches, vias, or other concave features that may contain one or more exposed materials. For example, an exemplary substrate may include silicon or some other semiconductor substrate material and an interlayer dielectric material that can form recesses, trenches, vias, or insulating structures. The exposed material at any point during the etching process may be, or include, one or more dielectric materials, contact materials, transistor materials, or any other materials that may be used in the semiconductor process.

[0035]

[0038] For example, as shown in Figure 4A, the first layer 410 of the material may be located on a substrate 405. The substrate 405 may be any number of materials used in semiconductor processing. The substrate material may be a dielectric material containing silicon, germanium, silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials, or may contain these, and may be the substrate 405 or a material formed within the structure 400. In the structure 400 shown in Figure 4A, the first layer 410 of the material may be a silicon-containing material such as silicon. The first layer 410 of the material may be patterned to form one or more features. The aspect ratio or height-to-width ratio of one or more features may be about 2:1 or greater, about 3:1 or greater, about 5:1 or greater, about 10:1 or greater, about 20:1 or greater, or greater. The second layer 415 of the material may be located on top of the first layer 410 of the material. The second layer 415 of the material may also be a silicon-containing material such as silicon oxide. A layer 420 of a silicon-and-nitrogen-containing material may lie on top of the second material layer 415. The layer of silicon-and-nitrogen-containing material 420 may be silicon nitride. The second material layer 415 and the layer 420 of the silicon-and-nitrogen-containing material may extend within one or more features defined by the first material layer 410. It should be understood that any number of additional materials may be formed on the illustrated structure 400. It should be understood that the described structure is not intended to be limiting and similarly encompasses any of the various other semiconductor structures. Other exemplary structures include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which silicon-and-nitrogen-containing materials such as silicon nitride can be selectively removed from other materials. This technique makes it possible to selectively remove silicon-and-nitrogen-containing materials from other exposed materials, including silicon-containing materials and other materials described elsewhere. In addition, while high aspect ratio structures can benefit from this technology, it may be equally applicable to lower aspect ratios and any other structures.

[0036]

[0039] Method 300 may include, in step 305, providing one or more precursors within a processing region of a semiconductor processing chamber housing the described substrate 405. The one or more precursors may include a hydrogen-containing precursor and / or an inert precursor. In step 310, a plasma emission of one or more precursors may be formed. In embodiments, one or more precursors may be flowed through a remote plasma region of the processing chamber, such as the region 215 described above, and a plasma may be formed from one or more precursors to generate a plasma emission. A substrate-level plasma may be generated, but in some embodiments, the plasma may be a remote plasma, thereby protecting the exposed substrate material from ion collisions that may be generated by the substrate-level plasma. Whether or not plasma-enhanced, in step 315, the one or more precursors or plasma emission may come into contact with the substrate 405, which includes an exposed layer 420 of a silicon- and nitrogen-containing material. This contact may etch a portion of the layer of silicon- and nitrogen-containing material 420.

[0037]

[0040] As described above, the precursors used in Method 300 and provided in Step 305 may include a hydrogen-containing precursor and / or an inert precursor. For example, non-limiting hydrogen-containing precursors may include diatomic hydrogen (H2), water (H2O), ammonia (NH3), or any other hydrogen-containing material. Exemplary inert precursors may, in some embodiments, include one or more of argon, xenon, or helium, and any other nonreactive material. In embodiments, the flow rate of the inert precursor may be greater than the flow rate of the hydrogen-containing precursor. For example, the flow rate ratio of the inert precursor to the hydrogen-containing precursor may be about 2:1 or greater, and the flow rate ratio of the inert precursor to the hydrogen-containing precursor may be about 5:1 or greater, about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 35:1 or greater, or greater. As the flow rate of the inert precursor increases, the hydrogen-containing precursor is diluted, and the etching rate of the silicon and nitrogen-containing material 420 layers can be controlled. Furthermore, the inert precursor may collide with the silicon and nitrogen-containing layer of material 420, which may soften the material for etching.

[0038]

[0041] In embodiments, one or more precursors may not contain halogen-containing precursors, and the processing area may be kept halogen-free during method 300. While conventional techniques have utilized halogen materials to etch nitrogen-containing materials, such as silicon-nitrogen-containing materials, this technique may not require halogen materials. Instead, this technique can remove nitrogen-containing materials, such as silicon-nitrogen-containing materials, as a halogen-free method while maintaining high selectivity. In addition, this technique can thus reduce and / or prevent the accumulation of halogen residues, which can cause problems in downstream processing.

[0039]

[0042] The plasma emitters may be formed at high plasma power to increase the gas density and increase the dissociation of hydrogen-containing precursors, thereby forming more hydrogen-containing plasma emitters that react with the silicon- and nitrogen-containing material layer 420. In some embodiments, the plasma emitters may be formed at power levels of approximately 800 W or higher, approximately 900 W or higher, approximately 1,000 W or higher, approximately 1,250 W or higher, approximately 1,500 W or higher, approximately 1,750 W or higher, approximately 2,000 W or higher, approximately 2,500 W or higher, approximately 3,000 W or higher, approximately 3,500 W or higher, approximately 4,000 W or higher, approximately 4,500 W or higher, approximately 5,000 W or higher, or higher. At lower plasma power levels, hydrogen dissociation may decrease, potentially reducing the etching rate of the silicon- and nitrogen-containing material layer 420.

[0040]

[0043] Plasma emitters of hydrogen-containing precursors can be characterized by high gas density while maintaining a low plasma potential. For example, the plasma potential of plasma emitters of hydrogen-containing precursors may be about 5.0 eV or less, about 4.9 eV or less, about 4.8 eV or less, about 4.7 eV or less, about 4.6 eV or less, about 4.5 eV or less, about 4.4 eV or less, about 4.3 eV or less, about 4.2 eV or less, about 4.1 eV or less, about 4.0 eV or less, about 3.9 eV, about 3.8 eV or less, about 3.7 eV or less, about 3.6 eV or less, about 3.5 eV or less, or even lower.

[0041]

[0044] As shown in Figure 4B, the contact can etch the layer 420 of the silicon-nitrogen-containing material. Although shown as removing the entire layer of silicon-nitrogen-containing material, method 300 can also be controlled to remove only a portion of the layer 420 of the silicon-nitrogen-containing material. By contacting the layer 420 of the silicon-nitrogen-containing material with an inert precursor and / or a hydrogen-containing precursor, or their plasma emissions, the Si-N bonds in the layer 420 of the silicon-nitrogen-containing material can be broken. Contact of the Si-N bonds and the resulting breakdown may form volatile byproducts such as silane (SiH4) and / or ammonia (NH3). During contact, due to differences in bond energies, at least a portion of the layer 420 of the silicon-nitrogen-containing material can be selectively etched into another material on the substrate 405, for example, a second layer 415 of material which may be silicon oxide. The Si-N bonds in the silicon-nitrogen-containing material 420 can be characterized by a bond energy of approximately 3.5 eV, while the Si-O bonds in the second layer 415 of the material can be characterized by a bond energy of approximately 4.5 eV. Therefore, by maintaining the plasma potential of the hydrogen-containing precursor at the aforementioned values, the Si-N bonds in the silicon-nitrogen-containing material 420 can be broken more selectively than the Si-O bonds in the second layer 415 of the material.

[0042]

[0045] Processing conditions can affect and facilitate etching by this technique. For example, the temperature at which the operation is performed can affect the extent to which a reaction may occur. During contact between a layer of silicon and nitrogen-containing material and its hydrogen-containing precursor or plasma emitter, a decrease in temperature can promote the reaction and increase selectivity. Therefore, in some embodiments of this technique, method 300 may be performed at substrate, pedestal, and / or chamber temperatures of about 50°C or less, and may be performed at temperatures of about 25°C or less, about 0°C or less, about -25°C or less, about -50°C or less, about -75°C or less, about -100°C or less, or below. The temperature may be further maintained within these ranges, a narrower range included within these ranges, or any temperature between any of these ranges.

[0043]

[0046] The pressure within the processing area of ​​the semiconductor processing chamber can also affect the operation being performed. To facilitate the etching and removal of by-products, the processing pressure may be about 100 mTorr or less, and may be maintained at pressures below about 80 mTorr, 60 mTorr, 40 mTorr, 20 mTorr, 15 mTorr, 10 mTorr, 8 mTorr, 6 mTorr, 4 mTorr, 3 mTorr, or less. The pressure may be further maintained at any pressure within these ranges, a narrower range included within these ranges, or any pressure between any of these ranges.

[0044]

[0047] By performing the above-described process, the etching rate of silicon nitride may be approximately 1.0 Å / min or more, approximately 1.5 Å / min or more, approximately 2.0 Å / min or more, approximately 2.5 Å / min or more, approximately 3.0 Å / min or more, approximately 3.5 Å / min or more, approximately 4.0 Å / min or more, approximately 4.5 Å / min or more, approximately 5.0 Å / min or more, approximately 5.5 Å / min or more, or higher. Similarly, the selective etching of silicon-nitrogen-containing materials against silicon materials or other materials containing silicon and oxygen may be maintained at approximately 5:1 or higher, and selective etching at approximately 10:1 or higher, approximately 15:1 or higher, approximately 20:1 or higher, approximately 25:1 or higher, approximately 30:1 or higher, approximately 35:1 or higher, approximately 40:1 or higher, approximately 50:1 or higher, approximately 75:1 or higher, approximately 100:1 or higher can be maintained. In the embodiment, other materials present, such as silicon materials or materials containing silicon and oxygen, may not be etched during the removal of materials containing silicon and nitrogen.

[0045]

[0048] The above description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0046]

[0049] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be considered to limit the scope of the Art.

[0047]

[0050] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any listed or unlisted intervening values ​​within the stated range, and any other listed or intervening values ​​within that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which either or both limit values ​​are included in a narrower range, or neither is included in a narrower range, is further included in this art, provided that any limit values ​​are specifically excluded from the stated range. Where a stated range includes one or both limit values, ranges excluding either or both of these included limit values ​​are also included.

[0048]

[0051] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” refers to multiple such precursors, and “a layer” refers to one or more layers and equivalents well known to those skilled in the art, and the same applies to other forms.

[0049]

[0052] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or actions, but not to exclude the presence or addition of one or more other features, integers, components, actions, acts, or groups.

Claims

1. A semiconductor processing method, To provide a hydrogen-containing precursor for a semiconductor processing chamber, wherein a substrate is placed on a substrate support within the processing chamber, and a layer of a material containing silicon and nitrogen is placed on the substrate. Forming plasma ejecta of the hydrogen-containing precursor, The process involves bringing a layer of the silicon and nitrogen-containing material into contact with the plasma emission of the hydrogen-containing precursor, wherein the contact etches a portion of the layer of the silicon and nitrogen-containing material, and the process involves bringing the layer of the silicon and nitrogen-containing material into contact with the plasma emission of the hydrogen-containing material. A semiconductor processing method, including the following.

2. The hydrogen-containing precursor is diatomic hydrogen (H ２ The semiconductor processing method according to claim 1, including ).

3. The semiconductor processing method according to claim 1, wherein the processing area is kept halogen-free.

4. The semiconductor processing method according to claim 1, wherein a layer of material containing silicon and oxygen, a layer of silicon-containing material, or both are disposed on the substrate.

5. The semiconductor processing method according to claim 1, further comprising providing an inert precursor together with the hydrogen-containing precursor to the processing region.

6. The semiconductor processing method according to claim 5, wherein the flow rate of the inert precursor is greater than the flow rate of the hydrogen-containing precursor.

7. The semiconductor processing method according to claim 1, wherein the plasma emission material is formed with a plasma output of approximately 800 W or more.

8. The semiconductor processing method according to claim 1, wherein the plasma emission is formed with a plasma output of approximately 2,000 W or more.

9. The aforementioned contact is made by silane (SiH ４ ), ammonia (NH ３ The semiconductor processing method according to claim 1, which forms ), or both.

10. The semiconductor processing method according to claim 1, wherein the substrate is characterized by a temperature of approximately 50°C or less.

11. The semiconductor processing method according to claim 1, wherein the substrate is characterized by a temperature of approximately -25°C or lower.

12. The semiconductor processing method according to claim 1, wherein the pressure inside the semiconductor processing chamber is maintained at approximately 100 mTorr or less.

13. The semiconductor processing method according to claim 1, wherein the contact is used to etch the layer of the material containing silicon and nitrogen at an etching rate of about 1 Å / min or more.

14. A semiconductor processing method, To provide a hydrogen-containing precursor for a semiconductor processing chamber, wherein a substrate is placed on a substrate support within the processing chamber, a layer of a material containing silicon and oxygen is placed on the substrate, and a layer of a material containing silicon and nitrogen is placed on the layer of the silicon and oxygen-containing material. Forming a plasma emission of the hydrogen-containing precursor, wherein the plasma emission is formed with a plasma output of approximately 1,000 W or more. The process involves bringing a layer of the silicon and nitrogen-containing material into contact with the plasma emission of the hydrogen-containing precursor, wherein the contact selectively etches a portion of the silicon and nitrogen-containing material layer with respect to the silicon and oxygen-containing material layer, A semiconductor processing method, including the following.

15. The semiconductor processing method according to claim 14, wherein the processing area is kept halogen-free.

16. The semiconductor processing method according to claim 14, wherein the substrate is characterized by a temperature of approximately 50°C or less.

17. A semiconductor processing method, To provide a hydrogen-containing precursor for a semiconductor processing chamber, wherein a substrate is placed on a substrate support within the processing chamber, a layer of a material containing silicon and oxygen is placed on the substrate, and a layer of a material containing silicon and nitrogen is placed on the layer of the silicon and oxygen-containing material. Forming plasma ejecta of the hydrogen-containing precursor, The process involves bringing a layer of the silicon and nitrogen-containing material into contact with the plasma emission of the hydrogen-containing precursor, wherein the contact selectively etches a portion of the silicon and nitrogen-containing material layer with respect to the silicon and oxygen-containing material layer, and the substrate is characterized by a temperature of approximately -50°C or lower. A semiconductor processing method, including the following.

18. The semiconductor processing method according to claim 17, further comprising providing helium to the processing region together with the hydrogen-containing precursor.

19. The semiconductor processing method according to claim 17, wherein the processing area is kept halogen-free.

20. The semiconductor processing method according to claim 1, wherein the plasma emission material is formed with a plasma output of approximately 1,000 W or more.

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