Self-aligned bit lines and storage node contacts for 4F2 DRAM

Abstract

This technology includes a vertical-cell dynamic random access memory (DRAM) array with improved resistivity and self-alignment of bit lines and storage node contacts, and a method for fabricating such an array. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending vertically, substantially orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. Furthermore, the array includes a configuration in which the bit lines, storage node contacts, or both are formed from a metallized material.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application is a self-aligned bit line and storage node contacts for 4F, filed on October 5, 2023. 2 We claim the interests and priority of U.S. Patent Application No. 63 / 588,214, entitled “DRAM,” which is incorporated herein by reference in its entirety.

[0002]

[0002] This disclosure generally refers to 4F 2 This disclosure describes the design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a 4F array having self-aligned metal bit lines or storage node contacts. 2 Let's discuss memory arrays. [Background technology]

[0003]

[0003] Advances in computing technology have made computing devices smaller and increased their processing power. Therefore, it is necessary to increase storage and memory to meet the programming and computing needs of the devices. By increasing the number of storage units with smaller form factors, miniaturization of devices with increased storage capacity can be achieved.

[0004]

[0004] Dynamic Random Access Memory (DRAM) architectures have been shrinking over time. For example, a one-transistor, one-capacitor (1T-1C) DRAM cell architecture is 8F 2 Sizes up to 6F 2 We successfully reduced the size to 6F (where F is the minimum feature size). 2 From 4th floor 2 Further design scheme modifications could help improve area density. 4F 2In the DRAM method, the storage node (capacitor) and the bit line are located above and below the vertical cell transistor, and the channel remains completely separated from the body. With this configuration, due to the body connection of the channel, the floating body effect that does not pose a problem in the current 8F 2 or 6F 2 DRAM cell architecture becomes a major technical issue in 4F 2 DRAM. In addition, such an arrangement also hinders the formation of bit line or storage node contacts. Therefore, improvement in the art is needed.

Summary of the Invention

[0005]

[0005] This technology generally relates to a vertical cell dynamic random access memory (DRAM) precursor structure, a method of fabricating such a structure, and a semiconductor device and a method of fabricating such a device. The DRAM precursor structure includes a substrate, one or more sacrificial layers formed on the substrate, one or more first epitaxially grown bonding material layers formed on the sacrificial layer, an epitaxially grown channel material formed on the first bonding material, and one or more second epitaxially grown bonding material layers formed on the channel material.

[0006]

[0006] In embodiments, the precursor structure includes locations where one or more sacrificial layers are epitaxially grown silicon germanium (SiGe). In more embodiments, germanium is present in one or more sacrificial layers in an amount of about 5% by weight or more. Furthermore, in embodiments, one or more sacrificial layers have a thickness of about 5 nm or more. Additionally or alternatively, in embodiments, one or more first epitaxially grown bonding material layers, one or more second epitaxially grown bonding material layers, or both one or more first epitaxially grown bonding material layers and one or more second epitaxially grown bonding material layers have a dopant concentration of about 50% or more of the average doping concentration of the bonding material layers along the bonding material layers or at any point within the bonding material layers. In more than one embodiment, one or more first epitaxially grown bonding material layers comprise n-type doped silicon, the channel material comprises silicon, and one or more second epitaxially grown bonding material layers comprise n-type doped silicon.

[0007]

[0007] The technology also generally covers methods for forming precursor structures. The method comprises growing one or more sacrificial layers on a semiconductor substrate. The method comprises epitaxially growing channel material on one or more sacrificial layers while providing one or more n-type dopants and forming one or more first junction layers. The method comprises epitaxially growing channel material on one or more first junction layers to form one or more channel layers. The method comprises epitaxially growing channel material on one or more channel layers while providing one or more n-type dopants and forming one or more second junction layers.

[0008]

[0008] In embodiments, the method includes cases where one or more sacrificial layers are grown to a height of about 10 nm or more. In more embodiments, one or more sacrificial layers contain germanium in an amount of about 5% by weight or more, based on the weight of one or more sacrificial layers. Embodiments include cases where one or more first junction layers, one or more second junction layers, or both one or more first junction layers and one or more second junction layers have a target doping concentration, and the dopant concentration along or at any point within the first junction layer, the second junction layer, or both the first and second junction layers is about 50% or more of the target doping concentration of the respective layer. Additionally or alternatively, in embodiments, one or more channel layers are grown to a height of about 10 nm or more.

[0009]

[0009] The technology also generally applies to vertical cell DRAM arrays. The array includes a plurality of metal bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, and a plurality of channels extending vertically. The array includes locations where the vertical direction is substantially perpendicular to the first and second horizontal directions, such that the plurality of metal bit lines intersect with the source / drain regions of the plurality of channels, and the plurality of word lines intersect with the gate regions of the plurality of channels. The array includes dielectric material spacers positioned between adjacent bit lines among the plurality of bit lines.

[0010]

[0010] In embodiments, the array includes dielectric material spacers comprising dielectric oxide. In more embodiments, at least a portion of the metal bit wires are offset from each channel of the plurality of channels by about 10% to about 90% of the width of each channel. Additionally or alternatively, embodiments include locations where at least a portion of the dielectric material spacers intersects at least partially with the source / drain regions of the plurality of channels. In even more embodiments, the bit wires are self-aligned bit wires located beneath a single crystalline channel. Furthermore, embodiments include one or more metal storage node contacts located at the upper ends of the plurality of channels.

[0011]

[0011] The technology also generally covers methods for forming vertical cell DRAM arrays. The method includes providing a substrate having a sacrificial material on top of a substrate material, and providing one or more channel materials disposed on top of the sacrificial layer. The method includes etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region. The method includes forming a dielectric material in one or more of the shallow trench isolations. The method includes removing at least a portion of the sacrificial material, forming a void space that at least partially intersects with a portion of the first source / drain region of the vertically extending channel, and forming a metallic bit wire within the void space.

[0012]

[0012] In embodiments, the method includes forming a word line in a word line trench, the word line intersecting the gate regions of a plurality of vertically extending channels. In more embodiments, the method includes locations where a portion of the sacrificial material is removed through one or more access holes. In yet another embodiment, the method includes locations where a portion of the sacrificial material is removed through exposed regions on the back or sides of the substrate. In embodiments, the method includes reducing the thickness of the substrate material before removing at least a portion of the sacrificial material. Furthermore, in embodiments, the method includes removing all of the sacrificial material. Additionally or alternatively, in embodiments, the channel material includes doped channel material and undoped channel material. In further embodiments, the method includes forming one or more of a plurality of vertically extending channels by depositing doped channel material on top of the sacrificial material, depositing undoped channel material on top of the doped channel material, and depositing a second doped channel material on top of the undoped channel material. In more embodiments, the method includes inverting the substrate and removing all or part of the substrate before removing the sacrificial material. Furthermore, in embodiments, the method includes siliconizing a first source / drain region before forming the metal bit wire. In embodiments, the metal bit wire includes tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, species containing these metals, alloys thereof, or combinations thereof.

[0013]

[0013] The technology also generally covers vertical cell DRAM arrays. The array includes a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, and a plurality of channels extending vertically. The array includes cases where the vertical direction is substantially orthogonal to the first and second horizontal directions such that the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. The array includes a plurality of metal storage node contacts.

[0014]

[0014] In some embodiments, the array includes locations where multiple metal storage node contacts self-align under a single crystal channel. In more embodiments, the multiple bit lines include metal bit lines located at the upper ends of multiple channels.

[0015]

[0015] The technology also generally covers methods for forming vertical cell DRAM arrays. The method includes providing a substrate having a sacrificial layer on a substrate material and one or more channel materials disposed on the sacrificial layer. The method includes etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region. The method includes forming a dielectric material in one or more of the shallow trench isolations. The method includes removing at least a portion of the sacrificial material and forming a void space that at least partially intersects with a portion of the first source / drain region of the vertically extending channel. The method includes forming one or more metallic storage node contacts in the void space.

[0016]

[0016] In an embodiment, the method includes forming a word line within a word line trench, the word line intersecting the gate regions of a plurality of channels. In more embodiments, the method includes forming one or more of a plurality of vertically extending channels by depositing a doped channel material over a sacrificial material, depositing an undoped channel material over the doped channel material, and depositing a second doped channel material over the undoped channel material. In yet another embodiment, the method includes inverting the substrate and removing all or a portion of the substrate before removing the sacrificial material. Further, in an embodiment, the method includes siliciding a first source / drain region before forming one or more metal storage node contacts. Additionally or alternatively, an embodiment includes the case where one or more metal storage node contacts include tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof.

[0017]

[0017] Such techniques can provide a number of advantages over conventional systems and techniques. For example, the process and system enable the formation of bit line or storage node contact junctions at an early stage of the process, significantly reducing the complexity and cost of forming the junctions compared to utilizing conventional approaches with thermal budget constraints. Additionally, the methods and systems described herein provide high-quality junctions for 4F 2 DRAM devices. Further, the process and system enable the formation of metal bit lines or storage node contacts without additional overlay and patterning processes and instead provide self-aligned metal bit lines or storage node contacts. These embodiments and other embodiments are described in more detail by the following description and the accompanying drawings, along with their many advantages and features.

[0018]

[0018] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0019] [Figure 1A] Shows a top view of an exemplary processing chamber according to an embodiment of the present technology. [Figure 1B] Shows a top view of a conventional 4F2 memory array. [Figure 1C] Is a perspective view of a conventional 4F2 memory array. [Figure 2] Shows selected steps in a forming method according to an embodiment of the present technology. [Figure 3A] Shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, in which a sacrificial layer is formed on a substrate. [Figure 3B] Shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, in which a joint is formed on the sacrificial layer. [Figure 3C] Shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, in which a channel is formed on the joint. [Figure 3D] Shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, in which a joint is formed on the channel. [Figure 3E] Shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, having a contact pad formed on the joint. [Figure 4A] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology, having one or more insulators. [Figure 4B] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology, having one or more insulators etched through the sacrificial layer. [Figure 4C] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology, having one or more insulators filled with an insulating material. [Figure 4D] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology, having one or more word line trenches. [Figure 4E]A perspective view of a semiconductor structure according to an embodiment of this technology, in which one or more 4F2 features are formed, is shown. [Figure 4F] This shows a perspective view of the semiconductor structure according to an embodiment of this technology, with the substrate rotated 180°. [Figure 4G] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, which has metallized features formed after the removal of sacrificial material. [Figure 5A] A perspective view of a semiconductor structure according to an embodiment of the present technology having one or more word line trenches is shown. [Figure 5B] A perspective view of a semiconductor structure according to an embodiment of this technology, in which one or more 4F2 features are formed, is shown. [Figure 5C] This shows a perspective view of the semiconductor structure according to an embodiment of this technology, with the substrate rotated 180°. [Figure 5D] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, which has metallized features formed after the removal of sacrificial material. [Modes for carrying out the invention]

[0020]

[0039] Some drawings are included as schematic diagrams. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0021]

[0040] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0022]

[0041] Historically, the bit density of DRAM chips increased by approximately 25% per node. However, the increase in bit density between nodes has decreased to about 20% compared to more recent generations, mainly due to the challenges associated with scaling the cell area. The cell design architecture of the latest DRAM technology is 6F 2 Based on shape dimensions, F is the minimum feature size of a given technology node. 6F 2 From 4th floor 2 Switching to a cell architecture could increase the bit density of the same technology node by 33%. Furthermore, 4F 2 The difficulty in patterning DRAM is 6F 2 This is significantly reduced compared to 4F. 2 The DRAM type capacitor and bit line are 6F 2 This is because, instead of being clustered on the same side as the DRAM, they are located at the two ends of the vertical cell transistors.

[0023]

[0042] However, 4F 2 Designing DRAM has its own challenges. For example, 4F 2 Because the memory cell has transistor channels positioned between the bit lines and the capacitor layer, there is no common substrate connecting the channels, resulting in a stray effect in these transistors. Furthermore, such a design scheme makes it possible to manufacture high aspect ratio structures that challenge existing doping techniques.

[0024]

[0043] In addition, if the capacitor is located at the top of the vertical channel, the bit line must be formed at the bottom of the vertical channel. This can be done by using a continuous line of silicon as the bit line. However, silicon, especially 6F 2Compared to the metal bit lines currently used in DRAM, it has a higher resistivity. Alternatively, the bit lines may be formed by patterning the metal bit lines from the back of the wafer after the bonding of the front wafers is complete and the substrate has been inverted. However, such a process requires complex patterning and alignment, which has proven difficult for processing throughput and consistent high-quality structure formation. For example, such a process requires multiple complex masking and etching steps to align the connections with the formed bit lines. Alternatively, bit 1 is positioned on the vertical channel while forming a capacitor through a back-side process after wafer bonding. However, similar to the problems that occur with back-side bit line formation, such an alternative example requires complex alignment and patterning of the storage node contacts relative to the vertical channel, and complex masking and etching steps to align the connections with the storage node contacts.

[0025]

[0044] This technology is 4F 2This technology overcomes these and other problems by providing a method for self-aligning metallic bit lines or storage node contacts in DRAM cells. Specifically, it has been found that, remarkably, by providing a substrate with a unique orientation, sacrificial material can be removed after the front-side processing is complete, and, for example, the region can be filled with a metallizing material that provides excellent resistivity for the bit lines or storage node contacts. By utilizing such sacrificial material, the voids formed by the removed sacrificial material can be self-aligned and filled with the metallizing material. This makes it possible to form bit lines or storage node contacts at the bottom of the semiconductor structure without requiring complex masking and etching processes. Furthermore, this technology also allows for customized doping of one or more source / drain regions when providing the substrate. Therefore, this technology can provide highly specific and consistent dopant levels, even when the resulting DRAM cell contains one or more high aspect ratios or other complex features.

[0026]

[0045] In the remaining disclosures, 4F 2 While this disclosure routinely identifies specific deposition and etching processes used to form vertical-cell dynamic random-access memory (DRAM) arrays such as DRAM devices, it will be readily apparent that the systems and methods are equally applicable to other DRAM devices, other devices affected by the levitation effect, and the processes for forming such devices. Therefore, this technology should not be considered limited to use in these specific devices or systems only. Before describing additional modifications and adjustments to this device according to embodiments of this technology, this disclosure describes one possible semiconductor device that may include one or more components according to embodiments of this technology.

[0027]

[0046] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105 for orientation or measurement processes, etc.

[0028]

[0047] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a general-purpose computer comprising a controller or an array of controllers and / or software stored on a non-temporary computer-readable medium that, when executed, can perform the steps described in relation to the methods according to embodiments of this art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0029]

[0048] Figures 1B and 1C show the conventional 4F 2 A top view and a perspective view of the memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells in the memory array 150. The memory array 150 may further include a plurality of bit lines 154 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 150. Individual cells in the memory array 150 can be selected by activating one of the plurality of bit lines 154 and one of the plurality of word lines 152. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having the word lines 152 may be formed on top of the second layer having the bit lines 154 such that the two layers do not intersect.

[0030]

[0049] Multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor 170, which may be referred to as a vertical pillar transistor or vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate, which will be described in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge in the vertical capacitor 156 to indicate a stored memory state. However, while Figures 1B and 1C show the arrangement of vertical transistors and capacitors in a rectangular orthogonal grid pattern, it should be understood that other orientations are also conceivable for use in this technique. For example, in embodiments, the capacitors and vertical transistors may be spaced apart in alternating columns offset by half the distance between the vertical transistors. That is, in the embodiment, the first row of memory cells may be regularly spaced in a row in a first direction, and the second row of memory cells may also be regularly spaced in a row in a first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, to be positioned approximately midway between the vertical transistors and capacitors of the first row. Such a pattern is sometimes called a "honeycomb" or "hexagonal pattern" in comparison to the square pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0031]

[0050] This conventional 4F 2It is useful to characterize the dimensions of the unit cell region 166 of the memory array for comparison with a simple memory array described later. For example, the capacitor footprint 158 ​​can be defined as the circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include the horizontal cross-sectional area of ​​the capacitor, which expands until its cross-sectional area contacts the capacitor region from an adjacent memory cell. Assume that the word line pitch 162 for multiple word lines 152 and the bit line pitch 164 for multiple bit lines 154 can be defined as 2F. This gives the overall cross-sectional area of ​​the unit cell region 166 to be 4F. 2 It will become.

[0032]

[0051] Figure 2 shows exemplary operation of Method 200 according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of arbitrary operations, some of which may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many operations are described to provide a broader range of structural forms, but may not be important to the present technology or may be carried out by alternative methods that are easily understood. In addition, while the method may describe the formation method perpendicularly from the word line side of the structure to the bit line side of the structure, it should be understood that other orientations from the bit line to the word line side may be utilized. Furthermore, while it is clear that the precursor semiconductor structure 300 described herein can be used to advantageously form a variety of challenging structures, the precursor structure 300, and the semiconductor structures 400 and / or 500, may only illustrate exemplary structures and methods for forming such structures. Moreover, it should be clear that these exemplary structures and methods for forming such structures are not limiting, and further structures and methods for forming such structures are also conceivable.

[0033]

[0052] Method 200 may include additional steps before commencing the listed steps. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The pre-processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is brought into the semiconductor processing chamber in which Method 200 may be performed.

[0034]

[0053] In any case, Method 200 may optionally include supplying a semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be a pedestal 104, such as a substrate support, and may be deposited on a substrate support / transfer platform that may be present in the processing area of ​​a chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the steps schematically shown in the remaining figures, and the illustrations will be described in conjunction with the steps of Method 200. It should be understood that the figures are only partial schematics, and the semiconductor substrate may include further components shown in the figures, as well as alternative components of any size or configuration from which aspects of the present art can still be beneficial.

[0035]

[0054] Method 200 may or may not include optional steps for developing the semiconductor structure into a specific manufacturing process. It should be understood that Method 200 can be performed on any number of semiconductor structures 300 or substrates 302, as shown in the figure, including exemplary structures on which selectively deposited material can be formed. As shown in Figure 3A, the substrate 302 may be any number of materials, for example, a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing.

[0036]

[0055] Furthermore, although various deposition and filling processes will be described, in embodiments, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), or plasma atomic layer deposition (PEALD). Therefore, it should be understood that any one or more of the above methods known in the art may be used unless otherwise specified. Similarly, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, for example, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0037]

[0056] In embodiments, the substrate 302 may include a bulk substrate, an epitaxially grown substrate, and / or silicon on an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> ), may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While a few examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is included in the spirit and scope of this disclosure.

[0038]

[0057] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with electron-donating elements during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and pores are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a pore concentration greater than the electron concentration. In p-type semiconductors, pores are majority carriers and electrons are minority carriers.

[0039]

[0058] As shown in Figure 3A, a structure 300 is provided which includes a substrate 302 on which a sacrificial layer 304 is formed in step 201. In embodiments, the sacrificial layer 304, also called a “sacrificial spacer,” can be deposited or grown on the substrate 302 in any way known in the art. In embodiments, the sacrificial material may be any selectively etchable material. For example, in embodiments, the sacrificial material may be, for example, epitaxially grown silicon germanium (SiGe) when silicon is used as the substrate. However, it should be apparent that other combinations of materials having different etching selectivity may also be used, as known in the art.

[0040]

[0059] In other words, the present technology has surprisingly found that by forming the semiconductor structure 300 according to the methods and disclosures herein, the semiconductor structure 300 can be uniquely formed to allow the self-alignment formation of one or more contacts on the bottom surface of the semiconductor structure 300. That is, by first forming a sacrificial spacer 304, the sacrificial spacer can hold the space required for one or more features. In addition, the sacrificial spacer can also function as an etching stop that provides a fully self-aligned feature in the embodiment.

[0041]

[0060] Nevertheless, when SiGe is used as the sacrificial layer 304 material, the germanium content is approximately 5% by weight or more, for example approximately 7.5% by weight or more, for example approximately 10% by weight or more, for example approximately 12.5% ​​by weight or more, for example approximately 15% by weight or more, for example approximately 25% by weight or less, for example approximately 25% by weight or less, for example approximately 22.5% by weight or less, for example approximately 25% by weight or more, for example approximately 27.5% by weight or more, for example approximately 30% by weight or more, for example approximately 32.5% by weight or more, based on the weight of silicon and germanium in the SiGe. For example, it may exist in amounts of approximately 35% or more by weight, approximately 37.5% or more by weight, approximately 40% or more by weight, approximately 42.5% or more by weight, approximately 45% or more by weight, approximately 47.5% or more by weight, for example, up to approximately 50% by weight, or for example, approximately 50% or less by weight, for example, approximately 40% or less by weight, for example, approximately 35% or less by weight, for example, approximately 30% or less by weight, for example, approximately 25% or less by weight, for example, approximately 20% or less by weight, for example, approximately 17.5% or less by weight, approximately 15% or less by weight, or any range or value in between these.

[0042]

[0061] Nevertheless, since the sacrificial layer 304 functions as a placeholder for later-formed metallized features, such as bit lines or storage node contacts, the thickness or height of the sacrificial layer can be selected based on the desired thickness or height of the resulting features. Accordingly, in embodiments, the sacrificial layer can be deposited or grown to a thickness of about 5 nm or more, for example about 10 nm or more, for example about 15 nm or more, for example about 20 nm or more, for example about 25 nm or more, for example about 30 nm or more, for example about 35 nm or more, for example about 40 nm or more, or for example about 60 nm or less, for example about 55 nm or less, for example about 50 nm or less, for example about 45 nm or less, for example about 40 nm or less, or any range or value in between these.

[0043]

[0062] Regardless of the material and thickness of the sacrificial layer 304, one or more bonding materials 306 may be formed on the sacrificial layer 304 in step 202, as shown in Figure 3B. In embodiments, the bonding material 306 may be grown or deposited on the sacrificial layer 304. In embodiments, the bonding material 306 may be grown or deposited directly on the sacrificial layer 304 (e.g., without an intervening layer between the sacrificial layer 304 and the bonding material 306), or it may be grown or deposited on one or more intervening layers (not shown). Nevertheless, in embodiments, the bonding material 306 may be any one or more of the substrate materials described above, and may be individually selected to be the same as or different from the material forming the substrate 302. Furthermore, in embodiments, p-type or n-type doping may be carried out by blanket doping, dopant injection, or a modified dopant profile, as well as other methods known in the art.

[0044]

[0063] However, in embodiments, the technology has found that junctions can be doped during the epitaxial growth of the semiconductor structure 300 by including one or more dopants. Such a process may be advantageous because it eliminates the need to dope the junction after the formation of one or more channels (described in more detail below) or as part of back-side processing. Thus, in embodiments, the junction material 306 may undergo blanket doping during layer growth or deposition. For example, in embodiments, the junction material 306 may be epitaxial silicon and may be exposed to P+, P-, N+ and / or N- blanket doping. Blanket doping can be carried out as is known in the art, such as by including dopants during epitaxial growth. If the junction material 306 includes one or more dopants, the junction material 306 may function as a source / drain region of the structure 300.

[0045]

[0064] Furthermore, as described above, this technology has found that by utilizing blanket doping during deposition or growth, a target, highly consistent doping level can be formed without the need for subsequent bonding treatment. For example, in embodiments, the bonding material 306 may have a dopant concentration of approximately 50% or more of the target doping concentration of the bonding material 306 at any point along or within the bonding material 306, for example, approximately 60% or more, approximately 70% or more, approximately 80% or more, approximately 85% or more, approximately 90% or more, approximately 92.5% or more, approximately 95% or more, approximately 97.5% or more, approximately 99% or more, approximately 99.5% or more, or any range or value in between these, of the average doping concentration of the bonding material 306. However, in embodiments, it should become clear that the target doping concentration may change as it moves from the substrate 302 toward the channel material 308 (for example, decreasing in embodiments). Therefore, in embodiments, a highly consistent doping level can be compared to the target doping level in the corresponding horizontally extending layer of the bonding material. For example, this technology has surprisingly found that by forming the junction as part of the precursor structure 300, each layer or portion of the junction has a highly consistent doping concentration with little to no variation across the entire layer. Furthermore, even when the target doping concentration is changed as the junction is formed vertically, high-precision doping is exhibited within each region or portion. Therefore, in embodiments, the above values ​​may relate to points within each junction layer having a dopant concentration that matches the target doping concentration of each layer or portion.

[0046]

[0065] In the embodiment, as shown in Figure 3C, the channel material 308 may be deposited on top of the bonding material 306 during operation 203. In the embodiment, the channel material 308 may be deposited directly on top of the bonding material 306 (for example, without an intervening layer between the bonding material 306 and the channel material 308), or it may be deposited on top of one or more intervening layers (not shown). Nevertheless, in the embodiment, the channel material 308 may be any one or more of the substrate materials described above, and may be individually selected to be the same as or different from the materials forming the substrate 302 and / or bonding material 306.

[0047]

[0066] However, in the embodiment, the channel material layer 308 may be formed from the same material as the bonding material 306, except that the dopant may be absent or present only in very small levels. Thus, in such embodiments, if epitaxial growth is utilized, epitaxial growth may continue without interruption during the formation of the bonding material 306 and the channel material 308, although the dopant may be incorporated at all or in very small levels during the growth of the channel material 308. Nevertheless, as described above, in the embodiment, other deposition methods may be utilized such that different materials, different processes, or combinations thereof occur between the bonding material 306 and the channel material 308. In any case, in the embodiment, the channel material 308 may be epitaxially grown silicon (or any of the other substrate materials described above) with a small amount of dopant present in the layer or no dopant present at all.

[0048]

[0067] In the embodiment, regardless of the selected material, the channel can be deposited to a height corresponding to the desired channel length. Therefore, in the embodiment, the channel can be measured from the bonding material 306 to the end top surface of the channel material 308 to be about 10 nm or more, for example about 15 nm or more, for example about 20 nm or more, for example about 25 nm or more, for example about 30 nm or more, for example about 35 nm or more, for example about 40 nm or more, for example about 45 nm or more, for example about 55 nm, for example about 60 nm or more, for example about 65 nm or more, for example about 70 nm or more, for example about 75 nm or more, for example about 80 nm or more, for example It can be deposited at a height of approximately 90 nm or more, for example, approximately 100 nm or more, for example, approximately 120 nm or more, for example, approximately 140 nm or more, for example, approximately 160 nm or more, for example, approximately 180 nm or more, for example, approximately 200 nm or more, for example, approximately 220 nm or more, for example, approximately 240 nm or more, or for example, approximately 250 nm or more, or for example, approximately 250 nm or less, for example, approximately 200 nm or less, for example, approximately 150 nm or less, for example, approximately 100 nm or less, or any range or value in between these.

[0049]

[0068] In embodiments, the second bonding material 310 may be grown or deposited on the channel material 308 in step 204, as shown in Figure 3D. In embodiments, the second bonding material 310 may be grown or deposited directly on the channel material layer 308 (for example, without an intervening layer between the channel material layer 308 and the second bonding material 310), or it may be grown or deposited on one or more intervening layers (not shown). Nevertheless, in embodiments, the second bonding material 310 may be any one or more of the substrate materials described above, and may be the same as or individually selected to be different from the materials forming the substrate 302, bonding material 306, and / or channel material layer 308. Furthermore, in embodiments, p-type or n-type doping may be carried out by blanket doping, dopant injection, or a modified dopant profile, as well as other methods known in the art.

[0050]

[0069] In embodiments, the second bonding material 310 may undergo blanket doping during layer growth or deposition. For example, in embodiments, the second bonding material 310 is epitaxial silicon and may be exposed to P+, P-, N+, and / or N- blanket doping. In embodiments, the doping of the second bonding material 310 may be the same as or different from that of the bonding material 306. Blanket doping may be carried out as is known in the art, such as by including dopants during epitaxial growth. If the second bonding material 310 includes one or more dopants, the second bonding material 310 may function as a second source / drain region of the structure 300.

[0051]

[0070] Furthermore, as described above, the technology has found that by utilizing blanket doping during deposition or growth, a highly consistent target doping level can be achieved. For example, in the embodiment, the second bonding material 310 has a dopant concentration of about 50% or more of the average doping concentration of the second bonding material 310 at any point along or within the second bonding material 310, for example, about 60%, about 70%, about 80%, about 85%, about 90%, about 92.5%, about 95%, about 97.5%, about 99%, or about 99.5% or more. In addition, the doping level may range from the target doping level (e.g., an embodiment where the average doping concentration is the target concentration) to any one or more of the above ranges.

[0052]

[0071] Furthermore, in the embodiment, the second bonding material 310 may be formed from the same material as the bonding material 306. Thus, in such an embodiment, if epitaxial growth is utilized, the epitaxial growth can continue without interruption during the formation of the bonding material 306, the channel material layer 308, and the second bonding material 310, although the dopant may be incorporated between the bonding material 306 and the second bonding material 310, but not during the formation of the channel material layer 308. Nevertheless, as described above, in the embodiment, other deposition methods may be utilized such that different materials, different processes, or combinations thereof occur between one or more of the first channel material layer 306, the channel material layer 308, and the second bonding material 310. In any case, in the embodiment, the second bonding material 310 may be epitaxially grown silicon (or any of the other substrate materials described above) with a dopant amount similar to, or generally equal to, that of the bonding material 306. In any case, such substrate formation processes (or substrates provided therefrom) may enable the acquisition of high aspect ratio structures or features, or other complex features (e.g., one or more turns or bends from a central access hole), with a level of consistency and target doping that is difficult to achieve using conventional processes.

[0053]

[0072] However, in some embodiments, one or more channel material layers 306 may instead be formed of a single material, such as any one or more of the substrate materials described above. In such embodiments, one or more channel material layers 306 may undergo source / drain formation, as is known in the art, such as by utilizing one or more injections after the formation of the trench isolation 414, as will be described in more detail below.

[0054]

[0073] In embodiments, the semiconductor structure 300 shown in Figure 3D may form a precursor structure as described herein. That is, a precursor structure formed according to the Art may be carefully formed to provide one or more self-aligned features. Nevertheless, in embodiments, the precursor semiconductor structure 300 may include forming a contact pad 312 on a second bonding material 310. The contact pad 312 may include one or more dielectric materials, such as an oxide-containing material, a nitride-containing material, or other materials known in the Art.

[0055]

[0074] While it is clear that the precursor semiconductor structure 300 can be used to favorably form various challenging structures, Figures 4A-4G and 5A-5D may illustrate exemplary structures and methods for forming such structures using the precursor semiconductor structure 300 for illustrative purposes only. However, these examples are non-limiting, and it should become clear that further structures and methods for forming such structures from the aforementioned precursors are conceivable.

[0056]

[0075] Nevertheless, as shown in Figure 4A, the structure 400 may have one or more trench isolations 414 formed through the bonding material 406, the channel material 408, and the second bonding material 410. Such trenches may be formed by patterning and etching, for example by utilizing a mask 416 and any etching process known in the art, as is known in the art. However, in embodiments, etching of the trench isolations 414 may be a two-step operation, as shown in Figures 4A and 4B. That is, the trenches 414 may first be etched according to any one or more methods known in the art, and then a selective second etching step may be performed on the sacrificial material 404. In this way, highly aligned and uniform trenches 414 can be formed in the structure 400.

[0057]

[0076] In other words, in addition to the advantages mentioned above, excellent depth control can be obtained by utilizing such selective etching. Furthermore, as will be explained in more detail with respect to word line etching in Figure 3D, by using a sacrificial material with different etching selectivity than the channel material and / or bonding material, a highly controlled etching depth can be achieved without additional lithography or patterning processes.

[0058]

[0077] As shown in the exemplary embodiment of Figure 4C, the trench 414 may be filled with an insulating material 420, such as a dielectric material. In this way, the insulating material 420 can electrically insulate and support the metallized features (as will be described in more detail below). Nevertheless, in embodiments, the insulating material 420 may be a dielectric material such as an oxide-containing material, a nitride-containing material, or a combination thereof. In embodiments, the insulating material 420 may be formed using any of the filling methods described above and may include one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, a combination thereof, or other dielectric materials known in the art.

[0059]

[0078] Referring to Figure 4D, in the illustrated embodiment, one or more word line trenches 422 may be formed in step 205. As Figures 4A to 4G may illustrate exemplary embodiments for forming metallic bit lines, the word line trenches 422 may advantageously extend perpendicularly to the sacrificial material 404. However, it should be understood that in embodiments, one or two-step etching may be utilized to form the word line trenches through the sacrificial material 404 to the substrate 402. In any case, in the illustrated embodiment, the sacrificial material 404 can be retained during the formation of the word line trenches 422 by utilizing materials that have etching selectivity for the bonding material 406, channel material 408, and bonding material 410. This allows space to be retained for forming self-aligned bit lines without requiring additional patterning or lithography steps, as will be described in more detail below.

[0060]

[0079] In this embodiment, after the formation of the trench 422, as shown in Figure 4E, 4F 2 One or more additional components related to the dynamic random access memory (DRAM) device may be formed. For example, the gate dielectric 424 may be formed generally around the outer periphery of the trench 422. Additionally or alternatively, if silicon is used as the channel material 408, the trench 422 may be subjected to in-situ vapor generation to provide silicon oxide as the gate dielectric 424 around the outer periphery of the trench 422. Nevertheless, in embodiments, the gate dielectric 424 may be a dielectric material such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or other dielectric materials known in the art, formed using any of the filling methods described above.

[0061]

[0080] Furthermore, as shown in Figure 4E, in the embodiment, the gate metal 426 may be formed in the trench 422 along the gate dielectric 424. The gate metal 426 may be a conductive material having low resistivity, known in the art or deposited by any one or more of the methods described above, such as tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, species containing these metals, alloys of these, or combinations thereof. Nevertheless, as shown, the gate metal 426 may be bottom-punched to remove the gate metal 426 from the bottom of the trench 422 and separate adjacent gates 426.

[0062]

[0081] After punching, the insulating material 428 can be filled into the trenches 422 between adjacent gates 426. Nevertheless, in embodiments, the insulating material 428 may be a dielectric oxide such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or one or more other dielectric materials known in the art, formed using any of the filling methods described above.

[0063]

[0082] Furthermore, as shown in the figures, an insulating plug 430 may be formed between the gate(s) 426 and the upper surface 432 of the channel 408. The plug 430 may be formed from any insulating material known in the art, such as one or more dielectric materials including silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. While silicon dioxide or silicon nitride as dielectric and / or spacer materials are periodically described herein, any number of dielectric materials may be used in embodiments of the art, and it should be understood that the art should not be limited to any specific dielectric material on which the feature may be formed.

[0064]

[0083] In embodiments, the joint 410 may undergo a metallization treatment, such as silicification, to form a metal interface on the joint 410. For example, a metal layer may be applied on the joint 410, which is then exposed to a silicification process to form a metallized contact 436. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Thus, the resulting interface may be any one or more metallized layers of the above metals and channel materials (such as silicon). Only in such examples may the interface layer be titanium silicide, molybdenum silicide, hafnium silicide, or combinations thereof.

[0065]

[0084] Nevertheless, one or more storage node contacts 434 may be formed on the metallized contacts 436. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. The storage node contact metal may be selected to be the same material as or different from the gate metal 426 described above. As shown in the illustration, in embodiments, a storage node landing pad 438 may also be formed on the storage node contacts 434.

[0066]

[0085] After the formation of the storage node contact features, the front-side DRAM capacitor may be completed in the embodiment. However, in the embodiment, as described above, the structure 400 may be subjected to one or more further processes, which may also be considered front-side processes.

[0067]

[0086] Nevertheless, in step 206, the structure 400 may be rotated 180 degrees (referred to herein as “inverted”) so that the leading top surface of the structure 400 can be oriented as the bottom surface. However, as will be described in more detail below, in some embodiments such a step may not be necessary to access the sacrificial layer 404. Nevertheless, as step 206, access to the sacrificial material 404 may be provided to selectively remove the sacrificial layer 404. As shown in Figure 4F, such access may be provided by thinning the substrate 402 from the back. In some embodiments, all or part of the substrate 402 may be removed from the back to access the sacrificial material 404.

[0068]

[0087] However, as is known in the art, sacrificial materials such as SiGe are highly selective. Therefore, in embodiments, step 206 may include providing one or more access holes through the substrate 402 to selectively etch the sacrificial material 404, instead of completely removing the substrate 402. Additionally or alternatively, lateral access from sides 444, etc., may be provided or extended, either alone or in combination with one or more access holes. Regardless of the method used, it should be apparent that the sacrificial material 404 is selected to have etching specificity that allows for selective etching of the sacrificial material 404 with respect to the insulating layers 420 and 428, as well as the bonding material 406, channel material 408, and bonding material 410. Thus, the insulating layer 420 remains positioned between adjacent void spaces 446 formed from the removal of the sacrificial material 404. Nevertheless, although embodiments are provided, it should become clear that the sacrificial material 404 can be removed in step 206 and by any method known in the art, as shown in Figure 4F, and the sacrificial material 404 provides a void space 446 defined by the insulating material 420 and the bonding material 406.

[0069]

[0088] Referring to the embodiment shown in Figure 4G, in step 207, the void space 446 may allow access to a first source / drain region (e.g., the bonding material 406 in the illustrated embodiment). The first source / drain region 406 may undergo a metallization process, such as silicification, to form a metal interface 450 between the void space 446 and the first source / drain region 406. For example, a metal layer may be applied over the first source / drain 406 and then exposed to the silicification process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Thus, the resulting interface may be any one or more metallized layers of the above metals and channel materials (such as silicon). Only in such examples may the interface layer be titanium silide, molybdenum silide, hafnium silide, or combinations thereof.

[0070]

[0089] Nevertheless, in embodiments, the void space 446 may then be filled with metal bit wire 448 material. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. The bit wire metal may be selected to be the same material as or different from the gate metal 426 described above. As shown in the illustrated embodiments, the bit wire metal 448 may be filled into the void space 446 in a highly aligned (e.g., self-aligned) manner. Thus, in embodiments, the metal bit wire 448 may be positioned directly above each channel 408 without requiring a masking or photoresist process.

[0071]

[0090] However, the technology has also surprisingly found that the processes and methods described herein can also include bit wire spacers or voids. For example, in an embodiment, the bit wire metal 448 can be filled into the void space 446 such that the bit wire metal 448 intersects at least partially with the source / drain region 406. For example, in the embodiment, the bit wire metal 448 can be offset from each of the channels 408 located above it, or can have a width smaller than its width, for example, the bit wire is offset by about 10% to about 90% of the width of each channel, for example, about 15% or more, about 20% or more, for example, about 30% or more, for example, about 40% or more, for example, about 50% or more, for example, about 60% or more, for example, about 70% or more, for example, about 80% or more, for example, about 85% or more, or about 85% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 15% or less, or any range or value in between (or has a width smaller than its width). The above-mentioned spacers can be removed downstream as needed to form a gap.

[0072]

[0091] In this embodiment, the insulating material 420 may be filled or etched after the trench 414 has been filled, such that only a portion of the trench 414 is filled with the insulating material 420. Thus, the metal bit wires 448 may be filled such that the bit wires 448 are slightly off-center from their respective channels, but are still supported by the insulating layer 420. In such an embodiment, the metal bit wires 448 may be considered as folded cells. Nevertheless, whether the offset (or reduced width) is used alone or in combination with the partially filled trench 414, it should be clear that at least a portion of the bit wire metal 448 intersects with their respective channels according to the above ratio. Furthermore, in such an embodiment, the sacrificial material 404 may be accessed from the partially filled trench 414. Thus, in this embodiment, the removal of the sacrificial material 404 and the filling of the bit wire metal 448 may be considered a front-end process, and after the formation of the metal bit wires 448, the remaining portion of the trench 414 may be filled with insulating material.

[0073]

[0092] Nevertheless, after filling, the bit wire 448 may optionally be further metallized. In any case, the structure 400 is 4F 2 Vertical cell DRAM arrays, such as DRAM arrays, can re-enter the normal process flow for further processing such as polishing, augmentation, or interconnection. For example, the semiconductor structure 400 may undergo contact redistribution, bonding pad formation, and / or copper contact formation. Despite the additional processing, the semiconductor structure exhibits significantly improved bit-line resistance and alignment, with little to no damage generally associated with the prior art.

[0074]

[0093] Referencing next to Figure 5A, an example of forming one or more self-aligned storage nodes may be provided. The structure 500 shown in Figure 5A can undergo a process similar to that described above with respect to Figures 4A to 4C, at which point one or more processes or processing steps may diverge. It should be understood that different processing steps may occur before Figure 5A, but in embodiments, Figure 5A may be formed from one or more processes that occur in a similar manner to Figures 4A to 4C through process 204, and therefore will not be repeated for clarity. It should be clear that the precursor semiconductor structure 300 can be used to favorably form a variety of challenging structures, but Figures 5A to 5D may show exemplary structures and methods for forming such structures using the precursor semiconductor structure 300 for illustrative purposes only. However, these examples are not limiting, and it should be clear that further structures and methods for forming such structures from the aforementioned precursors are conceivable.

[0075]

[0094] Referring to Figure 5A, in the embodiment, one or more word line trenches 522 may be formed in step 205. Since Figures 5A to 5D may show the formation of one or more metal storage node contacts, the word line trenches 522 may advantageously extend perpendicularly through the sacrificial material 504. In the embodiment, one or two-step etching may be utilized to separate adjacent portions of the sacrificial layer 504 so as to form word line trenches through the sacrificial material 504 to the substrate 502 and to separate them spaced apart under the respective joints 506 and channels 508. As illustrated, the sacrificial material 504 can be neatly aligned with the respective channels, allowing the storage node contacts to be formed self-aligned and precisely. In any case, in the illustrated embodiment, by utilizing a material having etching selectivity for the joint material 406, channel material 408, and joint material 410, the sacrificial material 404 can be retained during the first etching formation of the word line trenches 522. This makes it possible to achieve a trench 522 with a highly controlled depth without further processing.

[0076]

[0095] After the formation of the trench 522, in this embodiment, as shown in Figure 5B, 4F 2 One or more additional components related to the dynamic random access memory (DRAM) device may be formed. For example, the gate dielectric 524 may be formed generally around the outer periphery of the trench 522. Additionally or alternatively, if silicon is used as the channel material 508, the trench 522 may be subjected to in-situ vapor generation to provide silicon oxide as the gate dielectric 524 around the outer periphery of the trench 522. Nevertheless, in embodiments, the gate dielectric 524 may be a dielectric material such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or other dielectric materials known in the art, formed using any of the filling methods described above.

[0077]

[0096] Furthermore, as shown in Figure 5B, in the embodiment, the gate metal 526 may be formed in the trench 522 along the gate dielectric 524. The gate metal 426 may be a conductive material having low resistivity, known in the art or deposited by any one or more of the methods described above, such as tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, species containing these metals, alloys of these, or combinations thereof. Nevertheless, as shown, the gate metal 526 may be bottom-punched to remove the gate metal 526 from the bottom of the trench 522 and separate adjacent gates 526.

[0078]

[0097] In the embodiment, after punching, the insulating material 528 may be filled into the trench 522 between adjacent gates 526. Nevertheless, in the embodiment, the insulating material 528 may be a dielectric oxide such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, a combination thereof, or one or more other dielectric materials known in the art, formed using any of the filling methods described above.

[0079]

[0098] Furthermore, as shown in the figures, an insulating plug 530 may be formed between the gate 526 and the upper surface 532 of the channel 508. The plug 530 may be formed from any insulating material known in the art, such as one or more dielectric materials including silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. While silicon dioxide or silicon nitride as dielectric and / or spacer materials are periodically described in this specification, any number of dielectric materials may be used in embodiments of the art, and it should be understood that the art should not be limited to any specific dielectric material on which the feature may be formed.

[0080]

[0099] In embodiments, the joint 510 may undergo a metallization treatment, such as silicification, to form a metal interface on the joint 510. For example, a metal layer may be applied on the joint 510, which is then exposed to a silicification process to form a metallized contact 536. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Thus, the resulting interface may be any one or more metallized layers of the above metals and channel materials (such as silicon). Only in such examples may the interface layer be titanium silide, molybdenum silide, hafnium silide, or combinations thereof.

[0081]

[0100] Nevertheless, in embodiments, one or more bit wires 534 may be formed on the metallized contact 536. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof. The bit wire metal may be selected to be the same material as or different from the gate metal 526 described above.

[0082]

[0101] After the bit lines are formed, the front DRAM capacitor can be completed. However, in some embodiments, as described above, the structure 400 may be subjected to one or more further processes, which may also be considered front-side processes.

[0083]

[0102] Nevertheless, in step 206, the structure 500 may be rotated 180 degrees (referred to herein as "inverted") so that the leading upper surface of the structure 500 can be oriented as the bottom surface. However, as described above, in embodiments, such a step may not be necessary to access the sacrificial layer 504. Nevertheless, as step 206, access to the sacrificial material 504 may be provided to selectively remove the sacrificial layer 504. As shown in Figure 5C, such access may be provided by thinning the substrate 502 from the back. In embodiments, all or part of the substrate 502 may be removed from the back to access the sacrificial material 504.

[0084]

[0103] However, as is known in the art, sacrificial materials such as SiGe are highly selective. Therefore, in embodiments, operation 206 may include providing one or more access holes through the substrate 502 to selectively etch the sacrificial material 504, instead of completely removing the substrate 502. Additionally or alternatively, lateral access from sides 544, etc., may be provided or extended, either alone or in combination with one or more access holes. Regardless of the method used, it should be evident that the sacrificial material 504 is selected to have etching specificity that allows for selective etching of the sacrificial material 504 with respect to the insulating layers 520 and 528, as well as the bonding material 506, channel material 508, and bonding material 510. Thus, the insulating layer 520 remains located between adjacent void spaces 546 formed from the removal of the sacrificial material 404. However, although examples are shown, it is evident that the sacrificial material 504 can be removed in step 206 and by any method known to those skilled in the art, as shown in Figure 5C. In Figure 5C, the sacrificial material 504 is removed, providing one or more void spaces 546 defined by the insulating material 520 and the bonding material 506.

[0085]

[0104] Referring to Figure 5D, in an embodiment, in step 207, the void space 546 may allow access to a first source / drain region (e.g., bonding material 506 in the illustrated embodiment). The first source / drain region 506 may undergo a metallization process, such as silicification, to form a metal interface 536 between the void space 546 and the first source / drain region 506. For example, a metal layer may be applied over the first source / drain 506 and then exposed to the silicification process. In an embodiment, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Thus, the resulting interface may be any one or more metallized layers of the above metals and channel materials (such as silicon). Only in such an example may the interface layer be titanium silide, molybdenum silide, hafnium silide, or combinations thereof.

[0086]

[0105] Nevertheless, the void space 546 can then be filled with a metal storage node contact 548 material. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. The storage node contact metal may be selected to be the same material as or different from the gate metal 526 described above. As shown in the illustrated embodiments, the storage node contact metal 548 can be filled into the void space 546 in a highly aligned (e.g., self-aligned) manner. Thus, in embodiments, the storage node contact 548 can be positioned directly above each channel 508 without requiring a masking or photoresist process.

[0087]

[0106] In the embodiment, after filling, the storage node contact 548 may optionally be further metallized. In any case, the structure 500 is 4F2 Vertical cell DRAM arrays, such as DRAM arrays, can re-enter the normal process flow for further processing such as polishing, augmentation, or interconnection. For example, the semiconductor structure 500 may undergo contact redistribution, bonding pad formation, and / or copper contact formation, including the formation of landing pads 550. Despite the additional processing, the semiconductor structure may exhibit alignment with little to no damage, with significantly improved resistance of the bit lines and storage node contacts, and generally associated with the prior art.

[0088]

[0107] The specific step shown in the drawing is 4F according to various embodiments. 2 It should be understood that this provides a specific method for forming a DRAM array. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in the figures may include multiple substeps that can be performed in various sequences depending on the individual step. In addition, since the various processes described herein may be suitable for other devices, additional steps may be added or removed depending on the specific application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0089]

[0108] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0090]

[0109] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0091]

[0110] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0092]

[0111] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0093]

[0112] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may sometimes describe processes as sequential, many processes can be executed in parallel or simultaneously. Moreover, the order of processes may be rearranged. A process terminates when a process is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0094]

[0113] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0095]

[0114] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0096]

[0115] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0097]

[0116] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A precursor structure for vertical cell dynamic random access memory (DRAM), circuit board and One or more sacrificial layers formed on the substrate, One or more first epitaxially grown bonding material layers formed on the sacrificial layer, An epitaxially grown channel material formed on a first bonding material, One or more second epitaxially grown bonding material layers formed on the channel material and A precursor structure for vertical cell dynamic random access memory (DRAM) equipped with a vertical cell dynamic random access memory (DRAM).

2. The vertical cell dynamic random access memory (DRAM) precursor structure according to claim 1, wherein the one or more sacrificial layers are epitaxially grown silicon germanium (SiGe).

3. The vertical cell dynamic random access memory (DRAM) precursor structure according to claim 2, wherein germanium is present in one or more sacrificial layers in an amount of about 5% by weight or more.

4. The vertical cell dynamic random access memory (DRAM) precursor structure according to claim 1, wherein one or more sacrificial layers have a thickness of approximately 5 nm or more.

5. The vertical cell dynamic random access memory (DRAM) precursor structure according to claim 1, wherein the one or more first epitaxially grown bonding material layers, the one or more second epitaxially grown bonding material layers, or both the one or more first epitaxially grown bonding material layers and the one or more second epitaxially grown bonding material layers have a dopant concentration of about 50% or more of the average doping concentration of each layer of the bonding material at any point along the bonding material layers or inside the bonding material layers.

6. The vertical cell dynamic random access memory (DRAM) precursor structure according to claim 1, wherein the one or more first epitaxially grown bonding material layers include n-type doped silicon, the channel material includes silicon, and the one or more second epitaxially grown bonding material layers include n-type doped silicon.

7. A method for forming a precursor structure for vertical cell dynamic random access memory (DRAM), Growing one or more sacrificial layers on a semiconductor substrate, Providing one or more n-type dopants, epitaxially growing a channel material on the one or more sacrificial layers to form one or more first bonding layers, The channel material is epitaxially grown on the one or more first bonding layers to form one or more channel layers, Providing one or more n-type dopants, the channel material is epitaxially grown on the one or more channel layers to form one or more second bonding layers. A method that includes this.

8. The method according to claim 7, wherein the one or more sacrificial layers are grown to a height of approximately 10 nm or more.

9. The method according to claim 8, wherein the one or more sacrificial layers contain germanium in an amount of about 5% by weight or more, based on the weight of the one or more sacrificial layers.

10. The method according to claim 7, wherein the one or more first bonding layers, the one or more second bonding layers, or both the one or more first bonding layers and the one or more second bonding layers have a target doping concentration, and the dopant concentration along or at any point within the first bonding layer, the second bonding layer, or both the first and second bonding layers is about 50% or more of the target doping concentration of each layer.

11. The method according to claim 7, wherein the one or more channel layers are grown to a height of about 10 nm or more.

12. A vertical cell dynamic random access memory (DRAM) array, A first set of metal bit wires arranged horizontally, A second set of horizontally arranged word lines, A plurality of channels extending in a vertical direction substantially perpendicular to the first horizontal direction and the second horizontal direction, wherein the plurality of metal bit lines intersect the source / drain regions of the plurality of channels and the plurality of word lines intersect the gate regions of the plurality of channels, A dielectric material spacer is disposed between adjacent bit wires among the plurality of metal bit wires. A vertical-cell dynamic random access memory (DRAM) array equipped with [a specific feature].

13. The vertical cell dynamic random access memory (DRAM) array according to claim 12, wherein the dielectric material spacer includes a dielectric oxide.

14. The vertical cell dynamic random access memory (DRAM) array according to claim 12, wherein at least a portion of the metal bit wires is offset from each of the plurality of channels by about 10% to about 90% of the width of each channel.

15. The vertical cell dynamic random access memory (DRAM) array according to claim 14, wherein at least a portion of the dielectric material spacer intersects at least partially with the source / drain regions of the plurality of channels.

16. The vertical cell dynamic random access memory (DRAM) array according to claim 12, wherein the bit lines are self-aligned bit lines located beneath a single crystal channel.

17. The vertical cell dynamic random access memory (DRAM) array according to claim 12, further comprising one or more metal storage node contacts located at the upper ends of the plurality of channels.

18. A method for forming a vertical cell dynamic random access memory (DRAM) array, The objective is to provide a substrate, wherein the substrate is Sacrificial material on the substrate material, and One or more channel materials placed on the sacrificial layer To provide a substrate that includes, Etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region, Forming a dielectric material in one or more of the shallow trench isolations, Removing at least a portion of the sacrificial material to form a void space that at least partially intersects with a portion of the first source / drain region of the vertically extending channel, Forming a metal bit wire within the aforementioned void space A method that includes this.

19. The method according to claim 18, further comprising forming a word line in a word line trench, wherein the word line intersects the gate regions of the plurality of vertically extending channels.

20. The method according to claim 18, wherein the portion of the sacrificial material is removed through one or more access holes.

21. The method according to claim 18, wherein the portion of the sacrificial material is removed through an exposed area on the back or side of the substrate.

22. The method according to claim 18, further comprising reducing the thickness of the substrate material before removing the at least portion of the sacrificial material.

23. The method according to claim 18, further comprising removing all of the aforementioned sacrificial material.

24. The method according to claim 18, wherein the one or more channel materials include doped channel materials and undoped channel materials.

25. The method according to claim 18, further comprising: depositing a doped channel material on the sacrificial material to form one or more of the plurality of vertically extending channels; depositing an undoped channel material on the doped channel material; and depositing a second doped channel material on the undoped channel material.

26. The method according to claim 18, further comprising inverting the substrate and removing all or part of the substrate before removing the sacrificial material.

27. The method according to claim 18, further comprising siliconizing the first source / drain region before forming the metal bit wire.

28. The method according to claim 18, wherein the metal bit wire comprises tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof.

29. A vertical cell dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of channels extending in a vertical direction substantially orthogonal to the first horizontal direction and the second horizontal direction, wherein the plurality of bit lines intersect the source / drain regions of the plurality of channels and the plurality of word lines intersect the gate regions of the plurality of channels, Multiple metal storage node contacts and A vertical-cell dynamic random access memory (DRAM) array equipped with [a specific feature].

30. The vertical cell dynamic random access memory (DRAM) array according to claim 29, wherein the plurality of metal storage node contacts are self-aligned under a single crystal channel.

31. The vertical cell dynamic random access memory (DRAM) array according to claim 29, wherein the plurality of bit lines include metal bit lines positioned at the upper ends of the plurality of channels.

32. A method for forming a vertical cell dynamic random access memory (DRAM) array, The objective is to provide a substrate, wherein the substrate is Sacrificial layer on the substrate material, and One or more channel materials placed on the sacrificial layer To provide a substrate that includes, Etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region, Forming a dielectric material in one or more of the shallow trench isolations, Removing at least a portion of the sacrificial material to form a void space that at least partially intersects with a portion of the first source / drain region of the vertically extending channel, To form one or more metal storage node contacts within the void space. A method that includes this.

33. The method according to claim 32, further comprising forming a word line in a word line trench, wherein the word line intersects with the gate regions of the plurality of channels.

34. The method according to claim 32, further comprising: depositing a doped channel material on the sacrificial material to form one or more of the plurality of vertically extending channels; depositing an undoped channel material on the doped channel material; and depositing a second doped channel material on the undoped channel material.

35. The method according to claim 32, further comprising inverting the substrate and removing all or part of the substrate before removing the sacrificial material.

36. The method according to claim 32, further comprising siliconizing the first source / drain region before forming the one or more metal storage node contacts.

37. The method according to claim 32, wherein the one or more metal storage node contacts include tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof.

Images