Pixel circuits and image sensors

Abstract

The present invention provides a pixel circuit and image sensor that offer a wider dynamic range than conventional designs and can read electrical signals at high speed while reducing power consumption. The pixel circuit includes a photodiode, a measuring unit that measures the amount of light corresponding to the current output from one end of the photodiode, and a gate unit provided between the photodiode and the measuring unit. The pixel circuit is supplied with a recharge signal to set one end of the photodiode to a predetermined potential. The gate unit connects the photodiode and the measuring unit so that the measuring unit measures the amount of light at multiple points within one cycle of the recharge signal.

Description

Technical Field

[0001] The present invention relates to a pixel circuit and an image sensor, and particularly to a pixel circuit and an image sensor that detect light using a photodiode.

Background Art

[0002] Conventionally, an image sensor in which pixels including an avalanche photodiode (APD) are arranged is known. In such an image sensor, photons incident on the APD generate photocharges, and avalanche multiplication occurs. As a result, weak light can be detected.

[0003] In recent years, in an image sensor using an avalanche photodiode for imaging, particularly, a SPAD sensor, which is an image sensor using a Single Photon Avalanche Diode (SPAD), is used. Since the SPAD sensor can count incident photons one by one at high speed, it is possible to read an electrical signal without noise, for example, perform high-speed photography.

[0004] However, conventional SPAD sensors consume more power due to a large number of electron droops in SPAD pixels. On the other hand, when the power consumption of the SPAD sensor is reduced, the dynamic range decreases. Also, when trying to expand the dynamic range in a conventional SPAD sensor, the pixel size increases, and an electrical signal cannot be read out at high speed.

Summary of the Invention

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to provide a pixel circuit and an image sensor that have a wider dynamic range than conventional image sensors and can read an electrical signal at high speed while suppressing power consumption.

[0006] According to a first aspect, the present application is a pixel circuit, comprising Photodiode and A measuring unit that measures the amount of light corresponding to the current output from one end of the photodiode, A gate portion is provided between the photodiode and the measuring unit, Includes, A recharge signal is supplied to set one end of the photodiode to a predetermined potential. The gate unit provides a pixel circuit that connects the photodiode and the measuring unit so that the measuring unit measures the light intensity at multiple points in time within one cycle of the recharge signal.

[0007] In this embodiment, the photodiode and the measurement unit are connected, and the amount of light is measured at multiple points within one cycle of the recharge signal. Therefore, while reducing power consumption, it has a wider dynamic range than conventional pixel circuits and can read out electrical signals at high speed. In addition, the pixel size of the pixel circuit can be reduced. Furthermore, electrical signal readout can be performed at high speed.

[0008] According to a possible implementation of the first embodiment, the gate unit is configured to connect the photodiode and the measuring unit at the same period as the period of the recharge signal.

[0009] In this implementation, the photodiode and the measurement unit are connected at the same period as the recharge signal, so that a signal for controlling the gate unit can be generated based on the recharge signal.

[0010] According to a possible implementation of the first embodiment, the gate unit is configured to connect the photodiode and the measurement unit in a sampling phase different from that of the recharge signal.

[0011] In this implementation, the photodiode and the measurement unit are connected at a different sampling phase than the recharge signal, so that a signal for controlling the gate unit can be generated based on the recharge signal.

[0012] According to a possible implementation of the first embodiment, the measuring unit includes a plurality of counters, and the gate unit is configured to connect the photodiode to each of the plurality of counters such that the plurality of counters perform counting operations at different times.

[0013] In this implementation, the photodiode and the measurement unit are connected with a different sampling phase than the recharge signal, allowing different intensities of light to be measured by individual counters.

[0014] According to a possible implementation of the first embodiment, the gate portion includes a plurality of switches, each of which is configured to connect the photodiode to one of the plurality of counters.

[0015] In this implementation, the photodiode and the measurement unit are connected with a different sampling phase than the recharge signal, allowing the gate switch to be controlled so that each counter measures light of different intensities.

[0016] According to a possible implementation of the first embodiment, the counter is configured to output a count value after the recharge signal has been supplied multiple times.

[0017] With this implementation, the count values ​​counted for each sampling phase are output separately, and by combining them, a single linear output characteristic can be obtained.

[0018] According to a possible implementation of the first embodiment, the measuring unit is configured to sum the count values ​​from a plurality of photodiodes to generate a single output.

[0019] This implementation adds the count values ​​from multiple photodiodes to produce a single output, allowing for improved sensitivity with a small pixel size by adding multiple count values.

[0020] According to the second aspect, the present application provides an image sensor in which the above pixel circuits are arranged in a two-dimensional lattice.

Brief Description of the Drawings

[0021] To more clearly explain the technical solutions in the embodiments, the following briefly describes the attached drawings necessary for explaining the embodiments of the present invention. Obviously, in the following description, the attached drawings only show some possible embodiments, and those skilled in the art can further derive other drawings from these attached drawings without creative effort.

[0022] [Figure 1] It is a diagram for explaining the operating principle of a conventional SPAD sensor. (a) shows an example of the cross-section of a SPAD, (b) shows the configuration of a pixel circuit of a SPAD sensor using the SPAD shown in (a), and (c) shows the relationship between the voltage and the count value at a specific position of the pixel circuit shown in (b).

[0023] [Figure 2A] In an example of a conventional image sensor, the relationship between illuminance and the count value is shown.

[0024] [Figure 2B] In an example of a conventional image sensor, the relationship between illuminance and the count value is shown.

[0025] [Figure 2C] In an example of a conventional image sensor, the relationship between illuminance and the count value is shown.

[0026] [Figure 2D] In an example of a conventional image sensor, the relationship between illuminance and the count value is shown.

[0027] [Figure 3] It is a diagram showing an example of the configuration of a sensor substrate of an image sensor according to an embodiment.

[0028] [Figure 4] This figure shows an example of the configuration of an image sensor circuit board.

[0029] [Figure 5] This figure shows the configuration of a pixel circuit according to one embodiment.

[0030] [Figure 6] Figure 5 is a timing diagram illustrating the signal output operation in the pixel circuit shown.

[0031] [Figure 7] This figure shows an example of the frame structure of a pixel signal.

[0032] [Figure 8] This figure shows an example of the offset period of a count gate.

[0033] [Figure 9] This figure shows the simulation results of the relationship between the number of photons and the count value.

[0034] [Figure 10] This diagram shows a conventional pixel circuit configuration.

[0035] [Figure 11] This is a timing diagram illustrating the signal output operation in the pixel circuit shown in Figure 10.

[0036] [Figure 12] Figure 10 is a diagram illustrating other signal output behaviors in the pixel circuit shown, where (a) is a timing diagram and (b) shows the relationship between illuminance and count value.

[0037] [Figure 13] This figure shows the simulation results of the SNR characteristics of an image sensor with respect to light intensity according to one embodiment.

[0038] [Figure 14] This figure shows the calculated power consumption of SPAD pixels.

[0039] [Figure 15] This figure shows the configuration of a pixel circuit according to one embodiment.

[0040] [Figure 16] This is a timing diagram to explain the signal output operation in a pixel circuit.

[0041] [Figure 17] This diagram shows the components of a single pixel circuit.

[0042] [Figure 18A] This figure shows an example of the pixel circuit configuration in mode (1).

[0043] [Figure 18B] This figure shows an example of the actual connection of the pixel circuit shown in Figure 18A.

[0044] [Figure 19A] This figure shows an example of the pixel circuit configuration in mode (2).

[0045] [Figure 19B] This figure shows an example of the actual connection of the pixel circuit shown in Figure 19A.

[0046] [Figure 20A] This figure shows an example of the pixel circuit configuration in mode (3).

[0047] [Figure 20B] This figure shows an example of the actual connection of the pixel circuit shown in Figure 20A.

[0048] [Figure 21] This figure shows the dynamic range of the image sensor in modes (1) to (3). [Modes for carrying out the invention]

[0049] To enable those skilled in the art to better understand the technical solutions of this disclosure, the following will clearly and completely describe the technical solutions in the embodiments of this disclosure with reference to the accompanying drawings in the mode of this disclosure. Obviously, the embodiments described are only a small part of, not all, of the embodiments of this disclosure. All other embodiments that can be obtained by those skilled in the art based on the embodiments of this disclosure without creative effort should be included within the scope of this disclosure.

[0050] First, referring to Figures 1 and 2A-D, we will explain the principle and operation control method of a typical SPAD-based image sensor (also called a "SPAD sensor").

[0051] Figure 1 illustrates the operating principle of a conventional SPAD sensor. In Figure 1, (a) shows an example of a cross-section of a SPAD, (b) shows the configuration of the pixel circuit of a SPAD sensor using the SPAD shown in (a), and (c) shows the relationship between voltage and count value at a specific position in the pixel circuit shown in (b).

[0052] The SPAD102 shown in Figure 1(a) has a P-type semiconductor layer (hereinafter referred to as "P-layer") 5 and an N-type semiconductor layer (hereinafter referred to as "N-layer") 1 joined together, and the N-layer 1 is surrounded by an N-type well layer 2. The pixel circuit shown in Figure 1(b) functions as a photocounter. The SPAD102 is connected to the counter 110 via an inverter 106. A line including a switch 104 for supplying a recharge signal is connected between the SPAD102 and the inverter 106. Here, the cathode potential of the SPAD102 is Vc, and the output potential of the inverter 106 is Vp.

[0053] A reverse bias voltage is applied to the SPAD102 by electrodes located above and below it, such that the potential of the N layer 1 is higher than the potential of the P layer 5. The reverse bias voltage applied to the SPAD is slightly higher than the breakdown voltage. When a photon 3 enters the P layer 5 from the bottom in Figure 1(a), it is absorbed by the P layer 5 and forms an electron 4 and a hole pair. This electron 4 is amplified by avalanche multiplication, lowering the voltage between the electrodes. When the voltage between the electrodes drops to the breakdown voltage, charge is released from the N layer 1. Then, when a recharge signal is supplied and the voltage rises, the pixel circuit returns to a state where it can detect photons (recharge operation).

[0054] As a result, as shown in Figure 1(c), when a photon 3 is incident on the SPAD, electrons are emitted from the N layer 1, causing the voltage Vc to decrease. Subsequently, the pixel circuit returns to its original potential due to the recharge signal. The output waveform of this voltage is output to the counter 110 as a waveform-shaped voltage Vp by the inverter 106, and the count value stored in the counter 110 is incremented.

[0055] Next, we will explain the relationship between illuminance and count value in conventional image sensor operation control methods.

[0056] Figure 2A shows the relationship between illuminance and count value in an example of a conventional image sensor. Typically, there is a proportional relationship between illuminance and count value. Therefore, to achieve a sufficiently wide dynamic range, the number of count bits per pixel should be increased. However, increasing the number of count bits increases the size of the pixel circuit and thus the pixel size. Furthermore, power consumption increases with increasing the number of count bits.

[0057] In the example shown in Figure 2B, the exposure time of the image sensor is interrupted to expand the dynamic range. The count value after the exposure interruption is then obtained by extrapolation. However, with this motion control method, if the subject changes during exposure, it is not possible to obtain an appropriate value by extrapolation. Also, when this motion control is performed, the pixel count is still high, and the pixel size is not reduced. As a result, power consumption is high, and electrical signals cannot be read out at high speed.

[0058] In the example shown in Figure 2C, multiple exposures are performed to increase the dynamic range by varying the exposure time. However, the pixel count remains high, and the pixel size cannot be reduced. As a result, power consumption is high, and electrical signals cannot be read out at high speed.

[0059] The example shown in Figure 2D illustrates the change in count value in an operation control method using a clustered multicycle clock recharge scheme. This method expands the dynamic range by shifting the recharge cycle to multiple different cycles. However, in this case, power consumption increases because the number of recharges increases. Also, the pixel count remains high, and the pixel size is not reduced. Furthermore, high-speed reading of electrical signals is not possible. In addition, the overall output becomes nonlinear because recharge signals of different periods are mixed in a single counter.

[0060] In the conventional motion control examples described above, the image sensor consumes a lot of power because of the large number of electron avalanches in the SPAD pixels. Also, the pixel size increases because of the large number of counter bits required per pixel.

[0061] Furthermore, because all count values ​​are output together in a single frame, it is not possible to obtain count value information quickly.

[0062] Furthermore, in methods of interrupting or changing the exposure time as shown in Figures 2B and 2C, the image will be damaged if the subject changes during the exposure time. Also, as shown in Figure 2D, when combining multiple different cycles with a single counter, the output value becomes non-linear because all count values ​​are mixed and output by a single counter.

[0063] This disclosure expands the dynamic range by controlling the signal input to the counter without modifying the recharge signal. This method allows for increased dynamic range while suppressing power consumption. It also allows for reduced pixel size and enables high-speed readout of electrical signals.

[0064] The specific embodiments of this disclosure will be described in detail below with reference to the drawings.

[0065] Figure 3 shows an example of the configuration of the sensor substrate of an image sensor according to this embodiment. The image sensor has a light-receiving section 304 of pixel circuits arranged in two dimensions on the sensor substrate 302.

[0066] Figure 4 shows an example of the configuration of an image sensor circuit board. The circuit board 400 has a logic array section 402 in which the logic sections 410 of the pixel circuit are arranged in a two-dimensional manner corresponding to the light receiving section 304. The logic array section 402 includes a vertical control section 404, a horizontal control section 406, and a signal processing section 408. These logic sections 410 are connected to the light receiving section 304 at their respective positions via signal lines. The circuit including the light receiving section 304 and the logic section 410 corresponding to the light receiving section functions as a pixel circuit that generates a pixel signal for one pixel in the image data.

[0067] The vertical control unit 404 receives a vertical synchronization signal, and the horizontal control unit 406 receives a horizontal synchronization signal. The logic array unit 402 receives an exposure control signal. The vertical control unit 404 and the horizontal control unit 406 control the logic unit 410 in synchronization with these signals.

[0068] The vertical control unit 404 sequentially selects rows in synchronization with the vertical synchronization signal. The logic unit 410 counts the number of photons during the exposure period and outputs a signal indicating the count value as a pixel signal. The horizontal control unit 406 synchronously selects columns in order to output a pixel signal in synchronization with the horizontal synchronization signal. The signal processing unit 408 performs predetermined signal processing, such as filtering, on the image data consisting of the pixel signals. The signal processing unit 408 outputs the processed image data. Embodiments of this disclosure are realized by supplying control signals from the vertical control unit 404 and the horizontal control unit 406 to the pixel circuit.

[0069] (First Embodiment)

[0070] A first embodiment of the present disclosure will be described with reference to Figure 5. The pixel circuit 500 shown in Figure 5 includes a SPAD 502, a measuring unit 510 that measures the amount of light corresponding to the current output from the cathode of the SPAD 502, and a gate unit 508 provided between the SPAD 502 and the measuring unit 510. The gate unit 508 has three switches. These switches function as gates for the measuring unit 510 and will be referred to as count gates in the following description. The measuring unit 510 has two-bit counters 510a, 510b, and 510c.

[0071] SPAD502 is connected to inverter 506. Count gates 508a, 508b, and 508c are provided between inverter 506 and counters 510a, 510b, and 510c, respectively. The on / off operation of count gates 508a, 508b, and 508c is controlled by count gate signals CNGa, CNGb, and CNGc, respectively, supplied from wiring (not shown).

[0072] Counters 510a to 510c are connected to output line 514. The count signal output to output line 514 is denoted as Vsig.

[0073] A recharge switch 504 is provided between the cathode of SPAD502 and the inverter 506 to supply a recharge signal RCG. The recharge signal RCG is supplied to the cathode side of SPAD502, setting the cathode side to a predetermined potential. The gate unit 508 connects SPAD502 and the measurement unit 510 so that the measurement unit 510 measures the amount of light at multiple points within one cycle of the recharge signal RCG. Here, the potential of the cathode of SPAD502 is V1, and the potential of the output of inverter 506 is V2. Also, the potentials of the inputs to counters 510a, 510b, and 510c are V3a, V3b, and V3c.

[0074] SPAD502 corresponds to the light receiving unit 304 in Figure 3, and the other components correspond to the logic unit 410 in Figure 4.

[0075] The signal output operation by the pixel circuit 500 is described below. The pixel voltage is reset at regular intervals by the recharge signal RCG. The reset results in a higher voltage V1. When a photon is incident on the SPAD 502, a charge is generated and the voltage V1 decreases. Voltage V1 is inverted by the inverter 506, and a signal of voltage V2 is output. Voltage V2 is sampled by count gates 508a to 508c and counted by separate counters 510a to 510c. Counters 510a to 510c are configured to output a signal Vsig containing the count value after the recharge signal RCG has been supplied multiple times. In this embodiment, the count value is output as the signal Vsig to the output line 514 for every three RCG pulses.

[0076] Figure 6 is a timing diagram illustrating the signal output operation in the pixel circuit shown in Figure 5. The recharge signal RCG is output at regular intervals at T0, T4, T7, T11, and T14. A count value is sampled every three cycles in which the recharge signal RCG is supplied, forming one subframe. Figure 6 shows the (m-1)th subframe and the mth subframe.

[0077] Figure 7 shows an example of the frame configuration of a pixel signal. In the embodiment shown in Figure 7, the main frame rate is set to 30 fps (frames per second), one main frame is 33 ms, and 1000 recharges are performed. Subframes are output every three recharge cycles, so one main frame contains 333 subframes. The frame rate of the subframes is 1000 fps. Therefore, changes in the subject can be detected at high speed by outputting each subframe.

[0078] In the i-th subframe, if the count values ​​of counters 510a, 510b, and 510c are Sub-ia, Sub-ib, and Sub-ic, respectively, then the count values ​​of the three counters in one frame can be expressed as follows:

number

[0079] Figure 8 shows an example of an offset cycle in a count gate. The gate unit 508 is configured to connect the SPAD 502 and the measurement unit 510 with the same period as the recharge signal RCG. The gate unit 508 is also configured to connect the SPAD 502 and the measurement unit 510 with a sampling phase different from that of the recharge signal RCG. There are three sampling phases in the count gate, and the sampling period is 33 μs, the same as the period of the recharge signal RCG. The sampling phase of the count gate signal CNGGa is immediately before the recharge signal RCG. The sampling phase of the count gate signal CNGb is delayed by 2 μs relative to the recharge signal RCG, and the sampling phase of the count gate signal CNGc is delayed by 100 ns relative to the recharge signal RCG. The sampling phase of the count gate can take any value. Therefore, the number of counters used for sampling and the number of count gates also change.

[0080] Returning to Figure 6, let's describe the output operation at times T0 to T16. The lightning bolt-shaped mark on the axis labeled "Photon" indicates the timing of a single photon incident on the pixel circuit. In the recharge signal RCG interval, intermediate intensity light is irradiated between T0 and T4, and two photons are incident from T3. Strong light is irradiated between T4 and T7, and five photons are incident from T5. Weak light is irradiated between T7 and T11, and one photon is incident at T10. No light is incident between T11 and T14.

[0081] The recharge signal RCG sets voltage V1 to high. When light is incident on SPAD502 at T3, T5, and T10, voltage V1 changes from high to low. Voltage V2 is the inverse of voltage V1.

[0082] The gate unit 508 is configured to connect the SPAD 502 to each of the counters 510a to 510c so that the counters 510a to 510c perform counting at different times.

[0083] More specifically, count gates 508a, 508b, and 508c are configured to connect SPAD502 to counters 510a, 510b, and 510c, respectively. The count gate signals CNGa to CNGc are pulse signals that have the same period as the recharge signal RCG, but with a different sampling phase than the recharge signal RCG. The ON operation of the count gates using the count gate signals starts at timings that are individually offset from the recharge signal RCG. For example, in the mth subframe, count gate 508a starts ON operation from T4, count gate 508b starts ON operation from T6, and count gate 508c starts ON operation from T5.

[0084] In the example shown in Figure 6, the count value outputs the signal Vsig for each pulse of the three recharge signals RCG. The count value information from counters 510a to 510c is output to output line 514 and accumulated in a total of 6 bits, Sub_frame_m-1. This information is contained in one subframe and output as the signal Vsig.

[0085] At T0, T4, T7, T11, and T14, the count gate signal CNGa is high, and voltage V3a is high. At T0, T4, T7, and T11, voltage V2 is high, and counter 510a performs counting operation. At T14, voltage V2 is low, and counter 510a does not perform counting operation. Therefore, the count value of counter 510a after three recharges is 3.

[0086] The count gate signal CNGb is high at T2, T6, T9, T13, and T16. At T2 and T6, voltage V2 is high. Voltage V3b becomes high, and counter 510b performs counting operation. At T9, T13, and T16, voltage V2 is low, and counter 510b does not perform counting operation. Therefore, the count value of counter 510a is 2 for the three recharge cycles.

[0087] The count gate signal CNGc is high at T1, T5, T8, T12, and T15. At T5, voltage V2 is high. Voltage V3c becomes high, and counter 510c performs counting operation. At T1, T8, and T15, voltage V2 is low, and counter 510c does not perform counting operation. Therefore, the count value of counter 510c is 1 for the three recharge cycles.

[0088] In the above operation, counter 510a counts all types of light: strong, medium, and weak. Counter 510b counts strong and medium light. Counter 510c counts only strong light. Therefore, each counter can measure light of different intensities.

[0089] Figure 9 shows the simulation results of the relationship between the number of photons and the count value. Ni is the average number of input photons per frame. In the three curves, Nout1 shows the count number due to the count gate signal CNGc, Nout2 shows the count number due to the count gate signal CNGb, and Nout3 shows the count number due to the count gate signal CNGa. According to the above method of controlling the operation of the pixel circuit, a different frame is generated for each sampling phase, so an output that is almost linear in response to the amount of light can be obtained. The final generated main frame is obtained by combining the main frames from each sampling phase.

[0090] In the configuration shown in Figure 5, if the recharge pulse of the recharge signal RCG records the count value three times, a 2-bit counter is required for each pixel in each sampling phase of the count gate. Thus, because the number of bits is sufficiently small compared to conventional counters, the size of the pixels can be reduced. The number of pulses recorded in the counter can be any number, for example, it can take any value from 1 to 1000. The count also changes according to the number of pulses.

[0091] Here, an embodiment of the present invention will be described in comparison with the prior art with reference to Figures 10 and 11.

[0092] Figure 10 shows the configuration of a conventional pixel circuit. SPAD1002 is connected to counter 1010 via inverter 1006. A line including a recharge switch 1004 for supplying a recharge signal RCG is connected between SPAD1002 and inverter 1006. Here, the cathode potential of SPAD1002 is denoted as V1, and the output potential of inverter 1006 is denoted as V2.

[0093] Figure 11 is a timing diagram illustrating the signal output operation in the pixel circuit shown in Figure 10. The operation of the pixel circuit from time T0 to time T6 will be described.

[0094] The recharge signal RCG is output at regular intervals at T0, T2, T4, and T6. The recharge signal RCG sets voltage V1 to High. At T1, T3, and T5, when light is incident on SPAD1002, voltage V1 changes from High to Low. Voltage V2 is output as the inverse value of voltage V1.

[0095] The recharge signal RCG interval is as follows: between T0 and T2, intermediate light is irradiated, and two photons are incident from T1. Between T2 and T4, strong light is irradiated, and five photons are incident from T3. Between T4 and T6, weak light is irradiated, and one photon is incident at T5. The count value is counted at T1, T3, and T5. The number of resets is limited by the recharge signal RCG, so the power consumption for resetting does not increase. However, in one cycle, the count value only increases by 1 regardless of the light intensity, so the dynamic range of the image sensor cannot be expanded.

[0096] Figure 12 is a timing diagram illustrating an alternative output operation of the pixel signal in the conventional pixel circuit shown in Figure 10. The operation of the pixel circuit from time T0 to time T19 will be described.

[0097] Figure 12(a) shows an example of a method for controlling the operation of a pixel circuit using a conventional multi-cycle clock charge. The recharge signal RCG is normally in the off state, and signals T0, T5, T11, T15, and T18 form the first pulse with a fixed period. Signals T1, T7, T12, T16, and T19 constitute the second pulse, offset by a fixed period from T0. Signals T3, T9, T13, T17, and T20 constitute the third pulse, offset by a fixed period from T0. Since the counter 1010 performs counting operations on the rising edge of voltage V2, it performs counting operations at T2, T4, T6, T8, T10, and T14. In the example shown in Figure 12(a), the dynamic range can be expanded by performing recharge operations by combining offset values ​​of different cycles. However, in the example shown in Figure 12(a), the number of recharges increases, resulting in higher power consumption compared to this embodiment. Furthermore, because all count values ​​are mixed and output by a single counter, the output becomes nonlinear, as shown in Figure 12(b), making high-speed detection impossible when the subject changes.

[0098] In contrast, the image sensor using the pixel circuit of the embodiment of the present invention shown in Figure 9 can obtain a wide dynamic range of 120 dB from a count value of 1 to the maximum saturation amount. The count values ​​of each sampling phase counted by counters 510a, 510b, and 510c are output separately, and by combining these, a single linear output characteristic can be obtained as a whole.

[0099] Figure 13 shows the simulation results of the SNR (Signal-to-Noise Ratio) characteristics of the image sensor with respect to light intensity according to an embodiment of the present invention. Here, SNR1 is the SNR of the output of counter 510c, SNR2 is the SNR of the output of counter 510b, and SNR3 is the SNR of the output of counter 510a. As shown in Figure 13, a sufficient SNR up to 28 dB is obtained by on / off control of each phase in the count gate signals CNGa~CNGc.

[0100] Figure 14 shows the power consumed by resetting a SPAD pixel with 12M pixels at a frame rate of 30fps. In Figure 14, the horizontal axis represents the number of electrons generated at one time (Qpix), and the vertical axis represents power consumption (W). The SPAD pixel consumes power each time it is reset. Power was calculated for the following three cases: 1000 resets per second (1000ct), 2000 resets per second (2000ct), and 3000 resets per second (3000ct). In the 1000ct curve, it can be seen that the power is kept below 2000mW over light intensities from 4000 to 12000(e).

[0101] As described above, according to the embodiments of the present invention, it is possible to provide an image sensor that can detect rapidly changing subjects, has low power consumption, a small pixel size, and a wide dynamic range. This image sensor can also be applied to noise-free night vision imaging.

[0102] Furthermore, by adding a mechanism to change the sampling phase of the photoelectric conversion signal for each counter, the dynamic range can be expanded without increasing the power consumption required for recharging.

[0103] Furthermore, by counting the photoelectric conversion signal with a separate counter for each sampling phase, a linear output can be obtained for each light intensity.

[0104] Furthermore, by outputting count values ​​multiple times per frame, changes in the subject can be detected at high speed, and the number of counter bits required per pixel can be reduced.

[0105] Furthermore, by outputting short subframes at high speed, the pixel circuit can be simplified, and the pixel size can be reduced.

[0106] (Second Embodiment)

[0107] Next, a second embodiment of the present invention will be described with reference to Figure 15. Figure 15 is a diagram showing the configuration of a pixel circuit 1500 according to one embodiment. SPAD 502 is connected to inverter 506. A line including a count gate 1508, which is a gate unit, is connected between inverter 506 and 4-bit counter 1510. The count gate signal that controls the count gate 1508 is denoted as CNG. Here, the cathode potential of SPAD 1502 is V1, and the output potential of inverter 506 is V2. Also, the input potential of counter 1510 is V3.

[0108] Counter 1510 is a measuring unit connected to output line 1514. The count signal output to output line 1514 is denoted as Vsig.

[0109] Figure 16 is a timing diagram illustrating the output operation of the pixel circuit 1500. The operation of the pixel circuit from time T0 to T18 will be described.

[0110] The recharge signal RCG is output at a fixed period at T0, T5, T9, T13, and T16. The count gate signal CNG is normally an off signal and is a combination of pulse signals with different sampling phases at the same period as the recharge signal RCG. That is, the count gate signal CNG constitutes a first pulse at a fixed period at signals T0, T5, T9, T13, and T16. The signals T1, T7, T10, T14, and T17 constitute a second pulse offset by a fixed period from T0. The signals T4, T8, T11, T15, and T18 constitute a third pulse offset by a fixed period from T0. Similar to the first embodiment, there are three counting phases, and one subframe is output after three resets. The counter 1510 performs counting operation if the count gate signal CNG is high when the count gate 1508 is on, i.e., when the voltage V2 is high. Therefore, the counting operation is performed at the rising time of V3, i.e., T4, T5, T7, T8, T9, and T13.

[0111] In this embodiment, the number of bits required for one pixel in the counter is 4 bits. Therefore, the number of bits in the multiple counters in the first embodiment may be less than the total number of bits.

[0112] (Third embodiment)

[0113] Next, a third embodiment of the present disclosure, which combines multiple pixel circuits, will be described.

[0114] Figure 17 shows the components of one pixel circuit according to an embodiment of the present invention. The pixel circuit 1700 includes a SPAD 1702, a recharge switch 1704 that controls the supply of a recharge signal RCG, a voltage control gate 1708, an inverter 1706, an OR circuit 1709, and a counter 1710. The voltage control gate 1708 is configured to control the input voltage of the inverter 1706. In this embodiment, a count gate 1711 functions as the gate unit and a counter 1710 functions as the measurement unit. In the following description, the counter will be counted as having 2 bits.

[0115] The OR circuit 1709 and counter 1710 may be shared with other pixel circuits. This allows the connection point between the inverter 1706 and the OR circuit 1709 to be adaptively changed. Furthermore, when the OR circuit 1709 and counter 1710 are shared, it is not necessary to use the OR circuits and counters included in other pixel circuits.

[0116] This embodiment describes an example of the configuration of a pixel circuit in a 2x2 pixel set. The following readout modes can be provided for a 2x2 pixel set. (1) 2x2 binning mode that merges 4 pixels, (2) 2x1 binning mode that integrates 2 pixels, (3) Full mode, which reads one pixel at a time. In the following description, the configuration of the pixel circuit follows the first embodiment.

[0117] Binning mode is a mode that improves sensitivity by integrating the charges of multiple pixels and outputting them as a single pixel. In the following embodiment, multiple counters are connected in parallel, and the measurement unit is configured to add the count values ​​from multiple photodiodes.

[0118] Figure 18A shows an example of the configuration of a pixel circuit in mode (1). Figure 18B also shows an example of the actual connection of the pixel circuit shown in Figure 18A. Pixel circuit 1801 includes a first pixel circuit 1800 with SPAD 1802a, a recharge switch 1804a, a count gate 1808a, an inverter 1806a, an OR circuit 1809a, and a counter 1810a. Similarly, the second pixel circuit has SPAD 1802b, a recharge switch 1804b, a count gate 1808b, an inverter 1806b, an OR circuit 1809b, and a counter 1810b. The third pixel circuit has SPAD 1802c, a recharge switch 1804c, a count gate 1808c, an inverter 1806c, an OR circuit 1809c, and a counter 1810c. Furthermore, the fourth pixel circuit includes SPAD1802d, recharge switch1804d, count gate1808d, inverter1806d, OR circuit1809d, and counter1810d.

[0119] The inverter 1806a of the first pixel circuit and the inverter 1806b of the second pixel circuit are connected to the OR circuit 1809b. The inverter 1806c of the third pixel circuit and the inverter 1806d of the fourth pixel circuit are connected to the OR circuit 1809d. Furthermore, the outputs of the OR circuits 1809b and 1809d are connected to the OR circuit 1809a.

[0120] OR gate 1809a is connected in parallel to counters 1810a, 1810b, and 1810c. Note that OR gate 1809c and counter 1810d are not used in this example.

[0121] In Figure 18B, the pixel circuit 1801 has a two-layer structure consisting of a first layer including SPADs 1802a to 1802d and a second layer including counters 1810a to 1810d. The first layer corresponds to the sensor board 302 shown in Figure 3, and the second layer corresponds to the circuit board 400 shown in Figure 4. In this example, as in the first embodiment, three pulses of the count gate signal CNG are supplied for one recharge signal RCG. As described above, the number of bits in the counter according to this embodiment is 2 bits for counting. Since the three counters are connected in parallel, the total number of bits for counting is 6 bits. For example, counter 1810a may be configured to output the upper 2 bits of the count value 2 × 2out1, counter 1810b may output the middle 2 bits of the count value 2 × 2out2, and counter 1810c may be configured to output the lower 2 bits of the count value 2 × 2out3. The four pixel signals are added together to produce one output.

[0122] Figure 19A shows an example configuration of mode (2). Figure 19B also shows an example of the actual connection of the pixel circuit shown in Figure 19A. In pixel circuit 1901, the first pixel circuit has SPAD 1902a, recharge switch 1904a, count gate 1908a, inverter 1906a, OR circuit 1909a, and counter 1910a. Similarly, the second pixel circuit has SPAD 1902b, recharge switch 1904b, count gate 1908b, inverter 1906b, OR circuit 1909b, and counter 1910b. The third pixel circuit has SPAD 1902c, recharge switch 1904c, count gate 1908c, inverter 1906c, OR circuit 1909c, and counter 1910c. Furthermore, the fourth pixel circuit includes SPAD1902d, recharge switch1904d, count gate1908d, inverter1906d, OR circuit1909d, and counter1910d.

[0123] The inverter 1906a of the first pixel circuit and the inverter 1906b of the second pixel circuit are connected to the OR gate 1909b. The OR gate 1909b is connected in parallel to the count gates 1908a and 1908b. The count gate 1908a is connected to the counter 1910a, which outputs the pixel signal L_out1. The count gate 1908b is connected to the counter 1910b, which outputs the pixel signal L_out2. For example, L_out1 can be the signal of the upper 2 bits of the count value, and L_out2 can be the signal of the lower 2 bits of the count value. In addition, the inverter 1906c of the third pixel circuit and the inverter 1906d of the fourth pixel circuit are connected to the OR gate 1909d. The OR gate 1909d is connected in parallel to the count gates 1908c and 1908d. The count gate 1908c is connected to the counter 1910c, which outputs the pixel signal R_out1. The count gate 1908d is connected to the counter 1910d, which outputs the pixel signal R_out2. For example, R_out1 could be the signal of the upper 2 bits of the count value, and R_out2 could be the signal of the lower 2 bits of the count value. OR gates 1909a and 1909c are not used in this example.

[0124] In Figure 19B, the pixel circuit 1901 has a two-layer structure consisting of a first layer including SPADs 1902a to 1902d and a second layer including counters 1910a to 1910d. In this example, the count gate signal CNG pulse is twice that of the recharge signal RCG. The counter count bits total 4 bits. The two pixel signals are added together to produce a single output.

[0125] Figure 20A shows an example configuration of mode (3). Figure 20B also shows an example of the actual connection of the pixel circuit shown in Figure 20A. In pixel circuit 2001, the first pixel circuit has SPAD2002a, recharge switch 2004a, count gate 2008a, inverter 2006a, OR circuit 2009a, and counter 2010a. Similarly, the second pixel circuit has SPAD2002b, recharge switch 2004b, count gate 2008b, inverter 2006b, OR circuit 2009b, and counter 2010b. The third pixel circuit has SPAD2002c, recharge switch 2004c, count gate 2008c, inverter 2006c, OR circuit 2009c, and counter 2010c. The fourth pixel circuit also includes SPAD2002d, recharge switch2004d, count gate2008d, inverter2006d, OR circuit2009d, and counter2010d.

[0126] In this example, the four OR gates 2009a to 2009d are not used. Therefore, inverters 2006a to 2006d are connected to counters 2010a to 2010d, respectively.

[0127] In Figure 20B, the pixel circuit 2001 has a two-layer structure consisting of a first layer including SPAD2002a to 2002d and a second layer including counters 2010a to 2010d. In this example, there is one pulse of the count gate signal CNG for one recharge signal RCG, and the counter has 2 bits.

[0128] Figure 21 shows the dynamic range of an image sensor using a pixel circuit for modes (1) to (3). In mode (1), three count gate signals CNG are output for one recharge signal RCG. Therefore, the dynamic range extends until all three curves in Figure 21 reach their maximum saturation level, i.e., 120 dB. In mode (2), the number of count gate signals CNG is doubled for one recharge signal RCG. Therefore, the dynamic range is the width until both curves in Figure 21 reach their maximum saturation level, i.e., approximately 95 dB. In mode (3), the count gate signal CNG is output once for each recharge signal RCG. Therefore, the dynamic range is the width until one curve in Figure 21 reaches its maximum saturation level, i.e., approximately 70 dB.

[0129] As described above, according to this embodiment, multiple binning modes can be created by switching the connections of the circuit elements included in the pixel circuit. This allows for free switching of sensitivity and resolution according to the shooting conditions.

[0130] The pixel circuit according to the above embodiment can constitute an image sensor arranged in a two-dimensional grid.

[0131] Furthermore, the pixel circuit and image sensor described in the above-mentioned embodiments can be applied to imaging devices mounted in various devices such as digital cameras, mobile phones, and in-vehicle cameras.

[0132] The foregoing description merely illustrates a specific method of implementing the present invention and is not intended to limit the scope of protection of the present invention. Any modifications or substitutions that can be readily conceived by those skilled in the art, within the scope of the technical scope disclosed herein, should be included within the scope of protection of the present invention. Accordingly, the scope of protection of the present invention should be subject to the scope of protection of the claims.

Claims

1. It is a pixel circuit, Photodiode and A measuring unit that measures the amount of light corresponding to the current output from one end of the photodiode, A gate portion is provided between the photodiode and the measuring unit, Includes, A recharge signal is supplied to set one end of the photodiode to a predetermined potential. The gate portion is a pixel circuit that connects the photodiode and the measuring unit so that the measuring unit measures the amount of light at multiple points in time within one cycle of the recharge signal.

2. The pixel circuit according to claim 1, wherein the gate portion is configured to connect the photodiode and the measurement portion with the same period as the period of the recharge signal.

3. The pixel circuit according to claim 1, wherein the gate portion is configured to connect the photodiode and the measurement portion in a sampling phase different from that of the recharge signal.

4. The pixel circuit according to claim 1, wherein the measuring unit includes a plurality of counters, and the gate unit is configured to connect the photodiode to each of the plurality of counters such that the plurality of counters perform counting operations at different times.

5. The pixel circuit according to claim 4, wherein the gate portion includes a plurality of switches, each of which is configured to connect the photodiode to one of the plurality of counters.

6. The pixel circuit according to claim 4, wherein the counter is configured to output a count value after the recharge signal has been supplied multiple times.

7. The pixel circuit according to claim 1, wherein the measurement unit is configured to generate a single output by adding count values ​​from a plurality of photodiodes.

8. An image sensor in which the pixel circuits according to any one of claims 1 to 7 are arranged in a two-dimensional grid.

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