Full wafer measurement based on a trained full wafer measurement model
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KLA CORP
- Filing Date
- 2024-03-26
- Publication Date
- 2026-06-02
AI Technical Summary
Current measurement techniques for semiconductor structures face challenges due to high resolution demands, multiple parameter correlations, increasing geometric complexity, and the use of opaque materials, leading to limited measurement accuracy and increased costs, with existing methods failing to utilize wafer-level process information effectively.
A whole-wafer measurement model is trained using Design of Experiments (DOE) data across an entire wafer, incorporating process behavior information to reduce parameter correlations and improve measurement robustness and accuracy by estimating parameter values at each measurement site.
The whole-wafer measurement model enhances measurement performance and robustness by reducing parameter correlations and dimensionality, enabling accurate estimation of parameters across the entire wafer surface.
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