Memory and storage devices

Abstract

A memory and storage device, wherein the memory comprises a plurality of memory cells arranged in an array and a set circuit, the plurality of storage cells are configured such that when a memory cell is selected, the data stored in the memory cell is read from a bit line to a first data bus, the set circuit is connected to the first data bus and receives a set signal, and when the memory is in a first mode, it is configured to conduct the first data bus based on the set signal and output a first data bit, and when the memory is in a second mode, it is configured to block the first data bus based on the set signal and output a predetermined data bit, the first mode being a normal read mode and the second mode being a duty cycle training mode. In this way, the first data bus can be selectively conducted or blocked in different operating modes of the memory to output the corresponding data, and the memory area can be saved by sharing the first data bus.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with an application number of 202410546174.1 and an invention title of "Memory and Storage Device", which was filed with the Chinese Patent Office on April 30, 2024, and all of its content is incorporated herein by reference.

[0002] This application relates to the field of semiconductor technology, and particularly to memory and storage devices.

Background Art

[0003] In the semiconductor industry, the clock signal of a memory chip such as DRAM (Dynamic Random Access Memory) is usually provided by an external control chip. During the process of generating, transmitting, and processing the clock signal inside the DRAM, a duty - cycle deviation may occur.

[0004] In order to correct the duty - cycle deviation of the above - mentioned clock signal, in related technologies, a duty - cycle adjustment circuit has been proposed, and this duty - cycle adjustment circuit can be used to correct the duty - cycle deviation of the above - mentioned clock signal.

Summary of the Invention

[0005] Embodiments of the present disclosure provide a memory and a storage device.

[0006] According to some embodiments of the present disclosure, a first embodiment of the embodiments of the present disclosure provides a memory comprising a plurality of memory cells arranged in an array and a set circuit, wherein the plurality of memory cells are configured such that when a memory cell is selected, data stored in the memory cell is read from a bit line to a first data bus, the set circuit is connected to the first data bus and receives a set signal, and is configured to conduct the first data bus and output a first data bit based on the set signal when the memory is in a first mode, and to block the first data bus and output a predetermined data bit based on the set signal when the memory is in a second mode, the first mode being a normal read mode and the second mode being a duty cycle training mode.

[0007] In some embodiments, the set circuit includes a setter, the set signal includes a first set signal and a second set signal, the input terminal of the setter is connected to the first data bus, the first set terminal receives the first set signal, and the second set terminal receives the second set signal, in the first mode the levels of the first set signal and the second set signal are different, and in the second mode the levels of the first set signal and the second set signal are the same.

[0008] In some embodiments, the memory further includes a decoding circuit configured to receive the register code of a mode register and generate the set signal by decoding.

[0009] In some embodiments, the memory further includes a latch circuit connected to the decoding circuit, which is configured to receive a mode register write signal, output a set signal if the mode register write signal is valid, and latch the set signal if the mode register write signal is invalid.

[0010] In some embodiments, the memory further comprises N parallel-to-serial converters, each of which is connected to correspond to M set circuits, receives data bits output from the M set circuits, samples the data bits based on a first clock signal, and generates second data by logic processing, each of which second data includes M bits of serial data, where N and M are even.

[0011] In some embodiments, the clock period of the first clock signal is M times the clock period of the system clock signal, and in each of the parallel-to-serial conversion circuits, the effective pulse periods of the first clock signal received by the M set circuits do not overlap with each other.

[0012] In some embodiments, when the memory is in the second mode, the serial levels of the M bits in each of the second data are the same, and N is equal to the number of bits in a given data pattern.

[0013] In some embodiments, the parallel-to-serial converter is configured to further receive a first write signal, and if the first write signal is valid, the parallel-to-serial converter is configured to trigger the generation of the second data.

[0014] In some embodiments, the memory further comprises N selection circuits, each of which is configured to be connected to two of the parallel-to-serial converters to receive the corresponding second data, wherein when the memory is in the first mode, the second data output by the N / 2 selection circuits in odd mode is the same as the second data output by the other N / 2 selection circuits in even mode, and when the memory is in the second mode, the second data output by the N / 2 selection circuits in odd mode is different from the second data output by the other N / 2 selection circuits in even mode, wherein the two parallel-to-serial converters connected to each of the N / 2 selection circuits are the same as the two parallel-to-serial converters connected to the corresponding selection circuit of the other N / 2 selection circuits.

[0015] In some embodiments, the selection circuits are configured such that when the memory is in the first mode, the second data output by the first N / 2 selection circuits in odd mode is the same as the second data output by the last N / 2 selection circuits in even mode, and when the memory is in the second mode, the second data output by the first N / 2 selection circuits in odd mode is different from the second data output by the last N / 2 selection circuits in even mode, and the two parallel-to-serial converters connected to each of the first N / 2 selection circuits are the same as the two parallel-to-serial converters connected to the corresponding selection circuit of the last N / 2 selection circuits.

[0016] In some embodiments, the N selection circuits further receive a second clock signal and output two third data by sampling, each of which the third data includes N / 2 parallel second data, wherein in odd mode, the second clock signal received by N / 2 selection circuits precedes the second clock signal received by the other N / 2 selection circuits by half a clock period, and in even mode, the second clock signal received by N / 2 selection circuits lags behind the second clock signal received by the other N / 2 selection circuits by half a clock period.

[0017] In some embodiments, the second clock signal includes a second odd clock signal and a second even clock signal, the clock periods of the second odd clock signal and the second even clock signal are the same, and at the same time only one of the second odd clock signal and the second even clock signal is active, the odd mode corresponds to the second odd clock signal being active, the even mode corresponds to the second even clock signal being active, in the odd mode, N / 2 of the selectors sample based on the second odd clock signal and the other N / 2 of the selectors sample based on the second odd clock delay signal, in the even mode, N / 2 of the selectors sample based on the second even clock delay signal and the other N / 2 of the selectors sample based on the second even clock signal, the second odd clock delay signal is delayed by half a clock period from the second odd clock signal, and the second even clock delay signal is delayed by half a clock period from the second even clock signal.

[0018] In some embodiments, the selection circuit includes an odd selection circuit and an even selection circuit, the odd selection circuit includes an odd sampling circuit connected to one of the parallel-to-serial converters to receive a first second data, the even selection circuit includes a selector and an even sampling circuit, connected to two of the parallel-to-serial converters, one end of the selector receives the first second data, the other end of the selector receives a second second data, the control end of the selector receives a first selection signal, in the odd mode the odd selection circuit receives the first second data and samples based on the second odd clock signal, and in the even mode the first selection signal is first level In the case of a certain state, the selector outputs the first second data; if the first selection signal is at a second level, the selector outputs the second second data, and the even sampling circuit samples based on the second even clock delay signal; or, in the odd mode, the odd selection circuit receives the first second data and samples based on the second odd clock delay signal; and in the even mode, if the first selection signal is at a first level, the selector outputs the first second data; if the first selection signal is at a second level, the selector outputs the second second data, and the even sampling circuit is configured to sample based on the second even clock signal.

[0019] In some embodiments, the memory further comprises an output module connected to N selection circuits and configured to receive the third data and output a fourth data to an input / output interface, wherein the fourth data includes N × M bits of serial data bits.

[0020] According to some embodiments of the present disclosure, a second embodiment of the embodiments of the present disclosure further provides a storage device comprising a memory as described in any of the first embodiments and a controller, the controller being coupled to the memory and configured to cause the storage device to perform the following operations: the operations being sending a command to the memory via the controller, the command including a normal read command or a duty cycle training mode command, the memory reading data based on the command received, and, if the command is a duty cycle training mode command, the storage device comparing the data received via the controller with predetermined data to determine and adjust the duty cycle of a system clock signal.

[0021] Embodiments of this disclosure provide a memory and a storage device, the memory comprising a plurality of memory cells arranged in an array and a set circuit, wherein the plurality of storage cells are configured such that when a memory cell is selected, the data stored in the memory cell is read from a bit line to a first data bus, the set circuit is connected to the first data bus and receives a set signal, and when the memory is in a first mode, it is configured to conduct the first data bus based on the set signal and output a first data bit, and when the memory is in a second mode, it is configured to shut off the first data bus based on the set signal and output a predetermined data bit, the first mode being a normal read mode and the second mode being a duty cycle training mode. By providing a set circuit to the first data bus in this way, the first data bus can be selectively conducted or shut off in different operating modes of the memory to output the corresponding data, and the memory area can be saved by sharing the first data bus. Furthermore, after the memory switches from the normal read mode to the duty cycle training mode, the first data bus is shut off and the data in the normal read mode is no longer switched, so power consumption is greatly reduced. [Brief explanation of the drawing]

[0022] [Figure 1] A schematic diagram showing the configuration of a memory according to an embodiment of the present disclosure. [Figure 2] A schematic diagram showing the configuration of a set circuit according to an embodiment of the present disclosure. [Figure 3] A schematic diagram showing another configuration of a memory according to an embodiment of the present disclosure. [Figure 4] A schematic diagram showing the configuration of a decoding circuit according to an embodiment of the present disclosure. [Figure 5] A schematic diagram showing another configuration of a memory according to an embodiment of the present disclosure. [Figure 6] A schematic diagram showing the configuration of a latch circuit according to an embodiment of the present disclosure. [Figure 7] A schematic diagram showing another configuration of a memory according to an embodiment of the present disclosure. [Figure 8] A schematic diagram showing the configuration of a parallel-serial conversion circuit according to an embodiment of the present disclosure. [Figure 9] An exemplary timing chart corresponding to the parallel-serial conversion circuit according to an embodiment of the present disclosure. [Figure 10] A schematic diagram showing the configuration of a first write signal generation circuit according to an embodiment of the present disclosure. [Figure 11] A schematic diagram showing another configuration of a memory according to an embodiment of the present disclosure. [Figure 12] A schematic diagram showing another configuration of a memory according to an embodiment of the present disclosure. [Figure 13] A schematic diagram showing the configuration of a selection circuit according to an embodiment of the present disclosure. [Figure 14] An exemplary timing chart 1 corresponding to the selection circuit according to an embodiment of the present disclosure. [Figure 15] An exemplary timing chart 2 corresponding to the selection circuit according to an embodiment of the present disclosure. [Figure 16] A schematic diagram showing the configuration of a storage device according to an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0023] One or more embodiments are illustrated by corresponding drawings, but these illustrative descriptions are not limiting to the embodiments, elements with the same reference numeral in the drawings represent similar elements, and unless otherwise specified, the drawings do not constitute a limitation of scale. To better illustrate the embodiments of this disclosure or technical solutions in the prior art, the drawings used in the embodiments are briefly introduced above. Clearly, the drawings described above represent only a few embodiments of this disclosure, and based on these drawings, those skilled in the art can obtain other drawings without creative effort.

[0024] To further clarify the objectives, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the drawings of the embodiments of this disclosure. Obviously, the embodiments described are part of, but not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art without creative work based on the embodiments of this disclosure are included within the scope of protection of this disclosure. Furthermore, although this disclosure describes the disclosures according to one or more exemplary embodiments, it should be understood that each aspect of these disclosures can also independently constitute a complete embodiment.

[0025] The brief explanations of terms used in this disclosure are solely for the purpose of facilitating the understanding of the embodiments described below and are not intended to limit the embodiments of this disclosure. Unless otherwise specified, these terms should be understood according to their general and ordinary meanings.

[0026] The terms “First,” “Second,” and so on in the specification, claims, and drawings of this disclosure are not intended to limit any particular order or sequence, but rather to distinguish similar subjects. It should be understood that the terms used herein are interchangeable where appropriate, and that, for example, the embodiments may be carried out in an order other than that shown in the illustrations or descriptions of the embodiments of this disclosure.

[0027] Furthermore, the terms “includes,” “has,” and any variations thereof are intended to encompass non-exclusive inclusion, for example, a product or device containing a set of components does not have to be limited to the components explicitly listed, and may include other components not explicitly listed or specific to those products or devices.

[0028] As used in this disclosure, the term “module” means known or subsequently developed hardware, software, firmware, artificial intelligence, phage logic, or combination of hardware and / or software code that can perform functions related to such elements.

[0029] Typically, a storage device includes a controller and memory. In some embodiments of this disclosure, the memory may be dynamic random access memory (DRAM), such as low-power double data rate (LPDDR) DRAM. The controller and memory communicate via several buses. For example, the memory receives commands and addresses on a command / address bus and provides data between the controller and the memory via a data bus.

[0030] Furthermore, various clock signals can be provided between the controller and memory via the clock bus. A clock signal is active when it periodically transitions between low and high clock levels. Conversely, a clock signal is inactive when it maintains a constant clock level and does not transition periodically.

[0031] Here, the clock bus may include signal lines, which are used to provide system clock signals CK_t and CK_c received by the memory, data clock signals WCK_t and WCK_c received by the memory, and access data clock signals RDQS_t and RDQS_c provided by the memory to the controller.

[0032] For a write command, when the memory is ready to receive write data from the controller, the controller provides the memory with WCK_t and WCK_c clock signals. The WCK_t and WCK_c clock signals may be used by the clock signal memory to generate an internal clock signal, which is used to time the operation of the circuit to receive the write data. The data is provided by the controller, and the memory receives the write data based on the WCK_t and WCK_c clock signals, and the write data is written to the memory corresponding to the memory address.

[0033] For a read command, when memory is ready to provide read data to the controller, the controller provides memory with WCK_t and WCK_c clock signals. The WCK_t and WCK_c clock signals may be used by memory to generate access data clock signals RDQS_t and RDQS_c. The RDQS_t and RDQS_c clock signals are provided from memory performing the read operation to the controller and are used to time the provision of read data to the controller. The controller can receive the read data using the RDQS_t and RDQS_c clock signals.

[0034] A clock signal has a duty cycle, which is the percentage of time the signal is active within one period of a binary periodic signal. For example, a clock signal can alternate between a logical high level (e.g., a high voltage level) and a logical low level (e.g., a low voltage level). A storage device can adjust the duty cycle of a clock signal to ensure that the clock signal matches a desired duty cycle (e.g., 50%).

[0035] The clock signal for DRAM is typically provided by an external controller, and duty cycle deviations can occur during the generation, transmission, and processing of this clock signal within the DRAM. To compensate for duty cycle deviations in the DRAM's internal clock signal, conventional technology has proposed a Duty Cycle Adjuster (DCA) circuit. The controller can use a DCA mode register to adjust the duty cycle of the DQ and DQS signals within the DRAM, thereby compensating for alignment problems of the DQ and DQS signals. Generally, adjusting the clock signal affects the DQ output, thereby ensuring that correct data is output.

[0036] The internal clock of a DRAM can be divided into two-phase and four-phase clocks. Taking the four-phase clock as an example, it can be divided into the first phase clock ICLK (0°), the second phase clock QCLK (90°), the third phase clock IBCLK (180°), and the fourth phase clock QBCLK (270°). The DCA circuit for a four-phase clock generally uses ICLK as a reference and adjusts the remaining three clock signals.

[0037] For controllers, it is necessary to identify ICLK and IBCLK in order to control the memory duty cycle adjustment. Therefore, the DRAM industry standard proposes DCA training assist mode I for two-phase clocks, which helps the controller identify whether the initial burst length (BL) is aligned with ICLK or IBCLK, i.e., which clock was sampled at. In DCA training assist mode II for four-phase clocks, the DRAM generates a data pattern internally and sends the data back to the controller. The controller determines whether the data pattern output by the DRAM starts with the first bit or the third bit by comparing it with a predetermined data pattern. If it starts with the first bit, the first bit of the output data was sampled at ICLK; if it starts with the third bit, the first bit of the output data was sampled at IBCLK. This allows the controller to identify ICLK and IBCLK and properly align the four-phase clocks.

[0038] Embodiments of the present disclosure provide a memory comprising a plurality of memory cells arranged in an array and a set circuit, wherein the plurality of memory cells are configured such that when a memory cell is selected, the data stored in the memory cell is read from a bit line to a first data bus, the set circuit is connected to the first data bus and receives a set signal, and when the memory is in a first mode, it conducts the first data bus based on the set signal to output a first data bit, and when the memory is in a second mode, it disconnects the first data bus based on the set signal to output a predetermined data bit, the first mode being a normal read mode and the second mode being a duty cycle training mode. By arranging the set circuit on the first data bus in this way, the first data bus can be selectively conducted or disconnected in different operating modes of the memory to output the corresponding data, and the memory area can be saved by sharing the first data bus. Furthermore, after the memory switches from the normal read mode to the duty cycle training mode, the first data bus is disconnected and the data in the normal read mode is no longer switched, so power consumption is greatly reduced.

[0039] The embodiments of this disclosure will be described in detail below with reference to the drawings. Those skilled in the art will understand that many technical details are provided in each embodiment of this disclosure to help the reader better understand the disclosure. However, the technical solutions for which this disclosure seeks protection can be achieved without these technical details or the various changes and modifications based on the embodiments below.

[0040] In one embodiment of the present disclosure, referring to Figure 1, Figure 1 is a schematic diagram showing the configuration of a memory according to an embodiment of the present disclosure. As shown in Figure 1, the memory comprises a plurality of memory cells arranged in an array and a set circuit 100, wherein when a memory cell is selected, the data stored in the memory cell is read from the bit line to a first data bus Abus, the set circuit 100 is connected to the first data bus Abus and receives a set signal, and when the memory is in a first mode, it is configured to conduct the first data bus Abus based on the set signal and output a first data bit, and when the memory is in a second mode, it is configured to block the first data bus Abus based on the set signal and output a predetermined data bit, the first mode being a normal read mode and the second mode being a duty cycle training mode.

[0041] Each memory cell contains one selection transistor and one capacitor. The gate of the selection transistor is connected to the word line, one end of the selection transistor is connected to the capacitor, and the other end is connected to the bit line. When a memory cell is selected, that is, when the memory receives a command and address signal from the controller and selects the memory cell at the corresponding address to perform a read / write operation, the gate of the selection transistor conducts upon receiving the word line signal. The data stored in the capacitor is then read from the bit line to the first data bus Abus, or the bit line receives data from the first data bus Abus and writes it to the capacitor. The data read from the bit line needs to be further amplified by circuits such as Local Sense Amplifier (Local SA) and Global Sense Amplifier (Global SA) before being transmitted to the peripheral circuits (the order of the circuit modules through which the written data passes is reversed). In the embodiments of this disclosure, the first data bus Abus refers to a data line located in a peripheral circuit that is electrically connected to a bit line, and the data transmitted on the first data bus Abus is data read from a memory cell and amplified, i.e., a single data bit, which is generally logical 0 or logical 1. Those skilled in the art will understand that the data transmitted by DRAM may include multiple data bits, and for example, one data transmitted in DDR5 may include 16 data bits (D0-D15). DDR5 includes multiple parallel first data buses Abus, each first data bus Abus used to transmit one data bit corresponding to one memory cell in a plurality of memory cells arranged in an array.

[0042] Continuing to refer to Figure 1, the set circuit 100 is connected to the first data bus Abus and receives the set signal. When the memory is in the first mode, i.e., the normal read mode, the set signal causes the first data bus Abus to conduct and outputs the first data bit. When the memory is in the second mode, i.e., the duty cycle training mode, the set signal causes the first data bus Abus to shut off and outputs a predetermined data bit.

[0043] In normal read mode, the first data bus Abus is made to conduct based on the set signal. At this time, the set circuit 100 is deactivated and acts as a transmission line, transmitting data on the first data bus Abus and outputting the first data bit. The first data bit refers to the data output in normal read mode, i.e., the data read from the memory cell. In duty cycle training mode, the first data bus Abus is turned off based on the set signal. At this time, the set circuit 100 is activated and generates a predetermined data bit. The predetermined data bit refers to the data output in duty cycle training mode, i.e., the memory generates a data pattern that has been set in advance according to the controller's instructions. In this way, by placing the set circuit 100 on the first data bus Abus, the first data bus Abus can be selectively made to conduct or turn off in different operating modes of the memory to output the corresponding data, and memory area can be saved by sharing the first data bus Abus. Furthermore, after the memory switches from normal read mode to duty cycle training mode, the first data bus Abus is shut off, and since the data in normal read mode is no longer switched, power consumption is significantly reduced.

[0044] In one embodiment of the present disclosure, referring to Figure 2, Figure 2 is a schematic diagram showing the configuration of a set circuit 100 according to an embodiment of the present disclosure. As shown in Figure 2, the set circuit 100 comprises a setter, the set signals include a first set signal BUSL and a second set signal BUSH, the input terminal of the setter is connected to a first data bus Abus, the first set terminal receives the first set signal BUSL, and the second set terminal receives the second set signal BUSH, where in the first mode the levels of the first set signal BUSL and the second set signal BUSH are different, and in the second mode the levels of the first set signal and the second set signal are the same.

[0045] Taking a first data bus Abus as an example, the first data bus Abus is used to transmit data in the memory cell read from the bit line. Here, "data" refers to the data of one data bit, i.e., the first data bit. The set circuit 100 may also be a setter, the input terminal of the setter is connected to the first data bus Abus, the first set terminal of the setter receives the first set signal BUSL, and the second set terminal of the setter receives the second set signal BUSH. In the first mode, i.e., the normal read mode, the levels of the first set signal BUSL and the second set signal BUSH are different; that is, the first set signal BUSL may be high level (logic 1), and the second set signal BUSH may be low level (logic 0). In this case, the setter is disabled and corresponds to a transmission line, and the first data bit is read normally via the first data bus Abus without any interference. In the second mode, i.e., the duty cycle training mode, the levels of the first set signal BUSL and the second set signal BUSH are the same, meaning that both the first set signal BUSL and the second set signal BUSH may be at a high level (logical 1), in which case the setter is enabled, and the output data is pulled down to 0 by the setter, i.e., the predetermined data bits output are equal to logical 0. Alternatively, both the first set signal BUSL and the second set signal BUSH may be at a low level (logical 0), in which case the setter is enabled, and the output data is pulled up to 1 by the setter, i.e., the predetermined data bits output are equal to logical 1. Understandably, the levels of the first set signal BUSL and the second set signal BUSH corresponding to whether the setter is enabled or disabled can vary, and Figure 2 shows only the case where the first set signal BUSL is low-level enabled and the second set signal BUSH is high-level enabled as an example.

[0046] In this way, the first set terminal of the setter receives the first set signal BUSL, and the second set terminal receives the second set signal BUSH. The first set signal BUSL and the second set signal BUSH configure the setter to be disabled in the first mode, conduction of the first data bus Abus to output the first data bit, and enabled in the second mode, blocking the first data bus Abus to output a predetermined data bit. The level state of the predetermined data bit is obtained by setting the levels of the first set signal BUSL and the second set signal BUSH. As a result, by setting the levels of the first set signal BUSL and the second set signal BUSH, different predetermined data bits can be generated, and furthermore, different predetermined data patterns can be generated, enabling duty cycle training.

[0047] According to DRAM industry standards, whether to enable DCA training mode and the predetermined data pattern are obtained by decoding based on the register code of the mode register MR42. As shown in Table 1 below, the multiple register codes of the mode register MR42 indicate whether to support DCA training mode and the corresponding predetermined data pattern for different DCA training modes. The mode register MR42 includes an 8-bit register code OP[7:0].

[0048] Here, OP[1:0] is used to indicate whether the memory supports DCA training mode. OP[1:0]=00 indicates that the memory does not support DCA training mode, OP[1:0]=01 indicates that the memory supports DCA two-phase clock training mode, i.e., DCA training assist mode I, and OP[1:0]=10 indicates that the memory supports DCA four-phase clock training mode, i.e., DCA training assist mode II (OP[1:0]=11 is reserved for future use (RFU), and the RFU described later has a similar meaning and will not be repeated).

[0049] OP[3:2] is used to indicate that the memory is in DCA training mode I. OP[3:2]=00 indicates the memory is in its default state, OP[3:2]=01 indicates that the memory's IBCLK-synchronized data is masked, i.e., the data is aligned to ICLK, and OP[3:2]=10 indicates that the memory's ICLK-synchronized data is masked, i.e., the data is aligned to IBCLK.

[0050] OP[6:4] is used to indicate that the memory is in DCA training mode II. OP[6:4]=000 indicates the memory is in its default state; OP[6:4]=001 indicates that the predetermined data pattern the memory writes / reads is 0001; OP[6:4]=010 indicates that the predetermined data pattern the memory writes / reads is 0011; OP[6:4]=011 indicates that the predetermined data pattern the memory writes / reads is 0111; OP[6:4]=100 indicates that the predetermined data pattern the memory writes / reads is 1000; OP[6:4]=101 indicates that the predetermined data pattern the memory writes / reads is 1100; and OP[6:4]=110 indicates that the predetermined data pattern the memory writes / reads is 1110.

[0051] OP[7] is used to indicate whether DCA training mode is supported in the current memory read state. If OP[7]=0, it indicates that DCA training mode II is not supported in the memory read state, and if OP[7]=1, it indicates that DCA training mode II is supported in the memory read state.

[0052] [Table 1]

[0053] Taking the register code OP[7:0]=10010010 for mode register MR42 as an example, OP[1:0]=10, OP[3:2]=00, OP[6:4]=001, and OP[7]=1, the memory accordingly enables DCA training mode II and generates the predetermined data pattern 0001.

[0054] In one embodiment of the present disclosure, referring to Figure 3, Figure 3 is a schematic diagram showing another configuration of the memory according to an embodiment of the present disclosure. As shown in Figure 3, the memory further comprises a decoding circuit 200, which is configured to receive the register code of a mode register and generate a set signal by decoding.

[0055] The decoding circuit 200 receives the register code OP[6:4] from the mode register MR42 and can generate a set signal by decoding. When the memory is in the second mode, i.e., DCA training mode, the set signal activates the set circuit 100, shutting off the first data bus Abus to output a predetermined data bit, where the predetermined data bit corresponds to one bit of a predetermined data pattern. Since the register code OP[6:4] contains three bits, the decoding circuit 200 can decode based on the register code OP[6:4] and generate a set signal with eight different level combinations, thereby generating the same predetermined data bit as the predetermined data pattern.

[0056] Referring to Figure 4, Figure 4 is a schematic diagram showing the configuration of a decoding circuit 200 according to an embodiment of the present disclosure. As shown in Figure 4, the decoding circuit 200 includes a decoder that receives the register code OP[6:4] of the mode register MR42 and generates set signals BUSL0 / BUSH0, BUSL1 / BUSH1, BUSL2 / BUSH2, and BUSL3 / BUSH3 by decoding. The decoder may be a 3-8 decoder that receives a 3-bit register code and generates 8-bit data bits by decoding. Here, each pair of data bits corresponds to one set signal, with one data bit corresponding to the first set signal BUSL and the other data bit corresponding to the second set signal BUSH. As described above, the level of one bit of a given data pattern, i.e., the level of a given data bit, can be generated based on the level conditions of the first set signal BUSL and the second set signal BUSH.

[0057] For example, if the register code OP[6:4]=000 for the mode register MR42, the decoder generates set signals BUSL0=BUSL1=BUSL2=BUSL3=1 and BUSH0=BUSH1=BUSH2=BUSH3=0 through decoding. Considering this together with Figures 2 and 4, in this case the first set terminal of the setter receives 1 and the second set terminal receives 0, the set circuit is disabled, and the first data bit is read normally via the first data bus Abus without any interference. If the register code OP[6:4]=001 for the mode register MR42, the decoder generates set signals BUSL0=BUSH0=0, BUSL1=BUSH1=1, BUSL2=BUSH2=1, and BUSL3=BUSH3=1 through decoding. In this case, taking the four set circuits 200 as a group, the first set terminal of the first set circuit 200 receives 0, the second set terminal receives 0, the set circuit 200 becomes active, and the output data is pulled up to 1. The first set terminals of the remaining three set circuits 200 receive 1, the second set terminals receive 1, the set circuits 200 become active, the output data is pulled down to 0, and the generated data pattern becomes 0001, which is equal to the predetermined data pattern. As a result, the controller can identify ICLK and IBCLK based on the fact that the first or third bit of the data pattern generated by the memory is sampled by the clock signal, and thereby perform DCA training and alignment of the four-phase clock. Note that the DCA training, the received register code, and the generated predetermined data pattern all relate to DCA training mode II, i.e., four-phase clock training. The correspondence of the set signals generated by decoding the register code OP[6:4] of the mode register MR42 is shown in Table 2 below. It should be noted that there can be various correspondences between register codes and set signal levels, and the case in Table 2 is just one example.

[0058] [Table 2]

[0059] In one embodiment of the present disclosure, referring to Figure 5, Figure 5 is a schematic diagram showing another configuration of the memory according to an embodiment of the present disclosure. As shown in Figure 5, the memory further comprises a latch circuit 300, which is connected to a decoding circuit 200 and configured to receive a mode register write signal MRW, to output a set signal if the mode register write signal MRW is valid, and to latch the set signal if the mode register write signal MRW is invalid.

[0060] As described above, the set signal generated by the decoding circuit 200 is transmitted to the set circuit 100, and when the memory is in the second mode, i.e., the duty cycle training mode, the set circuit 100 becomes active and generates a predetermined data bit in a predetermined data pattern based on the set signal. Here, the decoding circuit 200 also generates a different set signal corresponding to the change in the register code of the mode register through decoding. Therefore, a latch circuit 300 is added between the decoding circuit 200 and the set circuit 100, and the latch circuit 300 receives the mode register write signal MRW and controls the latch circuit 300 to trigger and output the latest set signal only when the mode register write signal MRW is active, and controls the latch circuit 300 to latch the set signal when the mode register write signal MRW is inactive, i.e., the set signal received by the set circuit 100 does not change. The purpose of this is to trigger and operate the latch circuit 300 only when the mode register write signal MRW is active, i.e., when the register code OP[6:4] of the mode register MR42 changes, causing the decoding circuit 200 to output the value of the set signal generated by decoding, and controlling the subsequent set circuit 100 to receive the set signal. This reduces the occurrence of glitches by not being affected when switching the corresponding predetermined data bits.

[0061] Referring to Figure 6, Figure 6 is a schematic diagram showing the configuration of a latch circuit 300 according to an embodiment of the present disclosure. As shown in Figure 6, the latch circuit 300 includes a latch, the signal input terminal of the latch receives a set signal generated by the decoding circuit 200, and the clock terminal of the latch receives a mode register write signal MRW. When the mode register write signal MRW is valid, the output terminal of the latch outputs a set signal, and when the mode register write signal MRW is invalid, the output terminal of the latch does not output. The latch may also be a D flip-flop.

[0062] In one embodiment of the present disclosure, referring to Figure 7, which is a schematic diagram showing another configuration of the memory according to an embodiment of the present disclosure. As shown in Figure 7, the memory further comprises N parallel-to-serial converters, each parallel-to-serial converter connected to M set circuits 100, configured to receive data bits output from the M set circuits 100, sample the data bits based on a first clock signal, and generate second data by logic processing, each second data containing M serial data bits, where N and M are even numbers.

[0063] In the case of the first parallel-to-serial conversion circuit 400_1, it is connected to M set circuits 100, receives data bits output from the M set circuits 100, samples the data bits based on the first clock signal, and generates second data B0 through logic processing. In the case of the Nth parallel-to-serial conversion circuit 400_N, it is connected to M set circuits 100, receives data bits output from the M set circuits 100, samples the data bits based on the first clock signal, and generates second data B(N-1) through logic processing. Here, for ease of distinction, the second data generated by the parallel-to-serial conversion circuits are named sequentially: the second data output from the first parallel-to-serial conversion circuit is B0, the second data output from the second parallel-to-serial conversion circuit is B1, and so on, until the second data output from the Nth parallel-to-serial conversion circuit is B(N-1). Each second data contains M bits of serial data. Note that the second data here refers to the data output from the parallel-to-serial conversion circuit, and not the data ultimately output from memory to the input / output interface. Since the N second data points here are output in parallel, as those skilled in the art will understand, the N second data points must be transmitted to the input / output interface after undergoing at least one parallel-to-serial conversion operation in order to achieve the final data output. In the case of each parallel-to-serial conversion circuit, the M set circuits 100 connected to it are also in parallel. In the case of N parallel-to-serial conversion circuits, the M set circuits connected to each parallel-to-serial conversion circuit are different. The terms 1st, 2nd, or Nth here do not limit the order of the outputs.

[0064] In one embodiment of the present disclosure, referring again to Figure 7, the clock period of the first clock signal is M times the clock period of the system clock signal, and in each parallel-to-serial conversion circuit, the effective pulse periods of the first clock signal received by the M set circuits 100 do not overlap with each other.

[0065] The first clock signal is an internal clock signal generated based on the system clock signal, which refers to the clock signal transmitted from the controller to the DRAM and corresponds to the DRAM's operating frequency. Generally, the operating frequency corresponding to the system clock signal of fifth-generation double data-rate synchronous dynamic random access memory (DDR5) is 6400 MHz, and the clock period of one system clock signal is approximately 312.5 ps. If the clock period of the system clock signal is too short, the sampling window corresponding to the effective pulse period will be too small, making sampling failures and mis-sampling more likely due to insufficient sampling time. Therefore, an internal clock signal with an expanded effective pulse width can be generated based on the system clock signal. For example, the effective pulse width of the first clock signal may be twice the effective pulse width of the system clock signal. In this way, it is possible to ensure that the sampling window is sufficient, and misreads and miswrites are less likely to occur.

[0066] Since the second data generated by the parallel-to-serial conversion circuit by sampling based on the first clock signal contains M bits of serial data, the clock period of the first clock signal may be M times the clock period of the system clock signal, and the effective pulse periods of the first clock signal received by the M set circuits 100 in each parallel-to-serial conversion circuit do not overlap with each other. As a result, within one clock period of the first clock signal, in other words, within M clock periods of the system clock signal, N second data are output in parallel, each second data contains M data bits output in series, and each data bit corresponds to one clock period of the system clock signal.

[0067] Referring to Figure 8, which is a schematic diagram showing the configuration of a parallel-to-serial conversion circuit according to an embodiment of the present disclosure, Figure 9 is a timing chart corresponding to the parallel-to-serial conversion circuit in Figure 8. As shown in Figure 8, the memory includes four parallel-to-serial conversion circuits 400_1 to 400_4, each of which includes four buffers (FIFO: First In First Out) and corresponding logic processing gate circuits, and is connected to four set circuits 100 (not shown), which receive data bits output from the four set circuits 100, sample the data bits based on first clock signals clk0, clk1, clk2, clk3, and generate second data B0, B1, B2, and B3 by logic processing. Each second data contains M bits of serial data, where N and M are even numbers.

[0068] For the first parallel-to-serial conversion circuit 400_1, the signal input terminal of the first buffer FIFO_1 is connected to the data bit bus output from the first set circuit. <0> Upon receiving the first clock signal clk0, the clock terminal of the first buffer FIFO_1 receives the intermediate data bits BUS. <0> The second buffer FIFO_2 has a signal input terminal that outputs the data bit Bus from the second set circuit. <4> The second buffer FIFO_2 receives the first clock signal clk1, and the output terminal of the second buffer FIFO_2 receives the intermediate data bits BUS. <4> It outputs the data bits Bus output from the third set circuit. The signal input terminal of the third buffer FIFO_3 is connected to the data bits Bus output from the third set circuit. <8> The clock terminal of the third buffer FIFO_3 receives the first clock signal clk2, and the output terminal of the third buffer FIFO_3 receives the intermediate data bits BUS. <8> It outputs the data bits Bus output from the fourth buffer FIFO_4. <12> The clock terminal of the fourth buffer FIFO_4 receives the first clock signal clk3, and the output terminal of the fourth buffer FIFO_4 receives the intermediate data bits BUS <12> It outputs the intermediate data bits BUS. The first input terminal of one NOR gate is the intermediate data bits BUS. <0> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <4> The output terminal receives the signal and is connected to the first input terminal of a NAND gate. The first input terminal of another NOR gate is connected to the intermediate data bit BUS. <8> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <12> The signal is received, and its output terminal is connected to the second input terminal of a NAND gate. The output terminal of the NAND gate outputs the second data B0, which contains 4 bits of serial data, i.e., Bus<0,4,8,12>. Note that the 1st, 2nd, 3rd, and 4th here are named in order of appearance and do not impose any substantial limitations on the actual connection relationships.

[0069] Regarding the second parallel-to-serial conversion circuit 400_2, the signal input terminal of the first buffer FIFO_1 is connected to the data bit bus output from the first set circuit. <1> Upon receiving the first clock signal clk0, the clock terminal of the first buffer FIFO_1 receives the intermediate data bits BUS. <1> The second buffer FIFO_2 has a signal input terminal that outputs the data bit Bus from the second set circuit. <5> The second buffer FIFO_2 receives the first clock signal clk1, and the output terminal of the second buffer FIFO_2 receives the intermediate data bits BUS. <5> It outputs the data bits Bus output from the third set circuit. The signal input terminal of the third buffer FIFO_3 is connected to the data bits Bus output from the third set circuit. <9> The clock terminal of the third buffer FIFO_3 receives the first clock signal clk2, and the output terminal of the third buffer FIFO_3 receives the intermediate data bits BUS. <9> It outputs the data bits Bus output from the fourth buffer FIFO_4. <13> The clock terminal of the fourth buffer FIFO_4 receives the first clock signal clk3, and the output terminal of the fourth buffer FIFO_4 receives the intermediate data bits BUS <13> It outputs the intermediate data bits BUS. The first input terminal of one NOR gate is the intermediate data bits BUS. <1> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <5> The output terminal receives the signal and is connected to the first input terminal of a NAND gate. The first input terminal of another NOR gate is connected to the intermediate data bit BUS. <9> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <13> The signal is received, and its output terminal is connected to the second input terminal of a NAND gate. The output terminal of the NAND gate outputs the second data B1, which contains 4 bits of serial data, i.e., Bus<1, 5, 9, 13>. For the sake of brevity of the illustration, the buffers of the second, third, and fourth parallel-to-serial conversion circuits are not shown in Figure 8, but this does not impose any limitations on the actual circuit configuration.

[0070] Regarding the third parallel-to-serial conversion circuit 400_3, the signal input terminal of the first buffer FIFO_1 is connected to the data bit bus output from the first set circuit. <2> Upon receiving the first clock signal clk0, the clock terminal of the first buffer FIFO_1 receives the intermediate data bits BUS. <2> The second buffer FIFO_2 has a signal input terminal that outputs the data bit Bus from the second set circuit. <6> The second buffer FIFO_2 receives the first clock signal clk1, and the output terminal of the second buffer FIFO_2 receives the intermediate data bits BUS. <6> It outputs the data bits Bus output from the third set circuit. The signal input terminal of the third buffer FIFO_3 is connected to the data bits Bus output from the third set circuit. <10> The clock terminal of the third buffer FIFO_3 receives the first clock signal clk2, and the output terminal of the third buffer FIFO_3 receives the intermediate data bits BUS. <10> It outputs the data bits Bus output from the fourth buffer FIFO_4. <14> The clock terminal of the fourth buffer FIFO_4 receives the first clock signal clk3, and the output terminal of the fourth buffer FIFO_4 receives the intermediate data bits BUS <14> It outputs the intermediate data bits BUS. The first input terminal of one NOR gate is the intermediate data bits BUS. <2> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <6> The output terminal receives the signal and is connected to the first input terminal of a NAND gate. The first input terminal of another NOR gate is connected to the intermediate data bit BUS. <10> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <14> The output terminal receives the signal, and is connected to the second input terminal of a NAND gate. The output terminal of the NAND gate outputs the second data B2, which contains 4 bits of serial data, i.e., Bus<2,6,10,14>.

[0071] Regarding the fourth parallel-to-serial conversion circuit 400_4, the signal input terminal of the first buffer FIFO_1 is connected to the data bit bus output from the first set circuit. <3> Upon receiving the first clock signal clk0, the clock terminal of the first buffer FIFO_1 receives the intermediate data bits BUS. <3> The second buffer FIFO_2 has a signal input terminal that outputs the data bit Bus from the second set circuit. <7> The second buffer FIFO_2 receives the first clock signal clk1, and the output terminal of the second buffer FIFO_2 receives the intermediate data bits BUS. <7> It outputs the data bits Bus output from the third set circuit. The signal input terminal of the third buffer FIFO_3 is connected to the data bits Bus output from the third set circuit. <11> The clock terminal of the third buffer FIFO_3 receives the first clock signal clk2, and the output terminal of the third buffer FIFO_3 receives the intermediate data bits BUS. <11> It outputs the data bits Bus output from the fourth buffer FIFO_4. <15> The clock terminal of the fourth buffer FIFO_4 receives the first clock signal clk3, and the output terminal of the fourth buffer FIFO_4 receives the intermediate data bits BUS <15> It outputs the intermediate data bits BUS. The first input terminal of one NOR gate is the intermediate data bits BUS. <3> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <7> The output terminal receives the signal and is connected to the first input terminal of a NAND gate. The first input terminal of another NOR gate is connected to the intermediate data bit BUS. <11> Upon receiving the signal, the second input terminal receives the intermediate data bit BUS. <15> The output terminal receives the signal, and is connected to the second input terminal of a NAND gate. The output terminal of the NAND gate outputs the second data B3, which contains 4 bits of serial data, i.e., Bus<3,7,11,15>. Here, we take the example where N=4 and M=4, that is, 16 bits of parallel data are output from 16 first data buses Abus. <0> ~Bus <15> After being processed by four parallel-to-serial conversion circuits, it generates four parallel second data sets B0 to B3, each second data set containing four bits of serial output data.In reality, N and M can be in various cases, for example, N=4 and M=2, i.e., a conversion from 8 to 2, or N=6 and M=4, i.e., a conversion from 24 to 4.

[0072] Here, the clock periods of the first clock signals clk0, clk1, clk2, and clk3 are four times the clock period of the system clock signal CK, and in each parallel-to-serial conversion circuit, the effective pulse periods of the first clock signals clk0, clk1, clk2, and clk3 received by the four set circuits 100 do not overlap with each other. As shown in Figure 9, the effective pulse width of the first clock signals is twice the effective pulse width of the system clock signal CK. The rising edge of the first active pulse of the first clock signal clk0 aligns with the rising edge of the first active pulse of the system clock signal CK; the falling edge of the first active pulse of the first clock signal clk0 aligns with the rising edge of the second active pulse of the system clock signal CK and the rising edge of the first active pulse of the first clock signal clk1; the falling edge of the first active pulse of the first clock signal clk1 aligns with the rising edge of the third active pulse of the system clock signal CK and the rising edge of the first active pulse of the first clock signal clk2; the falling edge of the first active pulse of the first clock signal clk2 aligns with the rising edge of the fourth active pulse of the system clock signal CK and the rising edge of the first active pulse of the first clock signal clk3; and the falling edge of the first active pulse of the first clock signal clk3 aligns with the rising edge of the fifth active pulse of the system clock signal CK and the rising edge of the second active pulse of the first clock signal clk0. In this way, it is possible to achieve that only one first clock signal is active at the same time, thereby enabling the output of four serial data bits. It should be noted that the terms "aligned" and "non-overlapping" used here refer to ideal cases; in actual circuits, delays exist, so overlap between the first clock signals is possible.

[0073] Considering Figure 9 and Table 3 below, within the first clock cycle of the system clock signal CK, the four parallel-to-serial conversion circuits correspond to output the second data B0B1B2B3=Bus<0~3>, within the second clock cycle of the system clock signal CK, the four parallel-to-serial conversion circuits correspond to output the second data B0B1B2B3=Bus<4~7>, within the third clock cycle of the system clock signal CK, the four parallel-to-serial conversion circuits correspond to output the second data B0B1B2B3=Bus<8~11>, and within the fourth clock cycle of the system clock signal CK, the four parallel-to-serial conversion circuits correspond to output the second data B0B1B2B3=Bus<12~15>.

[0074] [Table 3]

[0075] In one embodiment of this disclosure, in conjunction with Tables 2 and 3, when the memory is in the second mode, the levels of the M bits of serial data bits in each second data are the same, and N is equal to the number of bits in a given data pattern. As shown in Table 2, when the memory is in the second mode, i.e., the duty cycle training mode, the register code OP[6:4] of the mode register MR42 generates a set signal via the decoding circuit 200, which activates the set circuit 100 and outputs a given data bit. Since there are 4 bits in the given data pattern, four parallel-to-serial converters are required to generate four second data. The four second data output on the first active pulse of the system clock signal are equal to the given data pattern (further converters are required). In the case of 16 parallel first data bus Abus, when the memory is in the first mode, the second data generated by each parallel-to-serial converter is data read from the memory cell, and when the memory is in the second mode, the second data B0 generated by the first parallel-to-serial converter 400_1 is Bus <0> =Bus <4> =Bus <8> =Bus <12> Therefore, the second data B1 generated by the second parallel-to-serial conversion circuit 400_2 is Bus <1> =Bus <5> =Bus <9> =Bus <13> Therefore, the second data B2 generated by the third parallel-to-serial conversion circuit 400_3 is Bus <2> =Bus <6> =Bus <10> =Bus <14> Therefore, the second data B3 generated by the fourth parallel-to-serial conversion circuit 400_4 is Bus <3> =Bus <7> =Bus <11> =Bus <15> Therefore, the register code OP[6:4] of the mode register MR42 controls the generation of different set signals, so the set circuit 100 is controlled to generate different predetermined data bits, thereby generating different data patterns.

[0076] In one embodiment of the present disclosure, continuing with reference to Figures 7 and 8, the parallel-to-serial converter is further configured to receive a first write signal FIFO_IN and, if the first write signal FIFO_IN is valid, to trigger the generation of second data.

[0077] As shown in Figure 8, the input terminal of the buffer FIFO further receives a first write signal FIFO_IN. Only when the first write signal FIFO_IN is valid does the buffer FIFO operate, writing the data bits output from the set circuit 100 to the buffer FIFO and outputting intermediate data bits by sampling. The first write signal FIFO_IN is generated based on a command received by the memory, such as a read command or a mode register read command.

[0078] Referring to Figure 10, which is a schematic diagram showing the configuration of a first write signal generation circuit according to an embodiment of the present disclosure. As shown in Figure 10, the input terminal of the OR gate receives the register code OP[6:4] of the mode register MR42, and the output terminal of the OR gate outputs a duty cycle training mode identification signal DCA_FLAG. The first input terminal of the NAND gate receives a command signal command, and the second input terminal receives the duty cycle training mode identification signal DCA_FLAG. The output terminal of the NAND gate is connected to one inverter, and the output terminal of the inverter outputs a first duty cycle write signal FIFO_IN_DCA. The command signal command is further connected to multiple buffers Buffer, and the output terminals of the buffers Buffer are connected to the output terminals of the inverter, which outputs a first write signal FIFO_IN.

[0079] As shown in Table 1, if the memory does not support duty cycle training mode (duty cycle training mode II is used as an example in this disclosure), the register code OP[6:4] of the mode register MR42 is 000, meaning the OR gate outputs the duty cycle training mode identification signal DCA_FLAG as 0. The first duty cycle write signal FIFO_IN_DCA generated after logic processing is also 0, meaning no data is written to the buffer FIFO. If the memory is in the second mode, i.e., duty cycle training mode, at least one bit of the register code OP[6:4] of the mode register MR42 is 1, meaning the OR gate outputs 1 as the duty cycle training mode identification signal DCA_FLAG. At this time, the memory receives the corresponding command signal command, and the first duty cycle write signal FIFO_IN_DCA generated after logic processing is also 1. At this time, the buffer FIFO operates normally and receives the data bits (predetermined data bits) output from the set circuit 100. Furthermore, if the memory does not support duty cycle training mode and the register code OP[6:4]=000 of the mode register MR42, the duty cycle training mode identification signal DCA_FLAG output from the OR gate will be 0 when the memory is in the first mode, i.e., normal read mode. However, the command signal command is valid in this case, and although the first duty cycle write signal FIFO_IN_DCA generated after logic processing will be 0, the first write signal FIFO_IN will be 1, and as a result the buffer FIFO operates normally and receives the data bit (first data bit) output from the set circuit 100.

[0080] In one embodiment of the present disclosure, referring to Figure 11, which is a schematic diagram showing another configuration of the memory according to an embodiment of the present disclosure. As shown in Figure 11, the memory further comprises N selectors, each selector configured to be connected to two parallel-to-serial converters to receive corresponding second data, wherein when the memory is in the first mode, the second data output by the N / 2 selectors in odd mode is the same as the second data output by the other N / 2 selectors in even mode, and when the memory is in the second mode, the second data output by the N / 2 selectors in odd mode is different from the second data output by the other N / 2 selectors in even mode, wherein the two parallel-to-serial converters connected to each selector of the N / 2 selectors are the same as the two parallel-to-serial converters connected to the corresponding selector of the other N / 2 selectors.

[0081] Taking N=4 and N / 2=2 as an example, the memory may include four selection circuits 500_1 to 500_4, each selection circuit connected to two parallel-to-serial conversion circuits (not shown) to receive the corresponding second data.

[0082] When the memory is in the first mode, i.e., the normal read mode, the second data output by the two select circuits in odd mode is the same as the second data output by the other two select circuits in even mode. When the memory is in the second mode, i.e., the duty cycle training mode, the second data output by the two select circuits in odd mode is different from the second data output by the other two select circuits in even mode. Here, the two parallel-to-serial converters connected to each of the two select circuits are the same as the two parallel-to-serial converters connected to the corresponding select circuit of the other two select circuits.

[0083] There are multiple possible combinations when dividing the four selection circuits here into two selection circuits and two other selection circuits. For example, the two selection circuits could be the first selection circuit 500_1 and the second selection circuit 500_2, and the other two selection circuits could correspond to the third selection circuit 500_3 and the fourth selection circuit 500_4. Alternatively, the two selection circuits could be the first selection circuit 500_1 and the third selection circuit 500_3, and the other two selection circuits could correspond to the second selection circuit 500_2 and the fourth selection circuit 500_4. Alternatively, the two selection circuits could be the first selection circuit 500_1 and the fourth selection circuit 500_4, and the other two selection circuits could correspond to the second selection circuit 500_2 and the third selection circuit 500_3.

[0084] In one embodiment of the present disclosure, continuing with reference to Figure 11, the selection circuits are configured such that when the memory is in a first mode, the second data output by the first N / 2 selection circuits in odd mode is the same as the second data output by the last N / 2 selection circuits in even mode; when the memory is in a second mode, the second data output by the first N / 2 selection circuits in odd mode is different from the second data output by the last N / 2 selection circuits in even mode; and the two parallel-to-serial converters connected to each of the first N / 2 selection circuits are the same as the two parallel-to-serial converters connected to the corresponding selection circuit of the last N / 2 selection circuits.

[0085] Let's take the example where the first two selection circuits are the first selection circuit 500_1 and the second selection circuit 500_2, and the last two selection circuits are the third selection circuit 500_3 and the fourth selection circuit 500_4. When the memory is in the first mode, the second data output by the first selection circuit 500_1 and the second selection circuit 500_2 in odd mode is the same as the second data output by the third selection circuit 500_3 and the fourth selection circuit 500_4 in even mode. When the memory is in the second mode, the second data output by the first selection circuit 500_1 and the second selection circuit 500_2 in odd mode is different from the second data output by the third selection circuit 500_3 and the fourth selection circuit 500_4 in even mode. Here, the two parallel-to-serial converters connected to the first selection circuit 500_1 are the same as the two parallel-to-serial converters connected to the third selection circuit 500_3, and the two parallel-to-serial converters connected to the second selection circuit 500_2 are the same as the two parallel-to-serial converters connected to the fourth selection circuit 500_4. This will be explained in detail below in conjunction with Figure 11 and Table 4.

[0086] The first selection circuit 500_1 and the third selection circuit 500_3 are connected to the first parallel-to-serial converter 400_1 and the third parallel-to-serial converter 400_3 (not shown), and receive the second data B0 output from the first parallel-to-serial converter 400_1 and the second data B2 output from the third parallel-to-serial converter 400_3. When the memory is in the first mode, the first selection circuit 500_1 outputs the second data B0 in odd mode, and the third selection circuit 500_3 outputs the second data B0 in even mode. When the memory is in the second mode, the first selection circuit 500_1 outputs the second data B0 in odd mode, and the third selection circuit 500_3 outputs the second data B2 in even mode. Alternatively, when the memory is in the first mode, the first selection circuit 500_1 outputs the second data B2 in even mode, and the third selection circuit 500_3 outputs the second data B2 in odd mode. When the memory is in the second mode, the first selection circuit 500_1 outputs the second data B0 in even mode, and the third selection circuit 500_3 outputs the second data B2 in odd mode.

[0087] The second selection circuit 500_2 and the fourth selection circuit 500_4 are connected to the second parallel-to-serial conversion circuit 400_2 and the fourth parallel-to-serial conversion circuit 400_4 (not shown), and receive the second data B1 output from the second parallel-to-serial conversion circuit 400_2 and the second data B3 output from the fourth parallel-to-serial conversion circuit 400_4. When the memory is in the first mode, the second selection circuit 500_2 outputs the second data B1 in odd mode, and the fourth selection circuit 500_4 outputs the second data B1 in even mode. When the memory is in the second mode, the second selection circuit 500_2 outputs the second data B1 in odd mode, and the fourth selection circuit 500_4 outputs the second data B3 in even mode. Alternatively, when the memory is in the first mode, the second selection circuit 500_2 outputs the second data B3 in even mode, and the fourth selection circuit 500_4 outputs the second data B3 in odd mode. When the memory is in the second mode, the second selection circuit 500_2 outputs the second data B1 in even mode, and the fourth selection circuit 500_4 outputs the second data B3 in odd mode.

[0088] [Table 4]

[0089] In one embodiment of the present disclosure, continuing with reference to Figure 11, the N selectors further receive a second clock signal and output two third data by sampling, each third data containing N / 2 parallel second data, wherein in odd mode, the second clock signal received by N / 2 selectors precedes the second clock signal received by the other N / 2 selectors by half a clock period, and in even mode, the second clock signal received by N / 2 selectors is delayed by half a clock period compared to the second clock signal received by the other N / 2 selectors.

[0090] As shown in Figure 11, the four selection circuits receive the second clock signal and output two third data D0 and D1 by sampling, each third data containing two parallel second data. As shown in Table 5 below, the third data D0 is generated by the first selection circuit 500_1 and the second selection circuit 500_2, and when the memory is in the first mode, the generated third data D0 is B0B1 in odd modes and B2B3 in even modes. When the memory is in the second mode, the generated third data D0 is B0B1 in odd modes and B0B1 in even modes. The third data D1 is generated by the third selection circuit 500_3 and the fourth selection circuit 500_4, and when the memory is in the first mode, the generated third data D1 is B2B3 in odd modes and B0B1 in even modes. When the memory is in the second mode, the generated third data D1 is B2B3 in odd mode and B2B3 in even mode.

[0091] [Table 5]

[0092] When the memory is in the first mode, in odd modes, the second clock signal received by the first selection circuit 500_1 and the second selection circuit 500_2 precedes the second clock signal received by the third selection circuit 500_3 and the fourth selection circuit 500_4 by half a clock period. That is, the third data D0 is sampled and generated before the third data D1. Therefore, the order of the third data ultimately output by the N selection circuits is D0D1, i.e., B0B1B2B3. In even modes, the second clock signal received by the first selection circuit 500_1 and the second selection circuit 500_2 is delayed by half a clock period compared to the second clock signal received by the third selection circuit 500_3 and the fourth selection circuit 500_4. That is, the third data D0 is sampled and generated after the third data D1. Therefore, the order of the third data ultimately output by the N selection circuits is D1D0, i.e., B0B1B2B3. Thus, when the memory is in the first mode, i.e., the normal read mode, the output third data is the same in odd / even modes, and normal data retrieval can be achieved.

[0093] When the memory is in the second mode, in odd modes, the second clock signal received by the first selection circuit 500_1 and the second selection circuit 500_2 precedes the second clock signal received by the third selection circuit 500_3 and the fourth selection circuit 500_4 by half a clock period. That is, the third data D0 is sampled and generated before the third data D1. Therefore, the order of the third data ultimately output by the N selection circuits is D0D1, i.e., B0B1B2B3. In even modes, the second clock signal received by the first selection circuit 500_1 and the second selection circuit 500_2 is delayed by half a clock period compared to the second clock signal received by the third selection circuit 500_3 and the fourth selection circuit 500_4. That is, the third data D0 is sampled and generated after the third data D1. Therefore, the order of the third data ultimately output by the N selection circuits is D1D0, i.e., B2B3B0B1. Thus, when the memory is in the second mode, i.e., the duty cycle training mode, the output third data differs between odd and even modes. The controller compares this with a predetermined data pattern to determine whether the output data is the first bit or the third bit, thereby determining whether the sampling clock corresponds to ICLKI or BCLK, and further performing duty cycle adjustment on the system clock signal.

[0094] In one embodiment of the present disclosure, referring to Figure 12, which is a schematic diagram showing another configuration of memory according to an embodiment of the present disclosure. As shown in Figure 12, the second clock signal includes a second clock odd signal OCK and a second clock even signal ECK, the clock periods of the second clock odd signal OCK and the second clock even signal ECK are the same, and at the same time only one of the second clock odd signal OCK and the second clock even signal ECK is active. The odd mode corresponds to the second clock odd signal OCK being active, and the even mode corresponds to the second clock even signal ECK being active. In the odd mode, N / 2 selectors sample based on the second clock odd signal OCK and the other N / 2 selectors sample based on the second clock odd delay signal OCKD. In the even mode, N / 2 selectors sample based on the second clock even delay signal ECKD and the other N / 2 selectors sample based on the second clock even signal ECK. Here, the second clock odd delay signal OCKD is delayed by half a clock period from the second clock odd delay signal OCK, and the second clock even delay signal ECKD is delayed by half a clock period from the second clock even delay signal ECK.

[0095] The second clock signal includes a second odd clock signal OCK and a second even clock signal ECK, both of which can be generated from the system clock signal. In this disclosure, taking as an example that the clock periods of the second odd clock signal OCK and the second even clock signal ECK are the same and twice the clock period of the system clock signal CK, when the second odd clock signal OCK is active, the second even clock signal ECK is masked, and when the second even clock signal ECK is active, the second odd clock signal OCK is masked. This ensures that data corresponding to only one active pulse of a clock signal is sampled at the same time, thereby avoiding missampling.

[0096] The first selection circuit 500_1 and the second selection circuit 500_2 receive the second odd clock signal OCK and the second even clock delay signal ECKD, while the third selection circuit 500_3 and the fourth selection circuit 500_4 receive the second odd clock delay signal OCKD and the second even clock signal ECK. This enables the following: In odd mode, the first selection circuit 500_1 and the second selection circuit 500_2 sample based on a valid second odd clock signal OCK to generate the third data D0, and the third selection circuit 500_3 and the fourth selection circuit 500_4 sample based on a valid second odd delay signal OCKD to generate the third data D1, resulting in the final output third data being D0D1. In even mode, the first selection circuit 500_1 and the second selection circuit 500_2 sample based on a valid second even delay signal ECKD to generate the third data D0, and the third selection circuit 500_3 and the fourth selection circuit 500_4 sample based on a valid second even signal ECK to generate the third data D1, resulting in the final output third data being D1D0. In this way, by setting different outputs for the third data D0 or D1 when the memory is in the first or second mode, data output corresponding to the normal read mode or duty cycle training mode can be achieved.

[0097] In one embodiment of the present disclosure, referring to Figure 13, which is a schematic diagram showing the configuration of a selection circuit according to an embodiment of the present disclosure. Figure 14 is a timing chart 1 (odd mode) corresponding to the selection circuit in Figure 13. Figure 15 is a timing chart 2 (even mode) corresponding to the selection circuit in Figure 13. As shown in Figure 13, each selection circuit includes an odd selection circuit and an even selection circuit, the odd selection circuit includes one odd sampling circuit connected to one parallel-to-serial converter to receive first second data, and the even selection circuit includes one selector MUX and one even sampling circuit, connected to two parallel-to-serial converters. One end of the selector MUX receives the first second data, the other end of the selector MUX receives the second second data, and the control end of the selector MUX receives the first selection signal SEL. In odd mode, the odd selection circuit receives the first second data and samples based on the second odd clock signal OCK. In even mode, if the first selection signal SEL is at the first level, the selector MUX outputs the first second data, and if the first selection signal SEL is at the second level, the selector MUX outputs the second second data. The even sampling circuit samples based on the second even clock delay signal ECKD. Alternatively, in odd mode, the odd selection circuit receives the first second data and samples it based on the second odd clock delay signal OCKD; in even mode, if the first selection signal SEL is at the first level, the selector MUX outputs the first second data; if the first selection signal SEL is at the second level, the selector MUX outputs the second second data, and the even sampling circuit samples it based on the second even clock signal ECK.

[0098] As shown in Figure 14, in odd mode, the second clock odd signal OCK is enabled, and the second clock even signal ECK is masked. Correspondingly, the second clock odd delay signal OCKD is enabled, and the second clock even delay signal ECKD is also masked. As a result, the odd selection circuits of the first selection circuit 500_1 and the second selection circuit 500_2 are enabled, receiving the first second data B0 and B1, sampling them based on the second clock odd signal OCK, and outputting B0B1 as the third data D0. The odd selection circuits of the third selection circuit 500_3 and the fourth selection circuit 500_4 are enabled, receiving the first second data B2 and B3, sampling them based on the second clock odd delay signal OCKD, and outputting B2B3 as the third data D1. Since the second odd-clock delay signal OCKD is delayed by half a clock period from the second odd-clock signal OCK, the generated third data D1 is also delayed by half a clock period from the third data D0, i.e., D0D1 = B0B1B2B3. As described above, since the levels of the M bits of serial data bits in each second data are the same, within different clock periods of the second odd-clock signal OCK, if the received second data is the same, the two third data outputs corresponding to the N selection circuits will also be the same. For example, if the second data B0B1B2B3 is 0001 and the corresponding effective pulse width is equal to the four clock periods of the second odd-clock signal OCK, then the output third data D0D1 will also be 0001 within the four clock periods of the second odd-clock signal OCK.

[0099] As shown in Figure 15, in even mode, the second clock even signal ECK is enabled, and the second clock odd signal OCK is masked. Correspondingly, the second clock even delay signal ECKD is enabled, and the second clock odd delay signal OCKD is masked. As a result, the even selectors of the first selector circuit 500_1 and the second selector circuit 500_2 are enabled, one end of the selector receives the first second data B0 and B1, the other end of the selector receives the second second data B2 and B3, and the control end of the selector receives the first selector signal SEL. The first selector signal can be generated based on the register code OP[6:4] of the mode register MR42. Specifically, the input end of one NOR gate is used to receive the register code OP[6:4] of the mode register MR42, and the output end of the NOR gate outputs the first selector signal SEL. As can be seen from Table 1, when the memory is in the second mode, i.e., the duty cycle training mode, at least one bit of the register code OP[6:4] of the mode register MR42 is 1, and the first selection signal SEL is 0. When the memory is in the first mode, the register code OP[6:4] of the mode register MR42 is 000, and the first selection signal SEL is 1. Correspondingly, when the first selection signal is at the first level (0), the selector outputs the first second data B0 and B1, and when the first selection signal is at the second level (1), the selector outputs the second second data B2 and B3, and the even sampling circuit samples based on the second clock even delay signal ECKD and outputs B0B1 or B2B3 as the third data D0. The even-numbered selector circuits, the third selector 500_3 and the fourth selector 500_4, become active. One end of the selector receives the first second data B2 and B3, the other end receives the second second data B0 and B1, and the control end of the selector receives the first selection signal SEL. The first selection signal can be generated based on the register code OP[6:4] of the mode register MR42. Specifically, the input end of one NOR gate is used to receive the register code OP[6:4] of the mode register MR42, and the output end of the NOR gate outputs the first selection signal SEL.As can be seen from Table 1, when the memory is in the second mode, i.e., the duty cycle training mode, at least one bit of the register code OP[6:4] of the mode register MR42 is 1, and the first selection signal SEL is 0. When the memory is in the first mode, the register code OP[6:4] of the mode register MR42 is 000, and the first selection signal SEL is 1. Correspondingly, when the first selection signal is at the first level (0), the selector outputs the first second data B2 and B3, and when the first selection signal is at the second level (1), the selector outputs the second second data B0 and B1, and the even sampling circuit samples based on the second clock even signal ECK and outputs B2B3 or B0B1 as the third data D1. Since the second clock even delay signal ECKD is delayed by half a clock period from the second clock even signal ECK, the generated third data D0 is also delayed by half a clock period from the third data D1, i.e., D1D0 = B2B3B0B1 (first selection signal SEL=0, i.e., corresponding to duty cycle training mode) or B0B1B2B3 (first selection signal SEL=1, i.e., corresponding to normal read mode). This ensures that in odd / even modes, the data output by the memory in normal read mode is the same, while the data output in duty cycle training mode is different, and the output data consists of the first bit corresponding to odd mode and the third bit corresponding to even mode, respectively. In this way, the controller can determine whether the current clock of the memory is ICLK or IBCLK based on the received data, and can further perform duty cycle adjustment on the clock signal.

[0100] As shown in Figure 15, in even mode, if the second data B0B1B2B3 is 0001 and the corresponding effective pulse width is equal to three clock periods of the second clock even signal ECK, the output third data D1D0 switches to 0011 in the fourth clock period of the second clock even signal ECK.

[0101] In one embodiment of the present disclosure, the memory further comprises an output module connected to N selection circuits and configured to receive two third data and output a fourth data to an input / output interface, the fourth data comprising N × M bits of serial data. As shown in Figures 14 and 15, since the two third data D0 and D1 are output in parallel, the memory further comprises an output module that samples the two parallel third data and outputs a fourth data to an input / output interface, the fourth data comprising N × M bits of serial data, which may be data read from a memory cell or a predetermined data pattern generated based on the register code OP[6:4] of the mode register MR42. Each data bit may correspond to one clock period of the system clock signal. In this way, the controller can determine ICLK or IBCLK based on whether the first BL received is the first bit or the third bit of a predetermined data pattern, and can further adjust the duty cycle of the clock signal.

[0102] Embodiments of this disclosure further provide a storage device comprising the memory provided in the above embodiments, and the storage device will be described in detail below. The above description of the embodiments is also applicable to embodiments of the storage device, and in order to avoid duplication, the contents mentioned in the above embodiments will not be repeated below.

[0103] The storage device comprises the memory provided in the above embodiment and a controller, the controller being coupled to the memory and configured to cause the storage device to perform the following operations, the operations being to send a command to the memory via the controller, the command including a normal read command or a duty cycle training mode command, the memory reading data based on the command received, and, if the command is a duty cycle training mode command, the storage device comparing the data received via the controller with predetermined data to determine and adjust the duty cycle of the system clock signal.

[0104] Referring to Figure 16, which is a schematic diagram showing the configuration of a storage device according to another embodiment of the present disclosure, as shown in Figure 16, the storage device comprises a memory 10 and a controller 20, the controller 20 being coupled to the memory 10 via a plurality of buses.

[0105] The controller 20 sends a command to the memory 10 via the command / address bus, and the command usually includes a read command or a duty cycle training mode command (DCA training command). The memory 10 reads data to the data bus based on the received command. The data here may be data stored in the memory cell or data generated by the memory based on the duty cycle training mode command. If the command is a duty cycle training mode command (DCA training command), the memory device compares the data received via the controller 20 with predetermined data, determines that the clock is ICLK if the first bit of the received data is the first bit of the predetermined data, determines that the clock is IBCLK if the first bit of the received data is the third bit of the predetermined data, and adjusts the duty cycle of the system clock signal accordingly to perform duty cycle training.

[0106] Those skilled in the art will understand that the embodiments described above are specific examples for realizing the present disclosure, and that in actual applications, various modifications can be made formally and in detail without departing from the spirit and scope of the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the scope of protection of the present disclosure shall be subject to the scope of protection of the claims.

Claims

1. It is memory, A plurality of memory cells arranged in an array, configured such that when a memory cell is selected, the data stored in the memory cell is read from the bit line to the first data bus Abus, The system includes a set circuit 100 connected to the first data bus Abus, which receives a set signal, and is configured to conduct the first data bus Abus and output a first data bit when the memory is in a first mode based on the set signal, and to disconnect the first data bus Abus and output a predetermined data bit when the memory is in a second mode based on the set signal, The first mode is a normal read mode, and the second mode is a duty cycle training mode, in which case the memory is configured.

2. The set circuit includes a setter, the set signal includes a first set signal BUSL and a second set signal BUSH, the input terminal of the setter is connected to the first data bus Abus, the first set terminal receives the first set signal BUSL, and the second set terminal receives the second set signal BUSH. In the first mode, the levels of the first set signal BUSL and the second set signal BUSH are different, and in the second mode, the levels of the first set signal BUSL and the second set signal BUSH are the same. The memory according to claim 1.

3. The system further includes a decoding circuit 200 configured to receive the register code of a mode register and generate the set signal by decoding it. The memory according to claim 1.

4. The system further includes a latch circuit 300 connected to the decoding circuit 200, which receives a mode register write signal MRW, and is configured to output the set signal when the mode register write signal MRW is valid, and to latch the set signal when the mode register write signal MRW is invalid. The memory according to claim 3.

5. The memory further comprises N parallel-to-serial conversion circuits, each of which is connected to correspond to M set circuits 100, receives data bits output from the M set circuits 100, samples the data bits based on a first clock signal, and generates second data by logic processing, each of which second data includes M bits of serial data bits, where N and M are even numbers. The memory according to claim 1.

6. The clock period of the first clock signal is M times the clock period of the system clock signal, and in each of the parallel-to-serial conversion circuits, the effective pulse periods of the first clock signal received by the M set circuits 100 do not overlap with each other. The memory according to claim 5.

7. When the memory is in the second mode, the serial data bit levels of M bits in each of the second data are the same, and N is equal to the number of bits in a predetermined data pattern. The memory according to claim 6.

8. The parallel-to-serial conversion circuit is further configured to receive a first write signal FIFO_IN, and if the first write signal FIFO_IN is valid, the parallel-to-serial conversion circuit is configured to trigger the generation of the second data. The memory according to claim 5.

9. The memory further comprises N selection circuits, each of which is configured to be connected to two of the parallel-to-serial conversion circuits to receive the corresponding second data. When the memory is in the first mode, the second data output by the N / 2 selection circuits in odd mode is the same as the second data output by the other N / 2 selection circuits in even mode. When the memory is in the second mode, the second data output by the N / 2 selection circuits in odd mode differs from the second data output by the other N / 2 selection circuits in even mode. Two parallel-to-serial converters connected to each of the N / 2 selection circuits are the same as two parallel-to-serial converters connected to the corresponding selection circuit of the other N / 2 selection circuits. The memory according to claim 5.

10. The N selection circuits are, When the memory is in the first mode, the second data output by the first N / 2 selection circuits in odd mode is the same as the second data output by the last N / 2 selection circuits in even mode. When the memory is in the second mode, the second data output by the first N / 2 selection circuits in odd mode is configured to be different from the second data output by the last N / 2 selection circuits in even mode. The two parallel-to-serial converters connected to each of the first N / 2 selection circuits are the same as the two parallel-to-serial converters connected to the corresponding selection circuit of the last N / 2 selection circuits. The memory according to claim 9.

11. The N selection circuits further receive a second clock signal and output two third data by sampling, each of which the third data includes N / 2 parallel second data. In odd-numbered modes, the second clock signal received by N / 2 of the selection circuits precedes the second clock signal received by the other N / 2 of the selection circuits by half a clock cycle. In even mode, the second clock signal received by N / 2 of the selection circuits is delayed by half a clock period compared to the second clock signal received by the other N / 2 of the selection circuits. The memory according to claim 9.

12. The second clock signal includes a second odd clock signal OCK and a second even clock signal ECK, the clock periods of the second odd clock signal OCK and the second even clock signal ECK are the same, and at the same time, only one of the second odd clock signal OCK and the second even clock signal ECK is valid. The odd mode corresponds to the second odd clock signal OCK being enabled, and the even mode corresponds to the second even clock signal ECK being enabled. In the odd mode, N / 2 of the selection circuits sample based on the second odd clock signal OCK, and the other N / 2 of the selection circuits sample based on the second odd clock delay signal OCKD. In the aforementioned even mode, N / 2 of the selection circuits sample based on the second clock even delay signal ECKD, and the other N / 2 of the selection circuits sample based on the second clock even signal ECK. The second odd clock delay signal OCKD is delayed by half a clock period from the second odd clock delay signal OCK, and the second even clock delay signal ECKD is delayed by half a clock period from the second even clock delay signal ECK. The memory according to claim 10.

13. Each selection circuit includes an odd selection circuit and an even selection circuit, the odd selection circuit includes an odd sampling circuit connected to one of the parallel-to-serial conversion circuits to receive first second data, the even selection circuit includes one selector MUX and one even sampling circuit, connected to two of the parallel-to-serial conversion circuits, one end of the selector MUX receives the first second data, the other end of the selector MUX receives second second data, and the control end of the selector receives a first selection signal SEL. In the odd mode, the odd selection circuit receives the first second data and samples it based on the second odd clock signal OCK. In the even mode, when the first selection signal SEL is at the first level, the selector MUX outputs the first second data; when the first selection signal SEL is at the second level, the selector MUX outputs the second second data; and the even sampling circuit samples based on the second clock even delay signal ECKD, or In the odd mode, the odd selection circuit receives the first second data and samples it based on the second odd clock delay signal OCKD. In the even mode, when the first selection signal SEL is at a first level, the selector MUX outputs the first second data; when the first selection signal SEL is at a second level, the selector MUX outputs the second second data; and the even sampling circuit is configured to sample based on the second even clock signal ECK. The memory according to claim 12.

14. An output module connected to N selection circuits, configured to receive two of the third data and output a fourth data to an input / output interface, wherein the fourth data includes N × M bits of serial data bits, further comprising the output module. The memory according to claim 11.

15. It is a memory device, A memory 10 according to any one of claims 1 to 14, The system comprises a controller 20, the controller 20 being coupled to the memory 10 and configured to cause the storage device to execute the following processes, the processes being: A storage device comprising: transmitting a command to the memory 10 via the controller 20, wherein the command includes a normal read command or a duty cycle training mode command, and the memory 10 reads data based on the received command; and, if the command is a duty cycle training mode command, the storage device compares the data received via the controller 20 with predetermined data, and determines and adjusts the duty cycle of the system clock signal.

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