Integration of devices onto the readout matrix

Abstract

The present invention relates to an optoelectronic device comprising: at least one pixel having an absorption layer made of a first material and disposed on a first surface of a first substrate, the absorption layer being intended to convert incident radiation into electric charge; a lower electrode for collecting the charge; and an upper electrode disposed on the absorption layer; and a readout circuit disposed on a second substrate and having at least one readout electrode dedicated to the pixel, wherein the first substrate has at least one via starting from a second surface of the first substrate opposite to the first surface, the via being electrically connected on one side to the lower electrode and on the other side to at least one hybrid connector for electrically and mechanically coupling the pixel to a readout electrode dedicated to the pixel.

Description

[Technical Field]

[0001] The present invention relates to a hybrid system, that is, a system consisting of two separate parts (each part made of a different material) assembled by an assembly layer. These systems may be optical, electronic, or optoelectronic, depending on the characteristics of the assembled parts. In particular, the present invention relates to integrating at least one photodetector structure based on a photoconductive material into a pixel matrix to form an imaging device.

[0002] Hybrid systems allow for the combination of two functionalities made from different materials. Examples include: - A detector in which the sensing part is combined with a readout circuit, enabling the collection and processing of the target signal. - For example, an electroluminescent display in which the light-emitting part is combined with a circuit for generating electrical signals suitable for light emission.

[0003] Specifically, the present art relates to the fabrication of an optoelectronic hybrid system comprising: an optical conversion portion based on at least one photoelectric element for generating charge carriers from incident photons; and an electronic portion consisting of readout circuits that are fully or partially mounted on a substrate and allow signals from each pixel of the optical conversion portion to be read out individually. Generally, the optical conversion portion comprises an absorption layer confined between two electrodes. The absorption layer converts an incident photon stream of wavelength λ into negative charge carriers ("electrons") in the conduction band and positive charges ("holes") in the valence band. The material used to make the absorption layer and the thickness of the absorption layer determine the frequency and amount of radiation absorbed. [Background technology]

[0004] Photoelectronic devices intended for the direct detection of ionizing radiation (X-rays) require absorption layers with larger lateral dimensions (width and length) compared to other photodetectors. Conventional materials used to create absorption layers within this range are either unsuitable for these large dimensions and reasonable manufacturing costs (e.g., single-crystal CdTe or Zn-doped single-crystal CdTe) or have limited absorption of the high energy required for X-ray imaging (e.g., amorphous selenium).

[0005] In relation to the present invention, semiconductor materials having a perovskite crystal structure offer a novel solution for fabricating absorption and photoconversion structures in optoelectronic devices. This type of material makes it possible to manufacture absorption layers with lateral dimensions exceeding 10 cm while maintaining photoconversion performance comparable to conventional materials. However, coupling a photoconversion portion based on an absorption layer having a perovskite crystal structure to an electronic portion presents several technical problems due to the mechanical, chemical, and thermal properties of perovskites. In relation to the description of the present invention, the term “coupling” means a set of specific operations and techniques for combining two parts having different functions (e.g., a readout circuit and a photodetector array). In relation to the description of the present invention, the term “perovskite layer” means a layer made of a material having a perovskite crystal structure or a perovskite-like structure. In relation to the description of the present invention, the perovskite used may be a 0-dimensional perovskite, a 1-dimensional perovskite, a 2-dimensional perovskite, a 3-dimensional perovskite, or a mixture of these different perovskites.

[0006] Zero-dimensional perovskites are perovskite-based crystalline materials that have a zero-dimensional nanometer structure. This means that the atoms within the crystal structure are uniformly arranged in a nanometer configuration. Zero-dimensional perovskites are often considered nanoparticles, nanocrystals, or nanocomposite materials.

[0007] One-dimensional perovskites are crystalline perovskite-based materials that have a linear one-dimensional structure. This means that the atoms within the crystal structure are uniformly arranged along a single direction. One-dimensional perovskites can take the form of nanowires, nanotubes, or nanofibers.

[0008] Two-dimensional perovskites are crystalline perovskite-based materials having a two-dimensional planar structure. This means that the atoms within the crystal structure are uniformly arranged on a flat surface. Two-dimensional perovskites can take the form of ultrathin sheets or films.

[0009] Three-dimensional perovskites are crystalline perovskite-based materials that have a three-dimensional structure. This means that the atoms within the crystal structure are uniformly arranged in three-dimensional space. Three-dimensional perovskites can exist in the form of bulk crystals or crystalline powders.

[0010] Integrating thick layers with a perovskite crystal structure onto a substrate (particularly the electronic portion of a hybrid system) presents several technical constraints. Specifically, there are no industrially viable, large-scale, and cost-competitive bonding technologies that would allow this type of material to be integrated into a hybrid system without compromising its mechanical, optical, and / or electronic properties.

[0011] Generally, two conventional integration techniques are used to assemble a photoconductive layer onto a readout matrix: "direct" integration and "indirect" integration (or hybridization). Direct integration involves directly depositing the absorption layer onto the readout circuit. In this case, direct integration presents several technical challenges. For example, the high thermal budget required to deposit the perovskite absorption layer by vacuum deposition or melting reduces the robustness of the electronic components of the readout circuit (transistors, metal wiring tracks, etc.). Furthermore, the temperature applied during deposition creates a difference in thermal expansion between the absorption layer and the substrate of the electronic portion of the optoelectronic device. This embrittles the mechanical structure of the absorption layer and causes adhesion problems at the interface of the layer. In addition, direct deposition can cause chemical reactivity problems between the metal wiring tracks of the readout circuit and the deposited perovskite absorption layer. Therefore, direct integration is not a preferred solution for integrating perovskite-based photodetector structures onto readout circuits.

[0012] Indirect integration (or hybridization) involves manufacturing the electronic and optical conversion components separately and then assembling them using hybridization methods (also known as coupling techniques). Hybridization of optoelectronic systems presents the following interdependent technical challenges: - Mechanical assembly of the optical conversion portion and the electronic portion that does not affect the optoelectronic and / or electrical performance of the hybrid device; - Interconnection is the construction of an electrical interconnection architecture between each pixel in the readout matrix and the corresponding detector device.

[0013] Accordingly, the present invention proposes an indirect integration technique to solve problems associated with coupling a thick perovskite layer to a readout circuit. The description of the present invention, detailed below, based on a perovskite layer, is provided for non-limiting illustrative purposes. The present invention also extends to materials other than perovskites, such as cadmium telluride (CdTe), zinc-doped cadmium telluride (CZT), amorphous selenium (Se), lead oxide (PbO), mercury iodide (HgI2), and lead iodide (PbI2). These materials may, in some cases, be in single-crystal and / or polycrystalline forms.

[0014] To better understand the problems addressed by this invention, we will first describe the structure of radiation detection devices manufactured by hybridization in the prior art. For this purpose, we consider the case of perovskite hybridized on a pixel matrix manufactured on a CMOS circuit.

[0015] Figure 1 is a partial cross-sectional view of a prior art photoelectron hybrid system having a photoelectron portion including a perovskite absorption layer.

[0016] The photoelectronic device D0 shown in Figure 1 is an ionizing radiation detector. It consists of a photoconversion part D0_opt with at least one pixel Pxl0 and an electronic part D0_elec with a readout circuit ROIC and a plurality of readout electrodes EL_read connected to the readout circuit ROIC.

[0017] The readout integrated circuit (ROIC) is fabricated on substrate sub2 using CMOS (complementary metal-oxide-semiconductor) technology, employing at least one transistor and a thin film of a conductive material, semiconductor material, or dielectric material. For each pixel Pxl0, a readout electrode EL_read is associated to read out the signal generated by the photocharge carriers produced by the photodetector structure of the pixel Pxl0.

[0018] Regarding the light conversion part of the device, for each pixel, it includes an absorption and light conversion layer AL common to all pixels, an upper electrode EL2 common to all pixels, and a lower electrode EL1 for collecting the generated charges. In the case of the architecture shown in FIG. 1, for each pixel, hybridization is performed using metal beads CEM that electrically connect the readout electrode EL_read to the lower electrode EL1 exclusively associated with the pixel. The beads CEM can be made of, for example, indium beads or copper micropillars, enabling each pixel to contact the readout circuit ROIC individually.

[0019] In the case of a perovskite absorption layer deposited over a large area, the surface of the perovskite on which the lower electrode EL1 is deposited is rough. Furthermore, since the surface state of the thick perovskite layer is difficult to control during manufacturing, this surface is not completely flat. Moreover, it is very difficult to manufacture a conductive lower electrode EL1 with a small matrix pitch (about 50 - 200 μm) over a large area on a perovskite material that is chemically sensitive to the resins, solvents, and etching agents used in photolithography. For these reasons, assuming depositing the lower electrode EL1 on the perovskite surface and implementing the hybridization process as described above on the perovskite surface is difficult due to chemical constraints, topological constraints, thermal constraints, and mechanical constraints. These problems related to the state (roughness, non-uniform flatness) of the surface on which the lower electrode EL1 is deposited limit the spatial resolution of the detector because the spacing between the lower electrodes EL1 is no longer controllable.

[0020] Therefore, it has been demonstrated that the prior art technical solutions of methods for pixelation, assembly, and interconnection on the readout circuit are not optimal for optoelectronic systems based on perovskite absorption layers. The same problems related to chemical incompatibility, thermal incompatibility, and mechanical incompatibility also exist in the following photodetection materials: cadmium telluride (CdTe), zinc-doped cadmium telluride (CZT), amorphous selenium (Se), lead oxide (PbO), mercury iodide (HgI2), and lead iodide (PbI2). These materials can be in single-crystalline and / or polycrystalline forms.

[0021] The scientific paper "High-sensitivity high-resolution X-ray imaging with soft-sintered metal halide perovskites" by Deumel et al. describes a process for manufacturing perovskite pellets by low-temperature powder compression. The described process includes an assembled layer made by liquefying MAPbI3 powder. The drawback of the described solution is that the composition of the assembled layer used affects the optoelectronic performance of the absorption layer. The nature, morphology, and contact surface with the substrate of the assembled layer modify the optoelectronic characteristics of the entire detector. Furthermore, the liquefaction process of MAPbI3 is not well controlled, and thereby this process is not suitable for industrial-scale manufacturing and large surface areas targeted for detectors. Several problems related to the drying of the liquefied layer being too fast and material loss due to solvent removal during the drying process occur.

Prior Art Documents

Non-Patent Documents

[0022]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0023] To overcome the limitations of existing solutions for hybridizing optoelectronic devices having at least one photodetector structure connected to a single readout electrode of a readout circuit, the present invention proposes several embodiments of an assembled hybrid system architecture. In particular, the present invention proposes an integration mode by indirect coupling that is suitable for the constraints of integrating thick layers of absorption photodetectors used in direct detectors for ionizing radiation. [Means for solving the problem]

[0024] The device according to the present invention is based on the fabrication of a thick absorption-type photodetector layer on a first substrate, which is adapted to the manufacturing conditions of the said layer. The photodetector layer is made from perovskite, or cadmium telluride (CdTe), or zinc-doped cadmium telluride (CZT), or amorphous selenium (Se), or lead oxide (PbO), or mercury iodide (HgI2), or lead iodide (PbI2). The first substrate according to the present invention ensures mechanical assembly and electrical conductivity between the electronic portion and the photoconversion portion.

[0025] The present invention makes it possible to decouple the manufacturing constraints of the absorption layer from the mechanical, thermal, chemical, and electrical constraints related to the readout circuit and the materials on its substrate, as well as the hybridization process.

[0026] Furthermore, the present invention enables the use of a substrate for the growth (or deposition) of a thick absorption layer having appropriate properties (mechanical, thermal, chemical, or electrical), and facilitates the direct deposition of said layer.

[0027] The present invention also helps overcome the problems of chemical compatibility, surface condition, flatness, and roughness of thick absorption layers faced in prior art hybrid solutions. The present invention also offers the possibility of reducing the lateral distance between lower electrodes and, consequently, the pixelation pitch, in order to improve the resolution of the detector.

[0028] More generally, the use of indirect integration according to the present invention is considered advantageous from an industrial standpoint because it allows certain critical steps related to the manufacturing technology of the readout circuit to be separated from the steps for manufacturing the photodetector structure (EL1, AL, EL2). Each of these two scientific and technological components can be manufactured, characterized, and tested individually before assembly.

[0029] One subject of the present invention is an optoelectronic device, - At least one pixel, An absorption layer made from a first material and disposed on a first surface of a first substrate, the absorption layer being intended to convert incident radiation into electric charge, • Lower electrode for collecting charge, • Upper electrode positioned on the absorption layer, at least one pixel having, - A readout circuit disposed on a second substrate and having at least one readout electrode dedicated to a pixel, Equipped with, The optoelectronic device comprises a first substrate having at least one via that starts from a second surface of the first substrate opposite to the first surface, the via being electrically connected on one side to a lower electrode and on the other side to at least one hybrid connector for electrically and mechanically coupling a pixel to a readout electrode dedicated to that pixel.

[0030] According to a particular aspect of the present invention, the first material is a perovskite, or cadmium telluride, or zinc-doped cadmium telluride, or amorphous selenium, or lead oxide, or mercury iodide, or lead iodide.

[0031] According to a particular aspect of the present invention, the via opens from a second surface of a first substrate to a first surface of a first substrate.

[0032] According to a particular aspect of the present invention, each pixel also comprises a conductive upper interface layer deposited on a first surface of a first substrate, wherein each via is confined between the end of the associated via and the volume of the absorption layer.

[0033] According to a particular aspect of the present invention, at least the via and / or upper interface layer constitutes a blocking layer for a predetermined type of charge carrier.

[0034] According to a particular aspect of the present invention, each via also comprises a conductive lower interface layer deposited on a second surface of a first substrate, the lower interface layer in contact with the lower end of the associated via.

[0035] According to a particular aspect of the present invention, the width of the lower interface layer is smaller than the separation distance between two adjacent readout electrodes.

[0036] According to a particular aspect of the present invention, the via is filled with a second conductive material.

[0037] According to a particular aspect of the present invention, the inner wall of the via is covered with a second conductive material.

[0038] According to a particular aspect of the present invention, vias are filled with a dielectric material.

[0039] According to a particular aspect of the present invention, the assembly formed by the upper interface layer, vias, and lower interface layer forms a capacitive element suitable for storing the generated charge.

[0040] According to a particular aspect of the present invention, in order to form a capacitive element suitable for storing the generated charge within the via, the via is filled with a stack comprising a dielectric material confined between two conductive materials.

[0041] According to a particular aspect of the present invention, the via does not open from a second surface of a first substrate to a first surface of a first substrate. The first substrate is made of a dielectric or semiconductor material, and the via is conductive.

[0042] According to a particular aspect of the present invention, the first substrate has a crystal structure that matches the lattice of the first material.

[0043] According to a particular aspect of the present invention, the first substrate is opaque to wavelengths in the visible region and / or to X-rays or gamma rays.

[0044] According to a particular aspect of the present invention, the first material is a CsPbBr3 perovskite.

[0045] Furthermore, the subject of this invention is a matrix image sensor equipped with the optoelectronic device according to the present invention.

[0046] Other features and advantages of the present invention will become clearer when viewed in conjunction with the accompanying drawings in the following description. [Brief explanation of the drawing]

[0047] [Figure 1] This diagram shows a cross-sectional view of an example of hybridization of optoelectronic devices using prior art. This diagram has already been explained. [Figure 2a] This shows a cross-sectional view of an example of hybridization of an optoelectronic device according to the first embodiment of the present invention. [Figure 2b] This shows a cross-sectional view of an example of hybridization of an optoelectronic device according to a second embodiment of the present invention. [Figure 2c] This shows a cross-sectional view of an example of hybridization of an optoelectronic device according to a third embodiment of the present invention. [Figure 2d] A cross-sectional view of an example of hybridization of an optoelectronic device according to a fourth embodiment of the present invention is shown. [Figure 2e] A cross-sectional view of an example of hybridization of an optoelectronic device according to a fifth embodiment of the present invention is shown. [Figure 3] A cross-sectional view of an example of hybridization of an optoelectronic device according to the sixth embodiment of the present invention is shown. [Figure 4]A cross-sectional view of an example of hybridization of an optoelectronic device according to the seventh embodiment of the present invention is shown. [Figure 5] This shows a cross-sectional view of an example of hybridization of an optoelectronic device according to the eighth embodiment of the present invention. [Figure 6] The process steps for manufacturing the optoelectronic device according to the present invention are shown. [Modes for carrying out the invention]

[0048] Figure 2a is a cross-sectional view of an example of hybridization of the optoelectronic device D1 according to a first embodiment of the present invention. The optoelectronic device D1 is intended, for example, for the detection of ionizing radiation. It is emphasized that the various features of the present invention are not limited to the described applications and are still applicable to all hybrid devices that require the assembly of layers for the electronic portion of the hybrid device.

[0049] The optoelectronic device D1 comprises an arbitrary photoconversion portion D1_opt based on at least one pixel Pxl for generating charge carriers from incident photons, and an electronic portion D1_elec consisting of a readout circuit ROIC with multiple readout electrodes EL_read for enabling individual readout of signals from each pixel Pxl of the photoconversion portion.

[0050] The readout circuit ROIC consists of a transistor-based processing chain fully mounted on a second substrate sub2. Alternatively, the readout circuit ROIC is partially mounted on the second substrate sub2. For example, only the selection transistors associated with each pixel are mounted on the second substrate sub2. The electrical signals generated by the optical conversion are propagated to an external processing chain mounted on another substrate (not shown). Alternatively, the second substrate sub2 supports only conductive transmission lines intended for propagating the generated electrical signals to an external processing chain mounted on another substrate (not shown). The present invention is compatible with the three readout circuit ROIC mounting configurations described above.

[0051] Each pixel Pxl includes an absorption layer AL, an upper electrode EL2, and a lower electrode EL1 for collecting the generated charges. The absorption layer AL is made of a first perovskite-type material and is disposed on the first surface of the first substrate sub1.

[0052] The absorption layer AL is intended to convert the incident radiation into charges. In the illustrated case, without loss of generality, the absorption layer is common to all pixels Pxl of the optoelectronic device D1. Alternatively, it is possible to define the extent of the absorption layer AL for each pixel by introducing a dielectric separation structure or by localizing the layer, for example using lithography techniques. The material used to make the absorption layer AL and its thickness determine the frequency and amount of radiation absorbed by the absorption layer. If the device D1 is intended for the detection of ionizing radiation (X-rays, gamma rays, ionizing particles, etc.), the first material is, for example, a material from the perovskite family or a perovskite derivative. The first material is a composite material ABX3: - A is · an inorganic cation such as cesium Cs, rubidium Rb, potassium K, sodium Na, or lithium Li, and · MA (methylammonium) = CH3-NH3 + , FA (formamidinium) = CH5N2 + , GA (guanidinium) = CH6N3 + ; EA (ethylammonium) = CH3CH2NH3 + ; DMA (dimethylammonium) = C2H6NH2 + ; AC (acetamidinium) = C2H3N2H4 + ; AZ (azetidinium) = C3H6NH2 + ; TBA (tetrabutylammonium) = C4H9NH3 + ; PYRI (pyridinium) = C5H5NH + ; PYRO (pyrrolidinium) = C4H8NH2 + ; isoP (isopropylammonium) = C3H7NH3 + ; PIP (piperidinium) = C5H 10 NH2 +Organic cations such as, The first group of elements, or alloy of the above elements from the first group of elements Selected from; - B is, Inorganic cations such as lead (Pb), tin (Sn), germanium (Ge), silicon (Si), strontium (Sr), barium (Ba), europium (Eu), thulium (Tm), ytterbium (Yb), and mercury (Hg), •Organic cations such as MDABCO=N-methyl-1,4-diazabicyclo[2.2.2]octane and ODABC=N-hydroxyl-N'-diazabicyclo[2.2.2]octanium, The second set of elements, or alloy of the above elements of the second group of elements Selected from; - X is selected from a third group of elements including halogens such as bromine (Br), iodine (I), chlorine (Cl), and fluorine (F), or from alloys of the above elements of the third group of elements.

[0053] Alternatively, the first material has the chemical formula A2C 1+ D 3+ It is a perovskite having X6, - A and X are selected from the first and third element groups, respectively; - C is, Inorganic cations such as gold (Au), silver (Ag), copper (Cu), thallium (Tl), lithium (Li), cesium (Cs), sodium (Na), rubidium (Rb), and potassium (K) The fourth group of elements, or alloy of the above elements from the fourth element group Selected from; - D is, Inorganic cations such as gold (Au), aluminum (Al), gallium (Ga), indium (In), tin (Sn), bismuth (Bi), and antimony (Sb) The fifth group of elements, or alloy of the above elements of the fourth element group Selected from.

[0054] Alternatively, the first material is chemical formula A2B 4+X6 or A3B2 3+ The perovskite has X9, where A, B, and X are selected from the first, second, and third element groups, respectively.

[0055] Alternatively, the first material is a chalcogenide or rudorffite.

[0056] The first material is derived from the perovskite family and may have a 0-dimensional, 1-dimensional, 2-dimensional, or 3-dimensional structure.

[0057] At least one of the lateral dimensions (length, width) of the absorbent layer AL is greater than 0.1 cm, preferably greater than 1 cm, and more preferably greater than 10 cm. More specifically, the absorbent layer AL is 0.01 cm 2 Larger, preferably 1 cm 2 Larger, and even more preferably 100 cm 2 It has a larger surface area. The thickness of the absorption layer AL ranges from several hundred nanometers to several millimeters, for example, 10 mm.

[0058] As an example in the field of medical X-ray imaging, when using a CsPbBr3 type perovskite composition, the following is used: - A layer of CsPbBr3 with a thickness of 100 μm to 400 μm for X-ray mammography. - A layer of CsPbBr3 with a thickness of more than 0.65 mm for X-ray radiography (in the range of 30-70 keV) to have an absorption of more than 90%. - A layer of CsPbBr3 with a thickness of more than 1.4 mm for use in X-ray radiography (in the range of 40-120 keV) to have an absorption of more than 90%.

[0059] The upper electrode EL2 is deposited on the absorption layer AL. In the illustrated case, without loss of generality, the upper electrode EL2 is made of a conductive layer common to all pixels Pxl. Alternatively, it is possible to form multiple upper electrodes EL2 made of several different conductive layers deposited on the absorption layer AL. The upper electrode EL2 may consist of a single layer or a stack of layers. It may also consist of at least one blocking layer to allow dark current to be minimized. This blocking layer may be essentially semiconducting or insulating. This blocking layer may be made of dielectric polymers (polyester, polyimide, polycarbonate, PMMA, parylene, PVC) or semiconducting polymers (poly-(3-hexylthiophene) (also known as P3HT), poly(triarylamine) (also known as PTAA), poly(9,9-dioctylfluorene-alt-N-(4-secondary butylphenyl)diphenylamine) (also known as TFB)).

[0060] In the illustrated example, the readout integrated circuit ROIC is fabricated on a second substrate sub2 using multiple transistors and thin layers of conductive material, semiconductor material, or dielectric material, according to CMOS (complementary metal-oxide-semiconductor) technology or TFT technology in amorphous silicon, IGZO, or organic (OTFT) silicon. Each pixel Pxl is associated with a readout electrode EL_read for reading out the signal generated by the photocharge carriers generated by the absorption layer AL of the pixel Pxl.

[0061] Device D1 also includes multiple hybridization connector CEMs. For example, hybridization is performed for each pixel Pxl by a metal bead CEM electrically connected to a read electrode EL_read exclusively associated with that pixel. The bead CEM can be made, for example, an indium bead or a copper micropillar, allowing each pixel to contact the read circuit individually. Other hybridization means can be used to create the hybridization connector CEMs, for example, but are not limited to the following: - Solder balls having at least one metallic element (bump) made of Pb, Sn, Ag, Au, Cu, Bi, or In, deposited by vapor deposition, screen printing, lithography, laser ablation, electrolytic deposition, or bead arrangement, and then assembled by brazing, soldering, photo-induced crosslinking, or thermocompression bonding; - Polymer balls (polymer bumps) deposited by screen printing and / or assembled by photo-induced crosslinking or thermocompression bonding; - Au, Cu, or Ni stud bumps assembled by thermocompression bonding; - Cu pillars assembled by brazing; - A conductive adhesive layer (e.g., a carbon-based adhesive) made to a size that efficiently collects charge along an axis perpendicular to the first substrate sub1 and minimizes electrical leakage in a plane parallel to the first substrate sub1; - Anisotropic conductive film (ACF) or anisotropic conductive adhesive ink. More specifically, a film or ink based on magnetic beads that can be oriented under a magnetic field.

[0062] A first substrate sub1 is positioned between the absorption layer AL and a plurality of hybridization connectors CEM. For each pixel Pxl, the first substrate sub1 includes at least one via V1 starting from a second surface of the first substrate sub1 opposite to the first surface on which the absorption layer AL is mounted. The via V1 is a via extending through the substrate sub1. For each pixel Pxl, at least one via V1 is a conductive via having a lower end in contact with the hybridization connector CEM and another end in contact with the absorption layer AL. At least one via V1 is filled with a second conductive material.

[0063] Alternatively, the inner wall of via V1 is covered with a second conductive material. In the illustrated embodiment, via V1 functions as the lower electrode EL1. For each pixel Pxl, via V1 ensures electrical conduction between the absorption layer AL and the read electrode EL_read dedicated to that pixel via the hybridized connector CEM. The opening of via V1 may be circular, parallelepiped, triangular, or any other shape. The surface area of ​​the via V1 opening for a pixel Pxl is preferably less than or equal to the surface area of ​​the read electrode EL_read associated with that pixel Pxl. For cylindrical vias, the diameter of via V1 is 100 nm to 10 mm. The second conductive material may be a metal (In, Bi, Sn, Pb, Cr, Pt, Ag, Au, Ti), a conductive organic material (polymer, graphene ink, carbon black-based ink, carbon nanotube-based ink), an Ag particle-based ink, or a conductive oxide (ITO, SnO2, TiO2).

[0064] A voltage is applied between the upper electrode EL2 and the lower electrode EL1, thereby allowing the generated charge to move to the lower electrode EL1. The amount of generated charge carriers collected by the lower electrode EL1 determines the amplitude of the readout signal associated with the pixel Pxl.

[0065] The first substrate sub1 is made of an inorganic material, an organic material, or a hybrid material. For example, substrate sub1 may be made of glass, plastic, silicon, or ceramic. The first substrate sub1 may be a single-layer substrate or a stack of several layers of several materials. The thickness of the first substrate sub1 is 1 μm to 10 mm.

[0066] Advantageously, substrate sub1 has a uniform, smooth, and flat underside that facilitates indirect coupling with the electronic portion. This offers the advantage of overcoming the surface condition, flatness, and roughness issues of the thick perovskite layer surface faced in prior art hybridization solutions. Furthermore, it offers the possibility of reducing the lateral distance separating the lower electrodes and, consequently, reducing the pixel pitch, in order to improve the detector resolution.

[0067] Advantageously, substrate sub1 is made from a material with a thermal expansion coefficient within the range of [CTE-50%, CTE+50%], where CTE is the thermal expansion coefficient of the absorption layer AL. For example, in the case of a CsPbBr3 absorption layer, the thermal coefficient of substrate sub1 is 1.5 × 10⁻⁶. -5 °K -1 ~4.5×10 -5 °K -1 This makes it possible to solve the problem of thermal expansion differences that arise during high-temperature deposition of the absorption layer AL. As a result, the mechanical robustness of the absorption layer AL is improved, and warping or cracking phenomena caused by thermal expansion differences after deposition are avoided.

[0068] Generally, substrate sub1 has chemical, thermal, mechanical, and electrical characteristics suitable for the process conditions for depositing the perovskite layer. Substrate sub1 plays two roles: - Electrical role: Ensures local electrical conduction between the two surfaces mentioned above to connect the absorption layer AL (source of generated charge) to the associated readout electrode EL_read. - Mechanical role: It functions as a mechanical support for the absorption layer, adapting to the specific constraints of perovskite deposition (high temperature, chemical inertness, etc.) and constraints related to hybridization techniques.

[0069] Advantageously, the use of the first substrate sub1 with via V1 allows the manufacturing constraints of the perovskite absorption layer AL to be separated from the mechanical strength constraints, thermal constraints, chemical constraints, and electrical constraints of the readout circuit ROIC.

[0070] Advantageously, the upper surface of the first substrate sub1 is provided with a germination layer made of perovskite material to promote the growth of the absorption layer AL by epitaxy or heteroepitaxy. Alternatively, the first substrate sub1 has a crystal lattice that matches the lattice of the first material constituting the absorption layer AL.

[0071] For example, if the material of the absorption layer AL is CsPbBr3, it may be advantageous to perform heteroepitaxy on a first substrate sub1 made of PbS, FeS2 (pyrite), mica (e.g., muscovite), PbSnSe, or GaAs. If the material of the first substrate sub1 does not allow direct heteroepitaxy of the absorption layer AL, an intermediate step can be taken by growing a surface layer on the first substrate sub1 by heteroepitaxy, and then performing perovskite heteroepitaxy on this surface layer. For example, lead chalcogenides are suitable for perovskite heteroepitaxy, but they are difficult to obtain in wafer substrate form. Therefore, it is possible to grow a layer of lead chalcogenide on the first substrate sub1 (e.g., by molecular beam epitaxy), and then grow a perovskite absorption layer on the lead chalcogenide layer.

[0072] Advantageously, the first substrate sub1 is made entirely or partially of a material that does not transmit wavelengths in the visible, ultraviolet, or near-infrared regions, or X-rays or gamma rays. This allows for the formation of local or general optical shielding to protect the photosensitive components of the readout circuit ROIC. For example, the performance of certain transistor technologies degrades when exposed to light or radiation. Examples include transistors based on amorphous silicon or indium gallium zinc oxide (IGZO). Optical shielding can be achieved by using an opaque layer within the structure of the first substrate sub1, by incorporating a pigment (carbon black) into the volume of the first substrate sub1, or by introducing atoms of an element with a high atomic number (e.g., Bi carboxylate) on the surface or within the volume of the substrate sub. In the case of local optical shielding, it is preferable to place the transistors of the readout circuit under the shielding zone of the first substrate sub1.

[0073] Figure 2b is a cross-sectional view of an example of hybridization of an optoelectronic device D1 according to a second embodiment of the present invention. In the illustrated embodiment, the optoelectronic device D1 also comprises, for each via V1, a conductive upper interface layer C1 deposited on a first surface of a first substrate sub1. The upper interface layer C1 is confined between the end of the associated via V1 and the volume of the absorption layer AL. Thus, each upper interface layer C1 is deposited on the upper surface of the substrate sub1. Each via V1 opens to the upper interface layer C1 associated with it. The upper interface layer may, but is not limited to, metals (In, Bi, Sn, Pb, Cr, Pt), conductive organic materials (polymers, graphene ink, carbon black ink, carbon nanotube ink), Ag-based inks, conductive oxides (ITO, SnO2, TiO2), or any other conductive material.

[0074] If via V1 is a conductive via, the lower electrode EL1 is formed from at least one via V1 and the associated upper interface layer C1. This modified form has the advantage of increasing the charge collection area between the absorption layer AL and via V1, and therefore improves the collection and transfer of generated charge.

[0075] Alternatively, an assembly formed by the upper interface layer C1 alone, or by the upper interface layer C1 and a second material filling each via V1, is formed of at least one material that functions as a blocking layer (the materials of the upper interface layer C1 and the vias V1 may differ). Thus, the assembly functions as a blocking layer for one type of charge carrier (holes or electrons).

[0076] If a blocking layer needs to block electron injection from the lower electrode EL1 to the absorption layer AL in the dark state, it must have an energy barrier of at least 0.4 eV. If the blocking layer is a metal, this barrier is defined between the work function of the metal and the bottom of the conduction band of the semiconductor material of the absorption layer AL. If the blocking layer is a semiconductor, this barrier is defined between the work function of the electrode metal and the bottom of the conduction band of the semiconductor (in the case of organic semiconductors, also called the LUMO (Lowest Unoccupied Molecular Orbital), also known as electron affinity).

[0077] If the blocking layer needs to block the injection of holes from the lower electrode EL1 to the absorption layer AL in the dark state, it must have an energy barrier of at least 0.4 eV. If the blocking layer is a metal, this barrier is defined between the work function of the metal and the top of the valence band of the semiconductor material of the absorption layer AL. If the blocking layer is a semiconductor, this barrier is defined between the work function of the conductive electrode and the top of the valence band of the semiconductor (in the case of organic semiconductors, also called the HOMO (Highest Occupied Molecular Orbital), also known as the ionization potential). This variant has the advantage of minimizing the dark current of the detector device D1.

[0078] Materials that can be used as blocking layers include, but are not limited to, SiO2, HfO2, Al2O3, LiF, MgF2, polymers (such as polyimide, PVC, PMMA, parylene, PC, PVDF, PVDF-TrFE), ceramics, and organic, inorganic, or organic / inorganic hybrid dielectrics such as perovskites. Alternatively, materials used to function as blocking layers include organic, inorganic, or organic / inorganic hybrid semiconductors such as silicon, SnO2, TiO2, NiOx, PTAA, TFB, P3HT, perylenediimide, ascendiimide, fullerenes and fullerene derivatives, and perovskites.

[0079] Figure 2c is a cross-sectional view of an example of hybridization of an optoelectronic device D1 according to a third embodiment of the present invention. Compared to the first embodiment, the optoelectronic device D1 also includes, for each via V1, a conductive lower interface layer C2 deposited on the second surface of the first substrate sub1. The lower interface layer C2 is in contact with the lower end of the associated via V1 and the associated hybridization connector CEM. The lower interface layer C2 may be made from metals (In, Bi, Sn, Pb, Cr, Pt), conductive organic materials (polymers, graphene inks, carbon black inks, carbon nanotube inks), Ag-based inks, conductive oxides (ITO, SnO2, TiO2), or any other conductive material.

[0080] If via V1 is a conductive via, the lower electrode EL1 is formed by at least one via V1 and the associated lower interface layer C2. This modified form has the advantage of improving the contact surface between via V1 and the hybridized connector CEM. The improved contact surface minimizes the electrical resistance to charge transfer from the absorption layer AL to the read electrode El_read.

[0081] Alternatively, the assembly formed by a second material filling each via V1, or by the second material filling each via V1 and the lower interface layer C2, includes at least one material that functions as a blocking layer (the materials of the lower interface layer C2 and the vias V1 may differ). Thus, the assembly functions as a blocking layer for one type of charge carrier (holes or electrons). The blocking layer in this variant can be made in a manner similar to the blocking layer described in the embodiment of Figure 2b.

[0082] Figure 2d is a cross-sectional view of an example of hybridization of the optoelectronic device D1 according to a fourth embodiment of the present invention. The device D1 comprises the upper interface layer C1 and the lower interface layer C2 described above.

[0083] If via V1 is conductive, the lower electrode EL1 is formed by a combination of via V1 and the associated upper interface layer C1 and lower interface layer C2.

[0084] Alternatively, the assembly formed by the upper interface layer C1, or the upper interface layer C1 and a second material filling each via V1, or the assembly formed by the upper interface layer C1, the second material filling each via V1, and the lower interface layer C2, includes at least one material that functions as a blocking layer (the materials of the upper interface layer C1, the lower interface layer C2, and the vias V1 may differ). Thus, the assembly functions as a blocking layer for one type of charge carrier (holes or electrons). The blocking layer in this variant can be manufactured in a manner similar to the blocking layer described in the embodiment of Figure 2b. This variant has the advantage of minimizing the dark current of the detector device D1. Alternatively, the second material filling each via V1 is a dielectric. The combination of the upper interface layer C1, the vias V1, and the lower interface layer C2 forms a capacitive element Cap1 suitable for storing the generated charge. This has the advantage of incorporating a storage capacitance for storing the generated charge into the first substrate sub1. Therefore, it is possible to create an optoelectronic device with the function of accumulating the generated charge. The upper interface layer C1 functions simultaneously as the lower electrode EL1 of the photodetector structure and as the first conductive plate of the capacitive element Cap1. The lower interface layer C1 functions as the second conductive plate of the capacitive element Cap1. The dielectric-filled via V1 functions as the insulating volume of the capacitive element Cap1. The dielectric material preferably has a dielectric constant of 10 or more and can be selected from ceramic fillers such as ZrO2, TiO2, or PZT, polymers (PVDF), or composite materials having ceramics.

[0085] Figure 2e is a cross-sectional view of an example of hybridization of the optoelectronic device D1 according to a fifth embodiment of the present invention. The capacitive element Cap1 is formed within via V1 by the following stack: conductor M2 / dielectric M1 / conductor M2'. The functionality of via V1 as a capacitive element due to the internal stack is consistent with all embodiments of the present invention described above.

[0086] Figure 3 is a cross-sectional view of an example of hybridization of an optoelectronic device D1 according to a sixth embodiment of the present invention. The first substrate sub1 is made of a dielectric or semiconductor material. The via V1 does not open from the lower surface of the first substrate sub1 to the upper surface of the first substrate sub1. The via V1 is conductive. The volume confined between the upper end of the via V1 and the upper surface of the first substrate has a thickness d1 of 100 μm or less, preferably less than 50 μm, and more preferably less than 10 μm. When the device is not exposed to radiation, this confined volume acts as a blocking layer against charge injection from the lower electrode. This allows for a reduction in the dark current of the optoelectronic device D1. When the absorption layer AL is exposed to incident radiation, the dielectric zone d1 becomes slightly conductive under the flow of incident radiation or traps charge at the interface between Sub1 and the absorption layer AL, allowing all or part of the electric field to propagate to the absorption layer AL. The generated charge can then be read out by the capacitive effect.

[0087] Figure 4 is a cross-sectional view of an example of hybridization of an optoelectronic device D1 according to a seventh embodiment of the present invention. The hybridization connector CEM is an anisotropic conductive layer. Preferably, the read electrode EL_read has an outward topology with respect to the surface of the second substrate sub2. The anisotropic conductive layer is, for example, an epoxy resin containing conductive microbeads. Once molded by compression, it exhibits conductivity only in a direction perpendicular to the surface of the first substrate sub1. The diameter of at least one crushed bead is at least smaller than the inter-pixel distance L2. For each pixel Pxl, the electrode EL1 comprises a via V1 and preferably a lower interface layer C2. Each lower interface layer C2 has a width L1 smaller than the separation distance L2 between two adjacent read electrodes EL_read. This allows indirect coupling without requiring an alignment process. Specifically, the read electrode EL_read and the unaligned lower interface layer C2 do not cause a short-circuit risk between two adjacent read electrodes EL_read due to the insertion of the unaligned lower interface layer C2.

[0088] Alternatively, each lower interface layer C2 has a width L1 that is smaller than the sum of the inter-pixel distance L2 and the width of the readout electrode EL_read.

[0089] Figure 5 is a cross-sectional view of an example of hybridization of an optoelectronic device D1 according to an eighth embodiment of the present invention. The hybridization connector CEM is an anisotropic conductive layer. Preferably, the read electrode EL_read has an outward topology with respect to the surface of the second substrate Sub2. The diameter of at least one grinding bead is at least smaller than the inter-pixel distance L2. For each pixel Pxl, the lower electrode EL1 is formed by a plurality of adjacent vias V1. Increasing the number of vias improves the conductivity of the lower electrode EL1, and therefore facilitates the collection of charge generated in the detection device D1. The surface area of ​​the via V1 opening of a pixel Pxl is less than or equal to the surface area of ​​the read electrode EL_read associated with that pixel Pxl. The distance separating two vias V1 is smaller than the distance separating two adjacent read electrodes EL_read.

[0090] Figure 6 shows the steps of process P1 for manufacturing the optoelectronic device D1 according to the present invention.

[0091] The first step is to manufacture a first substrate sub1 having a plurality of vias V1. The first substrate sub1 has a first surface and a second opposite surface. The vias V1 may or may not be through holes starting from the second surface. According to the first variant, this step is carried out by perforating the first substrate sub1. The perforation operation can be carried out using a subtractive method, such as chemical or physical etching, or laser ablation. A laser beam is applied to a single point on the second surface of the substrate sub1 in order to create holes by melting and evaporation. By adjusting the wavelength and radiant power according to the material of the first substrate sub1, perforation with nanometer precision can be performed. The laser beam scans a selected zone in order to create holes within the volume of the first substrate sub1. For example, in the case of a first substrate made of polyimide, a laser with a wavelength of 532 nm is suitable for forming a series of vias V1 having a diameter of 100 nm to 1000 μm. Laser technology offers several advantages over conventional methods: speed, precision, flexibility, and cost-effectiveness. Furthermore, laser drilling reduces the susceptibility of the first substrate sub1 to burnout, without affecting the mechanical robustness of the substrate sub1.

[0092] Alternatively, a first substrate sub1 having multiple vias V1 can be manufactured by filling a fakir matt-type mold with thermosetting resin.

[0093] Once the perforated structure is obtained, the pore is filled entirely or partially with one or more materials according to the manufactured embodiment of the present invention. The filling may be complete or consist of deposition on the inner wall. The material in via V1 may be a conductive material, an insulating material, or a stack of several different materials.

[0094] The second step ii) is to deposit the absorption layer AL on the first surface of the first substrate sub1, as described above. The absorption layer AL is made of a material having a perovskite crystal structure. The deposition of the absorption layer can be carried out by direct or indirect deposition. Advantageously, the absorption layer is deposited by direct deposition. In this case, non-inclusively, the following techniques may be used: liquid crystal growth, liquefaction, spraying, melt deposition, powder sintering, vacuum deposition by close-space sublimation (CSS), vacuum deposition by evaporation, application of microcrystalline paste, epitaxy, and heteroepitaxy.

[0095] The third step (iii) is to deposit the upper electrode EL2 on the absorption layer AL. This step can be carried out using standard techniques for depositing thin metal layers or conductive inks.

[0096] The fourth step iv) is to fabricate a readout circuit ROIC on the second substrate sub2. The readout circuit ROIC has multiple different readout electrodes EL_read on its upper surface. Each readout electrode EL_read is dedicated to one pixel Pxl. The fabrication of the multiple different readout electrodes EL_read is carried out, for example, by one or more sequences of deposition, lithography, and etching of conductive layers used in the microtechnology and nanotechnology industries. The fourth step iv) is independent of the preceding steps. The fourth step iv) may be carried out before or concurrently with steps i) to iii).

[0097] At the end of steps i) to iii), the manufacturing of the optical conversion portion D1_opt of device D1 according to the present invention is completed. At the end of the fourth step iv), the manufacturing of the electronic portion D1_elec of device D1 according to the present invention is completed.

[0098] The fifth step (v) is to assemble the optical conversion portion D1_opt and the electronic portion D1_elec via the hybridization connector. This assembly is performed so that for each pixel Pxl, at least one via V1 is electrically connected to a dedicated read electrode El_read via at least one hybridization connector CEM. Optionally, during assembly, an alignment sub-step is performed to ensure that the optical conversion portion D1_opt is precisely aligned with the electronic portion D1_elec. Different hybridization methods can be used to manufacture the hybridization connector CEM, but are not limited to these: - Metal solder balls (bumps) assembled by brazing, soldering, or thermocompression bonding; - Polymer balls (polymer bumps) deposited by screen printing and assembled by photo-induced crosslinking or thermocompression bonding; - A conductive adhesive layer made to a size that efficiently collects charge along an axis perpendicular to the first substrate sub1 and minimizes electrical leakage in a plane parallel to the first substrate sub1; - Anisotropic conductive film (ACF) or anisotropic conductive adhesive ink.

[0099] To manufacture the device D1 shown in Figures 2b and 2d, process P1 also includes step ii') of depositing a plurality of upper interface layers C1 on a first surface of a first substrate sub1 aligned with the upper end of via V1. This step ii') must be performed before step ii) of depositing the absorption layer AL.

[0100] To manufacture the device D1 shown in Figures 2c and 2d, process P1 also includes step ii'') depositing a plurality of lower interface layers C2 on a second surface of a first substrate sub1 aligned with the lower end of via V1. This step ii'') must be performed before assembly step v).

[0101] Alternatively, step ii) of depositing an absorption layer AL on the first substrate sub1 is performed before the step of manufacturing vias V1 on the first substrate sub1.

Claims

1. The optoelectronic device (D1) is, At least one pixel (Pxl), An absorption layer (AL) made from perovskite and disposed on a first surface of a first substrate (sub1), wherein the absorption layer (AL) is intended to convert incident radiation into electric charge, The lower electrode (EL1) for collecting the aforementioned charge, The upper electrode (EL2) is disposed on the absorption layer (AL), A pixel (Pxl) having, A readout circuit (ROIC) is disposed on a second substrate (sub2) and includes at least one readout electrode (EL_read) dedicated to the pixel (Pxl), Equipped with, The first substrate (sub1) comprises at least one via (V1) starting from a second surface of the first substrate (sub1) opposite to the first surface, the via (V1) being electrically connected on one side to the lower electrode (EL1) and on the other side to at least one hybridization connector (CEM) for electrically and mechanically coupling the pixel (Pxl) to the read electrode (EL_read) dedicated to the pixel (Pxl). Optoelectronic device (D1).

2. The optoelectronic device (D1) according to claim 1, wherein the via (V1) opens from the second surface of the first substrate (sub1) to the first surface of the first substrate (sub1).

3. The optoelectronic device (D1) according to claim 1 or 2, wherein each pixel (Pxl) also comprises a conductive upper interface layer (C1) deposited on the first surface of the first substrate (sub1), the upper interface layer (C1) being confined between the end of the associated via (V1) and the volume of the absorption layer (AL).

4. The optoelectronic device (D1) according to claim 3, wherein at least the via (V1) and / or the upper interface layer (C1) constitute a blocking layer for a predetermined type of charge carrier.

5. The optoelectronic device (D1) according to any one of claims 2 to 4, wherein each pixel (Pxl) also comprises a conductive lower interface layer (C2) deposited on the second surface of the first substrate (sub1), and the lower interface layer (C2) is in contact with the lower end of the associated via (V1).

6. The optoelectronic device (D1) according to claim 5, wherein the width (L1) of the lower interface layer (C2) is smaller than the separation distance (L2) between two adjacent read electrodes (EL_read).

7. The via (V1) is filled with a second conductive material, Alternatively, the optoelectronic device (D1) according to any one of claims 1 to 6, wherein the inner wall of the via (V1) is covered with a second conductive material.

8. The via (V1) is filled with a dielectric material, The optoelectronic device (D1) according to claim 5 or 6, combined with claim 4, wherein the assembly formed by the upper interface layer (C1), the via (V1), and the lower interface layer (C2) forms a capacitive element (Cap1) suitable for storing the generated charge.

9. The optoelectronic device (D1) according to any one of claims 1 to 6, wherein the via (V1) is filled with a stack including a dielectric material (M1) confined between two conductive materials (M2, M2') in order to form a capacitive element (Cap1) suitable for storing the generated charge within the via.

10. The optoelectronic device (D1) according to claim 1, wherein the via (V1) does not open from the second surface of the first substrate (sub1) to the first surface of the first substrate (sub1), the first substrate is made of a dielectric material or a semiconductor material, and the via (V1) is conductive.

11. The optoelectronic device (D1) according to any one of claims 1 to 10, wherein the first substrate (sub1) has a crystal structure that matches the crystal structure of the first material.

12. The optoelectronic device (D1) according to any one of claims 1 to 11, wherein the first substrate (sub1) does not transmit wavelengths in the visible region and / or X-rays or gamma rays.

13. The first material is CsPbBr ３ The optoelectronic device (D1) according to any one of claims 1 to 12, wherein the optoelectronic device is a perovskite.

14. A matrix image sensor comprising the optoelectronic device according to any one of claims 1 to 13.

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