Method for evaluating chip power consumption, method for generating power consumption models, and computer devices

Abstract

This application relates to a method for evaluating chip power consumption, a method for generating a power consumption model, and a computer device. The method for evaluating chip power consumption includes the steps of: determining static modeling parameters and dynamic evaluation parameters of a chip to be measured; calculating intermediate calculation results based on the static modeling parameters and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation results; and obtaining evaluation results of the power consumption of the chip to be measured based on the dynamic evaluation parameters and the target power consumption model. Here, the static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, the dynamic evaluation parameters are chip design parameters that change within the power consumption constraints of the current power consumption scene, and the first mapping relationship indicates the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraints. The present invention solves the problem of low efficiency in chip power consumption evaluation methods and realizes an efficient and accurate chip power consumption evaluation method.

Description

[Technical Field]

[0001] This application claims priority to Chinese patent application CN202310773235.3, filed on June 28, 2023, with the title of the invention being "Method for evaluating chip power consumption, method for generating a power consumption model, and computer device," and its entire contents are incorporated herein by reference.

[0002] This application relates to the technology of chips, and more particularly to methods for evaluating chip power consumption, methods for generating power consumption models, and computer devices. [Background technology]

[0003] With advancements in manufacturing processes and packaging technologies, the integration density (i.e., the number of transistors per unit volume) and power consumption density of integrated circuits are constantly increasing. Consequently, power consumption has become a crucial consideration in integrated circuit design. In related technologies, power consumption evaluation techniques are typically used to evaluate integrated circuit chips at the Register Transfer Level (RTL), pre-physical implementation, and post-physical implementation stages. A common feature of these three stages of power consumption evaluation is that all chip elements related to power consumption evaluation must be input at once before calculating the power consumption of the overall design. As a result, for chips of a certain size, the amount of input data related to power consumption calculation becomes very large, making the efficiency of evaluating the power consumption of integrated circuit chips very low.

[0004] Currently, no effective solution has been proposed to address the problem of low efficiency in detecting chip power consumption in related technologies. [Overview of the project] [Problems that the invention aims to solve]

[0005] The embodiments of this application aim to provide a method for evaluating chip power consumption, a method for generating a power consumption model, and a computer device that can solve the problem of low detection efficiency of chip power consumption in the prior art. [Means for solving the problem]

[0006] In the first aspect, an embodiment of the present invention provides a method for evaluating chip power consumption. This method is The steps include determining the static modeling parameters and dynamic evaluation parameters of the chip to be measured, The steps include: calculating intermediate calculation results based on the static modeling parameters and the first mapping relationship, and generating a target power consumption model that stores the intermediate calculation results; The step includes obtaining an evaluation result of the power consumption of the chip to be measured based on the dynamic evaluation parameters and the target power consumption model, Here, the static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, the dynamic evaluation parameters are chip design parameters that change within the power consumption constraints of the current power consumption scene, and the first mapping relationship shows the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraints.

[0007] In some embodiments, the step of determining the static modeling parameters of the chip under test includes obtaining static factor information corresponding to scene demand information and determining the static modeling parameters of the chip under test from the static factor information. and / or The step of determining the dynamic evaluation parameters of the chip to be measured is: This includes acquiring dynamic factor information corresponding to the scene demand information and determining the dynamic evaluation parameters of the chip to be measured from the dynamic factor information.

[0008] In some embodiments, generating the target power consumption model storing the intermediate calculation results includes: determining a data template corresponding to the scene demand information; obtaining model data required for the data template of the intermediate calculation results; generating a target power consumption model based on the model data and the data template.

[0009] In some embodiments, the target power consumption model includes model detailed data, the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data, and / or the target power consumption model includes model metadata, the model metadata includes at least model description data, and the model description data is used to describe the attributes of the target power consumption model.

[0010] In some embodiments, the static modeling parameters include a hierarchical sub-module of at least one measured chip, and the intermediate calculation results include intermediate calculation results corresponding to the hierarchical sub-module.

[0011] In some embodiments, each of the hierarchical sub-modules includes a plurality of element units, and the method further includes: for each of the element units, obtaining static modeling parameters corresponding to different power consumption types of the element unit and a first mapping relationship corresponding to different power consumption types; calculating intermediate calculation results of different power consumption evaluation types for different element units based on the static modeling parameters of the different power consumption types and the first mapping relationship corresponding to the different power consumption types; merging intermediate calculation results with the same power consumption type within the same hierarchy to generate intermediate calculation results corresponding to the hierarchical sub-module. The same power consumption type corresponds to the same said first mapping relationship.

[0012] In some embodiments, the method further acquires the blocking information for the chip to be measured, determines at least two blocked chip regions of the chip to be measured based on the blocking information, and generates at least two target power consumption models corresponding to the blocked chip regions based on the static modeling parameters; inputs the dynamic evaluation parameter for each blocked chip region into the corresponding target power consumption model, and obtains a power consumption evaluation result corresponding to the blocked chip region.

[0013] In a second aspect, embodiments of the present application provide another method for evaluating chip power consumption. The method includes obtaining a target power consumption model in response to a user's power consumption evaluation request; obtaining dynamic evaluation parameters; and obtaining an evaluation result of the power consumption of the chip to be measured based on the dynamic evaluation parameters and the target power consumption model. The target power consumption model is used to store an intermediate calculation result calculated based on a static modeling parameter of the chip to be measured and a first mapping relationship, the first mapping relationship is used to indicate the correspondence between the static modeling parameter and the intermediate calculation result at least under power consumption constraint conditions, the static modeling parameter describes chip design parameters fixed within the power consumption constraint conditions of the current power consumption scenario, and the dynamic evaluation parameter refers to chip design parameters that change within the power consumption constraint conditions of the current power consumption scenario.

[0014] In some embodiments, the step of obtaining an evaluation result of power consumption based on the dynamic evaluation parameters and the target power consumption model To determine the second mapping relationship, and This includes obtaining an evaluation result for power consumption based on the dynamic evaluation parameters, the intermediate calculation results, and the second mapping relationship. The second mapping relationship is used to show the correspondence between the dynamic evaluation parameters under the power consumption constraints, the intermediate calculation results of the target power consumption model, and the power consumption evaluation results.

[0015] In the third aspect, embodiments of the present invention provide a method for generating a power consumption model. The method includes the steps of determining static modeling parameters of a chip under measurement, The step includes calculating an intermediate calculation result based on the static modeling parameters and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation result, in order to obtain an evaluation result of the power consumption of the chip to be measured. The aforementioned static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scenario. Here, the first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraint conditions. The power consumption evaluation results are generated based on the dynamic evaluation parameters and the target power consumption model. The aforementioned dynamic evaluation parameters represent chip design parameters that change within the power consumption constraints of the current power consumption scenario.

[0016] In some embodiments, the target power consumption model includes model detail data, and the model detail data includes at least chip description data and intermediate calculation results corresponding to the chip description data. and / or The aforementioned target power consumption model includes model metadata, The model metadata includes at least model description data, which is used to describe the attributes of the target power consumption model.

[0017] In the fourth aspect, an embodiment of the present invention provides a computer device. The computer device comprises a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, it implements the chip power consumption evaluation method described in the first or second aspect, or the power consumption model generation method described in the third aspect. [Effects of the Invention]

[0018] Compared to conventional technologies, the chip power consumption evaluation method, power consumption model generation method, and computer device according to the embodiments of the present invention divide the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. These parts are determined by determining static modeling parameters and dynamic evaluation parameters of the chip to be evaluated, calculating intermediate calculation results based on the static modeling parameters and a first mapping relationship, generating a target power consumption model that stores these intermediate calculation results, and obtaining power consumption evaluation results based on the dynamic evaluation parameters and the target power consumption model. Here, static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, dynamic evaluation parameters are chip design parameters that are changing within the power consumption constraints of the current power consumption scene, and the first mapping relationship is used to indicate at least the correspondence between the static modeling parameters and the intermediate calculation results. As a result, after modeling is completed, subsequent power consumption evaluation steps depend only on the generated power consumption model, and multiple power consumption evaluation calculations can be performed simply by inputting the relevant dynamic evaluation parameters. Therefore, the efficiency of evaluating the power consumption of the same chip design under different environments and operating conditions has been improved, solving the problem of low efficiency in chip power consumption evaluation methods and realizing an efficient and accurate chip power consumption evaluation method.

[0019] Details of one or more embodiments of the present application are presented in the following drawings and description, in order to make other features, purposes, and advantages of the present application clearer and easier to understand. [Brief explanation of the drawing]

[0020] [Figure 1] This is an application environment diagram for a chip power consumption evaluation method based on an embodiment of the present invention. [Figure 2] This is a flowchart of a method for evaluating chip power consumption based on an embodiment of the present invention. [Figure 3] This is a flowchart of a method for evaluating another type of chip power consumption based on an embodiment of the present invention. [Figure 4] This is a flowchart of a method for evaluating chip power consumption based on a preferred embodiment of the present invention. [Figure 5] This figure shows the structure of a chip power consumption evaluation device based on an embodiment of the present invention. [Figure 6] This diagram shows the structure of a chip power consumption evaluation system based on an embodiment of the present invention. [Figure 7] This figure shows the internal configuration of a type of computer device based on an embodiment of the present invention.

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute part of the present application. The exemplary embodiments and descriptions thereof are used to illustrate the present application and do not constitute an unreasonable limitation of the present application. [Modes for carrying out the invention]

[0022] To provide a clearer understanding of the purpose, technical solutions, and advantages of this application, the following description and explanation will be provided with a combination of drawings and embodiments. The specific embodiments described herein are for illustrative purposes only and do not limit the application. All other embodiments that can be obtained by an ordinary person of the art without creative work based on the embodiments provided herein are all within the scope of protection of this application. Furthermore, although the efforts undertaken in this development process may be complex and time-consuming, for an ordinary person of the art relating to the disclosed content, some design, manufacturing, or production modifications based on the disclosed content are ordinary technical means and should not be considered insufficient.

[0023] The term “Examples” as used herein means that certain features, structures, or characteristics described in accordance with an Example may be included in at least one Example of this Application. Where the term appears in different parts of the Description, it does not always refer to the same Example, nor does it mean that each Example is mutually exclusive, independent, or optional. A person ordinary in the Art should understand, expressly or implicitly, that the Examples described herein can be combined with other Examples, provided that they do not conflict.

[0024] Unless otherwise defined, technical or scientific terms in this application have the same meaning as those understood by a person of ordinary skill in the art. Similar expressions in this application, such as “one,” “a piece,” “a kind,” and “the relevant,” do not imply a limitation on quantity, and the corresponding element may be singular or plural. Furthermore, “includes,” “contains,” “possesses,” and their derivatives in this application are intended to imply non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or units, but may include steps or units not listed, or other steps or units specific to those processes, methods, products, or devices. Also, “connection,” “linking,” “joining,” and similar expressions in this application are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect. In this application, “plural” means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist. For example, "A and / or B" encompasses three states: when only A exists, when both A and B exist, and when only B exists. Terms such as "first," "second," and "third" used in this application are for distinguishing similar objects and do not imply that the objects have a specific order.

[0025] The chip power consumption evaluation method provided by the embodiment of the present invention is applicable to the application environment shown in Figure 1. In this environment, terminal device 12 communicates with server 14 via a network. Terminal device 12 is used to receive user operations. Server 14 responds to user operations to obtain static modeling parameters and dynamic evaluation parameters of the chip to be measured. Server 14 performs calculations based on the static modeling parameters and a first mapping relationship to obtain intermediate calculation results. Then, it generates a target power consumption model that stores these intermediate calculation results. Here, the first mapping relationship is used to show at least the correspondence between the static modeling parameters and the intermediate calculation results. Server 14 obtains power consumption evaluation results based on the dynamic evaluation results and the target power consumption model, and feeds back the power consumption evaluation results to the user through terminal device 12. Terminal device 12 includes, but is not limited to, various personal computers, such as laptop computers and tablet computers. Server 14 can be implemented as an independent server or a server cluster consisting of multiple servers.

[0026] This embodiment provides a method for evaluating chip power consumption. Figure 2 is a flowchart of one chip power consumption evaluation method according to an embodiment of the present invention. As shown in Figure 2, this flowchart includes the following steps.

[0027] In step S210, the static modeling parameters and dynamic evaluation parameters of the chip under measurement are determined. The static modeling parameters describe the chip design parameters that are fixed within the power consumption constraints of the current power consumption scenario. The dynamic evaluation parameters refer to the chip design parameters that change within the power consumption constraints of the current power consumption scenario.

[0028] Here, the aforementioned target chip refers to a chip at any stage of integrated circuit design. For example, it could be a chip at the RTL stage or before physical implementation, where the design is not yet complete but it already possesses certain chip structure data, or it could be a chip whose design is completely finished. In other words, power consumption evaluation analysis can be performed on the current chip design at any stage of integrated circuit design.

[0029] The aforementioned static modeling parameters refer to parameters that may affect chip power consumption in the current power consumption evaluation scene demand, but do not change during the current chip power consumption evaluation process; in other words, chip parameters that remain stationary. The aforementioned static modeling parameters include at least chip structural information, and further include parameters related to the chip structure itself, such as chip structure, parasitic parameters, and chip timing information.

[0030] The aforementioned dynamic evaluation parameters refer to chip parameters that, in the current power consumption scene evaluation scene demand, may cause changes in power consumption due to changes in chip design. In other words, there are parameters that change dynamically in the chip power consumption evaluation process. The aforementioned dynamic evaluation parameters are parameters used to quickly evaluate changes in power consumption due to different values ​​or combinations of values ​​of design parameters, and include parameters such as process angle, temperature, voltage, frequency, and chip operation data.

[0031] Static modeling parameters and dynamic evaluation parameters constitute the complete parameters of the chip under test for power consumption evaluation in the current power consumption evaluation scene (i.e., all parameters within the power consumption constraints). Therefore, it is not possible to calculate power consumption evaluation results by relying solely on static modeling parameters or dynamic evaluation parameters. All parameters within the power consumption constraints include chip structure parameters, chip operation parameters, chip environment parameters, etc. Power consumption constraints refer to the rules for calculating the power consumption of the chip under test. The same power consumption evaluation type corresponds to the same power consumption constraints. When evaluating the power consumption of the chip under test in any power consumption evaluation scene, it is necessary to evaluate different types of power consumption. Power consumption evaluation types include switching power consumption, internal power consumption, static power consumption, leakage power consumption, etc. Each of these elements has its own power consumption constraints.

[0032] Furthermore, since power consumption evaluation analysis for the chip being measured typically needs to be performed in different scenarios, the corresponding static modeling parameters and dynamic evaluation parameters can be determined according to the current evaluation scenario demands.

[0033] In some embodiments, if the current power consumption evaluation scenario is one in which the power consumption of a chip under different operating environments needs to be rapidly evaluated, then the evaluation scenario requires changing the operating environment but not the operation of the chip. This allows us to determine that the corresponding static modeling parameters include chip operation parameters in addition to the aforementioned chip structure parameters, and that the corresponding dynamic evaluation parameters include environmental parameters. If the current power consumption evaluation scenario is one in which the power consumption of a chip under different operating conditions needs to be rapidly evaluated, then the evaluation scenario requires changing the operation of the chip but not the operating environment. This allows us to determine that the corresponding static modeling parameters include environmental parameters in addition to the aforementioned chip structure parameters, and that the corresponding dynamic evaluation parameters include chip operation parameters. If the current power consumption evaluation scenario is one in which the power consumption of a chip under different operating environments and different operations needs to be rapidly evaluated, then the evaluation scenario requires changing both the operating environment and the operation of the chip. This allows us to determine that the static modeling parameters include chip structure parameters, and the dynamic evaluation parameters include environmental parameters and chip operation parameters.

[0034] In step S220, intermediate calculation results are calculated based on the static modeling parameters and the first mapping relationship, and a target power consumption model is generated that stores these intermediate calculation results. Here, the first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results within the power consumption constraints, and the target power consumption model is used to form new power consumption constraints that show the correspondence between the intermediate calculation results and the power consumption evaluation results. Specifically, some power consumption calculation results can be determined through the static modeling parameters and the first mapping relationship, and a target power consumption model can be generated based on these some power consumption calculation results.

[0035] The first mapping relationship described above is used to show at least the correspondence between static modeling parameters and intermediate calculation results. Intermediate calculation results can be obtained by calculation using the first mapping relationship. The first mapping relationship is determined based on scene demand information. Once the scene demand is determined, it is possible to determine which mapping relationships to use and through which static modeling parameters intermediate calculation results can be obtained in the current scene. The obtained intermediate calculation results refer to the power consumption of chip design parameters that do not change in the current scene. For example, the intermediate calculation results may include the hierarchical structure of the power consumption information design for a certain chip structure, the power consumption value of the current hierarchical structure, and possibly the circuit network information of the current hierarchical structure.

[0036] Furthermore, the target power consumption model functions as an intermediate form for the entire power consumption evaluation analysis process. The intermediate calculation results stored within the target power consumption model can be used to form power consumption constraints expressed in those intermediate calculation results. That is, new power consumption constraints can be formed between the intermediate calculation results and the power consumption evaluation results. These new power consumption constraints can represent the relationship between the intermediate calculation results, dynamic evaluation parameters, and the power consumption evaluation results. The intermediate form established by the target power consumption model serves to store power consumption calculation results related to partial parameters that do not change within the current power consumption evaluation scene in the power consumption analysis process, i.e., the static modeling parameters, reducing the time and resources required for each calculation during subsequent power consumption calculations based on changing parameters. Additionally, it is advantageous for accelerating the chip power consumption evaluation process because it allows for the rapid generation of chip evaluation results based on dynamic evaluation parameters during subsequent specific power consumption evaluations. As a supplementary explanation, the storage format of the target power consumption model includes, but is not limited to, ASCII text files or binary files. Furthermore, this model file can be directly stored in a storage space such as computer memory. Simultaneously, for models saved in text file format, the format may include, but is not limited to, YAML, JSON, XML, HTML, or other markup or programming languages. The target power consumption model may be saved in a single file or split into multiple files.

[0037] In step S230, the power consumption evaluation result is obtained based on the dynamic evaluation parameters and the target power consumption model. If power consumption evaluation is required after completing the modeling in step S220, the profile and execution script required for power consumption evaluation are loaded, and the modeling tool software on which the target power consumption model is deployed is executed. The determined dynamic evaluation parameters are then input into the invoked target power consumption model, and the modeling tool software is used to perform a complete power consumption calculation based on the dynamic evaluation parameters and intermediate calculation results, finally obtaining the evaluation result of the power consumption of the measured chip.

[0038] Furthermore, in steps S220 to S230 described above, the first mapping relationship between the static modeling parameters and the intermediate calculation results can be comprised of one or more power consumption calculation formulas. Different power consumption evaluation types have different mapping relationships. Mapping relationships of the same power consumption type correspond to the same mapping relationship. Power consumption evaluation types include, but are not limited to, switching power consumption, internal power consumption, static power consumption, and leakage power consumption. For example, the aforementioned power consumption calculation formula can be set as a calculation formula for the switching power consumption of a single grid. This power consumption calculation formula can be considered a type of power consumption constraint, as shown in Formula 1 below.

[0039] (Official 1) P s =C × V 2 ×f×TR

[0040] In the above formula, P srepresents the switching power consumption, C represents the total capacity of the power grid, including the parasitic capacitance and the input pin capacitance of the load unit. V represents the supply voltage. F represents the operating frequency of the chip. TR represents the flip rate. In some power consumption evaluation scenarios, the chip design parameters fixed within the current power consumption constraint conditions determined based on Formula 1 are C, V, and f, and the changing chip design parameter is TR. The first mapping relationship is C×V 2 ×f, and the intermediate calculation result is the calculation result of C×V 2 ×f. The new power consumption constraint relationship formed by the target power consumption model is P s = intermediate calculation result × TR. Or, in some other power consumption evaluation scenarios, the chip design parameters fixed within the power consumption constraint conditions are C and V, and the changing chip design parameters are f and TR. The first mapping relationship is C×V 2 and the intermediate calculation result is the calculation result of C×V 2 . The new power consumption constraint relationship formed by the target power consumption model is P s = intermediate calculation result × f × TR.

[0041] Or, the above power consumption calculation formula can further include the calculation formula of internal power consumption. In the calculation process, the logic gates in the chip can be approximated as resistors, thereby obtaining the corresponding power consumption value caused by the short-circuit current. This power consumption calculation formula can be regarded as a kind of power consumption constraint condition, as shown in Formula 2 below.

[0042] (Formula 2) P I =(V 2 / R)×f×TR

[0043] In the above formula, P IV represents internal power consumption, R represents the idovalence resistance of the logic gate, V represents the supply voltage, F represents the operating frequency of the chip, and TR represents the flip rate. In some power consumption evaluation scenarios, the fixed chip design parameters within the power consumption constraints are V, R, and f, while the variable chip design parameter is TR. The first mapping relationship is (V 2 (V) × f 2 This is the calculation result of ( / R) × f. The power consumption constraint relationship formed by the target power consumption model is P I = Intermediate calculation result × TR. Alternatively, in some other power consumption evaluation scenarios, the fixed chip design parameters within the power consumption constraints are V and R, and the variable chip design parameters are f and TR. The first mapping relationship is V 2 / R, and the intermediate calculation result is V 2 This is the calculation result of / R. The power consumption constraint relationship formed by the target power consumption model is P I = Intermediate calculation result × f × TR

[0044] Alternatively, the above formula for calculating power consumption may include a formula for calculating static power consumption / leakage power. This formula for calculating power consumption can be considered as one of the power constraints, as shown in Formula 3 below.

[0045] (Official 3) P L = c0 × T 2 ×e^(c1 / T)

[0046] In some power consumption evaluation scenarios, P is used in the above formula. L c0 is static power consumption, c0 and c1 are empirical parameters relating to the circuit configuration and belong to the fixed chip parameters among the power consumption constraints, and T is temperature and belongs to the variable chip design parameters.

[0047] The above power consumption calculation formulas allow us to establish at least a first mapping relationship between static modeling parameters and intermediate calculation results. For example, for the single-line network switching calculation formula shown in Formula 1 or the internal power consumption calculation formula shown in Formula 2, only the total capacity C is a static modeling parameter. That is, the total capacity C does not change in subsequent evaluations, while V, f, and TR can all change. Therefore, for the power consumption of this network or logic gate, a first mapping relationship between the static modeling parameter C and the intermediate calculation results can be determined based on Formulas 1 and 2.

[0048] After obtaining intermediate calculation results based on static modeling parameters and a first mapping relationship, a target power consumption model is generated that stores these intermediate calculation results. The target power consumption model can be used to form a new power consumption constraint relationship that shows the correspondence between the intermediate calculation results and the power consumption evaluation results. This new power consumption constraint relationship represents the calculation rules between the intermediate calculation results, dynamic evaluation parameters, and the power consumption evaluation results. Next, the power consumption evaluation results can be obtained based on the dynamic evaluation parameters and the target power consumption model. For example, in the calculation formula for switching power consumption of a single-line network shown in Formula 1 above, or the calculation formula for internal power consumption shown in Formula 2 above, the total capacity C is a static modeling parameter, and V, f, and TR can all change. Therefore, for the power consumption of this network or logic gate, the value of the total capacity C and the above expression are recorded in the power consumption model through the first mapping relationship described above, and then the intermediate calculation results are obtained and a target power consumption model is generated. The specific power consumption value is obtained in the subsequent power consumption evaluation process by substituting the specific values ​​of V, f, and TR and performing calculations. Alternatively, in the static power consumption calculation formula shown in Formula 3 above, C0 and C1 are empirical parameters related to the circuit structure and belong to the static modeling parameters, while T is temperature and belongs to the dynamic evaluation parameters. Therefore, for the static power consumption of logic gates, the values ​​of C0 and C1, and the above expression can be recorded within the target power consumption model. The specific power consumption value can be obtained in the subsequent evaluation process by substituting the specific temperature value of the dynamic evaluation parameter and performing the calculation. Furthermore, in the model generation process, this embodiment can also employ interpolation methods to improve the accuracy of power consumption calculations. For example, linear interpolation can be used to generate switching power consumption, and nonlinear interpolation can be used for internal power consumption and static power consumption.

[0049] It can be seen that the process of calculating power consumption based on dynamic evaluation parameters is similar to the process of generating the power consumption model described above. It is further explained that the power consumption modeling and evaluation method in this embodiment does not restrict the specific design stage; that is, it can be used in both the front-end and back-end design processes, and there is no difference in the usage process or method, only the input files differ. Similarly, for the different application scenarios mentioned above, only the input content differs, and the modeling and evaluation methods are the same. Therefore, by using the target power consumption model as an intermediate form, it is advantageous to improve the simulation evaluation efficiency of chip power consumption by converting the variable elements in the power consumption calculation process into a computable model.

[0050] In related technologies, all elements of the chip being measured, such as its environment, operation, and structure, are input at once during power consumption analysis, and then the complete chip power consumption is calculated. If any parameter of the input information changes, the power consumption evaluation tool needs to re-run the complete power consumption calculation. For a chip of a certain size, the related input data required for its power consumption calculation is usually large; for example, the size of a standard cell library file can reach 1.5G, the size of a parasitic parameter file can reach 10G or more, and the VCD file describing the circuit operation can reach another 100G. Because the analysis and processing of these files takes a considerable amount of time, the overhead of redundant calculations is large, and the overall efficiency when evaluating the power consumption of the same chip under different environments and operating conditions is greatly reduced.

[0051] Compared to power consumption calculation methods in related technologies that output all elements at once, leading to reduced calculation efficiency of chip power consumption, the embodiment of this application, through steps S210 to S230 described above, first models a power consumption calculation model based on fixed static modeling parameters of the chip under test, generates a target power consumption model as an intermediate form, and further inputs dynamic evaluation parameters of the chip under test during power consumption evaluation, and finally obtains the evaluation result of the power consumption of the chip under test based on the dynamic evaluation parameters and the target power consumption model. This divides the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After the modeling is completed, the subsequent power consumption evaluation step only needs to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting the relevant dynamic evaluation parameters. Therefore, significant data integration and compression are achieved based on the generated power consumption model, the processing cost of parameters is greatly reduced, the overall efficiency is improved when evaluating power consumption under different environments and operating conditions of the same design chip, effectively solving the problem of low chip power consumption evaluation efficiency and realizing an efficient and accurate chip power consumption evaluation method.

[0052] In some embodiments, determining the static modeling parameters and dynamic evaluation parameters of the chip under test further includes the steps of acquiring static factor information corresponding to scene demand information and determining the static modeling parameters of the chip under test based on said static factor information, and / or acquiring dynamic factor information corresponding to scene demand information and determining the dynamic evaluation parameters of the chip under test based on the dynamic factor information. Here, the static factor information may include files for acquiring static modeling parameters corresponding to the current scene demand, or data information entered by the user for the calculation of intermediate results. The dynamic factor information may include files for acquiring dynamic evaluation parameters or data entered by the user that may change the chip design for the final power consumption evaluation. The static factor information and dynamic factor information may be files or data in text or binary format. Before generating the target power consumption model, only the static modeling parameters can be acquired and the target power consumption model can be generated. Alternatively, all parameters can be acquired after the scene has been examined, and only the static modeling parameters can be used in the target model generation stage, while the dynamic evaluation parameters can be used only in the power consumption evaluation stage. Furthermore, the dynamic evaluation parameters can be quickly replaced at this stage. In some embodiments, when acquiring static factor information corresponding to scene demand information, the user can acquire the scene demand information, input the scene in the user interface where power consumption needs to be evaluated (i.e., scene demand information), and then confirm the necessary static elements based on the scene demand information. Confirmation methods include manually determining the static elements, or, after the user selects the current scene demand information in the user interface, displaying a message in the user interface suggesting the corresponding static elements based on the selected scene demand information, and prompting the user to input the corresponding static factor information based on the suggested message. Static elements include chip structure information, etc.Next, after confirming the necessary static elements based on the current power consumption evaluation scene demand information from the user, the system retrieves the corresponding static factor information entered by the user based on the static elements (for example, a file containing the static elements or data related to the static elements), and then, in response to the request to generate a target power consumption model, retrieves the appropriate static modeling parameters from the static factor information entered by the user.

[0053] In some embodiments, scene demand information is acquired, and dynamic factors are determined based on this scene demand information. Dynamic factor information entered by the user is acquired based on the dynamic factors. In response to a power consumption evaluation request, dynamic evaluation parameters are acquired from the dynamic factor information entered by the user. Here, the scene demand information refers to an evaluation of power consumption for an integrated circuit design chip, which is determined by the operator in conjunction with the actual situation. For example, this scene demand information may be used to indicate that chip power consumption is evaluated in different operating environments, or to indicate that chip power consumption is evaluated in different chip operations, etc. In this embodiment, the method of acquiring dynamic factor information and acquiring dynamic evaluation parameters based on dynamic factor information is similar to the method of acquiring static factor information and acquiring static modeling parameters based on static factor information described above, so it will not be explained further here.

[0054] In some embodiments, to determine the static modeling parameters and dynamic evaluation parameters of the chip under measurement, pre-configured scene demand information and processing parameters of the chip under measurement are acquired, and the processing parameters are classified according to the scene demand information to obtain the static modeling parameters and dynamic evaluation parameters. Although the dynamic evaluation parameters were determined before generating the target power consumption model, the target power consumption model may also be generated using only the static modeling parameters according to the scene needs, without using the dynamic evaluation parameters. During the power consumption evaluation stage, the power consumption evaluation can be sped up by simply locking the static modeling parameters and changing the dynamic evaluation parameters.

[0055] Specifically, for analysis scenes of chip power consumption corresponding to different scene demand information, the fixed and variable parameters of the chip will also differ. Furthermore, by classifying the processing parameters of the chip under measurement according to the above scene demand information, it may be determined which types of processing parameters belong to static modeling parameters and which types belong to dynamic evaluation parameters. In addition, the specific values ​​of the dynamic evaluation parameters must be determined during subsequent evaluations and input into the above target power consumption model for calculation. Specifically, if the scene demand information indicates the need to quickly evaluate the power consumption of the chip under measurement in different operating environments, the determined static modeling parameters may include the chip structure and chip operation information in the processing parameters described above, and the dynamic evaluation parameters may include the environmental parameters among the processing parameters described above. If the operating scene demand information indicates the need to quickly evaluate the power consumption of the chip under measurement under different operating conditions, the corresponding static modeling parameters may include the chip structure and environmental parameters, and the dynamic evaluation parameters may include chip operation information. If the aforementioned scene demand information indicates the need to quickly evaluate the power consumption of the chip in different operating environments and under different operating conditions, the static modeling parameters may include the chip structure, and the dynamic evaluation parameters may include environmental parameters and chip operation information.

[0056] In some embodiments, the above chip structure information may include a design constraint file (syopsys design format, abbreviated as SDC), RTL, Unified Power Format (UPF), netlist, standard unit library, Library Exchange Format / Design Exchange Format (lef / def), Standard parasitic exchange format (spef), timing information, clock tree model, and wire load model. The above chip operation information may include data for recording the status of chip inversion, such as flip rate and quiescent probability, Fast Signal Database (FSDB), Video Compact Disc (VCD), or Switching activity interchange format (SAIF) file. The above environmental parameters may include process angle, power supply voltage, on-chip temperature, and frequency.

[0057] According to the above-described embodiment, by determining static and dynamic factor information based on different scene demand information, and further determining static modeling parameters and dynamic evaluation parameters, the above embodiment can be applied to different power consumption evaluation scenes, which is advantageous for improving the evaluation accuracy and evaluation efficiency of chip power consumption.

[0058] In some embodiments, generating a target power consumption model based on intermediate calculation results involves obtaining the necessary model data from a data template of the intermediate calculation results, and then generating the target power consumption model from this model data and the data template. This data template has a defined data storage format and content, can be made into a visualized template, and can be presented to the user upon request.

[0059] Here, the above model data is stored in response to the request of the data template. This data template is a template that does not contain data, such as a mathematical formula or graph format used when generating the model. This data template may be pre-set, generated, and stored by the user, or it may be adaptively generated based on parameters entered by the user. For example, if it is detected that the number of currently entered static modeling parameters is greater than a certain threshold, it explains that there are many input points at the moment. Then, during modeling, a graph template such as a power consumption value-voltage relationship table or a power consumption value-frequency relationship table may be automatically generated. Furthermore, the data template may include visualization templates using table templates that can be scalars, multidimensional tables, functions, descriptions of chip hierarchical design structures, etc. Therefore, when outputting the power consumption evaluation results described above, visualization results can be generated based on these power consumption evaluation results and the visualization template, and these visualization results can be transmitted to a terminal device for display. That is, after calculating the power consumption evaluation results, the power consumption evaluation result data is substituted into the above visualization template, and then the visualization results are adaptively generated and displayed by the terminal device. As described above, by adaptively generating and storing multiple visualization templates based on the target power consumption model, visualization results can be quickly drawn and generated using the visualization templates during power consumption analysis. This makes it convenient for users to query and understand the evaluation status of chip power consumption. Furthermore, the displayed content includes two parts: metadata and detailed data in the target power consumption model.

[0060] In some embodiments, the target power consumption model includes model detail data, where the model detail data includes at least chip description data and intermediate calculation results corresponding to the chip description data. This chip description data is used to describe chip design information relating to the intermediate calculation results, such as chip hierarchical structure information, power supply network information, etc., and power consumption description information corresponding to the chip design information. This chip description data is used to store intermediate calculation results relating to chip design information, such as intermediate calculation results for a certain hierarchical design of the chip. And / or, the aforementioned target power consumption model includes model metadata, where the aforementioned model metadata includes at least model description data for describing the attributes of the current target power consumption model, and this data can be used to analyze the target power consumption model during the power consumption evaluation stage.

[0061] Here, model metadata includes, but is not limited to, model description data such as model version information, data unit information in the model, model-related parameters, model generation time, input information used during model generation, and mathematical formula templates used in the model. Specifically, model version information can be generated cumulatively based on the current modeling iteration and is used to distinguish different model versions. For example, the aforementioned model version information may be ν1.0. Model data unit information and model parameters can be determined based on the currently entered static modeling parameters. For example, model data unit information may be voltage: millivolts, current: milliamperes, etc., and is used to determine the units of data provided in the model. The aforementioned model parameters may include parameters such as temperature and voltage. Input information used during model generation includes file names, environmental parameters, etc., for iteratively building the model. The above model mathematical formula template is used to clarify how power consumption included in the model is calculated. The above model metadata also includes other data that is not directly related to specific chip data, but data related to the model itself will not be described here.

[0062] Here, detailed data includes, but is not limited to, chip description data such as the chip-top module name, chip power supply network information, power consumption information for each design hierarchy unit of the chip, and other specific chip power consumption information. Specifically, the chip-top module name is used to clarify the specific module that the model refers to. Chip power supply network information is used to distinguish different power supply networks during the power consumption evaluation stage. For example, the chip power supply network information may include the number and name of the VDD network. Power consumption information for each design hierarchy unit of the chip can be identified in the form of a scalar, a multidimensional table, or a function. For example, one overall Top module contains multiple submodules such as A, B, and C. Each submodule further contains its own submodules. For example, submodule A contains a and b. In this case, in order to calculate the power consumption of modules at each hierarchical level, hierarchical information and power consumption information can be recorded simultaneously. For example, the power consumption data for the Top / A / a module is x, the power consumption data for the Top / A / b module is y, the power consumption data for the Top / B module is m, and the power consumption data for the Top / B module is m. Data such as x, y, m, and n can be represented in the form of scalars, multidimensional tables, functions, etc. It should be noted that both metadata and detailed data belong to the model content. In the power consumption evaluation process, model metadata such as model description data is mainly used for analyzing model data, deduplication, and constructing the corresponding computational model, while model detailed data such as chip description data is used to calculate the final chip power consumption value in the power consumption evaluation stage.

[0063] In some embodiments, step S230, generating power consumption evaluation results based on the dynamic evaluation parameters and target power model, further includes the steps of determining a second mapping relationship and obtaining power consumption evaluation results based on the dynamic evaluation parameters, intermediate calculation results and the second mapping relationship. This second mapping relationship indicates the correspondence between the dynamic evaluation parameters within the power consumption constraints, the intermediate calculation results of the target power consumption model and the power consumption evaluation results.

[0064] In some embodiments, the second mapping relationship is determined based on scene demand information or from a target power consumption model. In some embodiments, the power consumption constraints for the intermediate calculation results and power consumption evaluation results formed using the target power consumption model can also be specified by describing the second mapping relationship. This power consumption constraint represents the calculation rules for dynamic evaluation parameters, the intermediate calculation results in the target power consumption model, and the power consumption evaluation results. Since the power consumption evaluation in this embodiment is related to scene demand, when determining the scene demand information, it is determined which mapping relationship will be used to calculate the intermediate calculation results and the final power consumption evaluation. Optionally, since the target power consumption model is determined based on scene demand information, the second mapping relationship may be stored in the target power consumption model. In this case, it can be retrieved directly from the target power consumption model during power consumption evaluation. For example, when the current scene demand is to quickly evaluate chip power consumption under different operating environments and conditions, and a first mapping relationship between static modeling parameter C and intermediate calculation results is determined based on formula 1 above, a target power consumption model can be constructed based on the first mapping relationship, and dynamic evaluation parameters and a second mapping relationship between the intermediate calculation results and the final power consumption evaluation results can be determined based on the scene demand information during power consumption evaluation. Alternatively, when generating a target power consumption model based on the first mapping relationship, the second mapping relationship determined based on the scene demand information can be stored in the target power consumption model, and the power consumption evaluation results can be obtained by directly retrieving this second mapping relationship from the target power consumption model during power consumption evaluation.

[0065] In some embodiments, the evaluation result of power consumption can be obtained by inputting dynamic evaluation parameters into the target power consumption model. In other embodiments, it is also possible to obtain an evaluation result of power consumption by obtaining intermediate calculation results from the target power consumption model and then calculating the dynamic evaluation parameters and intermediate calculation results using the calculation method indicated by the second mapping relationship.

[0066] In some embodiments, during the power consumption evaluation process, metadata of the target power consumption model is primarily used by evaluation tools for analyzing model data, deduplication, and constructing corresponding computational models, while detailed data of the target power consumption model is used for specific chip power consumption calculations during the power consumption evaluation phase.

[0067] In some embodiments, the static modeling parameters described above include at least one hierarchical submodule of the chip under test, and the intermediate calculation results described above include intermediate calculation results corresponding to the hierarchical submodule. That is, if the chip under test of the same design includes at least one hierarchical submodule, the static modeling parameters of each hierarchical submodule can be obtained by any of the above method embodiments, and the intermediate calculation results of each hierarchical submodule can be calculated based on them.

[0068] In some embodiments, each hierarchical submodule includes multiple element units. The method for evaluating the chip power consumption described above further includes the following steps.

[0069] In step S221, static modeling parameters corresponding to different power consumption types of each element unit, and a first mapping relationship corresponding to different power consumption types are obtained for each element unit. Here, identical power consumption types correspond to the same first mapping relationship. The power consumption types include, but are not limited to, various types such as switching power consumption, internal power consumption, static power consumption, and leakage power consumption.

[0070] In step S222, intermediate calculation results for different power consumption evaluation types for different element units are calculated based on static modeling parameters for different power consumption types and the first mapping relationships corresponding to those different power consumption types.

[0071] In step S223, intermediate calculation results with the same power consumption type within the same hierarchical level are integrated to generate intermediate calculation results corresponding to the hierarchical submodule.

[0072] In steps S221 to S223 above, the intermediate calculation results of the same power consumption type may be compressed together based on standard unit data of the same design hierarchy within the chip using the target power consumption model, in order to significantly reduce the amount of data in the power consumption model. For example, the coefficients of multiple polynomials that have the same form may be integrated. Specifically, taking the case of calculating the switching power consumption of each element unit as an example, assuming that the hierarchical submodule contains three logic gates U1, U2, and U3, the calculated switching power consumption values ​​for each logic gate calculated using formula 1 above are, respectively, P S1 =C1×V 2 ×f×TR, P S2 =C2×V 2 ×f×TR, P S3 =C3×V 2 ×f × TR. Here, in several power consumption evaluation scenes, the static modeling parameter is capacitance C, and the intermediate calculation results for the switching power consumption of each element unit are obtained using the corresponding capacitance values ​​C1, C2, and C3 for each logic gate. The calculated value of the total switching power consumption of each logic gate is P S =C1×V 2 ×f×TR+C2×V 2 ×f×TR+C3×V 2 ×f×TR=(C1+C2+C3)×V 2The formula is ×f × TR. In other words, in the model file, the intermediate calculation results of the three element units are merged, calculated using the values ​​of C1 + C2 + C3, and then recorded as a single numerical value, allowing for the integration of intermediate calculation results with the same power consumption type at the same hierarchical level. If the static modeling parameters are capacitance C and power supply voltage V, the intermediate calculation results of the three element units are integrated into C1V1 + C2V2 + C3V3. Here, V1, V2, and V3 are the power supply voltage values ​​corresponding to each logic gate, and furthermore, the intermediate calculation results corresponding to the above hierarchical submodule are obtained, rather than directly saving the three numerical values ​​in the original data. Similarly, a similar integration process can be applied to power consumption evaluation types such as internal power consumption and leakage power consumption. This achieves effective data compression.

[0073] Through steps S221 to S223 described above, data compression is performed on all static calculated values ​​based on the level of the hierarchical submodule to obtain the power consumption evaluation result after compression. This reduces the amount of data in the power consumption model, thereby effectively reducing the memory space occupancy.

[0074] In some embodiments, the aforementioned chip under measurement includes multiple element units. The aforementioned chip power consumption detection method further includes the following steps: Specifically, the steps include: calculating a sub-power consumption value corresponding to an element unit based on dynamic evaluation parameters and a target power consumption model; acquiring identification information corresponding to the element unit and obtaining a power consumption evaluation result based on the aforementioned identification information and sub-power consumption value; detecting a power consumption query command for the aforementioned element unit; in response to the detected power consumption query command, searching for a sub-power consumption value within the power consumption evaluation result and identifying a corresponding target sub-power consumption value from all sub-power consumption values ​​based on the identification information; and generating a power consumption query result based on the target sub-power consumption value and transmitting the power consumption query result to a terminal device for display. By individually storing the power consumption value of each element based on the identification information, when a user needs to search for a power consumption value corresponding to a single element such as an individual logic gate, the search can be performed based on the identification information corresponding to the element unit. This effectively improves the convenience for the user when searching for power consumption values.

[0075] In some embodiments, the above-described chip power consumption evaluation method further includes the steps of: acquiring blocking information for the chip under test; identifying at least two blocked chip regions of the chip under test based on this blocking information; and generating target power consumption models corresponding to at least two such blocked chip regions based on the static modeling parameters; and inputting dynamic evaluation parameters for each blocked chip region into the corresponding target power consumption model to obtain an evaluation result of the power consumption corresponding to the blocked chip region. Here, the blocking information can be pre-configured by an employee. For example, it is possible to configure the system to block a certain design chip according to its function. By doing so, the steps in any of the above-described method embodiments can be applied to different regions of the chip under test, and one corresponding target power consumption model can be constructed for each. This improves the calculation accuracy and efficiency of the power consumption model. In another embodiment, simulation and power consumption evaluation can be performed on the same batch of design chips using a unified target power consumption model.

[0076] This embodiment provides yet another type of chip power consumption evaluation method. Figure 3 is a flowchart of another type of chip power consumption evaluation method according to an embodiment of the present invention. As shown in Figure 3, this flowchart includes the following steps.

[0077] In step S310, a target power consumption model is obtained in response to the user's request for evaluation of power consumption. Here, the aforementioned target power consumption model stores intermediate calculation results calculated based on the static modeling parameters of the chip under measurement and a first mapping relationship. This first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraints. The target power consumption model is used to form new power consumption constraints that can indicate the correspondence between the intermediate calculation results and the power consumption evaluation results.

[0078] In step S320, dynamic evaluation parameters are obtained. Here, the static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, while the dynamic evaluation parameters are chip design parameters that change within the power consumption constraints of the current power consumption scene.

[0079] In step S330, the evaluation result of the power consumption of the chip to be measured is obtained based on the target power consumption model and dynamic evaluation parameters.

[0080] In steps S310 to S330 described above, during the analysis and evaluation of power consumption, the dynamic evaluation parameters of the target chip are input into a target power consumption model that stores intermediate calculation results, which are pre-constructed and generated based on the static modeling parameters of the target chip. Furthermore, the final power consumption evaluation result is calculated based on the dynamic evaluation parameters and the intermediate calculation results obtained in the partial calculation. This significantly improves the efficiency of power consumption evaluation, effectively solves the problem of low detection efficiency of chip power consumption, and realizes an efficient and accurate power consumption calculation method.

[0081] In some embodiments, obtaining power consumption evaluation results based on the dynamic evaluation parameters and target power consumption model described above further includes the steps of determining a second mapping relationship and obtaining power consumption evaluation results based on the dynamic evaluation parameters, intermediate calculation results and the second mapping relationship in the power consumption constraints. The second mapping relationship is used to show the correspondence between at least the dynamic evaluation parameters, the intermediate calculation results of the target power consumption model and the power consumption evaluation results.

[0082] Furthermore, this disclosure provides a method for generating a power consumption model, which includes the following steps.

[0083] First, the static modeling parameters of the chip to be measured are determined. These static modeling parameters describe the chip design parameters that are fixed within the power consumption constraints of the current power consumption scenario.

[0084] Next, an intermediate calculation result is calculated based on the static modeling parameters and the first mapping relationship described above, and a target power consumption model is generated that stores the intermediate calculation result to obtain an evaluation result of the power consumption of the target chip. Here, the first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation result, at least under the power consumption constraint conditions. The power consumption evaluation result described above is generated based on dynamic evaluation parameters and the target power consumption model. The dynamic evaluation parameters are chip design parameters that change under the power consumption constraint conditions of the current power consumption scene.

[0085] In the above embodiment, a target power consumption model is pre-constructed, storing intermediate calculation results based on static modeling parameters and a first mapping relationship. This allows for rapid generation of chip evaluation results by simply inputting dynamic evaluation parameters during subsequent chip power consumption simulations and evaluations, relying on the generated power consumption model to perform multiple power consumption evaluation calculations. Consequently, there is no need to re-run a complete calculation when a chip element changes, effectively improving efficiency when evaluating the power consumption of the same design chip under different environments and operating conditions.

[0086] In some embodiments, the above target power consumption model includes model detail data, where the model detail data includes at least chip description data and intermediate calculation results corresponding to the chip description data. And / or, the above target power consumption model includes model metadata, where the model metadata includes at least model description data for describing the attributes of the target power consumption model.

[0087] The present application will be described below with reference to preferred embodiments of the present invention. Figure 4 is a flowchart of a method for evaluating chip power consumption based on a preferred embodiment of the present application. As shown in Figure 4, the flowchart includes the following steps.

[0088] Step S401 obtains an input file containing static modeling parameters necessary for modeling. This input file can be in text or binary format. Furthermore, a profile and execution script required for the modeling tool are prepared. Here, the input file can also be adaptively checked through a master device such as the terminal device or server mentioned above. To avoid problems such as errors in evaluating chip power consumption due to input errors, the check includes verification of the integrity and format accuracy of the input file. The profile is used to provide evaluation modes, log levels, etc. The script is used to instruct the execution procedure of the modeling tool. For example, the execution procedure may include reading the file and then performing analysis. Examples of execution procedures described in the script include reading the input file, setting the execution mode, analyzing the execution timing, analyzing power consumption, outputting the power consumption analysis results, and exporting the file.

[0089] In step S402, in response to the user's request to generate a target power consumption model, the system loads a modeling profile, runs a modeling script, retrieves the static modeling parameters required for power consumption modeling from the input file, performs the fixed-part power consumption modeling, and generates intermediate calculation results. However, the loading of the profile and the execution of the script may not be visible, depending on whether the tool displays the loading process through the log or interface.

[0090] In step S403, the information necessary for the target power consumption model is obtained from the intermediate calculation results, and the target power consumption model is generated.

[0091] In step S404, the input file for dynamic evaluation parameters necessary for power consumption evaluation detection is obtained.

[0092] In step S405, in response to a power consumption evaluation request from the user, the power consumption evaluation profile is loaded, the power consumption evaluation script is executed, and the dynamic evaluation parameters and target power consumption model necessary for power consumption evaluation are obtained from the input file using the power consumption evaluation profile and evaluation script, and power consumption is evaluated.

[0093] In step S406, in response to the user's request for power consumption evaluation, the system checks the completeness of the input content and whether the input format is correct, eliminating as many potential problems as possible before going live. Subsequently, the analysis results are obtained through calculations, and finally, the power consumption evaluation result is obtained.

[0094] The steps shown in the flowchart or diagram above can be executed in a computer system, such as a set of computer-executable instructions. While the flowchart shows a logical sequence, the steps illustrated or described may be executed in a different order depending on the circumstances.

[0095] This embodiment also provides a chip power consumption detection device. This device is used to implement the above embodiments and preferred embodiments, and will not be repeated what has already been described. The terms “module,” “unit,” “subunit,” etc., used below refer to a combination of software and / or hardware to implement the intended function. The devices described in the following embodiments are preferably implemented by software, but implementation by hardware, or a combination of software and hardware, is also possible and considered.

[0096] Figure 5 is a block diagram of the configuration of a chip power consumption evaluation device according to an embodiment of the present application. As shown in Figure 5, the device includes a parameter module 52, a modeling module 54, and an evaluation module 56. The parameter module 52 is for determining static modeling parameters and dynamic evaluation parameters of the chip to be measured. Here, static modeling parameters describe invariant chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, and dynamic evaluation parameters are chip design parameters that change within the power consumption constraints of the current power consumption scene. The modeling module 54 is for calculating intermediate calculation results based on the static modeling parameters and a first mapping relationship, and for generating a target power consumption model that stores the intermediate calculation results. The first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraints. The evaluation module 56 is for obtaining evaluation results of the chip power consumption to be measured based on the dynamic evaluation parameters and the target power consumption model.

[0097] In the above embodiment, the modeling module 54 models a power consumption calculation model based on fixed static modeling parameters of the chip under measurement, generates a target power consumption model as an intermediate form, and obtains an evaluation result of the power consumption of the chip under measurement based on the current dynamic evaluation parameters and the target power consumption model through the evaluation module 56 during power consumption evaluation. As a result, the chip power consumption analysis process is divided into two parts: power consumption modeling and power consumption evaluation. After modeling is completed, the subsequent power consumption evaluation step only needs to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by simply inputting the relevant dynamic evaluation parameters. Therefore, significant data integration and compression are achieved based on the generated power consumption model, the processing cost of parameters is greatly reduced, the overall efficiency is increased when evaluating the power consumption of the same design chip under different environments and operating conditions, the problem of low evaluation efficiency for chip power consumption is effectively solved, and an efficient and accurate chip power consumption evaluation device is realized.

[0098] In some embodiments, the parameter module 52 described above is also used to acquire static factor information corresponding to scene demand information and to determine static modeling parameters of the chip under measurement from said static factor information, and / or, the parameter module 52 acquires dynamic factor information corresponding to scene demand information and to determine dynamic evaluation parameters of the chip under measurement from said dynamic factor information.

[0099] In some embodiments, the modeling module 54 is also used to determine a data template corresponding to scene demand information. The modeling module 54 obtains the model data necessary for the data template in the intermediate calculation results and generates a target power consumption model based on the model data and the data template.

[0100] In some embodiments, the target power consumption model includes model detail data, which includes at least chip description data and intermediate calculation results corresponding to the chip description data. And / or, the target power consumption model includes model metadata, where the model metadata includes at least model description data for describing the attributes of the target power consumption model.

[0101] In some embodiments, the evaluation module 56 determines a second mapping relationship. This second mapping relationship indicates at least the correspondence between the dynamic evaluation parameters in the power consumption constraints, the intermediate calculation results in the target power consumption model, and the power consumption evaluation results. Based on the dynamic evaluation parameters, the intermediate calculation results, and the second mapping relationship, the evaluation module 56 obtains the aforementioned power consumption evaluation results.

[0102] In some embodiments, the static modeling parameters include at least one hierarchical submodule of the chip under measurement. The intermediate calculation results include intermediate calculation results corresponding to the hierarchical submodule.

[0103] In some embodiments, each hierarchical submodule comprises multiple element units. Each modeling module 54 obtains static modeling parameters corresponding to different power consumption types of the element unit and a first mapping relationship corresponding to the different power consumption types for each element unit. Here, the same power consumption type is associated with the same first mapping relationship. Based on the static modeling parameters for different power consumption types and the first mapping relationships corresponding to different power consumption types, the modeling module 54 calculates intermediate calculation results for different power consumption evaluation types for each element unit. The modeling module 54 merges the intermediate calculation results for the same power consumption type at the same hierarchical level to generate the intermediate calculation result corresponding to the hierarchical submodule.

[0104] In some embodiments, the chip to be measured includes a plurality of element units. The chip power consumption evaluation device further comprises a display module. The evaluation module 56 is used to calculate sub-power consumption values ​​corresponding to the element units based on the aforementioned dynamic evaluation parameters and target power consumption model, utilizing the target power consumption model. The evaluation module 56 acquires identification information corresponding to the element unit and obtains a power consumption evaluation result from the identification information and the sub-power consumption value. The display module further detects a power consumption inquiry command for the element unit and, in response to the detected power consumption inquiry command, searches for the sub-power consumption value in the power consumption evaluation result and determines a corresponding target sub-power consumption value from among all sub-power consumption values ​​based on the identification information. The display module also generates a power consumption inquiry result based on the target sub-power consumption value and transmits the power consumption inquiry result to a terminal device for display.

[0105] In some embodiments, the chip power consumption detection device further includes a block division module. The block division module acquires blocking information for the chip to be measured and determines at least two blocked chip regions of the chip to be measured based on the blocking information. The modeling module 54 generates at least two target power consumption models corresponding to the blocked chip regions based on the static modeling parameters. The evaluation module 56 inputs dynamic evaluation parameters for each blocked chip region into the corresponding target power consumption model to obtain an evaluation result of power consumption according to the blocked chip region.

[0106] Each of the above modules may be a functional block, a program module, implemented by software, or implemented by hardware. For modules implemented by hardware, each of the above modules may be located on the same processor, or they may be located on different processors in any combination.

[0107] This embodiment also discloses a chip power consumption detection system. Figure 6 is a block diagram showing the configuration of a chip power consumption detection system according to an embodiment of the present application. As shown in Figure 6, the system includes a master device 62 and a terminal device 12. The terminal device 12 acquires static modeling parameters and dynamic evaluation parameters of the chip to be measured and transmits the aforementioned static modeling parameters and dynamic evaluation parameters to the master device 62, respectively. The master device 62 is used to perform the steps in any of the above method embodiments. The master 62 may include hardware devices for controlling various computer, server, server cluster, or other chip power consumption simulation evaluation flows. Furthermore, signals may be transmitted between the terminal device 12 and the master device 62 by a transmission device. In one embodiment, the transmission device may include a single network adapter (abbreviated as Network Interface Controller, NIC) that can connect to other network devices via a base station and communicate with the Internet. In another embodiment, the transmission device may be a radio frequency module (abbreviated as Radio Frequency, RF) for wireless communication with the Internet.

[0108] In the above embodiment, the master device 62 first models a power consumption calculation model based on fixed static modeling parameters of the chip under test, generates a target power consumption model as an intermediate form, inputs dynamic evaluation parameters of the chip under test during power consumption evaluation, and finally obtains an evaluation result of the power consumption of the chip under test based on the dynamic evaluation parameters and the target power consumption model. This divides the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After modeling is completed, the subsequent power consumption evaluation step only needs to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting the relevant dynamic evaluation parameters. Therefore, significant data integration and compression are achieved based on the generated power consumption model, the processing cost of parameters is greatly reduced, the overall efficiency is increased when evaluating the power consumption of the same design chip under different environments and operating conditions, the problem of low chip power consumption detection efficiency is effectively solved, and an efficient and accurate chip power consumption evaluation system is realized.

[0109] In some embodiments, a computer device is provided. This computer device can be a server. Figure 7 shows the internal configuration of one type of computer device according to an embodiment of the present invention. As shown in Figure 7, the computer device according to this embodiment includes a processor, memory, a network interface, and a database connected via a system bus. Here, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the execution of the operating system and computer programs on the non-volatile storage medium. The database of the computer device is used to store a target power consumption model. The network interface of the computer device is used to communicate with an external terminal via a network connection. When this computer program is executed by the processor, a method for evaluating chip power consumption is realized.

[0110] Those skilled in the art will see that the configuration shown in Figure 7 is merely a block diagram of a partial configuration relating to the scheme of the present application and does not constitute a limitation of the computer devices to which the scheme of the present application applies. A specific computer device may contain more or fewer components than shown, or may be a combination of several components or a different arrangement of components.

[0111] This embodiment also provides a type of computer device including memory and a processor. A computer program is stored in this memory. The processor is configured to perform the steps in any one of the above method embodiments when executing the computer program.

[0112] Optionally, the above computer device may also include transmission devices and input / output devices connected to the above processors, respectively.

[0113] Optionally, in this embodiment, the above-described processor can be configured to perform the following steps via a computer program.

[0114] In step S210, the static modeling parameters and dynamic evaluation parameters of the chip under measurement are determined. Here, the static modeling parameters describe the chip design parameters that are fixed within the power consumption constraints of the current power consumption scene, while the dynamic evaluation parameters are the chip design parameters that change within the power consumption constraints of the current power consumption scene.

[0115] In step S220, intermediate calculation results are calculated based on the aforementioned static modeling parameters and the first mapping relationship, and a target power consumption model is generated that stores the intermediate calculation results. Here, the first mapping relationship is used to show at least the correspondence between the static modeling parameters and the intermediate calculation results within the power consumption constraint conditions.

[0116] In step S230, the power consumption evaluation result is obtained based on the aforementioned dynamic evaluation result and target power consumption model.

[0117] For specific examples of this embodiment, refer to the examples described in the above-mentioned embodiments and optional embodiments. This embodiment will not be described further here.

[0118] Furthermore, in accordance with the chip power consumption evaluation method in the embodiments described above, the embodiments of the present invention further provide a type of storage medium. A computer program is stored in this storage medium. When the computer program is executed by the processor, any one type of chip power consumption evaluation method in the embodiments described above is realized.

[0119] Those skilled in the art will understand that all or part of the processes described in the above embodiments can be implemented by directing the relevant hardware with a computer program. The aforementioned computer program is stored in a non-volatile computer-readable storage medium. When executed, this computer program encompasses the flow of each embodiment of the above methods. References to memory, databases, or other media used in each embodiment provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random-access memory (RAM) or external cache memory. As a non-limiting explanation, RAM can be obtained in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), extended SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct memory bus RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0120] Technicians in the field should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described, but any combination of these technical features should be considered to fall within the scope described in this document, as long as it is not inconsistent.

[0121] The above embodiments merely represent some methods of carrying out the present application, and although their descriptions are relatively specific and detailed, they should not limit the scope of the claims of the present invention. Furthermore, several modifications and improvements can be made by a person of ordinary skill in the art, provided they do not deviate from the concept of the present application. All such modifications or improvements fall within the scope of protection of the present application. Therefore, the scope of the claims of the present application should be defined by the attached claims.

Claims

1. A method for evaluating chip power consumption, The steps include determining the static modeling parameters and dynamic evaluation parameters of the chip to be measured, The steps include: calculating intermediate calculation results based on the static modeling parameters and the first mapping relationship, and generating a target power consumption model that stores the intermediate calculation results; The step includes obtaining an evaluation result of the power consumption of the chip to be measured based on the dynamic evaluation parameters and the target power consumption model, A method for evaluating chip power consumption, characterized in that the static modeling parameters describe chip design parameters fixed within the power consumption constraints of the current power consumption scene, the dynamic evaluation parameters are chip design parameters that change within the power consumption constraints of the current power consumption scene, and the first mapping relationship shows the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraints.

2. The step of determining the static modeling parameters of the chip to be measured includes obtaining static factor information corresponding to scene demand information and determining the static modeling parameters of the chip to be measured from the static factor information. and / or The step of determining the dynamic evaluation parameters of the chip to be measured is: The chip power consumption evaluation method according to claim 1, characterized in that it includes acquiring dynamic factor information corresponding to the scene demand information and determining the dynamic evaluation parameters of the chip to be measured from the dynamic factor information.

3. Generating a target power consumption model that stores the aforementioned intermediate calculation results means that The steps include determining a data template that corresponds to the scene demand information, The steps include obtaining the model data necessary for the data template of the intermediate calculation result, A method for evaluating chip power consumption according to claim 1, comprising the step of generating the target power consumption model based on the model data and the data template.

4. The aforementioned target power consumption model includes model detail data, The aforementioned model detail data includes at least chip description data and intermediate calculation results corresponding to the chip description data, and / or The aforementioned target power consumption model includes model metadata, The aforementioned model metadata includes at least model description data, The chip power consumption evaluation method according to claim 1, characterized in that the aforementioned model description data is used to describe the attributes of the target power consumption model.

5. The step of obtaining an evaluation result of power consumption based on the aforementioned dynamic evaluation parameters and target power consumption model is: To determine the second mapping relationship, and This includes obtaining the power consumption evaluation result based on the dynamic evaluation parameters, the intermediate calculation result, and the second mapping relationship, The chip power consumption evaluation method according to claim 1, characterized in that the second mapping relationship is used to show the correspondence between at least the dynamic evaluation parameters in the power constraint conditions, the intermediate calculation results in the target power consumption model, and the power consumption evaluation results.

6. The static modeling parameters include at least one hierarchical submodule of the chip under measurement, The chip power consumption evaluation method according to claim 1, characterized in that the intermediate calculation result of the target power consumption model includes the intermediate calculation result corresponding to the hierarchical submodule.

7. Each of the hierarchical submodules includes a plurality of element units, Based on the static modeling parameters and the first mapping relationship, the intermediate calculation results of the target power consumption model can be calculated. For each of the element units, the steps include obtaining static modeling parameters corresponding to different power consumption types of the element unit, and a first mapping relationship corresponding to different power consumption types. Based on the static modeling parameters for the different power consumption types and the first mapping relationship corresponding to the different power consumption types, The steps include calculating intermediate calculation results for different power consumption evaluation types for different element units, The steps include: merging intermediate calculation results with the same power consumption type within the same hierarchical level to generate intermediate calculation results corresponding to the hierarchical submodule; Includes, The chip power consumption evaluation method according to claim 6, characterized in that identical power consumption types correspond to the same first mapping relationship.

8. The method further includes the steps of obtaining blocking information for the chip to be measured and determining at least two blocked chip regions of the chip to be measured based on the blocking information, The step of calculating an intermediate calculation result based on the static modeling parameters and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation result, includes the step of generating at least two target power consumption models corresponding to the block chip region based on the static modeling parameters, The chip power consumption evaluation method according to any one of claims 1 to 7, characterized in that each target power consumption model is used, together with the corresponding dynamic evaluation parameters of the blocked chip region, to obtain an evaluation result of the power consumption of the blocked chip region.

9. A method for evaluating chip power consumption, The steps include: obtaining a target power consumption model in response to a user's power consumption evaluation request, Steps to obtain dynamic evaluation parameters, The step includes obtaining an evaluation result of the power consumption of the chip to be measured based on the dynamic evaluation parameters and the target power consumption model, The aforementioned target power consumption model is used to store intermediate calculation results calculated based on the static modeling parameters of the chip under measurement and the first mapping relationship. The aforementioned static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scenario. The first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results, at least under the power consumption constraints. A method for evaluating chip power consumption, characterized in that the aforementioned dynamic evaluation parameters refer to chip design parameters that change within the power consumption constraints of the current power consumption scenario.

10. The step of obtaining an evaluation result of power consumption based on the aforementioned dynamic evaluation parameters and target power consumption model is: To determine the second mapping relationship, and This includes obtaining an evaluation result for power consumption based on the dynamic evaluation parameters, the intermediate calculation results, and the second mapping relationship. The chip power consumption evaluation method according to claim 9, characterized in that the second mapping relationship is used to show the correspondence between the dynamic evaluation parameters in the power consumption constraint conditions, the intermediate calculation results of the target power consumption model, and the power consumption evaluation results.

11. A method for generating a power consumption model, The steps include determining the static modeling parameters of the chip to be measured, The step includes calculating intermediate calculation results based on the static modeling parameters and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation results, The aforementioned static modeling parameters describe chip design parameters that are fixed within the power consumption constraints of the current power consumption scenario. The first mapping relationship is used to show the correspondence between the static modeling parameters and the intermediate calculation results, at least within the power consumption constraint conditions. The power consumption evaluation results are generated based on the dynamic evaluation parameters and the target power consumption model. A method for generating a power consumption model, characterized in that the dynamic evaluation parameters represent chip design parameters that change within the power consumption constraints of the current power consumption scene.

12. The target power consumption model includes model detail data, and the model detail data includes at least chip description data and intermediate calculation results corresponding to the chip description data. and / or The aforementioned target power consumption model includes model metadata, The method for generating a power consumption model according to claim 11, characterized in that the model metadata includes at least model description data, and the model description data is used to describe the attributes of the target power consumption model.

13. A computer device, Equipped with memory and a processor, The aforementioned memory stores computer programs. The computer device is characterized in that, when the processor executes the computer program, it implements the chip power consumption evaluation method described in any one of claims 1 to 10 or the power consumption model generation method described in claim 11 or claim 12.

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