Vertical field-effect element and manufacturing method

Abstract

This disclosure relates to a vertical field-effect transistor (FET). The vertical FET according to the present invention includes a substrate (101) and a first electrode (102) configured as either the source or the drain of the transistor. The device includes a second electrode (104) configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode in an overlapping region. Furthermore, the device includes a gate configuration comprising an active layer (103) sandwiched between the first electrode and the second electrode, a gate conductor portion (107), and a gate insulating layer (106) disposed between the active layer (103) and the gate conductor portion (107) to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) includes a one-dimensional material whose longitudinal axis is oriented parallel to the substrate (101), and / or a two-dimensional material whose plane is oriented substantially parallel to the substrate (101). This disclosure further includes methods (3000) for manufacturing such vertical field-effect transistors and complementary logic devices.

Description

Technical Field

[0001] The present disclosure relates to field effect devices such as field effect transistors (FETs), and more particularly to vertical field effect transistors and methods of manufacturing the same.

Background Art

[0002] Semiconductor devices used for integrated circuits have been significantly miniaturized over the past few decades as predicted by Moore's law. The channel length of transistors has changed from several micrometers to several nanometers. This miniaturization has made it possible to increase the integration density of transistors within one chip, improving the performance of the manufactured devices.

[0003] A field effect transistor (FET) includes three main terminals: a source, a drain, and a gate. A fourth terminal is associated with the body or substrate but is generally connected to the source, whereby the FET is controlled as a three-terminal device. Current can flow from the source to the drain through a channel formed within an active (e.g., semiconductor) material, and its conductivity is controlled by the voltage applied to the gate.

[0004] In a conventional design, both the source and the drain are arranged on a two-dimensional plane and formed on the surface of a semiconductor substrate, providing a so-called planar transistor. Then, a conductive channel is formed on the semiconductor substrate, and the length of the channel is determined by the distance between the source and the drain. To adjust the conductivity of the channel, a voltage is applied to a gate electrode that is arranged within the region between the source and the drain and separated from the semiconductor substrate by a dielectric. When a voltage is applied, the current flows (mainly) in the horizontal direction, i.e., parallel to the plane including the source, the drain, and the channel.

[0005] Channel length affects transistor performance in terms of various metrics such as speed and power. In particular, the switching speed of a planar transistor can be improved by shortening the channel, i.e., reducing the channel length. However, the reduction of conventional planar transistors has reached its physical limits. In fact, when the channel length is on the same order as the width of the depletion layer of the source and drain junctions, short-channel effects (SCE) can occur, such as leakage current, drain-induced barrier degradation, or speed saturation. As a result, the gate's ability to properly control the current flow within the channel decreases.

[0006] To mitigate SCE (Sensitivity-Controlled Emission), various gate device structures have been proposed that allow for improved gate control by providing a larger contact area between the gate and the channel region, such as FinFETs or GAA (Gate-All-Around) FETs. These designs include 3D shapes, which improve the "wrapping" of the channel by the gate. Thus, in FinFET transistors, the gate surrounds the channel with three faces of a silicon fin, rather than a single face as in planar arrangements. This wrapping results in improved control capability, enabling shorter channel lengths and faster switching times. GAA FET transistors go a step further, as all four faces of the channel are surrounded by the gate, further improving control capability, resulting in even shorter channel lengths and thus faster switching times. Overall, such 3D structures have enabled channel length reductions down to the nanometer level. However, the manufacturing processes involved are complex and require advanced techniques such as extreme ultraviolet (EUV) lithography. Furthermore, the three-dimensional shape imposes new constraints on downscaling due to the mechanical and structural properties of the resulting structure.

[0007] As a further development to increase the integration density of transistors on a substrate, VTFETs (vertical transport field effect transistors) have been proposed (e.g., U.S. Patent No. 10134893 or U.S. Patent No. 10134642). In this design, the source and drain are no longer located on the same horizontal two-dimensional plane. Instead, these sources and drains are set at different heights relative to the substrate, so that the current flows along at least a portion of the channel in a direction substantially perpendicular to the substrate surface. Such an arrangement makes it possible to increase the integration density of transistors per unit area of ​​the substrate.

[0008] Throughout this disclosure, a vertical field-effect transistor (VFET) refers to a transistor in which the source and drain are not located on the same horizontal plane, i.e., a transistor in which the channel between the source and drain extends at least partially vertically.

[0009] Apart from novel gate structures, materials other than silicon (Si) are being evaluated as active materials. In fact, the electron mobility of bulk materials like Si decreases significantly as we move to the nanoscale, and therefore, a shift to different materials seems necessary to continue downscaling. Accordingly, two-dimensional (2D) materials such as semiconductor carbon nanotubes (CNTs) or transition metal chalcogenides (TMDs) have been proposed as alternatives to Si for the channels of modern FETs. The use of such new materials comes with its own challenges, particularly concerning the fabrication of the materials themselves and their integration into functionally operating devices.

[0010] In summary, the ongoing need to increase the integration density of field-effect elements has led to the creation of numerous transistor shapes and structures using a variety of different materials. There is still a need for transistor designs that enable further integration while maintaining or improving the performance of FET transistors, leading to channel scaling to the subnanometer scale. Furthermore, corresponding manufacturing processes are also required. [Overview of the Initiative]

[0011] In one aspect of the present disclosure, a vertical field-effect transistor (FET) is provided. The vertical FET comprises a substrate and a first electrode disposed on the substrate and configured as either the source or the drain of a transistor. The transistor further comprises a second electrode configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode in an overlapping region. An active layer is sandwiched between the first electrode and the second electrode. The vertical FET includes a gate having a gate conductor portion and a gate insulating layer, the gate insulating layer being disposed between the gate conductor and the active layer. The active layer comprises a one-dimensional material whose longitudinal axis is oriented substantially parallel to the substrate, and / or the active layer may comprise a two-dimensional material whose plane is oriented substantially parallel to the substrate.

[0012] In this embodiment, a vertical FET is presented in which current flows from the source through the active layer to the drain. The direction of the current is substantially orthogonal to the plane defined by the substrate, and the channel length is determined by the thickness of the active layer. In other words, in the case of a one-dimensional material, the current flows transversally (orthogonal to the longitudinal axis of the one-dimensional material). When a two-dimensional material is used, the current flows transversally to the plane of the two-dimensional material. Therefore, transversal transport can be considered as movement along the direction in which each material exhibits quantum confinement. The VFET according to this embodiment makes it possible to increase the integration density of transistors within a given region of the substrate while shortening the channel length.

[0013] In this embodiment, the gate insulating layer is positioned between the gate conductor and the active layer to prevent direct contact between the gate conductor and the active layer; that is, the gate insulating layer forms a barrier between the gate conductor and the active layer. However, the gate insulating layer does not prevent the generation of the field effect in the active layer.

[0014] Throughout this disclosure, the term "active material" refers to a material whose conductivity can be actively adjusted, for example, by applying a voltage, so that it can form conductive channels. In particular, this active material may include semiconductor materials. Correspondingly, an "active layer" refers to a layer containing such an active material.

[0015] Throughout this disclosure, the term “overlapping region” should be understood as an area or region on which the second electrode is positioned along the first electrode, i.e., in a top view, the second electrode blocks at least a portion of the first electrode. Such overlapping regions may exhibit multiple shapes and dimensions. The overlapping periphery may be considered as the outer edge of the overlapping region, i.e., the edge encompassing the overlapping region. It should be understood that overlapping does not in any way imply any direct contact between electrodes within such overlapping region.

[0016] Throughout this disclosure, the terms “sandwiching” and “sandwich structure” may be used to refer to a configuration in which the active layer is positioned between two electrodes, directly adjacent to those electrodes. Thus, throughout this disclosure, a sandwich configuration is understood to mean that the active layer extends over an overlapping region to prevent any direct contact between the electrodes.

[0017] Throughout this disclosure, a one-dimensional (1D) material is understood to be a material containing one-dimensional elements, such as nanotubes. Correspondingly, a reference to the longitudinal axis of a one-dimensional material is understood to refer to the longitudinal axis of the one-dimensional elements that make up the one-dimensional material.

[0018] Further embodiments of the present disclosure provide a method for manufacturing a vertical field-effect transistor. The method includes forming a first electrode on a substrate, depositing an active layer on the first electrode, and forming a second electrode on the active layer, thereby creating a sandwich structure including an overlapping region having an outer periphery. The method further includes defining a gate region, the gate region exposing at least a portion of the active layer. A gate insulating layer is then deposited covering at least the exposed portion of the active layer, and a gate conductor is deposited on the gate insulating layer. Finally, the method includes defining electrical contacts of the first electrode, the second electrode, and the gate.

[0019] According to an embodiment of this further aspect of the present disclosure, a method for manufacturing a vertical FET by minimal or reduced processing steps is provided. By embodiments of the method, downscaling of the channel and / or a longer contact length between the channel and the source / drain electrodes are enabled, thereby reducing contact resistance and improving performance.

Brief Description of the Drawings

[0020] [Figure 1] A top view, a side side view (A-A'), and a front cross-sectional view (B-B') of a vertical field-effect transistor according to an embodiment are schematically shown. [Figure 2] An example of the arrangement of four vertical FETs on a substrate is schematically shown. [Figure 3A-C] A series of steps in an example of a method for manufacturing a vertical field-effect transistor are schematically shown. [Figure 3D-F] A series of steps in an example of a method for manufacturing a vertical field-effect transistor are schematically shown. [Figure 3G-I] A series of steps in an example of a method for manufacturing a vertical field-effect transistor are schematically shown. [Figure 3J-L] A series of steps in an example of a method for manufacturing a vertical field-effect transistor are schematically shown. [Figure 4A-C] A series of steps in another example of a method for manufacturing a vertical field-effect transistor including fins are schematically shown. [Figure 4D-F] A series of steps in another example of a method for manufacturing a vertical field-effect transistor including fins are schematically shown. [Figure 4G-H] A series of steps in another example of a method for manufacturing a vertical field-effect transistor including fins are schematically shown. [Figure 4I-K] A series of steps in another example of a method for manufacturing a vertical field-effect transistor including fins are schematically shown. [Figure 4L]Schematically shows a series of steps in another example of a method for manufacturing a vertical field effect transistor including fins. [Figure 5A-D] Schematically shows a series of steps in a further embodiment of a method for manufacturing a vertical field effect transistor including fins, a side gate, and a gate alignment for minimizing overlap with the source and / or drain. [Figure 5E-H] Schematically shows a series of steps in a further embodiment of a method for manufacturing a vertical field effect transistor including fins, a side gate, and a gate alignment for minimizing overlap with the source and / or drain. [Figure 5I-L] Schematically shows a series of steps in a further embodiment of a method for manufacturing a vertical field effect transistor including fins, a side gate, and a gate alignment for minimizing overlap with the source and / or drain. [Figure 5M-O] Schematically shows a series of steps in a further embodiment of a method for manufacturing a vertical field effect transistor including fins, a side gate, and a gate alignment for minimizing overlap with the source and / or drain. [Figure 6A-D] Schematically shows a series of steps in an example of a method for manufacturing a vertical field effect transistor including a gate-all-around (GAA) configuration with a gate alignment for minimizing overlap with the source and / or drain. [Figure 6E-H] Schematically shows a series of steps in an example of a method for manufacturing a vertical field effect transistor including a GAA configuration with a gate alignment for minimizing overlap with the source and / or drain. [Figure 6I-L] Schematically shows a series of steps in an example of a method for manufacturing a vertical field effect transistor including a GAA configuration with a gate alignment for minimizing overlap with the source and / or drain. [Figure 6M-O]A schematic sequence of steps in an example of a method for fabricating a vertical field-effect transistor, including a GAA configuration with gate alignment to minimize overlap with the source and / or drain, is schematically shown. [Figure 7A-C] The initial steps (up to the deposition of the second electrode) in an example of a method for fabricating a vertical field-effect transistor containing carbon nanotubes (CNTs) as the active material are schematically shown. [Figure 7D] The initial steps (up to the deposition of the second electrode) in an example of a method for fabricating a vertical field-effect transistor containing carbon nanotubes (CNTs) as the active material are schematically shown. [Figure 8A-C] The initial steps (up to the deposition of the second electrode) in another example of a method for fabricating a vertical field-effect transistor containing a stack of single-walled carbon nanotubes (SWCNTs) as the active material are schematically shown. [Figure 8D] The initial steps (up to the deposition of the second electrode) in another example of a method for fabricating a vertical field-effect transistor containing a stack of single-walled carbon nanotubes (SWCNTs) as the active material are schematically shown. [Figure 9A-C] The initial steps (up to the deposition of the second electrode) in a further example of a method for fabricating a vertical field-effect transistor containing a network (web) of SWCNTs as the active material are schematically shown. [Figure 9D] The initial steps (up to the deposition of the second electrode) in a further example of a method for fabricating a vertical field-effect transistor containing a network (web) of SWCNTs as the active material are schematically shown. [Figure 10A-B] The initial steps (up to the deposition of the second electrode) in a further example of a method for fabricating a vertical field-effect transistor containing a two-dimensional transition metal dichalcogenide (TMD) as the active material are schematically shown. [Figure 10C-D]The initial steps (up to the deposition of the second electrode) in a further example of a method for fabricating a vertical field-effect transistor containing a two-dimensional transition metal dichalcogenide (TMD) as the active material are schematically shown. [Figure 11A-C] A schematic example of a method for manufacturing a complementary field-effect transistor (CFET) inverter configuration is shown by placing a second (upper) vertical FET on top of a first (lower) vertical FET. [Figure 11D-F] A schematic example of a method for manufacturing a complementary field-effect transistor (CFET) inverter configuration is shown by placing a second (upper) vertical FET on top of a first (lower) vertical FET. [Figure 11G-I] A schematic example of a method for manufacturing a complementary field-effect transistor (CFET) inverter configuration is shown by placing a second (upper) vertical FET on top of a first (lower) vertical FET. [Figure 11J-L] A schematic example of a method for manufacturing a complementary field-effect transistor (CFET) inverter configuration is shown by placing a second (upper) vertical FET on top of a first (lower) vertical FET. [Figure 11M-O] A schematic example of how to manufacture a complementary field-effect transistor (CFET) inverter configuration is shown by placing a second (upper) vertical FET on top of a first (lower) vertical FET. These figures show the process after the first (lower) FET has already been manufactured, following the example depicted in Figures 3A to 3L. [Figure 12] A schematic example of a CFET inverter including upper and lower contacts is shown. [Figure 13] A schematic example of a CFET inverter obtained by placing a second vertical FET on top of a first vertical FET is shown, and the vertical FET is an embodiment of a transistor including fins as shown in Figures 4A to 4L. [Figure 14]A schematic example of a CFET inverter obtained by placing a second vertical FET on top of a first vertical FET is shown, and the vertical FETs are based on the GAA arrangement transistors shown in Figures 6A to 6O. [Figure 15] A schematic example of a CFET inverter obtained by placing a second vertical FET on top of a first vertical FET is shown, and the vertical FET is based on the example of a transistor containing SWCNT as the active material shown in Figures 7A to 7D. [Figure 16] A schematic example of a CFET inverter obtained by placing a second vertical FET on top of a first vertical FET is shown, where the vertical FETs include unzipped SWCNTs. [Figure 17] Figures 10A to 10D schematically show an example of a CFET inverter in which a two-dimensional transition metal dichalcogenide (TMD) is used as the active material. [Figure 18] A schematic example of a CFET inverter in which different semiconductors are used for the active layers of the upper and lower transistors is shown. [Figure 19] A schematic example of a CFET inverter is shown, where the active layer of each transistor includes multiple sublayers, each of which contains low-dimensional materials of various families. [Figure 20] A schematic example of a CFET inverter is shown, in which the active layer includes multiple sublayers, each sublayer containing a low-dimensional material of a similar family. [Figure 21A-D] A schematic outline of a further series of steps in an example of a method for manufacturing a vertical field-effect transistor is shown below. [Figure 21E-H] A schematic outline of a further series of steps in an example of a method for manufacturing a vertical field-effect transistor is shown below. [Figure 22A-D] A schematic diagram outlines a series of steps in an example of a method for fabricating a vertical field-effect transistor, including a dual-gate structure. [Figure 22E-H] A schematic diagram outlines a series of steps in an example of a method for fabricating a vertical field-effect transistor, including a dual-gate structure. [Figure 22I-L] A schematic diagram outlines a series of steps in an example of a method for fabricating a vertical field-effect transistor, including a dual-gate structure. [Figure 22M-O] A schematic diagram outlines a series of steps in an example of a method for fabricating a vertical field-effect transistor, including a dual-gate structure. [Figure 22P] A schematic diagram outlines a series of steps in an example of a method for fabricating a vertical field-effect transistor, including a dual-gate structure. [Figure 23] This flowchart shows an example of a method for manufacturing a vertical field-effect transistor. [Figure 24] This flowchart shows an example of a method for manufacturing the active layer of a vertical field-effect transistor. [Modes for carrying out the invention]

[0021] Each embodiment is provided for illustrative purposes only, and not as an limitation. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in this disclosure. For example, features illustrated or described as part of one embodiment can be used in conjunction with other embodiments to obtain yet another embodiment. This disclosure covers modifications and variations that fall within the scope of the appended claims and their equivalents. Furthermore, the drawings are intended to illustrate various embodiments and manufacturing processes. For clarity, various dimensions are not to scale to facilitate identification of various components.

[0022] Figure 1 shows an example of a vertical field-effect transistor 100. The figure shows three different views of the transistor: a top view (left side), a side section view (i.e., a view along the plane A-A' shown in the top view), and a front section view (i.e., a view along the plane B-B' shown in the top view). This arrangement of the top view and section view is repeated for many of the other views.

[0023] The vertical FET 100 includes a substrate 101. The substrate 101 may be a silicon (Si) wafer, but other substrates known in the art, such as silicon germanium (SiGe) or III-V semiconductor wafers, may also be used. In Figure 1, a first electrode 102 is placed on the substrate 101. This first electrode functions as either the source or the drain of the transistor 100. Various conductive materials, including metals (Pd, Rh, Mo, Sc, Au, Pt, W, Ti, etc.), nitrides (TiN), oxides (TCO), two-dimensional materials (e.g., graphene), or one-dimensional materials (e.g., metallic carbon nanotubes), may be used for the first electrode 102.

[0024] Throughout this disclosure, two-dimensional materials may be considered as crystalline materials consisting of a single or several layers of atoms. In two-dimensional materials, two dimensions are outside the nanoscale range. Two-dimensional materials include, for example, graphene, nanofilms, nanolayers, and nanocoatings. One-dimensional materials may be considered as materials in which only one dimension is outside the nanoscale range. One-dimensional materials include nanotubes (CNTs, MoS2 nanotubes, or WS2 nanotubes), nanorods, nanowires, and others.

[0025] Throughout this disclosure, low-dimensional materials may be considered materials that have at least one dimension small enough (nanoscale) for the material's physical properties to exist somewhere between individual atoms and the bulk material. These may include zero-dimensional, one-dimensional, two-dimensional, and three-dimensional materials.

[0026] The first electrode can be obtained by standard semiconductor manufacturing techniques, including chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or ink-based additive manufacturing.

[0027] A layer 103 of an active material (e.g., a semiconductor) is placed on top of the first electrode. In the example in Figure 1, the active layer 103 only partially covers the first electrode 102. However, various configurations are possible, as shown in further embodiments. The active material used in the active layer 103 may include the following, namely, two-dimensional materials (TMDs such as MoS2, WS2, WSe2, etc.) ] ), metalloids such as semimetallic graphene, xenes (e.g., phospholene, silicene), MXene, semiconductor alloys, amorphous silicon (one-dimensional materials such as semiconductor CNTs, MoS2 nanotubes, WS2 nanotubes, nanowires, or nanorods), organic semiconductors, perovskites, and further inorganic semiconductors such as IGZO (Indium gallium zinc oxide). A variety of options are available, including [this].

[0028] As shown in Figure 1, the second electrode 104 is deposited on the active layer 103. The same material described for the first electrode 102 can also be used for the second electrode 104. Different materials may be used for the first electrode 102 and the second electrode 104 of the same transistor. For example, this allows for the use of various conductors for work function engineering to adjust the electrical resistance at the contact with the active material. The active layer 103 functions as the channel of the transistor, and in this case, the channel length of the transistor depends on the thickness of the active layer 103.

[0029] The second electrode 104 overlaps with the first electrode 102 in a specific overlapping region. In this example, the overlapping region forms a rectangular ring. The overlapping region defines the outer perimeter, which in the embodiment shown in Figure 1 defines a rectangular shape with length d1 and width d2, as shown in the figure. The sum of the overlapping regions d1 and d2 (outer perimeter) is similar to the concept of channel width in conventional planar FETs.

[0030] The figure also shows the first interlayer dielectric layer 105. Various dielectric materials can be used for the interlayer dielectric (ILD) layer, such as organic and inorganic oxides or other low dielectric constant materials. The ILD layer can be obtained by standard deposition techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), sputtering, or spin coating (e.g., SOD).

[0031] The vertical field-effect transistor further includes a gate having a gate conductor portion and a gate insulating layer, the gate insulating layer 106 having a U-shaped cross-section, surrounding the gate conductor portion 107 and being arranged in contact with the active layer 103.

[0032] The gate insulating layer 106 is in contact with a portion of the active layer 103 along its thickness. For the gate insulating layer 106, a material with a high dielectric constant is preferred. Therefore, SiO2, SiO2 x N y A, or preferably a high dielectric constant material (e.g., HfO2, Al2O3, HfSiON, ZrO2, La2O3, Ta2O5, TiO2, BaTiO3) may be used. The gate structure further includes a gate conductor 107 disposed within an internal space defined by a U-shaped gate insulating layer 106.

[0033] As shown in Figure 1, the gate conductor 107 is deposited (i.e., formed or grown) on the gate insulating layer 106, thereby preventing direct contact between the gate conductor 107 and either of the electrodes 102 and 104 or the active layer 103. Applying a specific voltage to the gate conductor 107 determines the flow of current between the first electrode 102 and the second electrode 104 through the active layer 103.

[0034] As shown in Figure 1, one feature of this design is that, assuming the substrate is placed on a flat horizontal surface, the current flows in a direction substantially perpendicular to the substrate, i.e., perpendicular to it. A second interlayer dielectric (ILD) 108 may be placed inside the transistor 100. The same dielectric material as the first dielectric layer 105 may be used for the second dielectric 108, but it should be understood that different dielectrics may be used for each dielectric within the same transistor.

[0035] Finally, three contacts may be provided to define the three terminals of the transistor. In particular, a first source / drain contact 109 is used to contact the first electrode 102, a second source / drain contact 110 is used to contact the second electrode 104, and a third contact 111 is used to contact the gate conductor 107. Similar to the electrodes, various materials can be used for the contacts. These include metals (e.g., Ti, Ru, W, Co, Ni), nitrides (TiN, TaN), binary alloys, metallic carbon nanotubes (CNTs), or conductive two-dimensional materials such as graphene.

[0036] Figure 1 provides a schematic diagram of a single transistor 100. As is well known to those skilled in the art, a very large number of such transistors can actually be fabricated on a single substrate. For illustrative purposes, Figure 2 provides a diagram showing a set of four transistors 201-204, which may also represent a small portion of the entire substrate.

[0037] Here, with reference to Figures 3A to 3L, an example of a manufacturing sequence for obtaining a vertical field-effect transistor as presented with reference to Figure 1 is described. Figure 3A shows the first step in the above sequence, which is the formation of the first electrode 302 on the substrate 301. The present invention is by no means limited to a specific substrate.

[0038] In some examples, the substrate 301 may be silicon (Si). Furthermore, the substrate may contain a dielectric layer, such as a thermally grown oxide. Alternatively, the dielectric layer can be deposited by standard deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0039] As already mentioned with reference to Figure 1, various materials can be used for the first electrode 302. The choice of material 1 or another may also affect the technique used for its formation. Lithography and additive manufacturing, which combine lift-off and / or etching-based processes, can be used to form the desired pattern. In some examples, the substrate 301 may first be patterned by photolithography and dry etching steps. Subsequently, the material for the first electrode 302 may be deposited (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). After that, a chemical mechanical planarization (CMP) process may be used to obtain a smooth surface and to remove the required amount of material.

[0040] The next possible step is shown in Figure 3B. This step involves the deposition (i.e., formation, covering, and growth) of the active layer 303. In this example, the active layer 303 is deposited over the entire area of ​​the substrate so as to completely cover the first electrode 302. Different materials, including one-dimensional and two-dimensional materials, can be used for the active layer 303, as already described with reference to Figure 1.

[0041] The next step (Figure 3C) is the deposition of the second electrode 304, which in this particular embodiment is also deposited over the entire area. The same materials and techniques already described with respect to the first electrode 302 and with reference to Figure 1 can be used for the second electrode 304. At this stage of the manufacturing process, a sandwich structure is created, comprising the first electrode 302 at the bottom, the second electrode 304 on top, and the active layer 303 between them.

[0042] In a further step (Figure 3D), photolithography and / or dry etching may be used to define the region of the transistor. As is known to those skilled in the art, an etch mask may be used to facilitate etching. In particular, in this step, the dimensions of the active layer 303 and the second electrode 304 are defined. In this step, the shape and dimensions of the overlapping region, i.e., the region in which the second electrode 304 overlaps with the first electrode 302, are defined. This overlapping region defines the overlapping outer periphery and corresponds to a rectangle having sides d1 and d2 in the illustrated embodiment.

[0043] Following the completion and definition of the sandwich structure, the next step may include the deposition of a first interlayer dielectric (ILD) layer 305 (Figure 3E). Such an ILD may be useful in preparation for the next step, in which a gate region 317, similar to a cavity or well in this case, is defined by a photolithography step and a dry etching step, as shown in Figure 3F. As is known to those skilled in the art, an etch mask may be used to facilitate etching. As shown in Figure 3F, the gate region 317 in this particular embodiment is entirely inside the outer periphery of the overlapping region, or embedded within the range of the outer periphery of the overlapping region. As a result, the gate of the transistor is completely surrounded by the semiconductor, thus providing a semiconductor-all-around (SAA) arrangement. Such an arrangement results in a large surface area between the gate and the active layer 303, which allows for a better ability of the gate to control the flow of current in the channel defined by the active layer 303.

[0044] After the gate region 317 (such as a cavity) is defined, the next step (Figure 3G) may be the formation or deposition of a gate dielectric to form a gate insulating layer 306 with a U-shaped cross-section. As shown in Figure 3G, in this manufacturing process, the gate dielectric is first deposited across the entire substrate, i.e., deposited not only within the gate region 317 but also on top of the ILD layer 305. The gate dielectric 306 may include, but is not limited to, various materials such as silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, yttrium oxide, silicon oxynitride, silicon nitride, boron nitride, zirconium silicon oxide, hafnium silicon oxide, zirconium oxide, lanthanum oxide, or preferably high dielectric constant materials (e.g., HfO2, HfSiO4, or O4SiZr). Depending on the selected material, the gate insulating layer 306 may be formed by standard techniques known to those skilled in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or preferably atomic layer deposition (ALD).

[0045] Following the deposition of the gate insulator described above, the gate conductor 307 is deposited in the next step (Figure 3H). Similar to the deposition of the gate insulator described above, the gate conductor in this example is also deposited over the entire area, that is, on top of the previously deposited insulating layer.

[0046] Figure 3I shows the step of removing excess material from both the insulating layer and the gate conductor, i.e., the step of removing material from the area extending beyond the boundary of the gate region 317 shown in Figure 3F. For this purpose, etching and chemical mechanical planarization (CMP) processes can be used. This step can also be used immediately after the deposition of the gate insulator and can be repeated after the deposition of the gate conductor.

[0047] Next, as shown in Figure 3J, a second interlayer dielectric (ILD) layer 308 can be deposited. This is followed by the formation of contact regions 319, 320, and 321 for the electrodes and gate. Figure 3K shows the patterning of ILD layers 305 and 308. This process involves photolithography and dry etching to expose the first electrode 302 by generating contact region 319, the second electrode 304 within contact region 320, and the gate structure 307 within contact region 321.

[0048] Finally, as shown in Figure 3L, contact material can be deposited to form the first electrode contact 309, the second electrode contact 310, and the gate structure contact 311. In this case, although not shown in the sequence above, the contact material can be deposited over the entire surface (corresponding to the deposition of insulating material and gate conductor shown in Figures 3G and 3H), and then selectively removed from areas not aligned with the electrodes and gate by a chemical mechanical planarization (CMP) process. Multiple contact material stacks can be used, such as a barrier layer by PVD or ALD (TiN, Ti) followed by materials (such as, but not limited to, two-dimensional or one-dimensional materials deposited by ALD, PVD, or CVD, or coatings of Al, Cu, W, CVD, or other materials). Other conductors such as ruthenium oxide and tantalum nitride can also be used.

[0049] The method described above requires relatively few processes: three photolithography steps for transistor manufacturing and one more step for contact apertures. Another advantage is that it enables scaling to less than 10 nm using single-exposure (no multi-patterning required) dry DUV (deep ultraviolet) lithography, without the need for expensive immersion lithography or EUV (extreme ultraviolet) lithography. Using EUV would allow for higher resolution and reduction in all dimensions.

[0050] Figures 4A to 4L show the manufacturing sequence of a second embodiment of a vertical FET. All steps are also presented, but this description will focus on aspects that differ from the sequence described earlier (see Figures 3A to 3L). In the first step, Figure 4A shows the formation of the first electrode 402 on the substrate 401. Note that in this sequence, the contact 409 for the first electrode 402 is formed in the early stages of the process. In this example, the transistor includes a bottom contact, whereas all transistors shown with reference to Figure 1 (and manufacturing sequences 3A to 3L) had the contact at the top. In any case, as will be understood by those skilled in the art, both configurations can be combined, for example, the first contact 109 in Figure 1 can also be arranged as a bottom contact. Conversely, the bottom contact 409 in Figure 4A can also be arranged as a top contact by following the steps shown for the equivalent contact with respect to the example in Figure 3.

[0051] Figures 4B to 4E relate to manufacturing steps that are broadly the same as or equivalent to those already described with respect to Figures 3B to 3E, and therefore no further explanation is considered necessary. In particular, the interlayer dielectric (ILD) layer 405 is deposited after the patterning of the second electrode 404 and the active layer 403.

[0052] Figure 4F differs from Figure 3F because the transistor in this embodiment includes a fin F4. Even though this embodiment includes a single fin, it should be understood that alternative designs including a larger number of fins can be realized in a similar manner. For clarity, the term "fin" refers to a fin-like structure created within the space between two cavities. Therefore, Figure 4F, unlike Figure 3F, shows how two gate regions or cavities are defined within the structure. More than two cavities can be created in a similar manner.

[0053] As a result, the first electrode 402, the second electrode 404, and a portion of the active layer 403 remain in the space between the two cavities, forming a fin F4. The use of such a fin allows for a larger contact area between the gate and the active layer. This larger contact area improves the gate's ability to control the flow of current within the transistor. After the two regions or cavities have been formed, the subsequent steps in this example are shown in Figures 4G to 4L. These steps are equivalent to those already shown in Figures 3G to 3L, the only major difference being the presence of the fin, and thus there are two cavities for depositing the gate insulator and gate conductor material. The gate insulating layer 406 and gate conductor 407 are used to create the gate structure of the transistor, and after the second dielectric layer 408 is deposited as shown in Figure 4J, contacts are created for the different terminals of the transistor. Figure 4L in particular shows the terminals for the first electrode 409, the second electrode 410, and the gate 411. Needless to say, the same materials and techniques described for the embodiment in Figure 3 will also be applied to this design.

[0054] Figures 5A to 5O show sequences of yet another embodiment of a vertical transistor according to one embodiment. As with the previous process, only the relevant changes to the basic process are detailed. In this case, a vertical transistor is manufactured in which the gate contact is located on one side and extends beyond the overlapping region, thus providing a so-called "side-gate" configuration. Such a "side-gate" configuration allows for horizontal alignment of the gate structure and the active layer, resulting in reduced parasitic capacitance between the gate conductor and the electrode. This special manufacturing process produces a vertical transistor with fins. However, this is merely an optional feature, and it should be understood that the same side-gate configuration, including a horizontally aligned gate, can be used in transistors with multiple fins or transistors without such fins. Referring to the figures, it will be clear that Figures 5A to 5E are equivalent to Figures 3A to 3E described previously, so no further explanation is needed. Therefore, Figure 5E shows the first electrode 502, the second electrode 504, the active layer 503, the substrate 501, and the first dielectric layer 505.

[0055] Figure 5F shows the formation of a gate region for the gate. As in Figure 4F, a fin F5 is present in this case as well, because the first electrode 502, the second electrode 504, and a portion of the active layer 503 formed on the substrate 501 are located in the space between the two elongated sections or cavities of the gate region. In contrast to previous embodiments, the gate in this manufacturing process is not completely surrounded by the outer periphery of the overlapping region. On the contrary, one section of the gate region (G5 in Figure 5F) extends laterally beyond the overlapping region. This difference enables the side gate arrangement in this embodiment.

[0056] Further characteristic steps can be described with reference to Figures 5G and 5H. Unlike previous embodiments, the gate insulating layer and gate conductor are not deposited or formed immediately after the formation of the region gate. Instead, an interlayer dielectric (ILD) layer SP51 is deposited (Figure 5G) and then etched (Figure 5H). Etching of the ILD layer SP51 can be performed by atomic layer etching (ALE) or reactive ion etching (RIE) (i.e., with or without plasma etching), and is controlled so that a spacer SP5 (similar to a cavity or well) is generated at the bottom of the region. This spacer reduces or minimizes the vertical overlap between the gate structure and the first electrode 502. For this purpose, the height of the spacer is controlled so that its upper surface is positioned slightly below the lower surface of the active layer 503, so that the gate conductor deposited in a later stage is at substantially the same level as the active layer 503. In particular, the spacer SP5 is such that there is a gap between the plane of the upper surface of the spacer SP5 and the plane of the lower surface of the active layer 503. The width of this gap corresponds to the thickness of the insulating layer 506 that will be deposited in a later stage, as described below.

[0057] After the spacer is defined, the process proceeds to the formation of the gate insulating layer 506 and the deposition of the gate conductor 507. Because the spacer SP51 is present and there is a gap between its upper surface and the lower surface of the active layer 503, this deposition results in a gate insulating layer whose lower surface and upper surface are substantially aligned with the lower surface of the active layer 503, and gate conductors 507 whose respective lower surfaces are substantially flush with the active layer 503, i.e., at the same height as the active layer 503. This is followed by etching and planarization of the same gate insulating layer 506 and gate conductor 507.

[0058] Within the region outside the gate area. These processing steps are shown in Figures 5I to 5K and are equivalent to those already described with respect to the previous manufacturing process.

[0059] Further specific aspects of this embodiment are illustrated in Figure 5L. The gate structure, including the gate insulating layer 506 and the gate conductor 507, is etched by a controlled etching process such that the top surface of the gate is substantially flush with or at the same height as the top surface of the active layer 503. The corresponding technical effect is that the gate structure is aligned with the active layer 503, thereby minimizing the overlap with the second electrode 504. This has the beneficial effect of reducing parasitic capacitance within the transistor. After the formation of the gate structure, the process proceeds to the deposition of the ILD layer 508 and the demarcation of the contacts. This is shown in Figures 5M to 5O, but is equivalent to Figures 3J to 3L, so further details are not considered necessary. Thus, contact regions 519, 520, and 521 are opened by photolithography and dry etching for the contacts of the first electrode 509, the second electrode 510, and the gate 511.

[0060] In this example, the term "flush" should be understood to mean that the gate conductor 507 is positioned at substantially the same level as the active layer 503 on both the bottom and top surfaces. The thickness of the gate conductor 507 is substantially the same as the thickness of the active layer 503, and each position is such that the overlap between the gate conductor 507 and the lower electrode 502 or upper electrode 504 is minimized. In a further variation of this same concept, the design may include a gate conductor 507 with a thickness smaller than that of the active layer 503. By appropriately adjusting the height of the spacer SP51 and etching the gate insulating layer 506 and the gate conductor 507 after deposition, it is possible to have a gate conductor 507 whose thickness falls within the range of the thickness of the active layer 503, or in other words, to allow the active layer 503 to overlap with the gate conductor 507 on both the bottom and top surfaces.

[0061] Next, a further example, including a Gate-All-Around (GAA) configuration, is presented with reference to Figures 6A to 6O. In this example, a gate surrounding the semiconductor is defined. In particular, the gate is positioned to surround the outer periphery of the overlapping region between the electrodes. As with the previous embodiment, this embodiment also allows for a large contact area between the gate and the active layer, thereby facilitating the operation of the transistor. More than one gate can be realized in a modified GAA configuration in which each side functions as a separate control gate.

[0062] Similar to the examples shown in Figures 5A to 5O, the example in Figure 6 also features a side gate aligned with the active layer. For this reason, only the novelty of this embodiment will be described below.

[0063] Figures 6A to 6C are generally roughly equivalent to Figures 4A to 4C, so no further explanation is considered necessary. In particular, in this case, the lower electrode 609 is also used for the first electrode 602. Figure 6D shows the patterning step for defining the overlapping region. As in previous embodiments, this patterning step includes photolithography and dry etching.

[0064] In this case, the first electrode 602, the second electrode 604, and the active layer 603 completely overlap, meaning they all have substantially the same dimensions, and as a result, after patterning, none of them extend beyond the other electrodes in the horizontal plane.

[0065] Figure 6F shows the patterning of the gate placement region 617 after the deposition of the ILD layer 608. As previously mentioned, since this is an embodiment of GAA, unlike previous designs, the gate region is no longer inside or embedded within the overlapping region, but surrounds it; that is, the gate region is adjacent to the outer periphery but located outside of it. Furthermore, as also shown in Figure 6F, a groove provided for the gate region extends laterally, thereby defining the side gate. The remaining steps (Figures 6G to 6O) include the formation of a spacer SP6 using an additional dielectric SP61, and etching of the gate structure (gate insulating layer 606 and gate conductor 607) to enable alignment of the gate with the active layer 603, as shown in Figure 6L. The steps required to achieve this alignment are equivalent to those described with reference to Figures 5A to 5O, so no further details are considered necessary.

[0066] The alignment of the gate conductor 607 and the active layer 603 is such that, when the thickness of the gate conductor 607 is substantially the same as the thickness of the active layer 603, the bottom / top surface of the gate conductor 607 is aligned with the bottom / top surface of the active layer 603. In a modified example of this embodiment, the thickness of the gate conductor 607 may be made smaller than the thickness of the active layer 603, so that the active layer 603 overlaps the gate conductor 607. In other words, by having a gate conductor 607 with a thickness smaller than the thickness of the active layer 603, it is possible to have a design in which the bottom surface of the gate conductor 607 is slightly above the bottom surface of the active layer 603, while the top surface of the gate conductor 607 is slightly below the top surface of the active layer 603. In this way, any overlap between the gate conductor 607 and the first electrode 602 or the second electrode 604 can be further minimized, thereby improving performance.

[0067] The remaining steps include defining the contacts 609 for the first electrode, 610 for the second electrode, and 611 for the gate, after the contact openings 620 for the second electrode and 621 for the gate have been provided. These steps are equivalent to those described with reference to Figures 5G to 5O, and therefore no further explanation is considered necessary.

[0068] Figures 21A to 21H show steps for yet another embodiment for manufacturing a vertical FET. In this example, the gate region is defined differently, as illustrated in the accompanying diagram.

[0069] Figure 21A corresponds to a situation similar to that previously described with reference to Figure 6D. At this stage of the manufacturing process, the system includes a first electrode 752 formed on the substrate 751. The contact for the first electrode 752 in this example is the bottom electrode 759. Meanwhile, the active layer 753 and the second electrode 754 are also present.

[0070] Referring to Figures 6C and 6D, it should be noted that the step shown in Figure 21A can be achieved after etching the second electrode 754 and the active layer 753 over the area not overlapping with the first electrode 752, so that the first electrode 752, the second electrode 754, and the active layer 753 completely overlap. However, in this case, patterning and etching may also remove some of the material of the substrate 751. Therefore, as also shown in Figure 21A, the upper surface of the substrate 751 after the etching step is not aligned with the lower surface of the active layer 753. In particular, as shown in Figure 21B, there is a gap between the upper surface of the substrate 751 and the lower surface of the active layer 753, the width of which substantially corresponds to the thickness of the gate insulating layer 756. As a result of etching, at least a portion of the active layer 753, corresponding to the thickness of the active layer 753, is exposed, and in this example there is a specific region 777 that functions as a gate region.

[0071] The next possible step in this embodiment is shown in Figures 21B and 21C, which includes depositing a gate insulating layer 756 onto the entire substrate and subsequently depositing a gate conductor 757 on top of the previously deposited insulating layer 756. In this way, the insulating layer 756 is positioned between the gate conductor 757 and all other parts (i.e., the active layer 753, the substrate 751, and the second electrode 754). Note that due to the gap that occurs between the upper surface of the substrate 751 and the lower surface of the active layer 753 during the etching process shown in Figure 21A, the upper surface of the gate insulating layer 756 is aligned with the lower surface of the active layer, thereby allowing the lower surface of the conductor 757 to be substantially aligned with the active layer 753 on each of its lower surfaces.

[0072] An ILD layer 755 is deposited on the entire surface to provide a flat surface, which is then etched in the steps shown in Figure 21E. This etching may be performed after the CMP process, but is done so that both the gate conductor 757 and the gate insulating layer 756 are removed from the area above the second electrode 754, thus enabling subsequent contact at that electrode. An additional dielectric layer 758 may be deposited in preparation for contact patterning to define contacts for both the second electrode 754 and the gate conductor 757. This can be seen in Figure 21G, and as a result, cavities 771 and 770 are formed, intended to contact the second electrode 754 and the gate conductor 757, respectively. The deposition of the dielectric layer 758 is optional. In this example, the transistor is completed in the steps shown in Figure 21H, where contact material is deposited to create contact 761 for the second electrode 754 and contact 760 for the gate conductor 757.

[0073] A combination of gate-all-around (GAA) and semiconductor-all-around (SAA) can also be realized using a similar method. In such a design, the gate area can be further increased to better control the gate-induced field effect of the active channel material (e.g., semiconductor). This combination is particularly useful for designs that include relatively large overlapping regions. While a gate surrounding a semiconductor can provide a large contact area, it may sometimes be difficult to induce the field effect across the entire semiconductor layer within the overlapping region. For this reason, the combination with an internal gate allows for a larger contact surface as well as a better distribution of the electric field. Such combinations are described here with reference to Figures 22A to 22N.

[0074] Figure 22A shows a stage similar to those already depicted in previous figures (e.g., Figure 6C). A first electrode 852 is formed on the substrate 851. In this example, the first electrode 852 has a bottom contact 859. An active layer 853 is deposited on top of the first electrode 852, and the active layer 853 is sandwiched between the first electrode 852 and the second electrode 854. As shown in Figure 22B, in this example, patterning and etching steps are performed so that the first electrode 852, the active layer 853 and the second electrode 854 overlap over the same overlapping region, i.e., they overlap substantially completely. The next step in the manufacturing sequence according to this embodiment is shown in Figure 22C, where an interlayer dielectric 855 is deposited.

[0075] Figure 22D schematically illustrates the main differences from the other embodiments described. Thus, not only is a single gate region defined, but a combination of the SAA and GAA approaches is used by defining two regions. In particular, a first region 867a is defined, which is located inside the outer periphery of the overlapping region. Thus, this first gate region 867a is similar to the gate region defined with reference to Figures 3A-3L (i.e., in the SAA configuration). A second gate region 867b is defined, surrounding the active layer 853. This second gate region 867b features a gate-all-around (GAA) concept similar to the embodiments shown with reference to Figures 6A-6O. By combining both approaches, a large contact area between the gate and the active layer 853 is achieved, resulting in a more uniform channel formation and improved transistor control capability.

[0076] To improve the behavior of the transistor, previous embodiments (see Figure 5L or Figure 6L) have already shown the use of a aligned gate configuration, i.e., an arrangement in which the gate conductor of the gate is substantially aligned with the active layer. This is also shown in this embodiment. Accordingly, Figure 22E shows the deposition of dielectric SP81, which is then etched to form spacer SP8, as shown in Figure 22F. The process for manufacturing spacer SP8 is equivalent to that already described with reference to previous embodiments, so no further details are considered necessary.

[0077] Figures 22G and 22H show the deposition of the gate insulating layer 856 and the gate conductor 857. Subsequently, portions of the gate insulating layer 856 and the gate conductor 857 that do not overlap the gate regions 867a and 867b are removed as already described in previous embodiments (see Figure 22I). Furthermore, to reduce parasitic capacitance and optimize device performance, the gate insulating layer 856 and the gate conductor 867 are etched as shown in Figure 22J, so that their upper surfaces are substantially aligned with the upper surface of the active layer 853.

[0078] The final step corresponds to the formation of electrical contacts. Following a process equivalent to that already described, the interlayer dielectric 858 (Figure 22K) is deposited, and a patterning step is performed as shown in Figure 22L to form cavities for contacts. In particular, cavity 870 is made for contact with the second electrode 854. Note here that, since there are two gate regions in this example, two cavities are used for the gates. In fact, the first gate cavity 871a is formed for the gate region located within the overlapping region (i.e., the SAA gate), and the second gate cavity 871b is formed to allow contact with the gate region surrounding the active layer 853. Finally, the conductive material is deposited to form the contacts. In particular, contact 860 is formed for the second electrode, and two contacts 861a and 861b are formed for both the gate conductor located in the inner region 867a and the gate conductor located in the outer region 867b, respectively.

[0079] In one modified example of this embodiment, gate conductor 861a and gate conductor 861b may be connected, as shown in Figure 22N.

[0080] In this example, the contact 860 for the second electrode 854 is not perfectly aligned. This is preferable in this particular example because the horizontal dimension of the second electrode 854 within the contact area is small. However, in further modifications, the contact 860 and the second electrode 854 can be aligned. In yet another modification, one side of the contact 860 may be in contact with the second electrode 854. These modifications are schematically shown in Figure 22O (aligned upper contact) and Figure 22P (side contact), respectively.

[0081] To date, various manufacturing processes resulting in vertical field-effect transistors, including various gate structures, have been disclosed. Beyond these, further modifications are possible depending on the specific active material used in the active layer. The following examples describe designs involving various materials. Even if these materials are presented with reference to one of the previous designs (in particular, the designs corresponding to Figures 3A–3L), this is not intended to constitute a limitation, for the same materials can be used in any of the previously disclosed modifications or in further modifications, which are also covered by the claims.

[0082] Figures 7A to 7D show the initial steps of the manufacturing process for a vertical field-effect transistor in another embodiment in which single-walled carbon nanotubes (SWCNTs) are used as the active material. In particular, the transistor in this embodiment has a single row of SWCNTs, which are arranged with their longitudinal axes parallel to the substrate, i.e., horizontally if the substrate is also positioned horizontally. As a result of this arrangement, current flows not only along the axis of the SWCNTs themselves but also transversally to the SWCNTs, and consequently, a channel length (thickness of the active material such as CNTs) in the range of less than 1 nm (~1 nm) can be obtained. In further examples, multi-walled CNTs, or other one-dimensional materials such as MoS2 nanotubes, WS2 nanotubes, nanowires, or nanorods can be used.

[0083] The first step of the process (Figure 7A) involves the formation of a first electrode 702 on the substrate 701, which is equivalent to the previous method. Subsequently, a single row of SWCNTs 703 is formed on the substrate, as also shown in Figure 7A. SWCNTs can be obtained, for example, by chemical vapor deposition (CVD), arc discharge, and then pre-purified before deposition on the substrate. Alternatively, carbon nanotubes can also be grown directly on the substrate. When using CNTs as the active material, it is important to note that there is a particular risk of short-circuiting between the first electrode 702 and the second electrode 704. In fact, several gaps G7 (see enlarged image of Figure 7A) may exist within the single row of SWCNTs 703. To mitigate this risk, several additional steps are proposed in this embodiment.

[0084] This additional step will be described with reference to Figures 7B and 7C. Thus, after the deposition of SWCNTs 703, a conformal insulating material 733 (e.g., SiO2) can be deposited on top of the SWCNTs 703 (Figure 7B). Standard techniques such as chemical vapor deposition (CVD) can be used for the deposition of the conformal dielectric 733, but ALD is the preferred technique. This dielectric material 733 is a filler material that fills all voids or gaps between the SWCNTs 703 to create a compact structure. Naturally, direct contact between the second electrode 704 and the active material, i.e., the single row of SWCNTs 703, is required during operation. For this reason, the method may further include etching the dielectric material 733 until the SWCNTs 703 are exposed, for example by atomic layer etching (ALE), and the etching environment can be vapor-based etching, wet etching, or plasma etching. Selective etching that does not affect the CNTs can be used, or a non-selective or limitedly selective precision etching environment can be used. It is noteworthy that insulator deposition by ALD can have less preference for nucleation and growth on materials such as CNTs, and that etching processes (if necessary) and CNT exposure processes that do not etch the CNTs are possible. As a result of the processing steps shown in Figures 7B and 7C, a compact active layer containing a single row of SWCNTs 703 is obtained within a matrix of dielectric material 733. Subsequent steps begin with the deposition of a second electrode 704 on the formed active layer and end with the formation of the final contact. However, these steps are equivalent to those already described with respect to, for example, Figures 3C to 3L, and therefore no further explanation is considered necessary.

[0085] The use of single-row SWCNT703 was mentioned in previous Figures 7A to 7D. However, the same process can be used for other one-dimensional materials such as multi-walled CNTs, MoS2 nanotubes, WS2 nanotubes, nanowires, or nanorods.

[0086] Figures 8A to 8D show a scenario in which SWCNTs are used in a stacked configuration. In this case, multiple, preferably at least five, rows of aligned SWCNTs 803 are used as the active material. The SWCNTs are provided on a substrate 801. By using aligned SWCNTs, the density of nanotubes between electrodes can be increased, and therefore the charge carrier density can be improved. In alternative examples, multilayer CNTs or other one-dimensional materials may be used instead of SWCNTs. The aligned nanotubes may be pre-purified and aligned during the deposition process, or they may be grown directly on the first electrode. As in the previous case, certain gaps (G8 in the magnified image of Figure 8A) may exist within the structure. For this reason, Figures 8B and 8C show the deposition of conformal dielectric material 833 and the subsequent etching process (Figure 8C), as already described in relation to the previous embodiment.

[0087] In the active layer, using multiple rows of SWCNTs 803, as opposed to single rows, offers a significant advantage in terms of the transistor's resistance to the presence of metallic carbon nanotubes. It is known that during the SWCNT manufacturing process, some SWCNTs acquire metallic properties. Using such SWCNTs in a configuration including single-row SWCNTs (as shown in Figure 7) would result in a short circuit between the first and second electrodes, thus damaging the transistor. By using multiple rows of CNTs in the manner shown in Figure 8, the current flows transversally through the SWCNTs, mitigating the risk of a short circuit between the first electrode 802 and the second electrode 804, and significantly reducing the probability of a completely electrical path of metallic CNTs existing between the source and drain. Using aligned CNTs also allows for increased current density.

[0088] Figures 9A to 9D show other variations in which SWCNTs are used as the active material. In this case, a network or web of carbon nanotubes 903 is used and provided on a substrate 901. The carbon nanotubes can be pre-purified and deposited during the process. The density of SWCNTs in this embodiment is lower than in the previous embodiment. Nevertheless, this solution has advantages in terms of ease of manufacturing. In any case, as also shown in Figures 9B and 9C, several steps are proposed to realize a compact active layer. As in the previously described case, a conformal dielectric 933 is used to provide a compact structure so as to prevent a short circuit between the first electrode 902 and the second electrode 904. As in the previous embodiment, by using multiple rows of CNTs in the manner shown in Figure 9, the risk of a short circuit between the first electrode 902 and the second electrode 904 is mitigated because the current flows transversally through the SWCNTs, and the probability of a completely electrical path of metallic CNTs existing between the source and drain is extremely low. Furthermore, as in previous embodiments, networks or webs of other one-dimensional materials can be used in various embodiments.

[0089] Figures 10A to 10D correspond to one embodiment in which different types of active materials are used. In this case, two-dimensional materials are utilized. In a particularly preferred embodiment, transition metal dichalcogenides (TMDs) such as MoS2 or WS2 are used. The selection of the optimal material depends, among other things, on whether the transistor is intended to have P-type or N-type properties. In that sense, various processes such as doping, annealing, or other kinds of known operations can be used to modify the active layer to change the properties of the active layer. The above two-dimensional materials can be grown, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD), transfer, spin coating deposition, dip coating, etc. The two-dimensional material has its planes arranged substantially parallel to the substrate, so that the current flows along the thickness of the two-dimensional material, i.e., transversally to the plane of the two-dimensional material. As shown in Figure 10A, the arrangement of the layers of the two-dimensional material 1003 on the substrate 1001 on which the first electrode 1002 is formed can result in the presence of several voids (G10 in the enlarged view). Consequently, steps equivalent to those already described for the CNT-based design are also required, and a conformal dielectric 1033 is used to provide a compact active layer to prevent short circuits between the first electrode 1002 and the second electrode 1004.

[0090] The vertical FETs in the embodiments of this disclosure exhibit a vertical current flow, which is particularly advantageous for vertical stacking in complementary circuits comprising at least one P-type transistor and one N-type transistor. Placing these two transistors vertically allows for further size reduction for complementary configurations. However, it should be understood that further examples are conceivable in which the P-type and N-type vertical FETs are arranged horizontally, i.e., the first vertical FET is positioned to the side (rather than above) the second vertical FET.

[0091] Figures 11A to 11O provide an example of the inverter manufacturing process. To avoid repeating details already provided, the starting point of this sequence corresponds to Figure 3L, i.e., the already manufactured vertical FET 1100. This vertical FET 1100 is assumed to be either P-type or N-type. The P-type or N-type characteristics of the transistor are determined, in particular, by the materials used for each electrode, because the materials determine the deformation of the valence band and conduction band of the semiconductor at the interface. The above type can also be determined by the properties of the semiconductor itself. Dopants may be added to obtain N-type characteristics (doping with electron donors) or P-type characteristics (donors with electron acceptors). Environmental dopants may be used, such as contact with organic or inorganic dopant materials / molecules. Furthermore, where applicable, the behavior of the semiconductor may also be determined by the conformal dielectric used to provide a compact active layer. Separately, it is known that certain materials exhibit P-type or N-type properties, or that specific treatments such as doping or annealing can be used to adjust their effective semiconductor properties. The metals used for the source and drain may be modified to adjust the polarity for P-type or N-type devices.

[0092] Various parts of the lower transistor 1100 are shown in Figure 11A. A substrate 1101 is used on which the first electrode 1102 is formed. An active layer 1103 is sandwiched between the first electrode 1102 and the second electrode 1104. The gate structure is formed as previously described and includes both a gate insulating layer 1106 and a gate conductor 1107. Finally, a first contact 1109 is fabricated for the first electrode 1102, a second contact 1110 is fabricated for the second electrode 1104, and a third contact 1111 is fabricated for the gate conductor 1107. As in previous examples, a first dielectric layer 1105 and a second dielectric layer 108 are also provided.

[0093] To manufacture the inverter, a second vertical FET 1200 is fabricated on top of the first FET 1100. The type of the second FET 1200 is complementary to the type of the first FET, i.e., opposite to that type. As shown in Figure 11B, an interlayer insulating layer 1201 is deposited on top of the first (or lower) vertical FET 1100. The ILD layer may contain any of the dielectric materials already described, while introducing other ILD layers. The ILD layer 1201 serves as the substrate for the second (i.e., upper) vertical FET 1200. Next, Figures 11C to 11I show the following manufacturing steps, which in this particular embodiment correspond to the steps already presented in, for example, Figures 3A to 3G, i.e., up to the deposition of the gate insulating layer 1206. For the upper transistor, the first electrode 1202, the active layer 1203, and the second electrode 1204 are fabricated. Next, the ILD layer 1205 is deposited to define the region 1217 for the gate placement of the upper transistor.

[0094] In Figure 11J, a certain difference can be identified, which relates to the functionality of the manufactured logic circuit, i.e., the inverter. To create the inverter, the gates of both P-type and N-type transistors are connected. For this reason, the etching of the gate insulating layer 1206 shown in Figure 11J is carried out in such a way that the insulating layer at the bottom of the gate region or cavity / well of the upper transistor 1200 is also removed, thus exposing the gate contact 1111 of the lower vertical FET 1100. Figure 11K shows the deposition of the gate conductor 1207, which in this case allows not only control of the upper vertical FET 1200 but also electrical connection of the gates of both transistors 1100 and 1200. With the gate conductor thus deposited across the entire surface, a CMP processing step is required, as in the previous case, which ensures that the gate insulating film 1206 and gate conductor 1207 are deposited only at the gate locations (Figure 11L).

[0095] After the gate conductor is removed, preparations are made for the process of defining various device contacts. To enable the above contacts, an additional ILD layer 1208 can be deposited, as shown in Figure 11M. Subsequently, the contacts can be patterned by photolithography and dry etching steps, as schematically shown in Figure 11N. The position of the contacts is again determined by the function of the logic circuit. The contact of the first electrode 1202 of the upper FET transistor 1200 is aligned with the contact 1110 of the second electrode 1104 of the lower vertical FET 1100. To enable this connection, a pattern 1229 is created within the structure. This connection corresponds to the output of the inverter. Meanwhile, a pattern 1119 is generated for the first electrode 1102 of the lower FET 1100, in this case making contact from above (see Figure 12 for an alternative embodiment). A further pattern 1220 is provided for the second electrode 1204 of the upper transistor 1200. Finally, pattern 1221 for the gate is created.

[0096] After all contacts have been patterned, the contact conductors are deposited, thus enabling electrical connection and inverter operation. In particular, the first contact 1109 is used to connect the first electrode 1102 of the first transistor 1100 to either Vdd or Vss. The second contact 1210 is used for the second electrode 1204 of the upper transistor 1200, which in this case is connected to the other of Vdd and Vss. The third contact 1211 is used for the gate conductor 1207 of the upper transistor 1200, which is also connected to the gate conductor 1107 of the lower transistor 1100, as previously shown. This contact is the input to the inverter. Finally, the fourth contact 1209 is used for the first electrode 1202 of the upper transistor 1200, which is connected to the second electrode 1104 of the lower transistor 1100. This fourth contact is the inverter output.

[0097] The inverter shown in Figure 11 is based on the vertical FET embodiment shown in Figures 3A to 3L, i.e., the finless SAA (Semiconductor-All-Around) transistor, but it should be understood that the same principles are applicable to other embodiments as well.

[0098] As a non-limiting example, Figure 12 shows an inverter configuration including a bottom contact 1249 for the first electrode of the lower vertical FET. The bottom contact is also used for the inverters in Figures 13 and 14, which are based on the structures introduced in Figures 4A-4L (SAA with fins) and 5A-5O (GAA), respectively. Figure 13 shows an inverter including vertical FETs, each containing fins. The arrangement of the gate insulating layer 1316 and gate conductor 1317 is similar to that of a transistor containing a fin structure. The same can be said for the upper transistor, based on the arrangement of its gate insulating layer 1326 and gate conductor 1327. In Figure 14, the arrangement of the gate insulating layers 1416, 1426 and gate conductors 1417, 1427 of the lower and upper transistors respectively results in a configuration in which the gate completely surrounds the overlapping outer periphery of the overlapping region of both transistors.

[0099] The use of embodiments of this disclosure for stacking vertical FETs in a complementary arrangement is not limited to any particular active material. Figure 15 provides an example of an inverter including a single row of SWCNTs 1513 for the lower transistor and another single row of SWCNTs 1523 for the lower transistor. In fact, even shorter channel lengths can be obtained by using unzipped or unwrapped SWCNTs. Such unzipped or unwrapped SWCNTs can be considered as curved graphene. This is illustrated in the inverter of Figure 16, which includes one row of unzipped SWCNTs 1613 for the lower transistor and another row of unzipped SWCNTs 1623 for the upper transistor. Such unzipped or unwrapped SWCNTs can be prefabricated and deposited on a substrate. Alternatively, standard single-row SWCNTs may be deposited. Next, a conformal dielectric layer can be deposited as described above to obtain a compact layer. Finally, etching of the dielectric layer can be performed such that at least some of the SWCNTs are also etched and thus a layer containing unzipped SWCNTs can be obtained. As in previous embodiments, in this case as well, one-dimensional materials other than SWCNTs can be used in further modifications of this embodiment. Finally, Figure 17 shows an example including two-dimensional materials 1713-1723 for the lower and upper transistors.

[0100] By leveraging the flexibility of manufacturing technology, vertical FETs containing various types of active materials can be combined within the same circuit. As an example, Figure 18 shows an inverter circuit in which the lower vertical FET contains an active layer 1813 of a two-dimensional material, and the upper vertical FET contains an active layer 1823 containing a single row of SWCNTs as the active material. The choice between one active material and another depends on the function required of each device, and in particular whether P-type or N-type properties are required. For example, in this art, it is known that most transition metal dichalcogenide (TMD) materials exhibit n-type behavior without intentional doping, while most semiconductor CNTs exhibit P-type behavior.

[0101] In yet another example, a vertical FET may be manufactured using an active layer containing multiple sublayers to achieve desired transistor characteristics. In this sense, Figure 19 shows an exemplary inverter in which the lower transistor has an active layer containing three sublayers, namely, one of the sublayers, sublayer 1913b, contains a single row of SWCNTs, and this sublayer is sandwiched by two further sublayers (1913a and 1913c) containing a two-dimensional material (e.g., WS2 or MoS2). In this particular embodiment, the reverse arrangement is used for the upper transistor, which similarly uses three sublayers for its active layer. However, in this case, the intermediate sublayer 1923b contains a two-dimensional material, and the other two sublayers (1923a and 1923c) contain a single row of SWCNTs. Other combinations may be possible. In particular, different numbers of sublayers may be used for the lower and upper transistors. Furthermore, the combination of active materials can be varied for other embodiments. For example, the active material layer may include sublayers with similar shapes but containing different types of semiconductors, such as a stack of two-dimensional material sublayers containing a combination of MoS2 and WS2 sublayers. Such an arrangement is presented in the inverter of Figure 20. In this design, both the lower and upper inverters include active layers containing different sublayers, but these sublayers are made of materials with similar shapes. For each active layer, the lower vertical FET includes sublayers 2013a-c, and the upper vertical FET includes sublayers 2023a-c.

[0102] While vertical FETs with active layers containing multiple sublayers have been presented in the context of inverter circuits, it should be understood that these are provided merely as examples. In fact, the same concept can be used for any other logic circuits and / or for individual transistors. Thus, the vertical FETs according to embodiments of this disclosure can be used in any electronic device that uses an integrated circuit. Examples of such electronic devices include, but are not limited to, mobile phones, personal computers, televisions, music players, drones, automobiles, radios, healthcare devices, memory, telecommunications systems, navigation systems, or wearables.

[0103] Figure 23 shows a flow diagram of a non-limiting method 3000 for manufacturing a vertical field-effect transistor according to one embodiment. In step 3100, method 3000 includes providing a substrate and forming a first electrode on the substrate. In step 3200, an active layer is deposited on the previously obtained first electrode. The method then proceeds to step 3300, where a second electrode is deposited so as to overlap the first electrode. The next step 3400 is patterning of the second electrode and the active layer. As a result of this patterning, a specific overlapping region is defined where the second electrode overlaps the first electrode. The overlapping region is defined by its outer periphery. The next step 3500 of method 3000 includes patterning a region for the transistor gate, which in some examples may be similar to a cavity or well. The above region is such that at least a portion of the previously deposited active layer is exposed. Then, it is necessary to form a gate structure for controlling the transistor. In step 3600, a gate insulating layer is formed to cover the exposed portion of the active layer, and in step 3700, a gate conductor is deposited on the gate insulating layer. The gate conductor is used to apply a voltage that controls the conduction state of the active layer, and the gate insulating layer ensures that the gate conductor does not come into direct contact with an electrode or channel. Finally, in step 3800, a first electrode, a second electrode, and contacts are deposited to enable connection between the gate and the outside.

[0104] As shown in the flow diagram in Figure 23, step 3200 requires the deposition of the active layer on the first electrode. This step is particularly difficult when the active material used is one that, due to its properties or formation process, is likely to be a non-compact layer containing voids or gaps. This may be the case when using two-dimensional materials or carbon nanotubes. The gaps mentioned above can result in direct electrical contact between the first and second electrodes, potentially short-circuiting the transistor. To prevent such a failure mechanism, a method 4000 for fabricating the active layer is shown in Figure 24. In 4100, a first layer of the active material is obtained on the first electrode of the transistor. This layer may exhibit varying degrees of porosity. The process then moves to step 4200, where a conformal packed interlayer dielectric (ILD) is deposited on top of the active material. This dielectric fills the gaps in the initial active layer, thus creating a compact structure. The active material must be in clear contact with the second electrode. For this reason, a third step 4300 is required to complete the active layer. In this step, the ILD layer is etched in a controlled manner (if necessary) until the active material is exposed, and thus the active material comes into contact with the second electrode deposited on its surface in a later step of the process shown in step 3300 of Figure 23.

[0105] For clarification, even though most examples involving one-dimensional materials are described with reference to CNTs, it should be understood that other one-dimensional materials such as MoS2 nanotubes, WS2 nanotubes, nanowires, or nanorods can also be used in the examples shown. Similarly, examples involving two-dimensional materials should not be understood as being limited to specific two-dimensional materials, and it will be clear that various materials such as graphene, MoS2, or WS2 can be used in various modifications.

[0106] For completeness, various aspects of this disclosure are described in the following numbered clauses.

[0107] Clause 1. A vertical field-effect transistor, circuit board and A first electrode provided on a substrate and configured as either the source or drain of a transistor, A second electrode configured as the other of the source and drain of a transistor, wherein the second electrode at least partially overlaps with the first electrode within an overlapping region, An active layer sandwiched between the first electrode and the second electrode, A gate having a gate conductor portion and a gate insulating layer, wherein the gate insulating layer is disposed between the gate conductor portion and the active layer, A vertical field-effect transistor equipped with [a specific feature].

[0108] Clause 2. The vertical field-effect transistor as described in Clause 1, wherein the active layer comprises a one-dimensional material, in particular carbon nanotubes (CNTs), and in particular the one-dimensional material has its longitudinal axis oriented parallel to the substrate.

[0109] Clause 3. A vertical field-effect transistor as described in Clause 2, wherein the active layer comprises carbon nanotubes (CNTs) in at least one of the following forms: a single layer of single-walled carbon nanotubes (SWCNTs), a single layer of multilayer CNTs, a single layer of unzipped SWCNTs, a layer containing multiple rows of oriented SWCNTs, a layer containing multiple rows of oriented multilayer CNTs, a network of unoriented SWCNTs, and a network of unoriented multilayer CNTs.

[0110] Clause 4. The active layer comprises a two-dimensional (2D) material, more specifically, the active layer comprises a transition metal dichalcogenide (TMD) material, more specifically, MX2 such as MoS2, WeS2, or WS2, in particular, the two-dimensional material having its planes arranged parallel to the substrate, the vertical field-effect transistor as described in any one of Clauses 1 to 3.

[0111] Clause 5. The active layer comprises a stack of two-dimensional material sheets, as described in Clause 4, in the vertical field-effect transistor.

[0112] Clause 6. The active layer further comprises a conformal dielectric, as described in any one of Clauses 2 to 5, for a vertical field-effect transistor.

[0113] Clause 7. A vertical field-effect transistor according to any one of Clauses 1 to 6, wherein at least one of the first electrode and the second electrode includes a metal, a metalloid, a one-dimensional conductor, a two-dimensional conductor, or a doped semiconductor.

[0114] Clause 8. A vertical field-effect transistor according to any one of Clauses 1 to 7, wherein the gate conductor portion comprises at least one of a metal, a metalloid, a one-dimensional conductor, a two-dimensional transition metal dichalcogenide, or a doped semiconductor.

[0115] Clause 9. A vertical field-effect transistor according to any one of Clauses 1 to 8, wherein the overlapping region has an outer periphery and the gate is at least partially located inside the outer periphery of the overlapping region.

[0116] Clause 10. The vertical field-effect transistor according to Clause 9, wherein the gate includes a first insulating layer having a U-shaped cross-section and a second insulating layer having a U-shaped cross-section, and the first insulating layer and the U-shaped second insulating layer are separated by a first electrode, an active layer and a portion of the second electrode.

[0117] Clause 11. A vertical field-effect transistor as described in Clause 9 or 10, wherein the gate is located entirely inside the outer periphery of the overlapping region.

[0118] Clause 12. A vertical field-effect transistor according to Clause 9 or 10, wherein the gate extends beyond at least one side of the outer periphery of the overlapping region.

[0119] Clause 13. A vertical field-effect transistor according to any one of Clauses 1 to 8, wherein the overlapping region has an outer periphery, and the gate is located outside the outer periphery of the overlapping region, adjacent to the outer periphery.

[0120] Clause 14. A vertical field-effect transistor as described in Clause 12 or 13, wherein the gate is positioned substantially flush with the active layer.

[0121] Clause 15. A vertical field-effect transistor as described in any one of Clauses 1 to 14, wherein the active layer comprises multiple sublayers.

[0122] Clause 16. A vertical field-effect transistor as described in Clause 15, wherein at least two sublayers each contain a different type of active material.

[0123] Clause 17. A vertical field-effect transistor as described in Clause 16, wherein at least a first sublayer comprises a one-dimensional semiconductor and at least a second sublayer comprises a two-dimensional semiconductor.

[0124] Clause 18. A vertical field-effect transistor as described in any one of Clauses 1 to 17, wherein the material of the first electrode, the second electrode, and / or the active layer is selected such that the transistor behaves as a P-type or N-type field-effect transistor.

[0125] Clause 19. A semiconductor structure comprising a first vertical field-effect transistor as described in Clauses 1 to 18 and a second vertical field-effect transistor as described in Clauses 1 to 18, wherein the second vertical field-effect transistor is located on top of the first field-effect transistor.

[0126] Clause 20. A semiconductor structure comprising a first vertical field-effect transistor as described in Clauses 1 to 18 and a second vertical field-effect transistor as described in Clauses 1 to 18, wherein the second vertical field-effect transistor is located on one side of the first field-effect transistor.

[0127] Clause 21. The semiconductor structure according to Clause 19 or 20, wherein the first field-effect transistor is either a p-type transistor or an n-type transistor, and the second field-effect transistor is the other of a p-type transistor and an n-type transistor.

[0128] Clause 22. A vertical field-effect transistor, specifically a method for manufacturing a vertical field-effect transistor as described in any one of Clauses 1 to 18, -Forming a first electrode on the substrate, - Depositing an active layer on the first electrode, -The method involves depositing a second electrode on the active layer to form a sandwich structure, wherein the sandwich structure includes an overlapping region having an outer periphery. - Forming a gate region, wherein the gate region exposes at least a portion of the active layer. - Depositing a gate insulating layer to cover the above portion of the exposed active material, - Depositing a gate conductor on a gate insulating layer, thereby positioning the gate insulating layer between the gate conductor and the active layer, -To form electrical contacts for the first electrode, the second electrode, and the gate conductor, Methods that include...

[0129] Clause 23. A method for manufacturing a vertical field-effect transistor according to claim 22, comprising depositing an active layer which comprises a layer containing CNTs and / or a two-dimensional material as a semiconductor material.

[0130] Clause 24. A method for manufacturing a vertical field-effect transistor as described in Clause 23, comprising depositing an active layer, which includes depositing a single row of carbon nanotubes, particularly a single row of unspun carbon nanotubes.

[0131] Clause 25. A method for manufacturing a vertical field-effect transistor as described in Clause 23, comprising depositing an active layer by depositing multiple rows of oriented CNTs, in particular multiple rows of SWCNTs.

[0132] Article 26. - After depositing the active layer, a conformal dielectric layer is deposited on top of the active layer. - Before depositing the second electrode, the conformal dielectric layer is etched to expose the active material of the active layer, A method for manufacturing a vertical field-effect transistor as described in any one of clauses 23 to 25, further including the following:

[0133] Clause 27. A method for manufacturing a vertical field-effect transistor as described in Clause 26, which involves etching the conformal dielectric to expose the active material of the active layer before depositing the second electrode, in particular by etching the active material.

[0134] Clause 28. A method for manufacturing a vertical field-effect transistor as described in any one of Clauses 22 to 27, wherein forming a gate region comprises forming a gate region that at least partially overlaps with an overlapping region.

[0135] Clause 29. A method for manufacturing a vertical field-effect transistor as described in Clause 28, wherein forming gate regions comprises forming at least two gate regions, the two gate regions being separated by a first electrode, an active layer, and a portion of the second electrode.

[0136] Clause 30. A method for manufacturing a vertical field-effect transistor according to Clause 28 or 29, wherein forming the gate region comprises forming the gate region within a region that is entirely located inside the outer periphery of the overlapping region.

[0137] Clause 31. A method for manufacturing a vertical field-effect transistor according to Clause 28 or 29, wherein forming a gate region includes forming a gate region in a region that extends beyond the outer periphery of an overlapping region.

[0138] Clause 32. A method for manufacturing a vertical field-effect transistor according to any one of Clauses 22 to 27, wherein forming a gate region includes forming a gate region within a region surrounding the outer periphery of an overlapping region.

[0139] Article 33. -Forming a spacer within the gate region before depositing the gate insulating layer, thereby forming a spacer within the gate region such that the bottom level of the resulting gate region has a height such that the bottom surface of the gate conductor is flush with the bottom surface of the active layer. - Etching the gate insulating layer and gate conductor after deposition, such that the uppermost part of the remaining gate insulating layer and gate conductor becomes substantially flush with the upper surface of the active layer. A method for manufacturing a vertical field-effect transistor as described in clause 31 or 32, further comprising:

[0140] Clause 34. A method for manufacturing a vertical field-effect transistor according to any one of Clauses 22 to 33, wherein forming a gate region includes forming a cavity, and depositing a gate insulating layer includes depositing a gate insulating layer covering the inner wall of the cavity.

[0141] Clause 35. A method for manufacturing a vertical field-effect transistor according to any one of Clauses 22 to 34, wherein the deposition of an active layer on the first electrode includes the deposition of a plurality of sublayers.

[0142] Clause 36. A method for manufacturing a vertical field-effect transistor as described in Clause 35, wherein the deposition of a plurality of sublayers comprises depositing at least a first sublayer and a second sublayer, the first sublayer comprising an active material different from that of the second sublayer.

[0143] Clause 37. A method for manufacturing a vertical semiconductor structure, comprising manufacturing a first vertical field-effect transistor in accordance with the method described in any one of Clauses 22 to 36, and manufacturing a second field-effect transistor on top of a previously manufactured transistor.

[0144] This specification uses examples to disclose teachings, including preferred embodiments, and to enable anyone skilled in the art to practice the teachings, including the manufacture and use of any apparatus or system, and the execution of any method incorporated therein. The patentable scope is defined by the claims and may include other examples conceivable by a person skilled in the art. Such other embodiments are intended to fall within the claims if they have structural elements not different from the language of the claims, or if they include equivalent structural elements not substantially different from the language of the claims. Aspects from the various embodiments described, and other known equivalents to each such aspect, can be mixed and combined by a person skilled in the art to construct additional embodiments and techniques in accordance with the principles of this application. Where reference numerals related to drawings are indicated in parentheses in a claim, they are for the purpose of improving the clarity of the claim and should not be construed as limiting the scope of the claim.

Claims

1. It is a vertical field-effect transistor, circuit board and A first electrode provided on the substrate and configured as either the source or the drain of the transistor, A second electrode configured as the other of the source and drain of the transistor, wherein the second electrode overlaps at least partially with the first electrode within an overlapping region. An active layer sandwiched between the first electrode and the second electrode, A gate having a gate conductor portion and a gate insulating layer, wherein the gate insulating layer is disposed between the gate conductor portion and the active layer, Equipped with, The active layer comprises a one-dimensional material whose longitudinal axis is oriented substantially parallel to the substrate, and / or the active layer comprises a two-dimensional material whose plane is oriented substantially parallel to the substrate. Vertical field-effect transistor.

2. The vertical field-effect transistor according to claim 1, wherein the active layer comprises carbon nanotubes (CNTs).

3. The vertical field-effect transistor according to claim 1 or 2, wherein the active layer further comprises a conformal dielectric.

4. The vertical field-effect transistor according to any one of claims 1 to 3, wherein the overlapping region has an outer periphery, and the gate is at least partially located inside the outer periphery of the overlapping region.

5. The vertical field-effect transistor according to claim 4, wherein the gate includes a first insulating layer having a U-shaped cross-section and a second insulating layer having a U-shaped cross-section, and the first insulating layer and the U-shaped second insulating layer are separated by the first electrode, the active layer and a portion of the second electrode.

6. The vertical field-effect transistor according to claim 4 or 5, wherein the gate is completely located inside the outer periphery of the overlapping region.

7. The vertical field-effect transistor according to claim 4 or 5, wherein the gate extends beyond at least one side of the outer periphery of the overlapping region.

8. The vertical field-effect transistor according to any one of claims 1 to 3, wherein the overlapping region has an outer periphery, and the gate is located outside the outer periphery of the overlapping region and adjacent to the outer periphery.

9. The vertical field-effect transistor according to claim 7 or 8, wherein the gate is arranged substantially flush with the active layer.

10. The vertical field-effect transistor according to any one of claims 1 to 9, wherein the active layer comprises a plurality of sublayers, and optionally, at least two sublayers each comprise a different type of active material.

11. A semiconductor structure comprising a first vertical field-effect transistor according to any one of claims 1 to 10 and a second vertical field-effect transistor according to any one of claims 1 to 10, wherein the second vertical field-effect transistor is disposed on top of the first field-effect transistor or on one side of the first field-effect transistor, and optionally the first field-effect transistor is either a P-type transistor or an N-type transistor, and the second field-effect transistor is the other of a P-type transistor and an N-type transistor.

12. A method for manufacturing a vertical field-effect transistor according to any one of claims 1 to 11, - Forming a first electrode on the substrate, - Depositing an active layer on the first electrode, - A sandwich structure is formed by depositing a second electrode on the active layer, wherein the sandwich structure includes an overlapping region having an outer periphery. - Forming a gate region, wherein the gate region exposes at least a portion of the active layer. - Depositing a gate insulating layer to cover the exposed portion of the active layer, - Depositing a gate conductor on the gate insulating layer, thereby the gate insulating layer is positioned between the gate conductor and the active layer, and depositing the gate conductor. - To form electrical contacts for the first electrode, the second electrode, and the gate conductor, Methods that include...

13. Forming the gate region includes forming the gate region in a region extending beyond the outer periphery of the overlapping region, or forming the gate region in a region surrounding the outer periphery of the overlapping region, and the method is Forming a spacer within the gate region before depositing the gate insulating layer, wherein the resulting bottom level of the gate region has a height such that the bottom surface of the gate conductor is substantially flush with the bottom surface of the active layer. The gate insulating layer and the gate conductor are etched after deposition, such that the uppermost part of the remaining gate insulating layer and the gate conductor becomes substantially flush with the upper surface of the active layer. A method for manufacturing a vertical field-effect transistor according to claim 12, further comprising:

14. A method for manufacturing a vertical field-effect transistor according to claim 12 or 13, wherein forming the gate region includes forming a cavity, and depositing the gate insulating layer includes depositing the gate insulating layer to cover the inner wall of the cavity.

15. Depositing an active layer involves depositing a layer containing CNTs and / or a two-dimensional material as a semiconductor material, and the method is After the deposition of the active layer, a conformal dielectric layer is deposited on the active layer. Before depositing the second electrode, the conformal dielectric layer is etched to expose the active material of the active layer, A method for manufacturing a vertical field-effect transistor according to any one of claims 12 to 14, further comprising:

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