Substrate etching using hydrostatic gas bearings

Abstract

Techniques and apparatus for processing semiconductor substrates are provided. In some embodiments, such techniques include: acting a first hydrostatic bearing gas through a first surface of a first electrode subassembly; receiving a semiconductor substrate between the first surface of the first electrode subassembly and a second surface of a second electrode subassembly located on the opposite side of the first electrode subassembly; acting a second hydrostatic bearing gas through the second surface; moving the second electrode subassembly to create rigidity between the semiconductor substrate and the first and second surfaces; and processing the edge portions of the semiconductor substrate using plasma generated by the first and second electrode subassemblies.

Description

Technical Field

[0001] Incorporation by Reference The PCT application is filed simultaneously with this specification as part of this application. Each application for which this application claims benefit or priority and which is identified in the simultaneously filed PCT application is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] Semiconductor manufacturing processes can create layers of film on a semiconductor substrate or wafer during fabrication, which can result in unwanted materials or metals on the substrate, particularly on the edges. Some processes, such as edge bevel removal (EBR), can substantially process the edges of the wafer to remove the material. EBR can be performed by applying reactive species (e.g., etching agents) generated by a plasma source to remove the material at desired locations, such as the edges of the wafer. However, EBR is reaching its performance limits because of increasing requirements for etching speed, yield, and accuracy of the etching profile.

[0003] The descriptions of the background and context included in this specification are provided only for the purpose of generally presenting the context of the present disclosure. Much of the present disclosure presents the research of the inventors, and it does not mean that such research is recognized as prior art merely because it is described in the background art section or presented as context elsewhere in this specification.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect of the present disclosure, an apparatus configured for processing a semiconductor substrate is disclosed. In some embodiments, the apparatus includes a first subassembly comprising a first surface, a first electrode, and a first orifice, and a second subassembly comprising a second surface, a second electrode, and a second orifice, wherein the second surface is positioned opposite the first surface to form a region sized to receive a semiconductor substrate between the first and second subassemblies, and when in the first configuration, a first hydrostatic bearing gas flows through the first orifice and a second hydrostatic bearing gas flows through the second orifice to create stiffness between the semiconductor substrate and the first surface, and substantially equal stiffness between the semiconductor substrate and the second surface, and the first and second electrodes are configured to generate plasma applied to the edge portion of the semiconductor substrate while the semiconductor substrate rotates about the central axis of the semiconductor substrate.

[0005] In another aspect of the present disclosure, a system configured for processing a semiconductor substrate is disclosed. In some embodiments, the system includes an upper electrode subassembly comprising an upper surface, an upper electrode, and an upper hydrostatic gas bearing orifice; a lower electrode subassembly comprising a lower surface, a lower electrode, and a lower hydrostatic gas bearing orifice, wherein the lower surface is positioned opposite the upper surface to form a region sized to receive a semiconductor substrate between the upper and lower subassemblies; and a stage assembly having multiple degrees of freedom, configured to move the semiconductor substrate into the region by at least a first degree of freedom, wherein in the first configuration, an upper hydrostatic gas bearing gas flows through the upper hydrostatic gas bearing orifice, and a lower hydrostatic gas bearing gas flows through the lower hydrostatic gas bearing orifice to create stiffness between the semiconductor substrate and the upper surface, and between the semiconductor substrate and the lower surface, and the upper and lower electrodes are configured to generate plasma applied to the edge portion of the semiconductor substrate while the stage assembly realizes a second degree of freedom on the semiconductor substrate.

[0006] Another aspect of the present disclosure discloses a method for processing a semiconductor substrate. In some embodiments, the method includes the steps of: acting a first hydrostatic bearing gas through a first surface of a first electrode subassembly; receiving a semiconductor substrate between the first surface of the first electrode subassembly and a second surface of a second electrode subassembly located opposite the first electrode assembly, after the step of acting the first hydrostatic bearing gas; acting a second hydrostatic bearing gas through the second surface, after the step of receiving the semiconductor substrate; moving the second electrode assembly to create rigidity between the semiconductor substrate and the first and second surfaces, after the step of acting the second hydrostatic bearing gas; and processing the edge portions of the semiconductor substrate using plasma generated by the first and second electrode subassemblies.

[0007] These and other features of embodiments of the present disclosure are described in detail below with reference to the relevant drawings. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a simplified diagram of a hardware configuration for removing material from a semiconductor substrate using a plasma source, according to several embodiments. [Figure 1B] This is a simplified diagram of a hardware configuration for removing material from a semiconductor substrate using a plasma source, according to several embodiments. [Figure 2] This is a schematic diagram of the hardware configuration of a material removal system configured to supply a pressurized jet of plasma toward a semiconductor substrate, according to several embodiments. [Figure 2A] Figure 2 is a cross-sectional view of the schematic hardware configuration of the material removal system. [Figure 2B] Figure 2 is a cross-sectional view of a part of the material removal system, showing the components of the system and the containment racks useful for implementing the system. [Figure 2C]Figure 2 is a cross-sectional view of a part of the material removal system, showing the components of the system and the containment racks useful for implementing the system. [Figure 2D] This figure shows indirect and direct plasma generation that may be used in conjunction with the material removal system described herein. [Figure 2E] This figure shows indirect and direct plasma generation that may be used in conjunction with the material removal system described herein. [Figure 2F] This figure shows three factors that may be involved in processing wafer edges using a plasma source, including radical generation, transport, and surface reactions. [Figure 2G] This is an enlarged view of the hardware configuration of a material removal system according to several embodiments. [Figure 2H] This is a cross-sectional view of a plasma source having a confinement shelf. [Figure 2I] This is a cross-sectional view of a plasma source having multiple confinement shelves. [Figure 2J] This is a cross-sectional view of a hardware component configured to provide a hydrostatic gas bearing during processing (e.g., etching its edges) of a semiconductor substrate, according to several embodiments. [Figure 2K] This is a cross-sectional view of a hardware component configured to provide a hydrostatic gas bearing during processing (e.g., etching its edges) of a semiconductor substrate, according to several embodiments. [Figure 2L] This is a cross-sectional view of a hardware component configured to provide a hydrostatic gas bearing during processing (e.g., etching its edges) of a semiconductor substrate, according to several embodiments. [Figure 2M] This is a cross-sectional view of a hardware component configured to provide a hydrostatic gas bearing during processing (e.g., etching its edges) of a semiconductor substrate, according to several embodiments. [Figure 3] This is a diagram of the edge of a semiconductor substrate resulting from the implementation of the material removal system disclosed herein. [Figure 4A]A diagram showing steps for loading a semiconductor substrate for processing. [Figure 4B] A diagram showing steps for loading a semiconductor substrate for processing. [Figure 4C] A diagram showing steps for loading a semiconductor substrate for processing. [Figure 4D] A diagram showing steps for loading a semiconductor substrate for processing. [Figure 5-1] A flowchart showing a method of processing a semiconductor substrate according to some embodiments. [Figure 5-2] A flowchart showing a method of processing a semiconductor substrate according to some embodiments. [Figure 6] A flowchart showing another method of processing a semiconductor substrate according to some embodiments. [Figure 7] A simplified block diagram of the system or apparatus described in this specification.

Best Mode for Carrying Out the Invention

[0009] The following terms are used throughout this specification.

[0010] As used herein, the term "semiconductor device fabrication operation" refers to an operation performed during the fabrication of a semiconductor device. As referred to in this specification, such fabrication operations may simply be referred to as "processes" or "processing". Examples of processing include deposition of materials onto a substrate, selective etching of materials from a substrate, and ashing of photoresist on a substrate. Typically, the overall fabrication process includes a plurality of semiconductor device fabrication operations each performed in its own semiconductor fabrication tool such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etching tool, etc. Categories of semiconductor device fabrication operations include subtractive processes such as etching processes and planarization processes, as well as material addition processes such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of an etching process, a substrate etching process includes a process of etching a mask layer, or generally, a process of etching any layer of material previously deposited on and / or present on the substrate surface. Such an etching process may etch a stack of layers within the substrate.

[0011] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially fabricated integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially fabricated integrated circuit" may refer to a semiconductor wafer at any one of many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Examples of semiconductor substrate materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe).

[0012] In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include a variety of articles such as magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components of pixelated display devices, flat panel displays, and micromechanical devices. The workpieces may vary in shape, size, and material.

[0013] This disclosure generally relates to processing semiconductor substrates to remove unwanted material from a portion of the substrate, such as the edges of the substrate. Some implementation configurations involve the use of at least one hydrostatic gas bearing and a spin substrate for processing edges with a plasma jet. Improved techniques are desirable that have high etching rates and improved etching profiles (e.g., short transitions from etched edges to untreated films) that are still cost-effective and reduce the system footprint.

[0014] Such improved techniques, according to some embodiments of the present disclosure, may utilize so-called atmospheric pressure plasma jet (APPJ) techniques for edge bevel removal (EBR) techniques in recipe-controlled etching for removing material (e.g., one or more existing layers) from a portion of a semiconductor substrate, which in some embodiments may involve operating one or more nozzles under atmospheric conditions to supply a pressurized jet of plasma radicals toward the substrate.

[0015] Since APPJ can be used to deposit materials using specific configurations, this disclosure is not necessarily limited to etching. That is, material removal systems 100 or 200 may be used for deposition despite their nominalization conventions, and their function is not limited to material removal. For example, precursors may be selected for chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD), as mentioned elsewhere below. However, the following description will focus primarily on material removal using etching to improve EBR.

[0016] Details of the components of a system using APPJ in EBR will be described with reference to Figures 1A to 2M. Such a system may be configured to emit plasma radicals that treat specific locations on a semiconductor substrate, for example, to remove material at the substrate edge. Using the hardware of such a system, a wafer may spin through a controlled plasma emission region on the aligner hardware, and the plasma source (e.g., a plasma jet) may be configured to etch (or, in some configurations, deposit) material on the wafer, including the front, edge, and / or back of the wafer. More specifically, the chemical properties of the plasma may etch areas near the wafer edge (or other parts of the wafer). In some embodiments of this disclosure, an arc-shaped jet, which may consist of a single jet region or an array of jets, may be utilized rather than using a single jet. In some implementations, such an array may be as simple as a jet distributed across the wafer radius. As suggested above, or rather, rather than etching, a suitable selection of the plasma supply gas may induce plasma-enhanced chemical vapor deposition of material.

[0017] Edge bevel removal (EBR) using atmospheric pressure plasma jet (APPJ) Figure 1A shows an exemplary diagram of plasma radicals applied to a semiconductor substrate 102 in several implementations of the material removal system 100 described herein. In some embodiments, the system 100 may include one or more source subassemblies 101, including an upper subassembly 104, a lower subassembly 106, and a plasma source 108. As described elsewhere, the plasma source 108 may include at least one plasma jet or at least one nozzle. In some embodiments, the upper subassembly 104 may include an electrode or electrode subassembly. In some embodiments, the upper subassembly 104 may provide a hydrostatic gas bearing or a hydrodynamic gas bearing. In some embodiments, the lower subassembly 106 may include an electrode or electrode subassembly separate from the electrode or electrode subassembly of the upper subassembly 104. In some embodiments, the lower subassembly 106 may provide the load capacity of hydrostatic gas bearings and hydrodynamic gas bearings. Hydrostatic gas bearings use a layer of pressurized gas that provides a low friction load-bearing interface between surfaces. A hydrodynamic gas bearing can form its load capacity through the relative velocity of the moving gas between a stationary surface and a moving surface (e.g., between the surface of a subassembly and the surface of a spin substrate). Hydrodynamic gas bearing capacity is beneficial because it allows for reduced gas consumption and enables some operations to be performed without the necessary flow of gas supplied from an external source.

[0018] In some embodiments, the semiconductor substrate 102 may be positioned or placed in the plasma emission region between the upper subassembly 104 and the lower subassembly 106, and as the substrate rotates along a selected direction 111 relative to the upper subassembly 104 and the lower subassembly 106, for example around the central axis 114 of the substrate, the components (including the plasma source 108) may substantially process the edges 102-e of the semiconductor substrate 102 in association. More specifically, in some configurations, the plasma source 108 may be substantially confined to the edge of the semiconductor substrate 102 by positioning the substrate edge 102-e in close proximity to the tip associated with the nozzle or jet of the plasma source 108. The plasma source 108 may be positioned along the upper subassembly 104 (for example, the tip of the plasma source 108 may be coplanar with the surface of the upper subassembly 104). In some embodiments, a portion of the semiconductor substrate 102 in close proximity to the plasma may be sandwiched between one or more surfaces of the upper and lower assemblies 104, 106 for precise gap control. For example, the upper subassembly 104 may include an opening for the hydrostatic gas bearing gas to flow to the upper surface of the semiconductor substrate 102. Its proximity may be at the micron level (e.g., in the range of microns to tens of microns, or less than about 100 microns). Advantageously, the resulting micron-level gap between the semiconductor substrate 102 and the hydrostatic gas bearing surface provides advantages such as plasma confinement (e.g., away from the inner portion or center of the substrate), edge purging (e.g., removal of residue from etched portions), rotational stability of the semiconductor substrate 102, and efficient processing. Advantageously, the plasma source 108 allows processing of the wafer edge with a short transition from etched edge to unprocessed film over a specified distance. The edge of the processed semiconductor substrate 102 may have a substantially vertical cut where the thickness transitions abruptly. The vertical cut can help prevent the flow of plasma radicals toward the inner portion or center of the substrate.

[0019] During processing (e.g., etching), the semiconductor substrate 102 may be spun in a selected direction 111 (e.g., counterclockwise or clockwise) around an axis 114 while being held in place by other hardware such as aligner hardware 110. Optionally, the aligner hardware 110 may be configured to translate, traverse, and / or spin (e.g., act in the XY or R-θ-Z directions). Optionally, the aligner hardware 110 may be configured to control another device, causing the other device to translate, traverse, and / or spin. The semiconductor substrate 102 may be held in place via its back side, for example, by a vacuum chuck (optionally, an electrostatic chuck or clamp) with the aligner hardware 110. Optionally, the source subassembly 101 may have a stage 112 coupled to it to actuate at least a portion of the source subassembly 101 (e.g., in the XYZ directions).

[0020] In some implementations, the aligner hardware 110 may be activated (e.g., moved in the XYZ directions) and / or the spin rate may be adjusted, while optionally, the radio frequency (RF) power associated with the plasma source 108 may be modulated to stop or start etching. An exemplary range of RF power frequencies may be between approximately 10 kilohertz (kHz) and approximately 100 megahertz (MHz). Abrupt transitions may increase the area on the wafer that results in an operating die, while a specified diameter ensures material removal at the desired location. Further details regarding material removal using the components of assemblies 104, 106 (e.g., electrodes) and the plasma source 108 are described below in detail with respect to Figures 2 to 2I.

[0021] Figure 1B shows an exemplary diagram of plasma radicals directed to the edge 102-e of a semiconductor substrate 102, according to several implementations of the system 100 described herein (e.g., in Figure 1). In this configuration, the plasma source 108 may be configured to emit a first gas (e.g., plasma radicals) and a second gas (e.g., shielding gas) through the first and second openings of the plasma source 108, respectively. In some implementations, the first and second gases may be emitted from openings other than the openings of the plasma source 108. The second gas may act as a shield, enabling concentrated application of radicals to a specific location (e.g., the edge) of the semiconductor substrate 102. The shielding gas also prevents the plasma radicals from dispersing or recombining with the surrounding air (e.g., as illustrated with respect to Figure 2F (recombination 221)), enabling concentrated application of plasma radicals to the substrate edge 102-e. In the illustrated example of operation, as the substrate 102 rotates around the axis 114, various parts of the substrate edge 102-e may be exposed to plasma radicals.

[0022] In some operations, the system configuration may be used to deposit layers on one or more portions of the substrate 102 (e.g., on the front side) on the inner portion 102-i or the substrate edge 102-e, for example, when the substrate 102 rotates.

[0023] Generally speaking, since the deposited film or component remains undisturbed, plasma radicals reaching areas other than the substrate edge 102-e (such as the inner portion 102-i) are undesirable. Therefore, in some configurations, the plasma source 108 (e.g., its nozzle) may be positioned or angled toward or away from the inner portion 102-i of the substrate 102. The example shown in Figure 1B shows the nozzle oriented away from the center of the substrate 102, which can help remove edge material and prevent radical accumulation in other parts of the substrate 102. For further assistance, in some configurations, a third gas, such as a purge gas and / or a hydrostatic bearing gas, may be supplied through a third opening adjacent to the surface of the substrate 102, received through a third channel 137 defined adjacent to or otherwise in close proximity to the plasma source 108 (e.g., another part of the upper subassembly 104). However, in some configurations, the third channel 137 may be part of the plasma source 108 (e.g., within the same housing). The third gas may be supplied with sufficient force to guide the plasma radicals away from the center of the substrate 102 toward the substrate edge 102-e and to sufficiently expose the substrate edge 102-e to the plasma radicals. In some cases, the purge gas and the hydrostatic bearing gas may be supplied through separate third and fourth openings. In other configurations, further inlets and openings may be present.

[0024] Advantageously, when used with relatively high-pressure gases (e.g., near atmospheric pressure or a specific proportion thereof) compared to conventional methods, the material removal system 100 can yield a higher reaction product density than is possible in low-pressure processes. The disclosed concept offers advantages and benefits such as high process controllability, extremely high throughput due to extremely high etching (or deposition) rates, much lower costs, the ability to easily integrate with etching (or deposition) tools, and direct writing capability for a much smaller product footprint when pursued as a standalone implementation. Thus, the topologies shown in Figures 1A and 1B, based in part on small component volume, can result in significant hardware cost reductions compared to current technologies.

[0025] Another advantage of using APPJ with EBR is that while wafer rotation can be fast (e.g., 60-120 rotations / minute), the modulation of RF power to the plasma jet associated with the plasma source 108 can be performed much faster. In addition to controlling plasma generation and transfer, the synchronization of power and substrate angle or position can generate a range of different film characteristics to tune the net etching profile as desired, for example, using on / off or high / low RF power modulation.

[0026] Figure 2 shows a schematic diagram of the hardware configuration of the material removal system 200 according to several embodiments. In some embodiments, the system 200 may include an upper electrode subassembly 202, a lower electrode subassembly 204, a plasma source (not shown), a stage 206 configured to actuate the upper and / or lower electrode assemblies (e.g., in the XYZ directions), and an aligner 212 configured to actuate the semiconductor substrate 210 (e.g., in the XY or R-θ-Z directions). In some implementations, the upper subassembly 104 in Figure 1 may correspond to or include the upper electrode subassembly 202, and the lower subassembly 106 in Figure 1 may correspond to or include the lower electrode subassembly 204. However, the system 200 as shown in Figure 2 does not have to rely on hydrostatic gas bearings depending on the implementation.

[0027] In some embodiments, the plasma source may be located together with the upper electrode subassembly 202 (e.g., adjacent, internal, or in close proximity). In some embodiments, the plasma source may be located together with the lower electrode subassembly 204 (additionally or alternatively). The plasma source may generate chemical reaction species, such as an etchant, which can be supplied to a portion of the semiconductor substrate 210 (e.g., an edge or other location) in a controlled manner as the semiconductor substrate 210 spins. The spatial distribution of the plasma (i.e., the etching profile) can be controlled by the electrode configuration and gas flow. For example, the RF power modulation of the upper electrode subassembly 202 and / or the lower electrode subassembly 204 may be controlled. Furthermore, as described with respect to Figure 1B, the first, second, and / or third gas flows may be controlled. Controlling these parameters with respect to the electrodes and gas flow can result in a desired etching profile on the wafer.

[0028] As background, plasma can be generated by applying an RF field to a gas (e.g., through one or more electrodes). The plasma generates reactive species, which may include electrons, ions, radicals, and neutral species. Ionization of the gas by the RF field ignites the plasma, creating free electrons in the plasma discharge region (e.g., within the plasma source). These electrons are accelerated by the RF field and can collide with gas-phase reactant molecules. These collisions between electrons and reactant molecules can form radical species involved in etching or deposition processes.

[0029] As the semiconductor substrate 210 spins (e.g., via the aligner 212) while being positioned between the upper and / or lower electrode assemblies 202, 204, a portion of the substrate (e.g., the edge) may be exposed to the etchant generated by the plasma source, thereby allowing the chemical properties of the plasma, as well as the modulation of the RF power applied to the upper and / or lower electrode assemblies 202, 204, to etch a portion of the substrate 210. In some cases, the interior of the semiconductor substrate 210 from which material should not be removed may be protected by a solid object (e.g., a cover) to prevent the diffusion of the etchant into the inner area of ​​the wafer. An example of such a solid object may be a containment shelf, as described with respect to Figures 2H and 2I. Thus, at least partially based on physical obstructions (and / or purge gas), even if the plasma-generated etchant fills the process volume, the material may only be removed at the wafer edge.

[0030] However, as mentioned above, industry demands for etching speed are increasing, and the required precision of the etching profile is becoming increasingly narrow. Considering this, the positioning of the semiconductor substrate 210 relative to the lower surface of the upper electrode subassembly 202 and the upper surface of the lower electrode subassembly 204 can be precisely controlled. More specifically, the gap between the two assemblies can be defined. In some cases, this requires a highly skilled operator or engineer and can take a considerable amount of time to optimize the hardware configuration. Solid objects or covers may also need to be redesigned to alter the etching profile. Once the hardware is set up and the chamber is closed, it becomes difficult to adjust the etching profile and etching width without opening the chamber.

[0031] Therefore, this disclosure can take advantage of the fact that gas diffusivity is low at high pressures. For example, for gases at high pressures such as atmospheric pressure, gas diffusivity is 760 times lower than under typical low-pressure operating conditions. Thus, the etching profile can be adjusted by controlling the gas curtain rather than by mechanical hardware. Furthermore, the point source may be selected to use a wafer spinner rather than a ring-shaped source with a fixed pedestal. This can reduce or minimize non-uniform etching around the wafer bevel because wafer rotation smooths out spatial and temporal plasma fluctuations. Moreover, atmospheric pressure EBR does not require a vacuum pump, which can reduce the machine's footprint and cost. Thus, the configuration of system 200 advantageously allows the etching material to be applied only to the wafer edge without a vacuum system, which can reduce cost and system footprint.

[0032] However, it will be recognized that system 200 may also be configured to apply the etchant to various parts of the wafer (e.g., non-edges) for desired etching profiles for other applications, such as compensating for existing wafer curvature. For example, the gap between electrode assembly 202 and electrode assembly 204 may be extended, and / or a protective solid object (e.g., a cover) may be absent or positioned so that the aligner 212 can move the wafer "deeper" into the assembly, allowing etching on non-edge parts (e.g., inner part 102-i shown in Figure 1B).

[0033] Figure 2A shows a schematic cross-sectional view of the hardware configuration of the material removal system 200 according to several embodiments. In some embodiments, the upper electrode subassembly 202, the lower electrode subassembly 204, and the stage 206 may be configured to receive a semiconductor substrate 210 actuated via an aligner 212, which may be used as described above with respect to Figure 2. In some embodiments, the upper electrode subassembly 202, the lower electrode subassembly 204, and the stage 206 may be part of the source subassembly 101 described with respect to Figure 1A. In some embodiments, the aligner 212 may include a chuck 213, one or more pins 214, and / or an alignment sensor 215.

[0034] The aligner 212 may include various components configured to firmly hold the semiconductor substrate 210 and actuate to insert it vertically into, for example, a source subassembly 101 (e.g., between the upper electrode subassembly 202 and the lower electrode subassembly 204). Details of this insertion technique will be described in detail with respect to Figures 4A-4D and 5, but here we provide an overview of the components. In some mounting configurations, the aligner 212 may be used to adjust the position of the substrate 210 on the chuck 213 so that the wafer spins with minimal eccentricity. For example, using a measured eccentricity to minimize edge movement of the upper electrode assembly substrate 202 under the plasma jet, the substrate 210 may also be servo-driven or actuated (e.g., in the x or y direction toward or toward the upper and lower electrode subassemblies 202, 204) as the substrate 210 spins.

[0035] Those skilled in the art will recognize various configurations for securing the substrate 210 to the chuck 213. In some embodiments, the chuck may be a vacuum chuck 213. That is, the aligner 212 can use the suction of the vacuum chuck to firmly hold the substrate 210 with sufficient holding force. Vacuum chucks are easy to implement, convenient, and cost-effective. In fact, vacuum chucks may be particularly suitable for processing performed at atmospheric pressure according to this disclosure, because a vacuum chamber, where the pressure is already dramatically lower than atmospheric pressure, would not be able to vacuum chuck the substrate 210. Other types of chucks may be used in vacuum or atmospheric environments, such as the following:

[0036] In an alternative embodiment, the chuck 213 may be an electrostatic chuck (ESC) capable of securely holding the substrate 210 using electrostatic force. In some cases, such an ESC may be a bipolar ESC having a pair of complementary, coplanar clamp electrodes (which may be embedded within a pedestal structure) that generate an electrostatic force. In some cases, the ESC may be a unipolar ESC having one clamp electrode, the one electrode having a voltage applied to it, or opposite charges may be induced in the substrate 210 using, for example, a counter electrode above the substrate 210 (or, in certain mounting configurations, for example, plasma generated above the substrate 210 if in a process chamber).

[0037] In some embodiments, the chuck may be configured to move with multiple degrees of freedom. One example of a degree of freedom is translation. Another example is rotation. The chuck may be configured to translate along the x, y, and / or z axes using, for example, an actuator, to move the substrate 210 in the corresponding direction. Furthermore, the chuck may be configured to rotate around the z axis, rotating the fixed substrate 210 at the same rotational speed (e.g., 60-120 revolutions / minute, e.g., 100 revolutions / minute). In some implementations, the chuck may be fixed to a separate stage (or separate actuator), e.g., a stage (not shown), configured to translate (along the x, y, and / or z axes) and / or spin or rotate (around the z axis), or to translate, spin, and / or rotate the chuck. Spinning around the z axis allows the nozzle to cover the entire circumference of the substrate 210 (e.g., along its outer edge), and by controlling the nozzle state (high / low or on / off), various etching patterns can be formed. In some configurations, the nozzle housing or nozzle may be configured to rotate, tilt, or angle around the x and / or y axes, so that when the substrate 210 is positioned on the nozzle, the nozzle can cover a large portion of the substrate 210. In some configurations, the position of the nozzle may be varied relative to the nozzle housing. For example, the nozzle may be repositioned along the x, y, z axes, radial (r) direction, and / or angular (θ) direction. Angle repositioning may result in the nozzle tilting relative to the nozzle housing, while the nozzle housing may remain at the same angular position or tilt.

[0038] In some embodiments, the pins 214 may be ceramic, metal, or elastomer pads or raised platforms configured to hold the semiconductor substrate 210 when the substrate is not secured by the chuck 213. For example, the semiconductor substrate 210 may be placed on the pins 214. In some cases, the substrate may be positioned at a specific location (e.g., relative to the chuck), or in a particular orientation or direction, according to a wafer notch or marker on the substrate and / or position detection by the alignment sensor 215. By properly positioning the semiconductor substrate 210 on the pins 214, it is possible to secure the chuck 213 to the semiconductor substrate 210 using, for example, the techniques described above (e.g., vacuum chucking or ESC). The central axis of the semiconductor substrate 210 may coincide with the central axis of the chuck 213 when the substrate 210 is properly aligned. In some implementations, the alignment sensor 215 may use one or more optical sensors (e.g., lasers) for imaging (e.g., cameras) or vision sensors for the position detection described above or for measuring wafer eccentricity. The alignment sensor 215 may be used to detect the position of the wafer notch, and this information may be used to consider various process conditions and / or wafer positioning that may be required to be close to the notch in order to obtain the desired etching result.

[0039] Further details regarding the related systems and components outlined above will follow.

[0040] Figure 2B shows an enlarged vertical cross-sectional view of the nozzle of a plasma source 208 that may be used in system 200 in several implementation configurations. The plasma source 208 may be an example of the plasma source 108. The plasma source 208 may include a first electrode 233 defined approximately in the center of the nozzle. A dielectric material 238 may be arranged to surround the first electrode 233, thereby defining a first channel 235 between the first electrode 233 and the dielectric material 238. The first channel 235 may be connected to a first gas source (Figure 1B) through a first inlet 231 defined at a first end, and to a first opening 242 at a second end defined near the top of the nozzle. The first channel 235 may be configured to receive a first gas from a first gas source through the first inlet 231. The second electrode 234 may be embedded in the dielectric material 238 and surround the first electrode 233. The dielectric material 238 may act as a barrier to the metal surface to prevent arc discharge and metal contamination when RF power is applied.

[0041] In some implementations, the first gas may be an etching agent gas. In some cases, the first gas may be a reaction gas or a mixture of gases, for example, an oxygen-based, fluorine-based, hydrogen-based, chlorine-based chemical, or another etching agent precursor, and / or an inert carrier gas such as argon, neon, or helium. The inert gas may be used to carry the plasma radicals of the etching agent through the first opening 242. It should be noted that the above examples of gases are provided as examples only and should not be considered limiting. When the system 200 is used for edge bevel removal, depending on the type of film (i.e., residue) on the edge of the substrate to be removed, the carrier gas may be any stable inert gas such as argon, neon, or helium, and the etching agent gas may contain oxygen, fluorine, chlorine, or any other halogen, or hydrogen. In some cases, when deposition is desired in the APPJ system, the first gas may be a mixture of the deposition gas and the carrier gas.

[0042] As described above, the RF power is modulated to alter the emission of plasma radicals as the substrate 210 spins, thereby creating, for example, a desired etching pattern on the front side of the substrate 210. Such modulation may be performed based on signals generated by the plasma source, controllers coupled to the upper electrode subassembly 202 and / or lower electrode subassembly 204, logic, differential drive units, etc.

[0043] Furthermore, the controller or logic may further control one or any combination of the following parameters: the rotational speed of the substrate, the nozzle position relative to the substrate (e.g., in the x, y, and / or z axes), and plasma parameters (such as plasma power, plasma frequency, gas flow rate, gas composition, and / or gas pressure). In some implementations, the plasma power may vary between on and off. In some implementations, the plasma power may vary between high RF power and low RF power, rather than being on / off. Other parameters affecting etching may include the residence time of the nozzle jet emission at any location on the wafer. Any of these parameters may affect the etching of one or more layers, for example, at the edges or other parts of the substrate 210. These parameters may be controlled while the substrate 210 is rotating or at the location where the nozzle is positioned relative to the substrate 210 (in the radial and azimuthal directions in XYZ space). In some implementations where multiple nozzles are used or included in a subassembly (e.g., upper electrode subassembly 202), each of the multiple nozzles may be controlled separately.

[0044] The dielectric material 238 placed inside the nozzle may further define a second channel 236 between the dielectric material 238 and the outer wall of the nozzle 239. The second channel 236 may be coupled to a second gas source (Figure 1B) through a second inlet 232 defined at the first end to receive a second gas, or a second opening 243 may be defined at the second end defined at the bottom of the nozzle. The second opening 243 may be defined adjacent to and surrounding the first opening 242. The second opening 243 may be a single opening or multiple openings (two are shown in Figure 2A) surrounding the first opening 242. The second gas may be an inert gas such as argon, neon, or helium. The second channel 236 may create a separate gas path for the second gas, or the second opening 243 at the top of the nozzle may guide the second gas upward without disturbing the plasma radicals flowing through the first opening 242. The second gas exiting from the second opening 243 may act as a shield for the plasma radicals mixed with the carrier gas exiting from the first opening 242 by surrounding the mixture of plasma radicals and carrier gas.

[0045] It will be understood that an additional third inlet or channel (not shown) adjacent to the first inlet 231 and / or second inlet 232 may supply a third gas, such as a purge gas and / or a hydrostatic bearing gas, through a third opening (not shown). The third channel 137 in Figure 1B may be an example of a third inlet or channel. In some implementations, the third gas may be supplied with sufficient force to guide plasma radicals away from the center of the substrate 210 toward the substrate edge and to sufficiently expose the substrate edge to plasma radicals. In some cases, the purge gas and hydrostatic bearing gas may be supplied through separate third and fourth inlets and openings. In other configurations, further inlets and openings may be present.

[0046] Referring again to Figure 2B, in some implementations, the second electrode 234 embedded in the dielectric material 238 may be oriented parallel to the first electrode 233, which is positioned approximately in the center of the nozzle. In some alternative implementations, the second electrode 234 embedded in the dielectric material 238 may be oriented at least partially perpendicular to the first electrode 233. Further alternative implementations may be molded to conform to the contour of the dielectric material 238, or oriented parallel to the first electrode 233. Regardless of orientation, the second electrode 234 may be positioned at a predetermined distance from the first electrode 233, and the predetermined distance may be determined to allow for the generation of plasma of the first gas received in the first channel 235. In some implementations, the first electrode 233 may be made of metal. In some implementations, the first electrode 233 and the second electrode 234 may be made of the same material. In some implementations, the first electrode 233 may be made of a different material than the second electrode 234. The material used for the second electrode 234 may be selected to withstand high temperatures. In some methods, the material used for the second electrode 234 may be selected to have a coefficient of thermal expansion (CTE) that matches the CTE of the dielectric material 238 in which the second electrode 234 is embedded. In some methods, the first and second electrodes 233,234 may be made of tungsten, molybdenum, iridium, rhenium, or platinum, and the dielectric material 238 may be made of aluminum nitride, aluminum oxynitride, silicon nitride, aluminum oxide, or yttrium oxide. In some implementations, the dielectric material 238 and / or the first electrode 233 may be cooled using one or more cooling elements (not shown). In some cases, the cooling elements may be placed in a region adjacent to the second electrode 234.

[0047] In some implementations, the first electrode 233, positioned close to the center of the nozzle, may be coupled to the aforementioned RF power supply, and the second electrode 234 may be grounded via a match network. In some other implementations, the first electrode 233 may be grounded, and the second electrode 234 may be coupled to the RF power supply via a match network. In yet another implementation, both the first electrode 233 and the second electrode 234 may be coupled to the RF power supply via a match network, and neither the first electrode 233 nor the second electrode 234 may be grounded.

[0048] In some configurations, a differential voltage may be applied to the first electrode 233 and the second electrode 234. For example, with an input voltage of 2 volts (V), the voltage applied to the first electrode would be +1V and the voltage applied to the second electrode would be -1V (i.e., each electrode may be supplied with half of the input voltage). In some cases, a differential drive (not shown) may be coupled to the RF power supply and used to switch the RF power input between the two electrodes (first electrode 233, second electrode 234). In some implementations, the differential drive may be an isolation transformer having a secondary winding used to provide the differential voltage.

[0049] The nozzle topology may be defined to supply high-density plasma radicals to the substrate 210 in order to achieve high-precision etching (or, in certain cases, deposition). In some exemplary implementations, the flow rate of the reaction gas in the first gas may be defined as between about 100 standard cubic centimeters / minute (sccm) and about 300 sccm, and the flow rate of the carrier gas stream may be defined as between about 1,000 sccm and about 30,000 sccm. In some embodiments, the pressure of the plasma generated in the region between the upper electrode assembly and the lower electrode assembly may exceed a threshold, e.g., at least 200 torr. In some implementations, the plasma pressure may be about 760 torr (atmospheric pressure). In some implementations, the plasma pressure may be any other percentage of atmospheric pressure.

[0050] The nozzle topology can result in an efficient and effective method of processing the substrate 210 using a simple process chamber with minimal hardware. Plasma can be generated remotely and supplied to the edges or other parts of the substrate 210. In addition to the first and second gases being applied to the substrate 210, a third gas may be supplied from a third channel defined adjacent to the nozzle. The third gas can act as a gas curtain, pushing the first gas, contained within the second gas, away from the center of the wafer, resulting in a concentrated application of plasma radicals, whether at the wafer edge or at a radius defined from the center. The simple design makes it possible to keep the process chamber lightweight and compact, and the process chamber can be stacked on other existing modules (e.g., load locks) without leaving additional footprint.

[0051] In some configurations, there may be "n" nozzles (where "n" is an integer) within the nozzle housing, and at least some of the n nozzles simultaneously supply plasma radicals to cover a large area of ​​the substrate 210 or its edge. In some configurations, the nozzle housing may contain 3, 5, 7, or 9 nozzles arranged in close proximity to each other. In some configurations, the "n" nozzles may be arranged along an arc defined within the nozzle housing. The arc may be defined to coincide with the curvature of the substrate edge. In some configurations, the "n" nozzles may be arranged substantially linearly rather than along an arc coinciding with the curvature of the substrate edge. In some cases, linear nozzles may extend radially to allow etching at various radial positions along the substrate. Although various configurations have been described herein with reference to the system 200 using nozzles, the configurations are not limited to nozzle operation, and other non-nozzle tools or components may also be engaged to process the substrate 210.

[0052] In certain embodiments, the nozzle housing and / or the nozzle itself may be configured to actuate in the z-axis (e.g., vertical) and / or radially depending on the distance to a portion of the semiconductor substrate, such as the edge of the semiconductor substrate 210. For example, the housing may actuate within the upper electrode subassembly 202, and / or the nozzle may actuate within the housing. The distance to a portion of the semiconductor substrate 210 may be measured, for example, using one or more optical sensors (e.g., lasers). Based on any variation in the distance between the housing or nozzle and the semiconductor substrate 210 (which may occur due to non-uniformity, curvature, eccentricity, etc., of the substrate), the housing or nozzle may be actuated in accordance with the measured distance (e.g., by a controller) to keep the distance constant.

[0053] Figure 2C is a cross-sectional view showing an upper electrode subassembly 202, a semiconductor substrate 210 (e.g., a wafer), and a lower electrode subassembly 204 according to several embodiments. As can be seen from the figure, the wafer is positioned (e.g., inserted) between the surfaces of the upper and lower electrode assemblies 202,204, and the edge of the semiconductor substrate 210 (wafer edge) is positioned beneath the plasma source 208. The plasma source 208 may be an example of the plasma source 108.

[0054] The plasma source 208 can generate radicals. In some configurations, the generated radicals may be transported to the wafer edge. Radical generation may include the application of RF power only to the upper electrode subassembly 202. This technique is sometimes called “indirect” plasma generation. However, in some configurations, radicals may be generated directly at the edge of the semiconductor substrate 210 by, for example, applying RF power to both the upper and lower electrode assemblies. This technique is sometimes called “direct” plasma generation.

[0055] Figure 2D illustrates indirect plasma generation and transport, where RF power may be applied to the upper electrode subassembly 202 (more specifically, the upper electrode 203), thereby generating radicals within the plasma source 208. In some embodiments, an inductively coupled plasma (ICP) source may be used, which is a type of plasma source in which energy is supplied by electromagnetic induction, i.e., by a current generated by a time-varying magnetic field. Plasma radicals are generated remotely from the material being processed (e.g., a layer or film on the semiconductor substrate 210). The generated radicals are then emitted from the plasma source 208 and can be transported along with a carrier gas through the nozzle of the plasma source 208. A portion of the semiconductor substrate 210 (e.g., a wafer edge) may be processed (e.g., etched) using the radicals transported thereto.

[0056] Figure 2E shows direct plasma generation, where RF power may be applied to the upper electrode subassembly 202 (upper electrode 203) and the lower electrode subassembly 204 (lower electrode 205), thereby generating radicals directly on a portion of the semiconductor substrate 210 (e.g., the wafer edge). In some embodiments, a capacitively coupled plasma (CCP) source may be used. Since the etchant is generated directly on the wafer edge, there is no transport, which favorably reduces the loss of radicals due to radical recombination 221 (e.g., O + O2 → O3), as shown in Figure 2F, thereby increasing etching. Such recombination and loss can still occur during indirect plasma generation and transport, particularly during transport, as radical oxygen atoms may react with molecular oxygen.

[0057] As shown in Figure 2F, examples of factors involved when processing wafer edges using plasma source 208 include (1) radical generation, (2) radical transport, and (3) surface reactions. Radical generation may include the decomposition of gas species such as molecular oxygen (O2 → O+O).

[0058] Factors influencing radical generation may include the O2 concentration (including in the carrier gas), plasma density and electron temperature, and the carrier gas used. In some implementations, the O2 concentration in the carrier gas may be less than 10%. High-pressure ICP may be used to produce optimal plasma density and electron temperature. The gas pressure in the reactor can be atmospheric pressure (about 760 Torre) or lower than atmospheric pressure, i.e., a percentage of atmospheric pressure (e.g., about 200 Torre or higher). Higher pressure may contribute to higher etching rates in EBR. The carrier gas may be an inert gas, such as helium (He), neon (Ne), or argon (Ar).

[0059] Factors influencing radical transport may include distance to the wafer, gas flow, and recombination conditions. In some implementations, the distance to the wafer edge is virtually zero, and a CCP source may be used to avoid transport. For example, the direct plasma generation technique described with respect to Figure 2E may be used. A high gas flow rate may be used (for example, to prevent etching of areas that should not be etched). For recombination, for example, an O2 pressure of less than 10% in an inert gas may be specified.

[0060] Surface reactions may include etching of the wafer edge. Factors influencing surface reactions may include temperature, which may be used to achieve etching. Gas composition may also affect the etching rate; high O2 concentrations in the purge gas and / or low O2 concentrations in the process gas have been found to result in high etching rates.

[0061] Figure 2G shows an enlarged view of the hardware configuration of the material removal system 200 according to several embodiments. The semiconductor substrate 210 may be supported and fixed by an aligner 212 (e.g., including a chuck) and inserted into the gap between the upper electrode subassembly 202 and the lower electrode subassembly 204. In some embodiments, the plasma source may include, for example, a tip 250 in the nozzle of the plasma source. The material of the tip 250 may be selected for high-temperature performance as needed. A refractory metal such as tungsten allows for high tip temperatures. In some implementations, the tip material may alternatively include other metals such as molybdenum, iridium, rhenium, or platinum. In some embodiments, the edges of the semiconductor substrate 210 may be at least partially confined by a solid object such as a confinement shelf 252. The confinement shelf 252 may be configured, positioned, and molded to confine and / or at least partially prevent the diffusion of etchants, materials, gases, plasma, etc., into the inner area of ​​the wafer.

[0062] In some embodiments, the system 200, in particular the aligner 212, may further include a chuck or be configured to interact with a chuck. In some embodiments, the chuck may comprise a stem portion and a chuck portion that interfaces with the substrate 210. The stem portion may be sufficiently narrow to accommodate the movement of the chuck into the gap between the upper electrode assembly 202 and the lower electrode assembly 204 (for example, the diameter of the stem portion is significantly smaller than the diameter of the substrate 210, e.g., less than half). An example of a chuck diameter may be 10 inches.

[0063] Returning to Figure 2G, one or more process gases 254 may be supplied to the plasma source. In different implementations, the process gases 254 may include a reactive gas or etching agent gas such as oxygen, and a carrier gas (e.g., an inert gas such as helium, neon, or argon). The process gases 254 may be excited to a plasma state (e.g., via RF power application using upper and / or lower electrodes) for direct or indirect plasma generation and transfer. The generated plasma radicals may be confined in a vacuum or process volume 255, at least partially based on the confinement shelf 252 and other components of the system (e.g., walls present across the confinement shelf 252).

[0064] The process gas 254 may be used to generate plasma at a specific pressure in the plasma source and discharge it through the tip 250. In some embodiments, the plasma may be atmospheric pressure plasma (also known as normal pressure plasma) having a pressure approximately equal to the pressure of the ambient atmosphere. In some embodiments, the plasma may have a pressure of at least about 200 Torr, or at least about 300 Torr. This is in contrast to some conventional EBR applications where the etchant is generated by a low-pressure plasma. However, the performance limits of low-pressure etchants (e.g., low etching rate, high diffusivity) and the width of the etching profile (e.g., control of etchant delivery, precision and location of where the etchant is delivered) can be improved by using a high-pressure plasma. Nevertheless, the plasma pressure may be modified depending on the implementation of the system disclosed herein and its intended use. In fact, adjusting the plasma pressure is easily done by the user or operator, and there is no need to optimize or redesign the hardware configuration when adjustment of the etching profile and etching width is desired.

[0065] Furthermore, one or more purge gases 256 may be supplied through the opening 257 to affect the etching profile of the EBR. Examples of purge gases 256 may include various ratios of etchant and carrier gas or inert gas. In some cases, the purge gas 256 may include nitrogen or air. The upper gap 259 may be designed to be small enough to substantially suppress plasma emission when the gap is small, but the combination of etchant and carrier gas released into the plasma emission region can contribute to the etching profile and etching rate. In some applications, the desired etching profile may transition rapidly from nominally no etching to a fully etched film and can be optimized by the ratio of etchant to carrier gas. The purge gas 256 may be released over the entire upper gap 259 in the upper portion of the semiconductor substrate 210 (e.g., on the front side). The semiconductor substrate 210 being processed by the material removal system may be very close to the dielectric surface of the upper electrode subassembly 202 (e.g., dielectric shield 260) and the dielectric surface of the lower electrode subassembly 204 (e.g., dielectric barrier 258). Therefore, the upper gap 259 may be very small. In some cases, the upper gap 259 may be about 3 mils (about 0.003 inches, or about 76.2 microns). In some cases, the upper gap 259 may be about 100 microns or less (e.g., microns to tens of microns). A lower gap 261 may exist between the semiconductor substrate 210 and the lower electrode subassembly 204. In some mounting configurations, the lower gap 261 may be similar in size to the upper gap 259. In some mounting configurations, the lower gap 261 may have a small (e.g., less than about 10 microns) but non-zero distance.

[0066] It is desirable to select a sufficiently narrow size for the upper gap 259 between the semiconductor substrate 210 and the upper electrode subassembly 202. When the upper hydrostatic gas bearing gas or purge gas 256 flows through the small gap in the upper gap 259, substantial rigidity can be introduced between the semiconductor substrate 210 and the dielectric surface (e.g., dielectric shield 260). The orifice of the tip 250 may be designed to have a choked flow between the outer diameter of the orifice and the small gap to the wafer. The viscous force through the small gap can result in a pressure that balances the pressure at the orifice exit. As the gap size increases, the viscous force decreases, thereby reducing the pressure at the orifice exit and increasing the flow. At the same time, the force between the dielectric and the substrate changes with the gap, thereby introducing rigidity. The purge gas 256 may contribute to the process outcome by suppressing plasma from entering the upper gap 259, which can ensure that etching does not diffuse excessively into the inner portion of the wafer (e.g., 102-i) and improve the reaction product density in the area around the wafer edge. Therefore, another consideration is that the gas flow can be controlled independently, for example, by configuring a purge gas 256 and / or a hydrostatic gas bearing gas to supply a desired amount of gas nominally discharged into the upper gap 259 at a flow rate of, for example, 0.1 to 100 standard liters / minute (slm), thereby optimizing wafer edge processing. The hydrostatic gas bearing surface area, orifice array spacing, orifice diameter, and pressure are selected to generate sufficient force and stiffness within a controlled range of the gap so that the spin substrate 210 does not come into contact with the hydrostatic gas bearing surface in the presence of out-of-plane wafer motion. Out-of-plane motion can be caused by reasons including imperfections in the motion of the aligner 212, strain of the substrate 210 including thermally induced strain by the plasma jet, and variations in the thickness of the substrate 210. The upper and lower hydrostatic gas bearings have considerable stiffness, balancing equally opposing forces and maintaining the wafer within a substantially constant gap.High rigidity allows the bearing force to increase rapidly with decreasing gap, thereby stabilizing wafer positioning to maintain a substantially consistent gap regardless of the movement of the aligner 212 or the non-flatness of the substrate 210.

[0067] In other words, the hydrostatic gas bearing can hold the substrate 210 on a relatively fixed plane and reduce friction against the hardware surface as the substrate rotates. As the substrate 210 rotates, chemical reaction species, such as etching agents generated in the upper electrode subassembly 202, may be applied to the edges or other parts of the substrate 210. For direct plasma generation, an RF voltage may be applied between the upper electrode 203 and the lower electrode 205, and the plasma can be generated in a relatively small, confined region around the wafer edge (e.g., within the process volume 255). In some etching implementation configurations, the chemical properties of the plasma may be selected to have volatile reaction products with the film being etched. For example, oxygen radicals may be specific to carbon (C) or carbon-based films, while fluorine (F) radicals may be selected for molybdenum (Mo) or tungsten (W) materials for removal. Appropriate reactants can be selected to target the metal or material being etched. For deposition, the chemistry of the plasma may be selected to have deposition products for plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD). Examples of precursors for silicon dioxide deposition include silane and tetraethoxysilane (TEOS). The deposition gas for silicon nitride may include, for example, silane, nitrogen, and ammonia. An exemplary precursor for tungsten deposition includes tungsten hexafluoride (WF6). These examples are illustrative and do not preclude other chemistry properties selected for specific film compositions.

[0068] In some exemplary operations, the distance or gap between the upper electrode subassembly 202 and the lower electrode subassembly 204 may be set or adjusted (for example, via z-axis movement of the electrode assembly and / or substrate 210 via a chuck) so that even a curved substrate can be accepted without touching the surfaces of the upper and lower electrode assemblies. The loading process will be described in more detail with reference to Figures 4A to 4D.

[0069] In some implementations, the plasma jet or plasma jet emitter of the nozzle may be rasterized on the surface of the substrate 210. Multiple nozzles (e.g., 2 to 10 nozzles or an array or group of plasma jets) may perform the rasterization. In some variations, the multiple nozzles may be fixed relative to each other, and in some cases, the multiple plasma jet emitters may be arranged within a given nozzle.

[0070] In some implementations, the material removal system 200 may include an exhaust section (not shown) for rapidly removing plasma radicals and residues released from the substrate 210 and / or its edges during or after the EBR operation performed by the system 200. Rapid removal of residues and radicals ensures that the residues do not contaminate the substrate surface and that the radicals do not damage any formed devices present on the substrate surface (e.g., the front side).

[0071] In some implementations, the upper and lower electrodes may be offset vertically and / or horizontally from each other so as not to lie on the same vertical axis. In such cases, the electric field lines may be forced to pass through the desired edge region of the semiconductor substrate 210 (e.g., etching).

[0072] Referring here to Figure 2H, a cross-sectional view of the plasma source 208 having a confinement shelf 252 is shown. In some embodiments, as suggested above, the confinement shelf 252 may be part of the upper electrode subassembly 202 (e.g., integrated) or it may be an additional physical feature that can otherwise be incorporated into the system hardware. In some configurations, the confinement shelf 252 may be associated with the plasma source 208 (e.g., adjacent or nearby). In some cases, the confinement shelf 252 may be extended to define an exclusion region on the semiconductor substrate 210 where the plasma can be substantially suppressed below the confinement shelf 252.

[0073] In some implementations, an additional confinement shelf 253 may be present, as shown in Figure 2I. Similar to the confinement shelf 252, the additional confinement shelf 253 may be configured to further restrict the volume in which the plasma can emit light. For example, the confinement shelf 253 may confine and / or at least partially prevent the diffusion of etchants, materials, gases, plasma, etc., from the process volume 255. Allowing plasma in a localized region (e.g., the process volume 255) with an edge of the semiconductor substrate 210, while suppressing plasma in a volume or region 262 that may be undesirable, may improve the efficiency of the plasma generation components (e.g., the plasma source 208, the upper electrode subassembly 202, and / or the lower electrode subassembly 202) and may prevent processing in undesirable areas. The small gap 259, which enables the hydrostatic gas bearing, also provides rigidity and pressure to balance the pressure at, for example, the orifice outlet of the plasma source 208, suppresses plasma generation in the upper gap 259 where processing in the inner portion of the semiconductor substrate 210 is undesirable, and can improve the effectiveness of confinement by controlling the etching profile and etching width.

[0074] Shelf features such as the containment shelf 252 and / or additional containment shelf 253 can prevent other atmospheric gases (e.g., nitrogen) from entering the process volume 255 and further isolate the plasma processing the wafer edge.

[0075] Therefore, by utilizing the various physical configurations described above, reactive species (e.g., etching agents) can be substantially confined using hydrostatic gas bearings in a narrow gap between the wafer and hardware (e.g., upper electrode subassembly) to process the edges of a spinning wafer. Precise positioning and processing of the wafer is possible by modulating RF power to actuate the upper and / or lower electrode assemblies (e.g., in the XYZ directions) and / or by acting the wafer (e.g., in the XY direction). While the wafer is spinning, rapid modulation of RF power (which can be faster than the wafer rotation, as described above) and / or changes in the emission or flow rate of the generated plasma allow for processing (e.g., etching) at desired locations to remove unwanted material from the wafer edges. Processing of non-edge areas, such as inner portions, may be further possible based on wafer acting (e.g., in the XY directions to insert deeper into the narrow gap). In some cases, deposition may be carried out on the front side of the wafer, for example, to reverse over-etching or achieve curvature compensation, or on the back side of the wafer, for achieving curvature compensation.

[0076] As described above, the RF power can be modulated to alter the emission of plasma radicals as the substrate 210 spins, thereby creating a desired etching pattern. Such modulation may be performed based on signals generated by a controller, logic, differential drive, etc., coupled to the plasma source 208, the upper electrode, and / or the lower electrode.

[0077] Furthermore, as will be mentioned elsewhere in this specification, the controller or logic may further control one or any combination of the following parameters: the rotational speed of the substrate, the tip position relative to the substrate (e.g., in the x, y, and / or z axes), and etching rate parameters (such as plasma power, plasma frequency, gas flow rate, gas composition, and / or gas pressure).

[0078] In some operations, parameters for control within the etching profile may include the radial position where material removal occurs. This may result in a specific radius (or diameter) of the substrate 210. In some configurations, the substrate radius may be defined to be within a range (or difference of 0.6 mm) between approximately 147.8 and 148.4 mm. In some configurations, the substrate radius may be defined to be within a range (or difference of 0.5 mm) between approximately 147.7 and 148.2 mm. In some cases, the substrate radius may be defined to have no range and be substantially a vertical cut. This range of the substrate radius may be narrowed by a precise margin (e.g., within 0.1 mm) to create a vertical cut that can help prevent radical flow toward the inner portion or center of the wafer, resulting in a sharp wafer thickness transition.

[0079] Several parameters can also affect the deposition method. Such deposition parameters may include plasma power (high / low between high and low RF power, rather than on / off or on to off), plasma frequency, gas flow rate, gas composition, gas pressure, and residence time of nozzle jet emission at any location on the wafer. Any of these deposition parameters may affect the local thickness and / or internal stress of the back layer. These parameters may be controlled while the substrate is rotating or where the nozzle is positioned relative to the substrate (in XYZ space, radially and azimuthal). In configurations where multiple nozzles are used or included in a nozzle housing, each of the multiple nozzles may be controlled separately.

[0080] Static gas bearing Figures 2J to 2M show cross-sectional views of hardware components configured to provide a hydrostatic gas bearing while processing a semiconductor substrate 210 (for example, etching the edges of the semiconductor substrate), according to several embodiments.

[0081] Figure 2J is a cross-sectional view of an upper electrode subassembly 202 configured to provide a hydrostatic gas bearing on a semiconductor substrate, according to several embodiments, and various components thereof. In some embodiments, the upper electrode subassembly 202 may further include a bracket 264 configured to be physically coupled to an upper electrode mount 266, and the upper electrode mount may be configured to be physically coupled to a cooling plate 268a and / or upper electrode 203. In some implementations, the cooling plate 268a may be configured to manage the temperature of the system 200. For example, a liquid-cooled cold plate may be included in the upper electrode assembly 202 to cool the upper electrode subassembly 202 for high power density operation. In alternative examples, to enable high power density, a coolant may be circulated within the body of the upper electrode 203 and around the inside of the tip 250. In some implementations, the cooling plate 268a may be made of a heat dissipation material with high thermal conductivity (e.g., copper, aluminum, or other suitable material) to prevent the upper electrode 203 or other surrounding components from overheating during high power density operation. In some cases, the bracket 264 may act as a stabilizing component coupled to another hardware component or object such as the stage 206, the lower electrode subassembly 204, a wall or other surface, or a process chamber. Similarly, the upper electrode mount 266 may be configured to firmly and stably hold other components of the upper electrode subassembly 202. The material of the body of the upper electrode 203 may be selected for optimized (low) cost and heat extraction. For example, aluminum may be selected. Since the dielectric shield 260 and dielectric barrier 258 may also have high thermal loads, ceramics with high thermal shock resistance, thermal conductivity, and electrical insulation may be selected for these dielectric components, one example being aluminum nitride (AlN). In some exemplary configurations, the area of ​​thermal load can also be ensured to be away from the edges of the ceramic and located at the center of the oversized diameter to relieve tensile stress created in the ceramic component due to differences in thermal expansion.

[0082] In some embodiments, such other components may include an upper hydrostatic bearing gas manifold 272, at least one upper hydrostatic bearing orifice 274a, an upper hydrostatic bearing surface 276, and / or one or more clamping mechanisms 278. In some implementations, the upper hydrostatic bearing gas manifold 272 may provide various inlets, paths, and outlets for the upper hydrostatic bearing gas 270 toward, for example, the upper surface of the semiconductor substrate 210. In various implementations and applications, the upper hydrostatic bearing gas 270 may be an inert gas such as argon, neon, helium, or nitrogen. In various implementations and applications, the upper hydrostatic bearing gas 270 may have a carrier gas to etching agent gas ratio. This ratio may be selected along the gap size to control the etching profile and etching rate. The upper hydrostatic bearing gas 270 may be released through at least one upper hydrostatic bearing orifice 274a.

[0083] When the upper hydrostatic bearing gas 270 is released from at least one upper hydrostatic bearing orifice 274a, the semiconductor substrate 210 and the upper hydrostatic bearing surface 276 may form a small upper gap 259 as described herein. In some configurations, the upper hydrostatic bearing orifice 274a may be configured to have a choke flow (contracted to increase the radiation velocity) between the outer diameter of the upper hydrostatic bearing orifice 274a and the small gap 259 to the substrate 210. The viscous force through the gap 259 may result in a pressure that balances the pressure at the orifice outlet. As the gap increases, the viscous force decreases, thereby lowering the pressure at the orifice outlet and increasing the flow. At the same time, the force between the dielectric shield 260 and the substrate 210 changes with the gap, thereby allowing for stiffness to exist.

[0084] Figure 2K is a cross-sectional view of a lower electrode subassembly 204 and various components thereof, configured to provide a lower hydrostatic gas bearing on a semiconductor substrate 210 according to several embodiments. In some embodiments, the lower electrode subassembly 204 may further include a bracket 264 (which in some mounting configurations may be separate from a bracket or part used with the upper electrode subassembly 202) configured to physically couple to a lower electrode mount 286, and the lower electrode mount may be configured to physically couple to a cooling plate 268b and / or the lower electrode 205. The cooling plate 268b may be similar to the cooling plate 268a, or the two cooling plates may have different sizes, shapes, compositions, etc. The lower electrode mount 286 may be configured to firmly and stably hold the other components of the lower electrode subassembly 204.

[0085] In some embodiments, such other components may include a lower hydrostatic bearing gas manifold 292, at least one lower hydrostatic bearing orifice 294a, a lower hydrostatic bearing surface 296, and / or one or more clamping mechanisms 298. In some mounting configurations, the lower hydrostatic bearing gas manifold 292 may have various inlets, paths, and outlets for the lower hydrostatic bearing gas 290, for example toward the bottom surface of the semiconductor substrate 210. In various mounting configurations and applications, the lower hydrostatic bearing gas 290 may be an inert gas such as argon, neon, helium, or nitrogen. In various mounting configurations and applications, the lower hydrostatic bearing gas 290 may have a carrier gas to etching agent gas ratio. This ratio may be selected along the gap size that controls the etching profile and etching rate that have the greatest impact toward the bottom of the bevel and toward the back side of the semiconductor substrate 210. The lower hydrostatic gas bearing gas 290 may be released through at least one upper hydrostatic gas bearing orifice 294a.

[0086] When the lower hydrostatic bearing gas 290 is released from at least one lower hydrostatic bearing orifice 294a, the semiconductor substrate 210 and the lower hydrostatic bearing surface 296 may form a small lower gap 261 as described herein. In some configurations, the lower hydrostatic bearing orifice 294a may be configured to have a choke flow between the outer diameter of the lower hydrostatic bearing orifice 294a and the small gap 261 to the substrate 210. The force between the dielectric barrier 258 and the substrate 210 changes with the gap, thereby creating stiffness. In some embodiments, the stiffness created by the upper hydrostatic bearing surface 276 and the substrate 210 may be substantially equal to the stiffness generated by the lower hydrostatic bearing surface 296 and the substrate 210.

[0087] Essentially, the components of the upper and lower electrode subassemblies 202,204 are parallel to each other and may be mirrored in many ways. Furthermore, direct plasma generation is enabled by positioning the upper and lower electrodes 203,205 in opposite directions, for example, as shown in Figure 2E. In some implementations, the entire source subassembly 201 may be aligned to the edge of the semiconductor substrate 210 using mechanical adjustments. Both the upper electrode subassembly 202 and the lower electrode subassembly 204 may use their respective upper and / or lower mounts 266,286, which have adjustability and compliance, to establish high parallelism between the upper and lower hydrostatic bearing surfaces 276 and 296 and the semiconductor substrate 210 when hydrostatic bearing gas is flowing. The motorized stage 206 may be configured to precisely move the lower electrode subassembly 204, for example, to control the total gap required to clamp the semiconductor substrate 210 while providing a small gap 259,261 between the wafer and the hydrostatic bearing surfaces 276,296.

[0088] However, there may be variations in the positioning and alignment of certain components of the upper and lower electrode subassemblies 202,204. For example, as described above, the upper and lower electrodes 203,205 may be offset by a specified amount; that is, in some configurations they may not be along the same axis. The upper and / or lower electrodes 203,205 may have tip-like features (e.g., tip 250,280) to result in a preferred electric field profile for generating high power density plasma. The horizontal and vertical offsets between tip 250 and tip 280 may be process tuning knobs for adjusting the etching (or deposition) rate around the edge of the substrate 210. Direct plasma generation may be used to increase the etching rate for reasons described elsewhere in this specification. In some configurations, away from the tip 250,280, the bodies of each electrode may have a large cross-section that can add heat capacity and conductivity to the surface from which heat can be extracted.

[0089] Figure 2L is an enlarged cross-sectional view of the hydrostatic gas bearing generated in relation to the semiconductor substrate 210. In some configurations, the upper hydrostatic gas bearing gas path 271 may be configured to provide a conduit for the upper hydrostatic gas bearing gas 270 to flow from a gas source (not shown) toward the substrate 210. In some cases, an upper hydrostatic gas bearing seal 273 and a lower hydrostatic gas bearing seal 293 may be implemented to ensure that all the hydrostatic gas bearing gas flows toward the substrate 210 and maintains the desired pressure without leakage. Depending on the implementation configuration, the upper hydrostatic gas bearing gas path 271 may be divided into multiple orifices, such as using an upper hydrostatic gas bearing orifice array 274 having three orifices in the embodiment shown in Figure 2L, and orifice 274a may be one of them. Similarly, the lower hydrostatic gas bearing gas path 291 may be divided into multiple orifices as shown in Figure 2L, and orifice 294a may be one of them.

[0090] Depending on the desired implementation configuration, the load capacity, stiffness, amount of wafer planarization, and gas flow characteristics associated with the hydrostatic gas bearing may be modified by altering the shape, diameter, and number of orifices, as well as the width and length of the upper and lower hydrostatic gas bearing pads 277, 297. The supplied gas pressure can also be a factor influencing these characteristics. For example, when the number of orifices is small (e.g., less than 10), the orifice diameter may be around 50 microns to several hundred microns. However, if many orifices are created by using a porous medium, for example, the effective size of the orifices may be on the scale of microns. The supplied gas pressure can strongly influence the final load capacity, gas consumption, and stiffness of the hydrostatic gas bearing. Examples of supplied gas pressures include 50 to 150 pounds / square gauge (PSIG). The area of ​​the rectangular, circular, or other hydrostatic gas bearing pads 277 may be, for example, 10 cm². 2 It may be to a certain extent. However, other exemplary ranges of the area of ​​the hydrostatic gas bearing pad 277 are 1 cm². 2 Less than ~ several tens of cm 2 The range may be up to . Applications can take into account wafer flatness, thermally induced deflection, and / or plasma confinement by gaps and gas flow in order to achieve bearings that produce desired process results with minimal gas consumption or cost. As shown in Figure 2M, the hydrostatic gas bearing pads refer to the area or portion of the upper and lower hydrostatic gas bearing surfaces 276,296 that provide the hydrostatic gas bearings. In some embodiments, the widths and lengths of the upper and lower hydrostatic gas bearing pads 277,297 may be substantially coincidental and substantially equal in order to avoid causing non-flatness in the substrate 210 in at least the area or width of the hydrostatic gas bearing pads 277,297.

[0091] In alternative implementations, the use of orifices for the hydrostatic gas bearing gas may include the use of a porous medium for the hydrostatic gas bearing pad area instead of individual orifices such as the illustrated 3-orifice array 274, 294. The material of the porous medium may be selected to be process-compatible and to have an appropriate proportion of pores open through its volume. Porous ceramics, such as aluminum nitride, aluminum oxynitride, silicon nitride, aluminum oxide, or yttrium oxide may be selected.

[0092] Depending on the configuration, the areas of the upper and lower hydrostatic gas bearing surfaces 276,296, the spacing of the orifice arrays 274,294 (which may include the upper hydrostatic gas bearing orifice 274a and the lower hydrostatic gas bearing orifice 294a), the diameter of each orifice 274a,294a, and the pressure and / or composition of the upper and lower hydrostatic gas bearing gases 270,290 can be selected (e.g., according to the examples of values ​​and ranges above) to generate sufficient force and stiffness within a controlled gap range, so that the spinning substrate does not come into contact with the hydrostatic gas bearing surfaces (e.g., the upper hydrostatic gas bearing surface 276 and the lower hydrostatic gas bearing surface 296) in the presence of out-of-plane wafer motion. In the disclosed embodiments, the upper and lower hydrostatic gas bearings may have considerable stiffness, balancing equally opposing forces to maintain the wafer in a substantially constant gap. Thus, in some embodiments, the stiffness created by the upper hydrostatic gas bearing surface 276 and the substrate 210 may be substantially equal to the stiffness created by the lower hydrostatic gas bearing surface 296 and the substrate 210. Advantageously, the opposing hydrostatic gas bearings may hold the edge of the substrate 210 between the hydrostatic gas bearing surface 276 and the hydrostatic gas bearing surface 296 without contact with the substrate 210, regardless of the source of out-of-plane motion. The stiffness of both the air bearings and the mounting frame (e.g., comprising upper and / or lower electrode mounts 266, 286) may be combined to define the total force-to-gap stiffness.

[0093] Using the embodiments and implementation configurations of the structural components described above, the upper and lower hydrostatic bearing gases 270, 290 may be supplied, for example, through the upper and lower hydrostatic bearing gas manifolds 272, 292, respectively. When an RF voltage is applied between the upper electrode 203 and the lower electrode 205, plasma can be generated in a relatively small, confined region around the wafer edge, for example, in the process volume 255. For etching, the chemistry of the plasma may be selected to have volatile reaction products with the film to be etched, such as oxygen reacting with carbon-based materials on the substrate. For deposition, the chemistry of the plasma may be selected to have deposition products for PECVD or PEALD. The hydrostatic bearing gases 270, 290 exiting each hydrostatic bearing orifice (e.g., 274a, 294a) can contribute to the process outcome by suppressing plasma generation or migration in the small gaps of the hydrostatic bearing surfaces (e.g., the gap 259 of the upper hydrostatic bearing surface 276 and the gap 261 of the lower hydrostatic bearing surface 296), thereby improving the reaction product density in the area around the substrate edge. Therefore, one consideration may be to control the hydrostatic bearings to supply a desired amount of gas nominally flowing out of the air bearings for process optimization. Possible gas flow rates for the hydrostatic bearing gases that can be used include, for example, 0.1 to 100 slm.

[0094] Figure 3 is an exemplary diagram showing a semiconductor substrate 302 with at least a portion of its edge 310 processed, indicated by a processing area 320. According to embodiments described herein, material may be removed in the processing area 320, and the remaining portion of the substrate 302 may still have a film or other material on it without damaging the material or the substrate. When EBR is performed using embodiments described herein, the transition between the unprocessed portion 306 and the etched portion 308, indicated by area 304, is extremely sharp, resulting in a clean bevel on the edge of the substrate 302.

[0095] Loading and processing of substrates The material removal system described above may include a loading process for etching or otherwise processing the semiconductor substrate, in which case the substrate is properly received without damage, and the hydrostatic gas bearings planarize the substrate and keep the plasma confined to the edges of the substrate. For example, the aligner subassembly 212 shown in Figure 2A may be used to align, fix, and position the substrate between the upper electrode subassembly 202 and the lower electrode subassembly 204, and then actuated to create a small gap above and below the substrate, as described in detail above. The specific steps continue.

[0096] Figures 4A to 4D show some steps of the process of loading a semiconductor substrate for processing using the material removal system described above, according to several embodiments.

[0097] Figure 4A shows process step 401 in which the semiconductor substrate 210 is initially loaded onto the aligner 212 and placed on one or more pins 214. In this figure, the substrate 210 may have already been aligned (e.g., using an alignment sensor 215) to minimize wafer eccentricity and may be servo-driven or actuated toward the upper and lower electrode subassemblies 202,204. In this case, the upper and lower electrode subassemblies 202,204 may not be in close proximity to the substrate 210.

[0098] Figure 4B shows process step 402 in which the chuck 213 can lift the semiconductor substrate 210 above the pins 214, for example by extension. In some embodiments, the chuck 213 can fix the semiconductor substrate 210 in place. In some mounting configurations, the chuck 213 may be a vacuum chuck configured to operate as described elsewhere in this specification. In some mounting configurations, the chuck 213 may be an ESC. While the semiconductor substrate 210 is fixed by the chuck 213, the chuck 213 may move the semiconductor substrate 210 to a set position perpendicular to the aligner 212 (e.g., z-axis) and / or horizontally (e.g., x-axis and / or y-axis). This movement may bring the semiconductor substrate 210 closer to the upper electrode subassembly 202.

[0099] Figure 4C shows process step 409 in which the aligner 212 can lift the semiconductor substrate 210 toward the upper electrode subassembly 202. In some methods, the upper hydrostatic gas bearing gas may be turned on before lifting the semiconductor substrate 210 toward the upper electrode subassembly 202 to prevent the semiconductor substrate 210 from contacting any surface of the upper electrode subassembly 202.

[0100] Figure 4D shows a process step 411 in which at least a portion of the lower electrode subassembly 204 (e.g., the lower electrode 205) may be raised toward the process position. In some methods, the lower hydrostatic gas bearing gas may be turned on before the lower electrode subassembly 204 is raised.

[0101] It will be understood that these process steps may be performed in a different order than those described. Variations in this loading sequence are possible. For example, process steps 401 and 402 may be modified to load the wafer directly onto the raised pad, reversing the steps of loading the substrate onto the aligner and extending the chuck above the pins. Also, some of the steps described later (e.g., substrate alignment) may be omitted by the steps of measuring eccentricity and compensating for eccentricity along the x-axis.

[0102] Figure 5 is a flowchart showing a method 500 for processing a semiconductor substrate according to several embodiments. The substrate has a front side, which may have electronic device features fabricated thereon. One or more blocks of method 500 may be implemented by or caused by an apparatus or system controlled by a computing device. Such a system may include, as described above, one or more electrodes, an RF power supply, and / or various hardware components such as actuators (e.g., stages, aligners). Structures for implementing the functions shown in one or more of the blocks shown in Figure 5 may include hardware and / or software components of such an apparatus or system, or computing devices such as a controller or computer-readable device that includes a storage medium for storing computer-readable instructions and / or computer-executable instructions configured to cause a processor device to perform an operation when executed by a processor device. Exemplary components of an apparatus or system are described below with respect to Figure 7.

[0103] It should also be noted that the operations of Method 500 may be performed in any suitable order, not necessarily in the order shown in Figure 5. Furthermore, Method 500 may include additional or fewer operations than those shown in Figure 5 for processing the semiconductor substrate.

[0104] In block 501, method 500 may include receiving the semiconductor substrate 210 onto one or more pins 214 of the aligner 212. The aforementioned process step 401 shown in Figure 4A may correspond to block 501.

[0105] In block 502, method 500 may include moving the semiconductor substrate 210 above one or more pins 214. In some embodiments, this may include the steps of securing the semiconductor substrate 210 using a chuck 213 (e.g., a vacuum chuck) and operating the chuck above the pins 214 (e.g., in the z direction). The aforementioned process step 402 shown in Figure 4B may correspond to block 502.

[0106] In block 503, method 500 may include spinning the semiconductor substrate 210 while measuring the eccentricity of the substrate. In some embodiments, the aligner 212 and its components may be used to spin the substrate (for example, the chuck 213 may be configured to rotate while holding the substrate in place) and / or to measure the eccentricity of the wafer (for example, using an alignment sensor 215).

[0107] In block 504, method 500 may optionally include orienting the semiconductor substrate 210 such that its eccentricity aligns with the axis of the aligner 212. The chuck may be stopped to allow the substrate 210 to descend onto the pins 214 of the aligner 212.

[0108] In block 505, method 500 may optionally include lowering a semiconductor substrate onto one or more pins 214 of the aligner 212.

[0109] In block 506, method 500 may optionally include translating the x-axis so that the spin axis of the aligner 212 is aligned with the center of the substrate 210. The aligner 212 may then lift the substrate 210 above the pins 214 and reactivate the chuck 213. This effectively ensures that the substrate 210 is centered around the spin axis of the aligner 212, and the substrate 210 can then rotate with minimal eccentricity.

[0110] If the semiconductor substrate 210 is not yet positioned between the upper electrode subassembly 202 and the lower electrode subassembly 204, the substrate may be moved (for example, in the x and / or y directions) relative to the upper electrode 203 and the lower electrode 205. For example, the edge of the substrate 210 may be positioned directly below the upper electrode 203, while the inner portion of the substrate 210 may be positioned above the lower electrode 205. In some mounting configurations, there may be an offset between the upper electrode 203 and the lower electrode 205 such that the upper and lower electrodes 203,205 are not on the same vertical axis.

[0111] Alternatively, positioning the semiconductor substrate 210 between the upper electrode subassembly 202 and the lower electrode subassembly 204 may be performed at another point in the loading process, for example, during block 501 (e.g., when the substrate 210 is received on the pins of the aligner 212, it may be positioned between the upper electrode subassembly 202 and the lower electrode subassembly 204), or before block 503 (e.g., after the chuck 213 has secured the substrate 210, the aligner 212 may move in the x and / or y directions).

[0112] In block 508, method 500 may include activating the upper hydrostatic bearing gas 270. In some embodiments, a source of upper hydrostatic bearing gas may be activated. When turned on, the upper hydrostatic bearing gas may flow out of one or more upper hydrostatic bearing orifices 274 through the upper hydrostatic bearing gas path 271 in the upper hydrostatic bearing gas manifold 272. In some implementations, the initial gas pressure here may be lower than during later processing to conserve gas supply or output.

[0113] In block 509, method 500 may include moving the semiconductor substrate 210 to a process position. The aforementioned process step 409 shown in Figure 4C may correspond to block 509. The substrate 210 may be moved very close to the upper electrode subassembly 202 (more specifically, the upper hydrostatic gas bearing surface 276) with a gap of 100 microns or less. The activation of the upper hydrostatic gas bearing gas 270 in block 508 may be performed before moving the substrate 210 to prevent contact between the substrate 210 and the upper hydrostatic gas bearing surface 276. In some cases, the semiconductor substrate 210 may be lowered rather than lifted, either additionally or alternatively.

[0114] In block 510, method 500 may include activating lower hydrostatic bearing gas. In some embodiments, a source for lower hydrostatic bearing gas may be activated. When activated, lower hydrostatic bearing gas may flow out of one or more lower hydrostatic bearing orifices 294 through the lower hydrostatic bearing gas path 291 in the lower hydrostatic bearing gas manifold 292.

[0115] In block 511, method 500 may include acting the lower electrode subassembly 204 to a process position. In some embodiments, a stage 206 associated with the lower electrode subassembly 204 (e.g., as shown in Figures 2 and 2A) may be configured to actuate the lower electrode subassembly 204 in the z direction. For example, the stage 206 may raise the lower electrode subassembly 204 to a process position such that the lower hydrostatic gas bearing surface 296 is very close to the substrate with a gap of 100 microns or less. Actuating the lower hydrostatic gas bearing gas 290 in block 510 may be performed before actinguating the lower electrode subassembly 204 to prevent contact between the substrate 210 and the lower hydrostatic gas bearing surface 296. In some cases, the upper electrode subassembly 202 may also be lowered or raised.

[0116] In block 512, method 500 may include spinning the semiconductor substrate 210. In some embodiments, the chuck 213 may be configured to rotate while holding the semiconductor substrate 210 in place. The spinning may be part of processing the substrate 210, for example, via an EBR in which the edges of the substrate 210 are etched while the substrate 210 is spinning.

[0117] To that end, in block 513, method 500 may include generating a plasma and processing the semiconductor substrate 210 with the plasma. In some embodiments, direct plasma generation at atmospheric pressure may be used. That is, RF power may be applied to the upper and lower electrodes 203,205 on both sides of the substrate 210, thereby generating plasma radicals directly at the edges of the substrate 210, as shown in Figure 2E. In some implementations, the plasma pressure may be a percentage of atmospheric pressure (e.g., at least about 200 Torr or at least about 300 Torr).

[0118] Advantageously, as described elsewhere in this specification, the hydrostatic gas bearing gas may provide an inert gas curtain to stabilize the rotation of the substrate and prevent plasma radicals from reaching parts of the substrate 210 other than the edges. Further confinement of the etchant plasma to the wafer edge may be a small process volume 255 combined with one or more confinement racks 252 and / or 253. These factors may result in a lean, high etching rate (e.g., about or at least about 1 mm / min) due to recombination 221 during transport (as may occur in the indirect plasma generation scheme of Figure 2D where RF power is applied to one of the electrodes (e.g., the upper electrode 203)).

[0119] In block 514, method 500 may include, for example, stopping the generation of plasma when the process is completed or paused.

[0120] In block 515, method 500 may include, for example, stopping the rotation of the semiconductor substrate when processing is completed or paused.

[0121] In block 516, method 500 may include lowering the lower electrode subassembly 204.

[0122] In block 517, method 500 may include lowering the semiconductor substrate 210 onto one or more pins. In some embodiments, the chuck 213 may be stopped to remove the vacuum from the processed substrate 210.

[0123] Figure 6 is a flowchart showing a method 600 for processing a semiconductor substrate according to several embodiments. The substrate has a front side, which may have electronic device features fabricated thereon. One or more blocks of method 600 may be implemented by or caused by an apparatus or system controlled by a computing device. Such a system may include, as described above, one or more electrodes, an RF power supply, and / or various hardware components such as actuators (e.g., stages, aligners). Structures for implementing the functions shown in one or more of the blocks shown in Figure 6 may include hardware and / or software components of such an apparatus or system, or computing devices such as a controller or computer-readable device that includes a storage medium for storing computer-readable instructions and / or computer-executable instructions configured to cause a processor device to perform an operation when executed by a processor device. Illustrative components of the apparatus or system are described below with respect to Figure 7.

[0124] It should also be noted that the operations of Method 600 may be performed in any suitable order, not necessarily in the order shown in Figure 6. Furthermore, Method 600 may include additional or fewer operations than those shown in Figure 6 for processing the semiconductor substrate.

[0125] In block 610, method 600 may include acting a first hydrostatic bearing gas through a first surface of the first electrode subassembly. In some embodiments, the upper electrode subassembly 202 may be an example of the first electrode subassembly, and the upper hydrostatic bearing surface 276 may be an example of the first surface of the first electrode subassembly. In some implementations, the first electrode subassembly may not necessarily refer to all components of the upper electrode subassembly 202 as shown in Figures 2J and 2L, but may refer to its parts such as the upper hydrostatic bearing gas path 271, the upper hydrostatic bearing gas manifold 272, the upper hydrostatic bearing orifice array 274, and / or the dielectric shield 260. In some embodiments, the upper hydrostatic bearing gas 270 may be an example of the first hydrostatic bearing gas.

[0126] In block 620, method 600 may include receiving a semiconductor substrate between a first surface of a first electrode subassembly and a second surface of a second electrode subassembly located on the opposite side of the first electrode assembly. In some embodiments, receiving the semiconductor substrate may be performed after activating the first hydrostatic bearing gas. In some embodiments, the lower electrode subassembly 204 may be an example of the second electrode subassembly, and the lower hydrostatic bearing surface 296 may be an example of the second surface of the second electrode subassembly. In some implementations, the second electrode subassembly may not necessarily refer to all components of the lower electrode subassembly 204 as shown in Figures 2K and 2L, but may refer to its parts such as the lower hydrostatic bearing gas path 291, the lower hydrostatic bearing gas manifold 292, the lower hydrostatic bearing orifice array 294, and / or the dielectric barrier 258. In some embodiments, the lower hydrostatic bearing gas 290 may be an example of the second hydrostatic bearing gas.

[0127] In some embodiments, the semiconductor substrate (e.g., semiconductor substrate 210) may be accepted using at least some of the process steps described with respect to Figures 4A to 4D, or some parts of the method 500 described with respect to Figure 5. For example, vacuum chucking may be used to firmly hold the semiconductor substrate as it moves in the x, y and / or z directions relative to the first and second electrode subassemblies.

[0128] In block 630, method 600 may include acting a second hydrostatic bearing gas through the second surface. In some embodiments, acting the second hydrostatic bearing gas may be performed after the semiconductor substrate has been accepted.

[0129] In block 640, method 600 may include moving a second electrode assembly to create rigidity between the semiconductor substrate and the first and second surfaces. In some embodiments, for example, rigidity may be created between the semiconductor substrate and the first surface that is substantially equal to the rigidity created between the semiconductor substrate and the second surface, so as to keep the semiconductor substrate flat while the semiconductor substrate is spinning. The rigidity and substantially constant gap between the substrate and the first and second surfaces may arise from the balance between substantially equal opposing forces (e.g., from substantially equal opposing flows of the first and second hydrostatic gas bearing gases) and the upper and lower hydrostatic gas bearings.

[0130] In some embodiments, the movement of the second electrode assembly may occur after the activation of the second hydrostatic gas bearing gas. In some cases, block 640 may correspond to a process step 411 in which the second electrode assembly rises toward the semiconductor substrate while the first and second hydrostatic gas bearing gases are acting.

[0131] In some implementations, for example, to conserve gas supply or output, the first and / or second hydrostatic bearing gases may be at a low initial flow rate before the semiconductor substrate is sufficiently close to the first and second surfaces. For example, the threshold distance between the semiconductor substrate and the first surface, and / or the threshold distance between the semiconductor substrate and the second surface, may be conditions that increase the flow rate. In some implementations, such threshold distances may be greater than the resulting gap between the semiconductor substrate and the first and second surfaces, for example, the threshold may be greater than 100 microns.

[0132] In block 650, method 600 may include processing the edge portions of a semiconductor substrate using plasma generated by the first and second electrode subassemblies. In some embodiments, processing the edge portions of the semiconductor substrate may include etching the edge portions while the semiconductor substrate is spinning. As described elsewhere in this specification, the semiconductor substrate may be rotated via an aligner or other movable stage. For example, a chuck 213 coupled to an aligner 212 may be used to fix the substrate in place and rotate it (for example, at a rotational speed of 60 to 120 revolutions per minute). In some embodiments, the plasma may be generated by applying RF power to the respective electrodes of the first and second electrode subassemblies. The upper electrode 203 and the lower electrode 205 may be examples of the respective electrodes, and may be positioned opposite each other at opposing edges of the substrate, for example.

[0133] Direct plasma generation may be performed at the edges of the substrate itself (for example, by igniting a process gas such as oxygen), or plasma radicals may be generated directly at the edge portion, thereby causing the substrate to spin and resulting in etching of the edge portion. The hydrostatic bearing provided by the first and second hydrostatic bearing gases can stabilize the substrate spin (for example, causing wafer planarization). The first and second hydrostatic bearing gases (in some implementations, in conjunction with one or more confinement shelves 252, 253) may further function to prevent plasma flow away from the edge portion towards the center of the substrate where processing is undesirable. The combination of the above features (present in the material removal systems described herein) can advantageously result in a high etching rate of the edges of the semiconductor substrate.

[0134] Device-Computer and Controller Embodiments Figure 7 shows a simplified block diagram of an APPJ-based material removal system or apparatus 700 described herein, which may include at least one subassembly 710, at least one actuator 720 (e.g., a chuck, an aligner), and at least one controller device 730 coupled to the subassembly 710 and / or the actuator 720. In some embodiments, the subassembly 710 may include one or more subassemblies, an example of which includes an upper subassembly and a lower subassembly (e.g., an upper electrode and a lower electrode) having one or more electrodes 712, respectively. Thus, at least one controller device 730 may be configured to be coupled to one or more electrodes 712. At least one controller device 730 may also be configured to be coupled to an external RF power supply 721. The controller 730 may use an internal RF power supply 719 and / or an external RF power supply 721 to power at least the components of the subassembly 710 and / or the actuator 720. In some embodiments, the subassembly 710 may further include one or more gas inlets (or inlet lines) 714. An example of a gas inlet 714 may include a first gas inlet for supplying process gas (and / or curtain gas) and / or a second gas inlet for supplying purge gas. The inlets 714 may be configured to deliver gas and / or plasma from a source to the outlet of the nozzle 716. The axis of the nozzle 716 may be at any angle with respect to a plane parallel to the substrate, and the angle is adjustable between orthogonal and non-orthogonal (angled). In some embodiments, while the substrate 702 is positioned in close proximity to a portion of the subassembly 710 (for example, between the upper and lower electrode assemblies, which have a small gap above the substrate 702 for the flow of purge gas or hydrostatic bearing gas), the actuator 720 may include a chuck (e.g., a vacuum chuck, an electrostatic clamp) and / or an aligner configured to hold, move (e.g., along XYZR-θ), and / or rotate the substrate 702.In some embodiments, the actuator 720 may include a stage (e.g., XYZ) configured to actuate at least a portion of the subassembly 710. For example, the aligner may move the substrate 702 in the XYZ directions into the space between an upper or lower assembly that holds the substrate 702 and is vertically movable to receive the substrate 702, according to the mounting configuration described herein.

[0135] In some embodiments, the subassembly 710 may include at least one nozzle 716, which is at least partially housed by the subassembly 710 or at least partially housed by a nozzle housing that can be at least partially housed within the subassembly 710. The nozzle 716 may be configured to guide a plasma jet into a process volume in which a portion of the substrate 702 is positioned, thereby etching and removing material on the edges of the substrate 702, for example. The actuator 720 may be configured to adjust the position of the substrate 702 relative to the nozzle 716 during etching, and the controller 730 may be configured to control an internal RF power supply 719 and / or an external RF power supply 721 to power, for example, a plasma source 718 to generate plasma radicals that etch the substrate edges. The plasma source 718 may be a direct plasma source (for example, capable of applying RF power to upper and lower electrodes) or an indirect plasma source (for example, capable of applying RF power to the upper electrode).

[0136] In some embodiments, the subassembly 710 may include one or more hydrostatic gas bearing components 717. Examples of these components may include an upper hydrostatic gas bearing gas manifold 272, an upper hydrostatic gas bearing seal 273, an upper hydrostatic gas bearing orifice array 274, an upper hydrostatic gas bearing surface 276, a lower hydrostatic gas bearing gas manifold 292, an upper hydrostatic gas bearing seal 293, a lower hydrostatic gas bearing orifice array 294, and / or a lower hydrostatic gas bearing surface 296. As described herein, these hydrostatic gas bearing components 717 may be collectively configured to supply gas (e.g., upper hydrostatic gas bearing gas 270, lower hydrostatic gas bearing gas 290) to provide hydrostatic gas bearings on the substrate being processed.

[0137] The apparatus 700 may be configured to implement the methods 500 and 600 described above using one or more of the components 710 to 730 described above. In some embodiments, the operation of the apparatus 700 may include generating and / or transferring plasma radicals from the plasma source 718 at approximately atmospheric pressure or a percentage thereof (e.g., at least about 200 to 300 Torre), and may improve the etching of a portion or edge of the substrate 702 with a purge gas and / or a static gas bearing gas. The apparatus 700 enables an etching rate of several microns / minute for material removal around the edges of the entire wafer edge, in accordance with throughput requirements.

[0138] In various configurations, the controller 730 may be further configured to adjust one or more process conditions during the operation of the apparatus 700. Process conditions may include the rotational speed of the substrate 702 using the actuator 720, the position and / or angle associated with the nozzle 716, the RF power of the RF power supply 719, the plasma power associated with the plasma jet of the nozzle 716, the plasma frequency associated with the plasma jet of the nozzle 716, the residence time of the plasma jet at a position on the substrate, the gas flow rate, the gas composition, the gas pressure, or any combination thereof. In some cases, the controller 730 may be configured to adjust the plasma power during a single rotation of the substrate 702. In some cases, the controller 730 may be configured to repeatedly adjust (e.g., high / low or on / off) the plasma power over a number of rotations of the substrate 702.

[0139] In some implementations, the actuator 720 may be configured to rotate the substrate 702 during EBR / etching of the substrate edge. The actuator 720 may also be configured to translate the substrate 702 (e.g., along the x and / or y axes) along a plane parallel to the substrate or along a plane perpendicular to the plane parallel to the substrate (e.g., the z-axis), or to move the substrate radially relative to the substrate. Depending on the application, the rotation speed of the substrate may be 60 to 120 revolutions per minute. In one example, the rotation speed may be about 100 revolutions per minute. The actuator 720 may also be configured to result in rasterized deposition of material. The actuator 720 may also be configured to maintain a small gap between the substrate and the surface of the subassembly 710 during etching, and the gap may be about 0 to 100 microns.

[0140] This disclosure may be described in the general context of computer code or machine-usable instructions, including computer-executable instructions such as program modules, which are executed by computers or other machines, such as personal data assistants or other handheld devices. Generally, a program module, which includes routines, programs, objects, components, data structures, etc., refers to code that performs a particular task or implements a particular abstract data type. This disclosure may be implemented in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, and specialized computing devices. This disclosure may also be implemented in a distributed computing environment where tasks are performed by remote processing devices linked through a communication network.

[0141] In some implementations, the “controller” (e.g., 190) is part of a system including various types of sensors as described herein. Such a system includes a fabrication tool having a camera sensor. Such a system may include a semiconductor processing apparatus including one or more process tools, one or more chambers, one or more platforms for processing, and / or specific processing components (such as a wafer pedestal, a gas flow system). These systems may be integrated with electronics for controlling pre-processing, in-processing, and post-processing operations of a semiconductor wafer or substrate. The controller may be implemented in analytical logic as described above, or coupled thereto. The controller may be implemented as logic, such as electronics having one or more integrated circuits, memory devices, and / or software that receive commands, issue commands, control operations, and / or enable sensing operations.

[0142] Electronic devices that can control various components or sub-parts of one or more systems may be referred to as “controllers.” Depending on the processing requirements and / or the type of system, a controller may be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, transfer of wafers to and from tools and other transfer tools, and / or load locks connected to or interfaced with a particular system.

[0143] Generally speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurement, etc. Integrated circuits may include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers (e.g., software) that execute program instructions. Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on a semiconductor wafer or system. In some embodiments, operating parameters may be part of a recipe defined by a process engineer to achieve one or more process steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0144] The controller may be configured to control or cause control of various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the following: process which may be used by the fabrication tool during fabrication operations, including adjusting or maintaining the delivery of process gas; temperature settings (e.g., heating and / or cooling), including substrate temperature and chamber wall temperature; pressure settings, including vacuum settings; plasma settings; RF matching circuit settings; and substrate position and movement settings, including the entry and exit of the substrate to and from the fabrication tool and / or load lock. Process gas parameters include process gas composition, flow rate, temperature, and / or pressure. Particularly in relation to the disclosed embodiments, controller parameters may also relate to the power, pulse rate, and / or RF frequency of the plasma generator.

[0145] Process parameters under the controller's control may be provided in the form of a recipe or entered using a user interface. Signals for monitoring the process may be provided by the system controller's analog and / or digital input connections. Signals for controlling the process are output to the depositor's analog and digital output connections.

[0146] In one example, instructions for igniting or maintaining a plasma are provided in the form of process recipes. The relevant process recipes may be arranged sequentially, so that at least some instructions for the process can be executed simultaneously. In some implementations, instructions for setting one or more plasma parameters may be included in a recipe preceding the plasma ignition process. For example, a first recipe may include instructions for a first time delay, instructions for setting the flow rates of the inert gas and / or reactive gas, and instructions for setting the plasma generator to a first power setpoint. A second subsequent recipe may include instructions for a second time delay and instructions for enabling the plasma generator to supply power under a defined set of parameters. A third recipe may include instructions for a third time delay and instructions for deactivating the plasma generator. It will be understood that these recipes may be further subdivided and / or repeated in any preferred manner within the scope of this disclosure. In some deposition processes, the duration of the plasma strike may correspond to a few seconds, such as about 3 to 15 seconds, or it may include longer durations, such as up to about 30 seconds. In certain implementations described herein, much shorter plasma strikes may be applied during the processing cycle. Such plasma strike durations may be less than about 50 milliseconds, and in certain examples, about 25 milliseconds are utilized. As described, the plasma may be pulsed.

[0147] In some embodiments, the controller is configured to control and / or manage the operation of the RF signal generator. In certain implementations, the controller is configured to determine upper and / or lower thresholds for the RF signal power sent to the fabrication tool, the actual (such as real-time) level of the RF signal power sent to the integrated circuit fabrication chamber, the RF signal output activation / deactivation time, the RF signal modulation duration (e.g., high / low or on / off state), the duty cycle, the operating frequency, and so on.

[0148] As a further example, the controller may be configured to control the timing of various operations, gas mixing, pressure within the fabrication tool, temperature within the fabrication tool, temperature of the substrate or pedestal, position of the pedestal, chuck and / or susceptor, and the number of cycles performed on one or more substrates.

[0149] The controller may include one or more programs or routines for controlling designed subsystems related to the fabrication tool. Examples of such programs or routines include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program. The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal and control the spacing between the substrate and other parts of the fabrication tool. The positioning program may also include instructions for moving the substrate in and out of the reaction chamber to deposit a film on the substrate and to clean the chamber.

[0150] The process gas control program may include code for controlling the gas composition and flow rate, as well as code for introducing gas into one or more process stations before deposition to stabilize the pressure within the process stations. In some implementations, the process gas control program includes instructions for introducing gas during film formation on substrates within the reaction chamber. This may include introducing a different number of cycles of gas to one or more substrates in a batch of substrates. The pressure control program may include code for controlling the pressure within the process stations by, for example, adjusting throttle valves in the exhaust system of the process stations, gas flow to the process stations, etc. The pressure control program may include instructions for maintaining the same pressure while depositing a different number of cycles on one or more substrates during batch processing.

[0151] The heater control program may include code for controlling the current to the heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0152] In some implementations, there may be a user interface associated with the controller. The user interface may include a display screen, a graphical software display and / or processing conditions for the device, as well as user input devices such as a pointing device, keyboard, touch screen, and microphone.

[0153] In some implementations, the controller may be part of, or coupled to, a computer integrated with, coupled to, networked to, or in some way networked to, the system. For example, the controller may be all or part of a “cloud” or fab-host computer system, enabling remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of processing operations, examine the history of past processing operations, examine trends or performance metrics from multiple processing operations, modify parameters of the current processing, set process steps to follow the current processing, or initiate new processing. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying the parameters of each process step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Therefore, as described above, the controllers may be distributed, for example, by comprising one or more individual controllers that are networked together and operate toward a common purpose, such as the processes and control described herein. An example of a distributed controller for such purposes may be one or more integrated circuits on a chamber that communicate with one or more remotely located integrated circuits (such as platform-level or part of a remote computer) that are combined to control the processes on the chamber.

[0154] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems related to or usable in the processing and / or manufacturing of semiconductor wafers.

[0155] The system software can be organized in many different ways, which may have various architectures. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary for the execution of the deposition process (and possibly other processes) according to the disclosed embodiments.

[0156] As described above, depending on one or more process steps performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transfer to carry wafer containers to and from tool locations and / or load ports in the semiconductor manufacturing plant.

[0157] Various modifications to the implementations described herein will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Accordingly, the claims are not intended to be limited to the implementations shown herein, but should be given the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0158] Certain features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any appropriate partial combination in multiple implementations. Furthermore, features may be described above as acting in a particular combination, and a patent may be claimed as such initially, although one or more features from the claimed combination may, in some cases, be removed from the combination, and the claimed combination may cover a partial combination or a variation of a partial combination.

[0159] Similarly, while the operations are shown in a specific order in the diagrams, this should not be understood as requiring that such operations be performed in that specific order, or in a sequential order, or that all of the operations shown be performed, in order to achieve the desired result. Furthermore, the diagrams may schematically illustrate another exemplary process in the form of a flow chart. However, other operations not illustrated can be incorporated into the schematicly illustrated exemplary process. For example, one or more additional operations can be performed before, after, simultaneously with, or in between any of the illustrated operations. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products. Furthermore, other implementations are within the scope of the following claims. In some cases, the operations described in the claims can be performed in a different order, and the desired result can still be achieved. [Explanation of Symbols]

[0160] 100 Material removal system, 101 Source subassembly, 102 Semiconductor substrate, 102-e Edge, 102-i Inner portion, 104 Upper subassembly, 106 Lower subassembly, 108 Plasma source, 110 Aligner hardware, 111 Direction, 112 Stage, 114 Central axis, 137 Third channel, 200 Material removal system, 202 Upper electrode subassembly, 203 Upper electrode, 204 Lower electrode subassembly, 205 Lower electrode, 206 Stage, 208 Plasma source, 210 Semiconductor substrate, 212 Aligner, 213 Chuck, 214 Pin, 215 Alignment sensor, 221 Recombination, 231 First inlet, 232 Second inlet, 233 First electrode, 234 Second electrode, 235 First channel, 236 Second channel, 238 Dielectric material, 239 Nozzle, 242 First opening, 243 Second opening, 250 Tip section, 252 Confinement shelf section, 253 Additional confinement shelf section, 254 Process gas, 255 Process volume, 256 Purge gas, 257 Opening, 258 Dielectric barrier, 259 Upper gap, 260 Dielectric shield, 261 Lower gap, 262 Region, 264 Bracket, 266 Upper electrode mount, 268a Cooling plate, 268b Cooling plate, 270 Upper hydrostatic gas bearing gas, 271 Upper hydrostatic gas bearing gas path, 272 Upper hydrostatic gas bearing gas manifold, 273 Upper hydrostatic gas bearing seal, 274 Upper hydrostatic gas bearing orifice array, 274a Upper hydrostatic gas bearing orifice, 276 Upper hydrostatic gas bearing surface, 277 Upper hydrostatic gas bearing pad, 278 Clamp feature, 280 Tip, 286 Lower electrode mount, 290 Lower hydrostatic gas bearing gas, 291 Lower hydrostatic gas bearing gas path, 292 Lower hydrostatic gas bearing gas manifold, 293 Lower hydrostatic gas bearing seal, 294 Lower hydrostatic gas bearing orifice array, 294a Lower hydrostatic gas bearing orifice, 296 Lower hydrostatic gas bearing surface, 297 Lower hydrostatic gas bearing pad, 298 Clamp mechanism, 302 Semiconductor substrate, 304 Range, 306 Untreated area, 308 Etched area, 310 Edge, 320 Processing area, 500 Method, 600 Method, 700 Material removal system or apparatus, 702 Substrate, 710 Subassembly, 712Electrode, 714 Gas inlet, 716 Nozzle, 717 Static gas bearing component, 718 Plasma source, 719 Internal RF power supply, 720 Actuator, 721 External RF power supply, 730 Controller device

Claims

1. An apparatus configured to process a semiconductor substrate, wherein the apparatus is A first subassembly comprising a first surface, a first electrode, and a first orifice, A second subassembly comprising a second surface, a second electrode, and a second orifice, wherein the second surface is positioned opposite the first surface to form a region between the first subassembly and the second subassembly that is sized to accept the semiconductor substrate. Equipped with, In the first configuration, a first hydrostatic bearing gas flows through the first orifice, and a second hydrostatic bearing gas flows through the second orifice, creating a rigidity between the semiconductor substrate and the first surface, and substantially equal rigidity between the semiconductor substrate and the second surface. The semiconductor substrate is configured such that, while the semiconductor substrate is rotating relative to the first and second subassemblies, the first and second electrodes generate plasma that is applied to the edge portion of the semiconductor substrate. Device.

2. The apparatus according to claim 1, wherein a hydrostatic gas bearing is located between the first surface and the semiconductor substrate based on the first hydrostatic gas bearing gas, and a hydrostatic gas bearing is located between the second surface and the semiconductor substrate based on the second hydrostatic gas bearing gas product.

3. The apparatus according to claim 1, wherein, in the first configuration, the first subassembly is positioned at a first distance with respect to the semiconductor substrate, and the second subassembly is positioned at a second distance substantially equal to the first distance with respect to the semiconductor substrate.

4. The apparatus according to claim 3, wherein the first distance creates a first gap of 100 microns or less between the first surface and the semiconductor substrate, and the second distance creates a second gap of 100 microns or less between the second surface and the semiconductor substrate.

5. The apparatus according to claim 3, wherein, in the first configuration, in order to position the first subassembly and the second subassembly, the first subassembly is lowered toward the semiconductor substrate using a movable stage, and the second subassembly is raised toward the semiconductor substrate using the movable stage.

6. In the first configuration, the semiconductor substrate is received in the region between the first surface and the second surface and fixed by a vacuum chuck coupled to a movable stage. The axis of the semiconductor substrate coincides with the axis of the vacuum chuck. The apparatus according to claim 1.

7. The apparatus according to claim 1, wherein, in the second configuration, the hydrostatic gas bearing gas does not flow through the first orifice or the second orifice.

8. The apparatus according to claim 1, wherein the first subassembly further comprises one or more shelf features configured to confine the generated plasma to a region in which the semiconductor substrate is exposed to the plasma when the first subassembly is in the first configuration.

9. The apparatus according to claim 8, wherein the confinement of the generated plasma within the region includes the step of preventing the generated plasma from diffusing to portions of the semiconductor substrate other than the edge portions by using at least one or more shelf features and the flow of the first hydrostatic gas bearing gas.

10. The first subassembly further comprises a plurality of first orifices, each of which is configured to release the first hydrostatic gas bearing gas. The second subassembly further comprises a plurality of second orifices, each of which is configured to release the second hydrostatic gas bearing gas. The apparatus according to claim 1.

11. The apparatus according to claim 1, wherein the first flow rate of the first hydrostatic bearing gas flowing through the first orifice is in the range of 0.1 to 100 standard liters / minute (slm), and the second flow rate of the second hydrostatic bearing gas flowing through the second orifice is in the range of 0.1 to 100 slm, and the first and second flow rates are substantially equal.

12. A system configured to process a semiconductor substrate, wherein the system An upper electrode subassembly comprising an upper surface, an upper electrode, and an upper hydrostatic gas bearing orifice, A lower electrode subassembly comprising a lower surface, a lower electrode, and a lower hydrostatic gas bearing orifice, wherein the lower surface is positioned opposite the upper surface to form a region sized to receive the semiconductor substrate between the upper subassembly and the lower subassembly, A stage assembly having multiple degrees of freedom, configured to move the semiconductor substrate to the region by at least the first degree of freedom, Equipped with, In the first configuration, the upper hydrostatic bearing gas flows through the upper hydrostatic bearing orifice, and the lower hydrostatic bearing gas flows through the lower hydrostatic bearing orifice, creating rigidity between the semiconductor substrate and the upper surface, and rigidity between the semiconductor substrate and the lower surface. While the stage assembly is realizing a second degree of freedom on the semiconductor substrate, the upper and lower electrodes are configured to generate plasma applied to the edge portion of the semiconductor substrate. system.

13. The system according to claim 12, wherein the first degree of freedom includes translation and the second degree of freedom includes rotation.

14. The system according to claim 12, wherein a hydrostatic gas bearing is located between the upper surface and the semiconductor substrate based on the upper hydrostatic gas bearing gas, and a hydrostatic gas bearing is located between the lower surface and the semiconductor substrate based on the lower hydrostatic gas bearing gas.

15. The system according to claim 12, wherein, in the first configuration, the upper electrode subassembly is positioned at a first distance of 100 microns or less from the semiconductor substrate, and the lower electrode subassembly is positioned at a second distance of 100 microns or less from the semiconductor substrate, and the first distance is substantially equal to the second distance.

16. The system further comprises a first movable stage coupled to the upper and lower electrode subassemblies, and a second movable stage separate from the first movable stage. The lower electrode subassembly is configured to rise toward the semiconductor substrate using the first movable stage, In the first configuration described above, in order to receive the semiconductor substrate within the region, the semiconductor substrate is fixed by a vacuum chuck coupled to the second movable stage. The system according to claim 12.

17. A method for processing a semiconductor substrate, wherein the method is The steps include acting a first hydrostatic bearing gas through a first surface of a first electrode subassembly, The steps include, after the step of activating the first hydrostatic gas bearing gas, receiving the semiconductor substrate between the first surface of the first electrode subassembly and the second surface of the second electrode subassembly located on the opposite side of the first electrode subassembly, The steps include, after receiving the semiconductor substrate, activating a second hydrostatic bearing gas through the second surface, The steps include: after the step of activating the second hydrostatic gas bearing gas, moving the second electrode subassembly to create rigidity between the semiconductor substrate and the first and second surfaces; The steps include processing the edge portion of the semiconductor substrate using the plasma generated by the first and second electrode subassemblies, and Methods that include...

18. The first electrode subassembly comprises a first electrode, and the second electrode subassembly comprises a second electrode. The method further includes the step of generating the plasma using the first and second electrodes while the semiconductor substrate is between the first surface and the second surface. The method according to claim 17.

19. The method according to claim 17, wherein the step of processing the edge portion of the semiconductor substrate includes the step of etching the edge portion while the semiconductor substrate is spinning.

20. The first electrode subassembly comprises one or more shelf features configured to confine the generated plasma to a region in which the semiconductor substrate is exposed to the plasma, The step of processing the edge portion of the semiconductor substrate includes the step of confining the plasma generated using one or more shelf features of the first electrode subassembly within the region, The step of confining the generated plasma within the region includes the step of preventing the generated plasma from diffusing to portions of the semiconductor substrate other than the edge portions by using at least one or more shelf features and the flow of the first hydrostatic gas bearing gas, The method according to claim 17.

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