Interconnect structure with overlapping metal vias

Abstract

The interconnect structure comprises a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first and second via metallization layers, the first metallization layer having a first metal wiring and a second metal wiring. The first metal via is disposed on the first metal wiring, and the second metal via is disposed on the second metal wiring. The second metal via is configured to overlap the first metal via.

Description

[Background technology]

[0001] This field relates to semiconductors, and more specifically, to techniques for forming interconnect structures. Generally, semiconductor devices may include multiple circuits that form integrated circuits fabricated on a substrate. A complex network of signal paths can be wired to connect circuit elements distributed on the surface of the substrate. Efficient wiring of these signals may involve forming multi-stage or multi-layer schemes (e.g., single or dual damascene wiring structures) during the back-end-of-line (BEOL) phase of manufacturing. For example, semiconductor devices provide electronic interconnects between integrated circuits on a substrate by relying on multiple metallization layers or metal wirings stacked on top of each other on a semiconductor substrate. Metallization layers may also be referred to as BEOL metallization layers that can be placed on a semiconductor material stack. Semiconductor contacts in the uppermost layer of the semiconductor material stack are electrically connected to metal contacts and metal interconnects in the metallization layers placed on the semiconductor material stack. [Overview of the project]

[0002] Exemplary embodiments of the present application include techniques for use in semiconductor manufacturing. In the exemplary embodiments, the interconnect structure comprises a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first and second via metallization layers. The first metallization layer has a first metal wiring and a second metal wiring. The first metal via is disposed on the first metal wiring, and the second metal via is disposed on the second metal wiring. The second metal via is configured to overlap the first metal via.

[0003] The interconnect structure of the exemplary embodiment is advantageous in that the area is significantly reduced, and as a result the overall dimensions are reduced, by forming the metal vias of the second via metallization layer in a configuration that overlaps with the metal vias of the first via metallization layer. The overlapping configuration further comprises forming a metallization layer having a first metal wiring and a second metal wiring between the first via metallization layer and the second via metallization layer, where the first metal via is located on the first metal wiring and the second metal via is located on the second metal wiring.

[0004] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first via metallization layer is located within the dielectric layer.

[0005] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, a second via metallization layer is further disposed within the dielectric layer.

[0006] In one or more additional exemplary embodiments that may be combined with the preceding paragraph, the upper surface of the first metal via is in contact with the lower surface of the first metal wiring, and the lower surface of the second metal via is in contact with the upper surface of the second metal wiring.

[0007] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the first via metallization layer is located on a second metallization layer having a first plurality of metal wirings, wherein a predetermined one of the first plurality of metal wirings is in contact with the first metal via.

[0008] In one or more additional exemplary embodiments that may be combined with the preceding paragraphs, the interconnect structure further comprises a third metallization layer disposed on the second via metallization layer, the third metallization layer having a second plurality of metal wirings, wherein a predetermined one of the second plurality of metal wirings is in contact with the second metal via.

[0009] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0010] According to another exemplary embodiment, an interconnect structure includes a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer. The first metallization layer has a first metal wiring having a first sidewall forming a first taper angle and a second metal wiring having a second sidewall forming a second taper angle. The first metal via is disposed at a first outer edge portion of the first sidewall of the first metal wiring. The second metal via is disposed at a second outer edge portion of the second sidewall of the second metal wiring. The second metal via is configured to overlap the first metal via.

[0011] Advantageously, the interconnect structure of the exemplary embodiment is formed such that the metal vias of the second via metallization layer overlap the metal vias of the first via metallization layer, resulting in a significantly reduced area and, as a result, a reduced overall dimension. The overlapping configuration further includes forming a metallization layer having a first metal wiring and a second metal wiring between the first via metallization layer and the second via metallization layer, where the first metal via is disposed on the first metal wiring and the second metal via is disposed on the second metal wiring.

[0012] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the first taper angle is the same as the second taper angle.

[0013] In one or more additional exemplary embodiments that may be combined with the foregoing paragraphs, the first via metallization layer is disposed on a second metallization layer having a first plurality of metal wirings, and a predetermined one of the first plurality of metal wirings is in contact with the first metal via.

[0014] In one or more additional exemplary embodiments that may be combined with the foregoing paragraphs, the interconnect structure further comprises a third metallization layer disposed on the second via metallization layer, the third metallization layer having a second plurality of metal wirings, wherein a predetermined one of the second plurality of metal wirings is in contact with the second metal via.

[0015] In one or more additional exemplary embodiments that may be combined with the foregoing paragraphs, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0016] In one or more additional exemplary embodiments that may be combined with the foregoing paragraphs, the first via metallization layer is disposed within a dielectric layer.

[0017] In one or more additional exemplary embodiments that may be combined with the foregoing paragraphs, the first metallization layer and the second via metallization layer are further disposed within the dielectric layer.

[0018] Another exemplary embodiment includes an integrated circuit having one or more interconnect structures. At least one of the one or more interconnect structures is an interconnect structure according to one or more of the above exemplary embodiments.

[0019] The integrated circuit of the exemplary embodiment is advantageous in that the area is significantly reduced, and as a result, the overall dimensions of the interconnect structure are reduced, by forming the metal vias of the second via metallization layer in a configuration that overlaps with the metal vias of the first via metallization layer. The overlapping configuration further comprises forming a metallization layer having a first metal wiring and a second metal wiring between the first via metallization layer and the second via metallization layer, where the first metal via is located on the first metal wiring and the second metal via is located on the second metal wiring.

[0020] In a further exemplary embodiment, the method comprises the steps of: forming a first via metallization layer having at least a first metal via; forming a metallization layer having a first metal wiring and a second metal wiring on the first via metallization layer, wherein the first metal wiring is arranged on the first metal via; and forming a second via metallization layer having at least a second metal via on the metallization layer, wherein the second metal via is arranged on the second metal wiring, the second metal via overlapping the first metal via.

[0021] The method of the exemplary embodiment also advantageously allows the metal vias of the second via metallization layer to be formed in a configuration that overlaps with the metal vias of the first via metallization layer, thereby resulting in an interconnect structure with a significantly reduced area and overall dimensions. The overlapping configuration further comprises forming a metallization layer having a first metal wiring and a second metal wiring between the first via metallization layer and the second via metallization layer, where the first metal via is located on the first metal wiring and the second metal via is located on the second metal wiring.

[0022] In a further exemplary embodiment, the method comprises the steps of: forming a first via metallization layer having at least a first metal via; depositing a conductive metal layer on the first via metallization layer; performing oblique ion beam etching on the conductive metal layer to form a metallization layer having a first metal wiring having a first sidewall with a first taper angle and a second metal wiring having a second sidewall with a second taper angle; and forming a second via metallization layer having at least a second metal via on the metallization layer. The first metal via is located at the first outer edge of the first sidewall of the first metal wiring. The second metal via is located at the second outer edge of the second sidewall of the second metal wiring. The second metal via is configured to overlap with the first metal via.

[0023] The method of the exemplary embodiment also advantageously allows the metal vias of the second via metallization layer to be formed in a configuration that overlaps with the metal vias of the first via metallization layer, thereby resulting in an interconnect structure with a significantly reduced area and overall dimensions. The overlapping configuration further comprises forming a metallization layer having a first metal wiring and a second metal wiring between the first via metallization layer and the second via metallization layer, where the first metal via is located on the first metal wiring and the second metal via is located on the second metal wiring.

[0024] These and other exemplary embodiments will be described in or become apparent in the following detailed description of exemplary embodiments, which will be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0025] Exemplary embodiments are described in more detail below with reference to the accompanying drawings.

[0026] [Figure 1]This is a vertical cross-sectional view of an interconnect structure in a first intermediate fabrication step according to an exemplary embodiment.

[0027] [Figure 2] This is a vertical cross-sectional view of the interconnect structure in a second intermediate fabrication step according to an exemplary embodiment.

[0028] [Figure 3] This is a vertical cross-sectional view of the interconnect structure in a third intermediate fabrication step according to an exemplary embodiment.

[0029] [Figure 4] This is a vertical cross-sectional view of the interconnect structure in the fourth intermediate fabrication step according to an exemplary embodiment.

[0030] [Figure 5] This is a vertical cross-sectional view of the interconnect structure in the fifth intermediate fabrication step according to an exemplary embodiment.

[0031] [Figure 6] This is a vertical cross-sectional view of the interconnect structure in the sixth intermediate fabrication step according to an exemplary embodiment. [Modes for carrying out the invention]

[0032] This disclosure generally relates to semiconductor devices, and more specifically to interconnect structures having overlapping metal via structures, and methods for fabricating them. However, it should be understood that the embodiments of this disclosure are not limited to exemplary methods, apparatus, systems, and devices, but are instead more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0033] In integrated circuits, an interconnect is a structure that electrically connects two or more circuit elements (e.g., transistors or power rails). In addition to providing electrical connections to front-end devices (such as transistors), interconnects also extend back to the power supply network. Therefore, interconnects, and the supporting components around them, are considered back-end-of-line (BEOL) components. Wiring and vias are the most important components of interconnect technology. In physical electronic circuits, wiring provides electrical connections within a single layer, and vias provide electrical connections between layers.

[0034] As technology continues to scale and transistors become smaller, increasingly tightly spaced interconnects are required to connect them. This scaling of interconnects pushes the limits of minimum width, minimum spacing, and minimum pitch. However, these size reductions and density increases introduce performance and reliability issues. In particular, the limit dimensions refer to the size of electronic components that must be maintained to avoid undesirable effects on the electrical characteristics of the device. Therefore, the geometric properties of interconnect structures are limited not only by manufacturing constraints but also by performance constraints.

[0035] Currently, interconnect structures are at a certain level, for example, V x-1 vias on one level, and on another level, for example, V x They are formed using vias on a level, and these are not overlapping configurations. Therefore, the area of ​​the interconnect structure is significantly larger, and as a result, the overall dimensions are increased. The exemplary embodiments described herein are at a certain level (i.e., V x-1 vias on level (i.e., V) and vias on another level (i.e., V) x The aforementioned drawbacks are overcome by forming the vias on the level in an overlapping configuration. The interconnect structure therefore has a significantly smaller area, and as a result, the overall dimensions are reduced.

[0036] Detailed embodiments of interconnect structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits, such as semiconductor devices. These embodiments can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only commonly practiced process steps are included to the extent necessary for understanding the embodiments described. The figures represent cross-sectional portions of the fabricated semiconductor structures and are not drawn to scale, but are instead drawn to illustrate the features of the embodiments described. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as representative grounds to teach those skilled in the art to employ the methods and structures of this disclosure in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0037] References in the specification such as "one embodiment," "another embodiment," "a different embodiment," and "embodiment" indicate that the described embodiment may include certain features, structures, or characteristics, but not all embodiments necessarily include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to an embodiment, it is understood that their influence on other embodiments, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0038] For the purposes of the following description, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “upper,” “lower,” and their derivatives shall refer to the structures and methods disclosed as oriented in the drawings. The terms “on top,” “above,” “upward,” “on top,” “positioned above,” or “positioned above” mean that the first element is on the second element and that intervening elements, such as interface structures, may be present between the first and second elements. The term “direct contact” means that the first and second elements are connected at the interface of the two elements without any intervening conductive, insulating, or semiconductor layers.

[0039] In this specification, terms such as "first," "second," etc., may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Therefore, the first element described below may be called the second element without deviating from the scope of this concept.

[0040] As used herein, “height” refers to the vertical dimension of an element (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the bottom to the top of the element and / or measured relative to the surface on which the element is located. Conversely, “depth” refers to the vertical dimension of an element (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the top to the bottom of the element. Where indicated, terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “height.”

[0041] As used herein, “width” or “length” refers to the size of an element in a figure (e.g., a layer, trench, hole, opening, etc.) measured from one side of the element to the opposite surface. Where indicated, terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “width” or “length.”

[0042] To avoid obscuring the presentation of embodiments of this disclosure, some processing steps, materials, or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and in some cases may not be described in detail. In addition, for the sake of brevity and to maintain focus on the specific features of the elements of this disclosure, descriptions of materials, processes, and structures previously discussed may not be repeated with respect to the subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the invention.

[0043] Please understand that the various layers, structures, and / or regions shown in the attached drawings are schematic and not necessarily drawn to scale. In addition, for the sake of clarity, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not imply that any layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures.

[0044] Generally, the various processes used to form semiconductor chips are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently, atomic layer deposition ("ALD"). Another deposition technique is plasma-enhanced chemical vapor deposition ("PECVD"), which uses the energy in a plasma to induce reactions on the wafer surface that would otherwise require higher temperatures associated with conventional CVD. High-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0045] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for later transfer to a substrate. In semiconductor lithography, the pattern is formed using a photosensitive polymer called a photoresist. The pattern created by lithography or photolithography is typically used to define or protect selected surfaces and parts of the semiconductor structure during a subsequent etching process.

[0046] Removal is any process that removes material from a wafer, such as etching or chemical-mechanical planarization (CMP). Examples of etching processes include either wet (e.g., chemical) or dry etching processes. An example of a removal process or dry etching process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that removes substrate material using a remote broad-beam ion / plasma source and physically inert gas and / or chemically reactive gas means. Like other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etching process is reactive ion etching (RIE). Generally, RIE uses chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma collide with the wafer surface and react with the surface material to remove it.

[0047] Where used herein with respect to thickness, width, proportion, range, etc., the terms “about” or “substantially” are intended to indicate that the quantity is not exact but close or approximate. For example, where used herein, the terms “about” or “substantially” suggest that there may be a small margin of error, such as less than 1% of the stated quantity.

[0048] Referring here to drawings where the same reference numerals represent the same or similar elements, Figures 1 to 6 illustrate various processes for fabricating an interconnect with a variable via structure. Note that the same reference numeral (100) is used to indicate the semiconductor structure throughout the various intermediate fabrication steps shown in Figures 1 to 6. Note also that the interconnect structures described herein may also be considered semiconductor devices and / or integrated circuits, or parts thereof. For the purpose of clarity, some fabrication steps leading to the manufacture of interconnect structures as shown in Figures 1 to 6 have been omitted. In other words, one or more well-known processing steps that are not shown but are well-known to those skilled in the art are not included in the figures. This is not intended to be construed as limiting any particular embodiment, or example, or the scope of the claims.

[0049] Figure 1 shows a vertical cross-sectional view of the interconnect structure 100 in the first intermediate fabrication stage. During this stage, the first metallization layer M x-1 , the first via metallization layer V x-1 , and the second metallization layer M x However, these are formed on the substrate 102. In exemplary embodiments, the substrate 102 may include semiconductor materials such as silicon, germanium, silicon-germanium alloy, silicon-carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. Typically, semiconductor materials include silicon. The substrate 102 may include a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. In exemplary embodiments, the substrate 102 may already have pre-built structures (not shown) such as field-effect transistors, transistors, diodes, resistors, capacitors, inductors, interconnects, electrically programmable fuses, or any combination thereof.

[0050] The interconnect structure 100 has a first metallization layer M having a plurality of metal wirings 104a to 104f disposed on a substrate 102 x-1 (where x is an integer greater than or equal to 1), and a first via metallization layer V having at least one metal via 106 x-1 and further includes. The first via metallization layer V x-1 Although one metal via 106 for the first via metallization layer V is shown, this is merely an example, and it should be understood that any number of metal vias for the first via metallization layer V x-1 is contemplated. In an exemplary embodiment, a subtractive patterning process is used to form the metal wirings 104a to 104f and at least one metal via 106 within the interconnect structure.

[0051] For example, in performing a subtractive patterning process, first, a metal layer is deposited on the substrate 102. Next, using lithography and etching techniques, the metal layer is formed into individual metal wirings 104a to 104f for the first metallization layer M x-1 and the first via metallization layer V x-1At least one metal via 106 is patterned. In the lithography and etching process, a hard mask (not shown) having the footprints and positions of the metal wirings 104a-104f and at least one metal via 106 is patterned using a lithographic stack (not shown), e.g., photoresist / organic planarizing layer (OPL) / anti-reflective coating (ARC). Alternatively, the hard mask may be formed by other preferred techniques such as sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multiple patterning (SAMP). The pattern is then transferred from the hard mask to the metal layer using etching, after which the hard mask is removed. Directional (e.g., anisotropic) etching processes, such as reactive ion etching (RIE), can be employed for etching. As a result of this subtractive etching process, a first metallization layer M x-1 Metal wiring 104a-104f and the first via metallization layer V x-1 At least one of the metal vias 106 has a distinct shape. That is, due to the directional nature of etching, the first metallization layer M x-1 Metal wiring 104a~104f and the first via metallization layer V x-1 At least one of the metal vias 106 has a tapered, downward-sloping side wall, and as a result, each of the metal wirings 104a to 104f and at least one of the metal vias 106 is wider at the bottom and narrower at the top.

[0052] Therefore, in the exemplary embodiment, each of the metal wirings 104a to 104f and at least one metal via 106 has a tapered shape, and as a result, the width of the upper portion of each of the metal wirings 104a to 104f and at least one metal via 106 is narrower than the width of the lower portion of each of the metal wirings 104a to 104f and at least one metal via 106.

[0053] First metallization layer M x-1 Metal wiring 104a~104f and the first via metallization layer V x-1 Suitable conductive metals for at least one metal via 106 include, for example, aluminum (Al), chromium (Cr), cobalt (Co), hafnium (Hf), iridium (Ir), molybdenum (Mo), nickel (Ni), niobium (Nb), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V), zirconium (Zr), and alloys thereof. It should be noted that patterning metals such as copper (Cu) in this manner using subtractive etching is not easy. That is, Cu does not produce any volatile products during reaction with common etching gases (e.g., fluorine, chlorine, oxygen, hydrogen, etc.). As a result, the etching rate required to enable subtractive etching of Cu wiring is very slow. Therefore, conductive metals such as Co, Ru, Mo, and / or W are employed.

[0054] First metallization layer M x-1 Metal wiring 104a~104f and the first via metallization layer V x-1 After patterning at least one metal via 106, an interlayer dielectric (ILD) layer 108 is deposited on and around the metal wirings 104a-104f and at least one metal via 106. Suitable materials for the ILD layer 108 include, for example, silicon dioxide (SiO₂). xThis includes oxide low dielectric constant materials such as ) and / or oxide ultralow-k interlayer dielectric (ULK-ILD) materials with a relative permittivity κ of less than 2.7. For comparison, silicon dioxide (SiO2) has a relative permittivity κ of 3.9. Suitable ultralow-k dielectric materials include, for example, porous organosilicate glass (pSiCOH). The ILD layer 108 can be deposited using processes such as CVD, ALD, or PVD. The upper surface of the ILD layer 108 can then be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0055] The subtractive patterning process described above is merely an example, and a first metallization layer M having metal wirings 104a to 104f arranged on a substrate 102 x-1 , and a first via metallization layer V having at least one metal via 106 x-1 Other processes for creating are contemplated in this disclosure. For example, a first metallization layer M having metal wirings 104a to 104f x-1 To form the ILD layer 108, first, an ILD layer 108 can be deposited on the substrate 102. In exemplary embodiments, the metal wirings 104a-104f can be formed using photolithography, etching, and deposition processes. For example, in some embodiments, a photoresist is applied to the surface to be etched; the photoresist is exposed to a pattern of radiation; and then the pattern is developed on the photoresist using a resist developer to generate a pattern (not shown) on the ILD layer 108. Once the patterning of the photoresist is complete, the photoresist is removed. The etching process may be subtractive etching, such as anisotropic etching such as RIE. The etching process may also be a selective etching process.

[0056] The conductive metal described above can then be deposited into the openings formed within the patterned ILD layer 108 using any conventional deposition process such as ALD, PVD, CVD, or electroplating. Subsequently, the upper surface of the interconnect structure 100 can be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0057] First via metallization layer V x-1 This is the first metallization layer M x-1 It can be formed by depositing an additional amount of ILD layer 108 on top. In exemplary embodiments, at least one metal via 106 can be formed using photolithography, etching, and deposition processes. For example, in some embodiments, a photoresist is applied to the surface to be etched; the photoresist is exposed to a pattern of radiation; and then the pattern is developed on the photoresist using a resist developer to generate a pattern (not shown) on the ILD layer 108. Once the patterning of the photoresist is complete, the photoresist is removed. The etching process can be subtractive etching, such as anisotropic etching such as RIE. The etching process can also be a selective etching process.

[0058] The conductive metal described above may then be deposited into one or more openings formed within the patterned ILD layer 108 using any conventional deposition process such as ALD, PVD, CVD, or electroplating to form at least one metal via 106. Subsequently, the upper surface of the interconnect structure 100 may be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0059] Next, using the process described above, the second metallization layer M x A first via metallization layer V can be formed. For example, in one embodiment, first a first via metallization layer V x-1A subtractive patterning process can be performed by depositing a metal layer on top. Next, using lithography and etching techniques, a second metallization layer M is created as described above. x A metal layer can be patterned on the metal wiring 110. In this embodiment, the metal wiring 110 is wider at the top and narrower at the bottom. In an exemplary embodiment, the metal wiring 110 has a tapered shape in which the width of the upper portion of the metal wiring 110 is narrower than the width of the lower portion of the metal wiring 110.

[0060] A suitable metal for the metal wiring 110 is the first metallization layer M x-1 The metal wiring 104a to 104f may be any of the above.

[0061] Second metallization layer M x After patterning the metal wiring 110, an additional ILD layer 108 is deposited on top of and around the metal wiring 110. Subsequently, a planarization process, such as a standard planarization process (e.g., a CMP process), can be performed to planarize the upper surface of the ILD layer 108.

[0062] In an alternative embodiment, a second metallization layer M having metal wiring 110 x This can be formed by depositing an additional amount of ILD layer 108 and then performing a photolithography, etching, and deposition process. For example, in some embodiments, a photoresist is applied to the surface to be etched; the photoresist is exposed to a pattern of radiation; and then the pattern is developed on the photoresist using a resist developer to generate a pattern (not shown) on the ILD layer 108. Once the patterning of the photoresist is complete, the photoresist is removed. The etching process may be subtractive etching, such as anisotropic etching such as RIE. The etching process may also be a selective etching process.

[0063] The conductive metal described above can then be deposited into the openings formed within the patterned ILD layer 108 using any conventional deposition process such as ALD, PVD, CVD, or electroplating. Subsequently, the upper surface of the interconnect structure 100 can be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0064] Figure 2 shows a cross-sectional view of the interconnect structure 100 in the second intermediate step. During this step, the hard mask layer 112 is first subjected to a second metallization layer M using any conventional deposition technique such as ALD. x It is deposited on top. The material of the hard mask layer 112 may include, for example, a multilayer of SiN, SiN and SiO2, or another suitable material.

[0065] Next, a mask layer 114, such as an organic planarization layer (OPL) or spin-on carbon (SOC), is deposited on the hard mask layer 112 using any conventional deposition process, such as spin-on coating or any other suitable deposition process. The mask layer 114 is then patterned and selectively etched using any selective etching process, such as RIE, until it reaches the hard mask layer 112 to form openings 116. In exemplary embodiments, a second metallization layer M is then deposited, as described later. x The opening 116 is positioned to perform an oblique selective etching process via [the specified method].

[0066] Figure 3 shows a cross-sectional view of the interconnect structure 100 in the third intermediate step. During this step, the hard mask layer 112 within the opening 116 is selectively etched using a selective etching process such as RIE or other suitable etching to form a second metallization layer M x The upper surface is exposed to form an opening 116'. Next, the mask layer 114 is removed by anisotropic dry etching or wet etching.

[0067] Figure 4 shows a cross-sectional view of the interconnect structure 100 in the fourth intermediate step. During this step, trenches 120 are formed through the opening 116' and the metal wiring 110 by a directional etching process. In an exemplary embodiment, the directional etching process is performed by directing oblique ions 118 to a non-zero angle of incidence θ with respect to a perpendicular to the plane corresponding to the upper surface of the interconnect structure 100. In a non-limiting but practical application, the absolute value of the angle of incidence (+ / - of the oblique ions relative to the perpendicular) may be in the range of about 10 degrees and about 80 degrees, and in a particular embodiment, it may be in the range of about 30 degrees and about 50 degrees.

[0068] In a non-limiting exemplary embodiment, the oblique ions 118 may be directed in a reactive ion beam etching operation, where the oblique ions 118 are provided as an ion beam for performing reactive ion etching. The oblique ions 118 are directed relative to the hard mask layer 112, and the second metallization layer M x The metal wiring 110 can be preferentially etched. As further shown, oblique ions 118 form trenches 120. The hard mask layer 112 is a second metallization layer M x Because it is etched at a much slower rate than the metal wiring 110, the presence of the hard mask layer 112 serves to shield the lower region in the interconnect structure 100.

[0069] The trench 120 is the first metallization layer M with respect to the vertical axis 121. x-1 The trench is inclined toward the metal wiring 104d, 104e, and 104f, exposing the ILD layer 108 and the second metallization layer M xThe metal wirings 110a and 110b are formed. Thus, the metal wiring 110a has an outer edge of a sidewall having a first taper angle θ in the range of about 30 to about 80 degrees, and the corresponding metal wiring 110b similarly has an outer edge of a sidewall having a first taper angle θ in the range of about 30 to about 80 degrees. In an exemplary embodiment, the outer edges of the other sidewalls of each of the metal wirings 110a and 110b have a second taper angle different from the first taper angle. In an exemplary embodiment, the first taper angle is different from the second taper angle. In an exemplary embodiment, the first taper angle is smaller than the second taper angle.

[0070] Figure 5 shows a cross-sectional view of the interconnect structure 100 in the fifth intermediate step. During this step, the hard mask layer 112 is removed using a known etching process such as wet etching or dry etching. Next, an additional amount of ILD layer 108 is applied to the trench 120 and the second metallization layer M x It is deposited on top of it.

[0071] Figure 6 shows a cross-sectional view of the interconnect structure 100 in the sixth intermediate step. During this step, a second via metallization layer V containing at least one metal via 122 is formed. x , and a third metallization layer M including metal wiring 124a~124g x+1 However, it is formed on the interconnect structure 100. In an exemplary embodiment, a second via metallization layer V xThe pattern can be formed using photolithography, etching, and deposition processes. For example, in some embodiments, a photoresist is applied to the surface to be etched; the photoresist is exposed to a radiation pattern; and then the pattern is developed on the photoresist using a resist developer to generate a pattern (not shown) on the ILD layer 108. Once the patterning of the photoresist is complete, the photoresist is removed. The etching process may be subtractive etching, such as anisotropic etching such as RIE. The etching process may also be a selective etching process.

[0072] When etching the ILD layer 108, an opening is formed such that the resulting metal via 122 partially overlaps with the metal via 106. In addition, the outer edge of the metal via 122 is formed by the second metallization layer M x The outer edge of the metal wiring 110b will come into contact with the metal wiring 110b. This overlapping configuration makes it possible to reduce the overall dimensions of the semiconductor substrate. The conductive metal described above can then be deposited in one or more openings formed in the patterned ILD layer 108 using any conventional deposition process such as ALD, PVD, CVD, or electroplating to form at least one metal via 122. Second via metallization layer V x One metal via 122 is shown for this, but this is merely an example, and the second via metallization layer V x It should be understood that any number of metal vias are intended for this. Subsequently, the upper surface of the interconnect structure 100 can be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0073] In an exemplary embodiment, the metal via 122 has a tapered shape in which the width of the upper portion of the metal via 122 is greater than the width of the lower portion of the metal via 122.

[0074] Third metallization layer M including metal wiring 124a~124g x+1However, as described above, they can be formed using photolithography, etching, and deposition processes. For example, in some embodiments, a photoresist is applied to the surface to be etched; the photoresist is exposed to a radiation pattern; and then, using a resist developer, the pattern is developed on the photoresist to create another pattern (not shown) on the ILD layer 108. Once the patterning of the photoresist is complete, the photoresist is removed. The etching process may be subtractive etching, such as anisotropic etching such as RIE. The etching process may also be a selective etching process.

[0075] As described above, by performing the oblique RIE operation, the first via metallization layer V x-1 The second metallization layer M is formed via the metal via 106. x The metal wiring 110a is subjected to the first metallization layer M x-1 It can be connected to the metal wiring 104c and the second via metallization layer V x The second metallization layer M is formed via the metal via 122. x The metal wiring 110b is placed in the third metallization layer M x+1 It can be connected to the metal wiring 124d, where the metal vias 106 and 122 are in an overlapping configuration.

[0076] The conductive metal described above may then be deposited into one or more openings formed within the patterned ILD layer 108 using any conventional deposition process such as ALD, PVD, CVD, or electroplating to form metal wiring 124a to 124g. Subsequently, the upper surface of the interconnect structure 100 may be planarized by performing a planarization process such as a standard planarization process (e.g., a CMP process).

[0077] In an exemplary embodiment, each of the metal wirings 124a to 124g has a tapered shape in which the width of the upper portion of each of the metal wirings 124a to 124g is greater than the width of the lower portion of each of the metal wirings 124a to 124g.

[0078] Semiconductor devices and methods for forming them according to the techniques described above can be employed in a variety of applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., cellular phones and smartphones), solid-state media storage devices, functional circuit configurations, and the like. Systems and hardware incorporating semiconductor devices are intended embodiments of the present invention. Based on the teachings provided herein, those skilled in the art may consider other implementations and applications of embodiments of the present invention.

[0079] In some embodiments, the techniques described above are used in relation to semiconductor devices that require or otherwise utilize CMOS, MOSFET, and / or FinFET technologies, for example. In non-limiting examples, semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices and / or semiconductor devices utilizing CMOS, MOSFET, and / or FinFET technologies.

[0080] According to an aspect of the present invention, the interconnect structure comprises a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer. The first metallization layer has a first metal wiring and a second metal wiring. The first metal via is disposed on the first metal wiring, and the second metal via is disposed on the second metal wiring. The second metal via is configured to overlap the first metal via.

[0081] In one embodiment, the first via metallization layer is located within a dielectric layer, and the first and second via metallization layers are further located within the dielectric layer.

[0082] In this embodiment, the upper surface of the first metal via is in contact with the lower surface of the first metal wiring, and the lower surface of the second metal via is in contact with the upper surface of the second metal wiring.

[0083] In this embodiment, the first via metallization layer is located on a second metallization layer having a first plurality of metal wirings. A predetermined one of the first plurality of metal wirings is in contact with the first metal via.

[0084] In this embodiment, a third metallization layer is located on the second via metallization layer. The third metallization layer has a plurality of second metal wirings. One of the plurality of second metal wirings is in contact with the second metal via.

[0085] In one embodiment, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via. The second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0086] According to an aspect of the present invention, the interconnect structure comprises a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer. The first metallization layer has a first metal wiring having a first sidewall forming a first taper angle and a second metal wiring having a second sidewall forming a second taper angle. The first metal via is disposed at the first outer edge of the first sidewall of the first metal wiring. The second metal via is disposed at the second outer edge of the second sidewall of the second metal wiring. The second metal via is configured to overlap with the first metal via.

[0087] In this embodiment, the first taper angle is the same as the second taper angle.

[0088] In this embodiment, the first via metallization layer is located on a second metallization layer having a first plurality of metal wirings. A predetermined one of the first plurality of metal wirings is in contact with the first metal via.

[0089] In this embodiment, a third metallization layer is located on the second via metallization layer. The third metallization layer has a plurality of second metal wirings. One of the plurality of second metal wirings is in contact with the second metal via.

[0090] In one embodiment, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via. The second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0091] In one embodiment, the first via metallization layer is located within a dielectric layer, and the first and second via metallization layers are further located within the dielectric layer.

[0092] According to an aspect of the present invention, the integrated circuit comprises one or more interconnect structures. At least one of the one or more interconnect structures has a first via metallization layer including at least a first metal via, a second via metallization layer including at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer. The first metallization layer has a first metal wiring and a second metal wiring. The first metal via is disposed on the first metal wiring, and the second metal via is disposed on the second metal wiring. The second metal via is configured to overlap the first metal via.

[0093] In this embodiment, the first metal wiring has a first sidewall forming a first taper angle, and the second metal wiring has a second sidewall forming a second taper angle. The first metal via is located on the first outer edge of the first sidewall of the first metal wiring. The second metal via is located on the second outer edge of the second sidewall of the second metal wiring. The first taper angle is the same as the second taper angle.

[0094] In this embodiment, the first via metallization layer is located on a second metallization layer having a first plurality of metal wirings. A predetermined one of the first plurality of metal wirings is in contact with the first metal via.

[0095] In this embodiment, a third metallization layer is located on the second via metallization layer. The third metallization layer has a plurality of second metal wirings. One of the plurality of second metal wirings is in contact with the second metal via.

[0096] In one embodiment, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via. The second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0097] In this embodiment, the first via metallization layer, the second via metallization layer, and the first metallization layer are arranged within a dielectric layer.

[0098] According to an aspect of the present invention, the method comprises the step of forming a first via metallization layer having at least a first metal via. The method also comprises the step of forming a metallization layer having a first metal wiring and a second metal wiring on the first via metallization layer, wherein the first metal wiring is arranged on the first metal via. The method also comprises the step of forming a second via metallization layer having at least a second metal via on the metallization layer, wherein the second metal via is arranged on the second metal wiring, and the second metal via overlaps with the first metal via.

[0099] In one embodiment, the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via. The second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

[0100] In the embodiment, the first metal via and the second metal via are formed by a subtractive etching process.

[0101] According to an aspect of the present invention, the method comprises the step of forming a first via metallization layer having at least a first metal via. The method also comprises the step of depositing a conductive metal layer on the first via metallization layer. The method also comprises the step of performing oblique ion beam etching on the conductive metal layer to form a metallization layer having a first metal wiring having a first sidewall with a first taper angle and a second metal wiring having a second sidewall with a second taper angle. The method also comprises the step of forming a second via metallization layer having at least a second metal via on the metallization layer. The first metal via is located at the first outer edge of the first sidewall of the first metal wiring. The second metal via is located at the second outer edge of the second sidewall of the second metal wiring. The second metal via is configured to overlap with the first metal via.

[0102] Various structures described above may be implemented in an integrated circuit. The resulting integrated circuit chip may be supplied by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher carrier) or a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-cost applications to displays, keyboards, or other input devices, and advanced computer products with a central processor.

[0103] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be comprehensive or limitless to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or the technical improvements to the technology available on the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first via metallization layer having at least a first metal via; A second via metallization layer having at least a second metal via; and A first metallization layer is disposed between the first via metallization layer and the second via metallization layer, the first metallization layer having a first metal wiring and a second metal wiring; Equipped with, The first metal via is located on the first metal wiring, and the second metal via is located on the second metal wiring; and The second metal via is configured to overlap with the first metal via. Interconnect structure.

2. The interconnect structure according to claim 1, wherein the first via metallization layer is disposed within the dielectric layer.

3. The interconnect structure according to claim 2, wherein the first metallization layer and the second via metallization layer are further disposed within the dielectric layer.

4. The interconnect structure according to claim 1, wherein the upper surface of the first metal via is in contact with the lower surface of the first metal wiring, and the lower surface of the second metal via is in contact with the upper surface of the second metal wiring.

5. The interconnect structure according to claim 1, wherein the first via metallization layer is disposed on a second metallization layer having a first plurality of metal wirings, and a predetermined one of the first plurality of metal wirings is in contact with the first metal via.

6. The interconnect structure according to claim 5, further comprising a third metallization layer disposed on the second via metallization layer, wherein the third metallization layer has a plurality of second metal wirings, wherein a predetermined one of the plurality of second metal wirings is in contact with the second metal via.

7. The interconnect structure according to claim 1, wherein the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

8. A first via metallization layer having at least a first metal via; A second via metallization layer having at least a second metal via; and A first metallization layer is disposed between the first via metallization layer and the second via metallization layer, the first metallization layer having a first metal wiring having a first sidewall forming a first taper angle and a second metal wiring having a second sidewall forming a second taper angle; Equipped with, The first metal via is located on the first outer edge of the first side wall of the first metal wiring; The second metal via is located on the second outer edge of the second side wall of the second metal wiring; and The second metal via is configured to overlap with the first metal via. Interconnect structure.

9. The interconnect structure according to claim 8, wherein the first taper angle is the same as the second taper angle.

10. The interconnect structure according to claim 8, wherein the first via metallization layer is disposed on a second metallization layer having a first plurality of metal wirings, and a predetermined one of the first plurality of metal wirings is in contact with the first metal via.

11. The interconnect structure according to claim 10, further comprising a third metallization layer disposed on the second via metallization layer, wherein the third metallization layer has a plurality of second metal wirings, wherein a predetermined one of the plurality of second metal wirings is in contact with the second metal via.

12. The interconnect structure according to claim 8, wherein the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

13. The interconnect structure according to claim 8, wherein the first via metallization layer is disposed within the dielectric layer.

14. The interconnect structure according to claim 13, wherein the first metallization layer and the second via metallization layer are further disposed within the dielectric layer.

15. One or more interconnect structures The interconnect structure comprises, and at least one of the one or more interconnect structures is: A first via metallization layer comprising at least a first metal via; A second via metallization layer comprising at least a second metal via; and A first metallization layer is disposed between the first via metallization layer and the second via metallization layer, the first metallization layer including a first metal wiring and a second metal wiring; It has, The first metal via is located on the first metal wiring, and the second metal via is located on the second metal wiring; and The second metal via is configured to overlap with the first metal via. Integrated circuit.

16. The first metal wiring has a first side wall forming a first taper angle, and the second metal wiring has a second side wall forming a second taper angle; The first metal via is located on the first outer edge of the first side wall of the first metal wiring; and The second metal via is located on the second outer edge of the second side wall of the second metal wiring. The integrated circuit according to claim 15.

17. The integrated circuit according to claim 16, wherein the first taper angle is the same as the second taper angle.

18. The integrated circuit according to claim 15, wherein the first via metallization layer is disposed on a second metallization layer comprising a first plurality of metal wirings, and a predetermined one of the first plurality of metal wirings is in contact with the first metal via.

19. The integrated circuit according to claim 18, wherein at least one of the one or more interconnect structures further comprises a third metallization layer disposed on the second via metallization layer, the third metallization layer having a second plurality of metal wirings, wherein a predetermined one of the second plurality of metal wirings is in contact with the second metal via.

20. The integrated circuit according to claim 15, wherein the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

21. The integrated circuit according to claim 15, wherein the first via metallization layer, the second via metallization layer, and the first metallization layer are arranged within a dielectric layer.

22. A step of forming a first via metallization layer having at least a first metal via; The steps of forming a metallization layer having a first metal wiring and a second metal wiring on the first via metallization layer, wherein the first metal wiring is arranged on the first metal via; and The step of forming a second via metallization layer having at least a second metal via on the metallization layer, wherein the second metal via is arranged on the second metal wiring; Equipped with, The second metal via is configured to overlap with the first metal via. method.

23. The method according to claim 22, wherein the first metal via has a tapered shape in which the width of the upper portion of the first metal via is narrower than the width of the lower portion of the first metal via, and the second metal via has a tapered shape in which the width of the upper portion of the second metal via is wider than the width of the lower portion of the second metal via.

24. The method according to claim 22, wherein the first metal via and the second metal via are formed by a subtractive etching process.

25. A step of forming a first via metallization layer having at least a first metal via; Steps include depositing a conductive metal layer on the first via metallization layer; A step of performing oblique ion beam etching on the conductive metal layer to form a metallization layer having a first metal wiring having a first sidewall with a first taper angle and a second metal wiring having a second sidewall with a second taper angle; and A step of forming a second via metallization layer having at least a second metal via on the metallization layer; Equipped with, The first metal via is positioned on the first outer edge of the first side wall of the first metal wiring; The second metal via is positioned at the second outer edge of the second side wall of the second metal wiring; and The second metal via is configured to overlap with the first metal via. method.

Images