High-speed, high-voltage fully differential power amplifier for beam deflection drivers

Abstract

This disclosure provides a deflector driver for driving a deflector in a charged particle inspection apparatus. The deflector driver may include a fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V. The fully differential output allows multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection apparatus based on the fully differential output.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Patent Application No. 63 / 530,241, filed on 1 August 2023, which is incorporated herein by reference in its entirety.

[0002]

[0002] Embodiments provided herein generally relate to inspection equipment, and more specifically to beam manipulation systems for inspection equipment. [Background technology]

[0003]

[0003] In the manufacturing process of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and free from defects. Inspection systems utilizing charged particle (e.g., electron) beam microscopes, such as optical microscopes or scanning electron microscopes (SEMs), can be employed. As the physical size of IC components decreases, the accuracy and yield of defect detection become more critical. However, the image resolution and throughput of inspection tools are struggling to keep pace with the increasingly shrinking feature size of IC components. The accuracy, resolution, and throughput of such inspection tools may be limited by a lack of deflector drive mechanisms that meet industry-required standards. [Overview of the project]

[0004]

[0004] Several embodiments provide a charged particle inspection apparatus. The apparatus may comprise a charged particle beam source configured to generate a primary charged particle beam for sample scanning; a deflector driver including a fully differential amplifier configured to generate a fully differential output with an absolute value greater than 100V; and a plurality of deflector electrodes coupled to the fully differential output and configured to influence the charged particle beam based on the fully differential output.

[0005]

[0005] Some embodiments provide a deflector driver for driving a deflector of a charged particle inspection apparatus. The deflector driver can include a fully differential amplifier configured to generate a fully differential output having an absolute value greater than 100V. The fully differential output can enable a plurality of deflector electrodes of the deflector to affect a charged particle beam of the charged particle inspection apparatus based on the fully differential output.

[0006]

[0006] Some embodiments provide a method of operating a deflector driver for driving a deflector of a charged particle inspection apparatus. The method can include generating, by a fully differential amplifier included in the deflector driver, a fully differential output having an absolute value greater than 100V; measuring, by a common mode control circuit included in the deflector driver, a common mode voltage of the fully differential output of the fully differential amplifier; providing, by the common mode control circuit, a difference between the common mode voltage and a reference voltage to the fully differential amplifier; and adjusting, based on the difference, the fully differential output of the differential amplifier. The adjusted fully differential output can enable a plurality of deflector electrodes of the deflector to affect a charged particle beam of the charged particle inspection apparatus based on the fully differential output. The fully differential amplifier and the common mode control circuit can be integrated into a single integrated circuit (IC) chip.

[0007]

[0007] Other advantages of embodiments of the present disclosure will become apparent from the following description in conjunction with the accompanying drawings in which specific embodiments of the invention are shown by way of example and illustration.

Brief Description of the Drawings

[0008]

[0008] The above and other aspects of the present disclosure will become more apparent from the description of the exemplary embodiments in conjunction with the accompanying drawings.

[0009] [Figure 1]

[0009] It is a schematic diagram showing an exemplary charged particle beam inspection system according to an embodiment of the present disclosure. [Figure 2A]

[0010] This is a schematic diagram showing an exemplary multi-beam tool that may be part of the exemplary charged particle beam inspection system shown in Figure 1, according to embodiments of the present disclosure. [Figure 2B]

[0011] This is a schematic diagram showing an exemplary single-beam tool that may be part of the exemplary charged particle beam inspection system shown in Figure 1, according to embodiments of the present disclosure. [Figure 3A]

[0012] This figure shows an exemplary configuration of a scan deflection system according to an embodiment of the present disclosure. [Figure 3B]

[0013] This is a diagrammatic representation of the deflection of a charged particle beam according to an embodiment of the present disclosure. [Figure 3C]

[0014] This figure shows an exemplary configuration of a deflection element according to an embodiment of the present disclosure. [Figure 4]

[0015] This is a schematic diagram showing an exemplary configuration of a deflection control unit related to a charged particle beam deflector according to an embodiment of the present disclosure. [Figure 5]

[0016] This figure shows a driver system architecture featuring a pseudo-differential amplifier utilizing dual single-ended power amplifiers. [Figure 6]

[0017] This diagram shows the circuit configuration of a single-ended power amplifier. [Figure 7]

[0018] This figure shows an exemplary driver system architecture with a fully differential power amplifier according to an embodiment of the present disclosure. [Figure 8]

[0019] This figure shows an exemplary fully differential power amplifier circuit configuration, along with a common-mode control circuit, according to an embodiment of the present disclosure. [Figure 9]

[0020] This flowchart shows an exemplary method for operating a deflector driver with a fully differential power amplifier according to embodiments of the present disclosure. [Modes for carrying out the invention]

[0010]

[0021] Herein, examples refer in detail to exemplary embodiments shown in the accompanying drawings. The following description refers to the accompanying drawings. In the accompanying drawings, unless otherwise noted, the same numbering in different drawings represents the same or similar elements. The embodiments described below in the description of exemplary embodiments do not represent all embodiments. Rather, these embodiments are merely examples of apparatus and methods in aspects related to the embodiments disclosed in the accompanying claims. For example, some embodiments are described in a context utilizing an electron beam, but this disclosure is not limited thereto. Other types of charged particle beams (including, for example, protons, ions, muons, or any other charged particle) can be similarly applied. Furthermore, other imaging systems such as optical imaging, photon detection, X-ray detection, and ion detection can also be used.

[0011]

[0022] Electronic devices consist of circuits formed on a single piece of semiconductor material called a substrate. Examples of semiconductor materials include silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits can be formed together on the same piece of silicon, and these are called integrated circuits or ICs. The size of these circuits has been dramatically reduced so that more circuits can be mounted on a substrate. For example, a smartphone IC chip is about the size of a thumbnail, yet contains more than 2 billion transistors, and the size of each transistor can be less than 1 / 1000th the size of a human hair.

[0012]

[0023] Manufacturing these ICs, which have extremely small structures or components, is a complex, time-consuming, and costly process that often involves hundreds of individual steps. Even an error in a single step can result in a defective finished IC, rendering it unusable. Therefore, one goal of the manufacturing process is to avoid such defects and maximize the number of functional ICs produced by the process, that is, to improve the overall process yield.

[0013]

[0024] One factor in improving yield is monitoring the chip manufacturing process to ensure that a sufficient number of functional integrated circuits are manufactured during the process. One way to monitor the process is to inspect the chip circuit structure at various stages of its formation. Inspection can be performed using a scanning charged-particle microscope (SCPM). For example, an SCPM may be a scanning electron microscope (SEM). SCPMs are used to image such extremely small structures, effectively taking "photographs" of the wafer structure. The images can be used to determine whether the structure was properly formed in the correct location. If there are defects in the structure, the process can be adjusted to make the defects less likely to recur.

[0014]

[0025] As the physical size of IC components shrinks, the accuracy and yield of defect detection become increasingly critical. Furthermore, the growing global demand for computing necessitates increased IC manufacturing or inspection speeds. However, increasing IC inspection speed can present technical challenges in maintaining high defect detection accuracy. IC inspection accuracy, resolution, and throughput can be limited by a lack of deflector drive mechanisms that meet the desirable industry standards. Currently, differential drive capability deflection driver systems are being utilized to achieve better signal-to-noise ratios (SNR). Specifically, when transmitting signals within or between PCBs, electromagnetic impedance (EMI) may be coupled to each signal, and such EMI coupling can lead to further noise problems. By transmitting signals differentially, EMI commonly coupled to two differential signals can be canceled out. The industry requires the provision of differential drive capability deflection driver systems with the following specifications:

[0015]

[0026] To meet industry demands for scan speeds (e.g., 1.2 gigasamples / second), deflection driver systems are desirable to operate faster with power bandwidths greater than 1 MHz. However, increasing the bandwidth of the power amplifier, a key component of the deflection driver system, is hindered by a trade-off between scan speed and stability. A wider power amplifier bandwidth allows for faster scan speeds, which also improves system yield. However, under the same gain-bandwidth product (GBW), increasing the circuit bandwidth means the power amplifier operates in a lower phase margin region, reducing circuit stability and consequently lowering the resolution of the inspection image. Therefore, it is desirable to design power amplifiers with higher bandwidth or GBW to achieve higher throughput while maintaining sufficient circuit stability. Furthermore, to provide sufficient flexibility in the design of the deflection drive system, it is desirable to design the power amplifier to have unity-gain stability with a phase margin greater than 60 degrees. However, increasing the power amplifier bandwidth can introduce more noise into the system, potentially degrading signal quality and image resolution. Therefore, there is a need in this field to provide increased power bandwidth without sacrificing signal quality, for example, by keeping the noise level low.

[0016]

[0027] For high-speed scanning, it is desirable for the deflection driver system to drive a higher voltage output. There is a trade-off between output voltage level and SNR. When the deflection drive signal has a higher voltage level, the noise floor is amplified when the drive signal is amplified, which can lower the SNR. Lower voltage levels may be considered to improve the SNR. However, lower voltage drive signals may not be able to deflect the beam across the entire inspection area. Furthermore, lower voltage drive signals may not be able to achieve the required inspection sensitivity at the edges of the inspection area. To increase the inspection area and improve edge sensitivity when using lower voltage drive signals, a more sensitive deflector can be used to compensate for the decrease in field strength, thereby ensuring the desired field strength level at lower voltages. Deflector sensitivity is usually improved by designing the deflector to be larger or longer, but this ultimately results in a decrease in image resolution, especially at the edges of the inspection area. Therefore, it is necessary in this art to provide a higher voltage deflection driver system without sacrificing signal quality. In this disclosure, higher voltage levels may refer to voltage levels greater than 100V, which can support industry scan rate requirements, such as 1.2 gigasamples / second, without sacrificing signal quality, for example, by maintaining lower noise levels.

[0017]

[0028] Furthermore, to achieve the desired scan throughput, it is desirable for the deflection driver system to offer a higher slew rate (e.g., greater than 500 V / μs). As the scan rate continuously increases, a higher slew rate becomes increasingly important to reduce scan overhead. Moreover, in future products, the output cables of the deflection driver system are likely to be longer due to the use of dynamic links, making a higher slew rate even more crucial for improving throughput. A slew rate greater than 500 V / μs can improve throughput by avoiding the excessive overhead caused by long cable routing.

[0018]

[0029] Furthermore, it is desirable to keep the noise level of the deflection driver system below 2.5 nV / sqrt(Hz). The noise specifications of conventional deflection driver systems (e.g., 3 nV / sqrt(Hz)) may have met industry noise standards in the past. However, with the emergence of newly developed products utilizing smaller pixel sizes, the demand for deflection driver systems with lower noise levels is increasing.

[0019]

[0030] Conventional fully differential amplifiers cannot meet the above design criteria, so conventional deflection driver systems have utilized pseudo-differential power amplifiers composed of dual single-ended power amplifiers. However, a pseudo-differential power amplifier consists of multiple individual power amplifiers, such as two single-ended power amplifiers integrated into their own IC chips. As a result, even with the selection of the most accurate components and thorough optimization of the printed circuit board (PCB) design, mismatches between the elements of the two individual amplifiers are unavoidable. Such mismatches limit the common-mode rejection ratio (CMRR), leading to higher noise levels and reduced image resolution. As already mentioned, conventional deflection driver systems utilizing pseudo-differential power amplifiers suffer from high noise levels, at least partially resulting from the low common-mode rejection ratio due to the mismatch between the elements of the two single-ended power amplifiers. Therefore, while conventional deflection driver systems with pseudo-differential power amplifiers can drive high-voltage signals, they could not meet the noise criteria required for next-generation systems, such as less than 2.5 nV / sqrt(Hz).

[0020]

[0031] According to some embodiments of this disclosure, a deflector driver system can be provided that utilizes a fully differential power amplifier instead of a pseudo-differential power amplifier. According to some embodiments of this disclosure, the deflector driver system can drive deflector drive signals with higher voltages that meet the above criteria at high speed. According to some embodiments of this disclosure, a differential power amplifier is provided that is configured to produce a fully differential output with an absolute value greater than 100V. According to some embodiments of this disclosure, a deflector driver system with an improved common-mode rejection ratio can be provided. According to some embodiments of this disclosure, the differential power amplifier can be fully integrated with the common-mode feedback circuit onto a single IC chip, thereby improving scan speed and throughput that meets the above criteria. According to some embodiments of this disclosure, the fully differential power amplifier can be integrated onto a single IC chip, thereby reducing noise resulting from element mismatches. According to some embodiments of this disclosure, a deflector driver system including a fully differential power amplifier and multiple digital-to-analog converters (DACs) can be mounted on a single PCB board, saving PCB area and improving PCB design efficiency. According to some embodiments of this disclosure, a deflector driver system with high speed, low noise, high voltage, and high slew rate drive differential drive capability can be provided.

[0021]

[0032] The relative dimensions of components in the drawings may be exaggerated for clarity. In the following description of the drawings, identical or similar reference numerals refer to identical or similar components or entities, and only differences relating to individual embodiments are described. Other purposes and advantages of the disclosure can be realized by the elements and combinations described in the embodiments described herein. However, embodiments of the disclosure are not necessarily required to achieve such exemplary purposes or advantages, and some embodiments may not achieve any of the purposes or advantages described.

[0022]

[0033] Without limiting the scope of this disclosure, several embodiments may be described in the context of providing scan deflection systems and scan deflection methods in systems utilizing electron beams ("e-beams"). Some scan deflection systems may use electric fields to influence charged particle beams, but this is not limited to these systems. Other types of charged particle beams are similarly applicable. For example, systems and methods can be applied to optical, photon, X-ray, ion, and the like. Deflection may be used, for example, to scan a beam on the surface of a cathode ray tube (CRT), lithography machine, scanning charged particle microscope (SCPM), or other analytical instrument. While some embodiments are described with reference to deflection systems that use electric fields to influence a beam, deflection can also be achieved, for example, using magnetic fields.

[0023]

[0034] As used herein, unless otherwise specified, the term “or” encompasses all possible combinations, except where impractical. For example, if a component is described as containing A or B, unless otherwise specified or impractical, the component may contain A, or B, or A and B. As a second example, if a component is described as containing A, B, or C, unless otherwise specified or impractical, the component may contain A, or B, or C, or A and B, or A and C, or B and C, or A and B and C. Expressions such as “at least one” do not necessarily modify the entire following list, nor do they necessarily modify each element of the list. Thus, “at least one of A, B, and C” should be understood as including only A, only B, only C, or any combination of A, B, and C. The phrases "one of A and B" or "any one of A and B" should be interpreted in the broadest sense, including either one A or one B.

[0024]

[0035] Figure 1 shows an exemplary electron beam inspection (EBI) system 100 according to several embodiments of the present disclosure. The EBI system 100 may be used for imaging. As shown in Figure 1, the EBI system 100 includes a main chamber 101, a load lock chamber 102, a beam tool 104, and an instrument front-end module (EFEM) 106. The beam tool 104 is located in the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional (one or more) loading ports. The first loading port 106a and the second loading port 106b receive a wafer front-opening unified pod (FOUP) that houses a wafer (e.g., a semiconductor wafer or a wafer made of (one or more) other materials) or a sample to be inspected (wafer and sample may be used synonymously). A "lot" is a set of wafers that can be loaded for processing as a batch.

[0025]

[0036] One or more robotic arms (not shown) of the EFEM106 may transfer a wafer to the load lock chamber 102. The load lock chamber 102 is connected to a load lock vacuum pump system (not shown) that removes gas molecules from within the load lock chamber 102 to reach a first pressure lower than atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transfer the wafer from the load lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules from within the main chamber 101 to reach a second pressure lower than the first pressure. After reaching the second pressure, the wafer is inspected by a beam tool 104. The beam tool 104 may be a single-beam system or a multi-beam system.

[0026]

[0037] The beam tool 104 is electronically connected to a controller 109. The controller 109 may be a computer configured to perform various controls of the EBI system 100. In Figure 1, the controller 109 is shown as being outside the structure, which includes the main chamber 101, the load lock chamber 102, and the EFEM 106, but it should be understood that the controller 109 may also be part of the structure.

[0027]

[0038] In some embodiments, the controller 109 may include one or more processors (not shown). A processor can be a general-purpose or dedicated electronic device capable of manipulating or processing information. For example, a processor can include a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a composite programmable logic device (CPLD), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), and any number or any combination of any type of circuitry capable of processing data. A processor may also be a virtual processor, including one or more processors distributed across multiple machines or devices connected via a network.

[0028]

[0039] In some embodiments, the controller 109 may further include one or more memories (not shown). The memories may be general-purpose or dedicated electronic devices capable of storing code and data accessible by the processor (e.g., via a bus). For example, the memories may include random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any combination of any number of any type of storage device. The code and data may include an operating system (OS) and one or more application programs (or "apps") for a particular task. The memories may also be virtual memory, including one or more memories distributed across multiple machines or devices connected via a network.

[0029]

[0040] Figure 2A shows a schematic diagram of an exemplary multibeam tool 104A (also referred to herein as apparatus 104A) and an image processing system 290 that may be configured for use in an EBI system 100 (Figure 1) according to an embodiment of the present disclosure.

[0030]

[0041] The beam tool 104A includes a charged particle source 202, a gun aperture 204, a focusing lens 206, a primary charged particle beam 210 emitted from the charged particle source 202, a source conversion unit 212, multiple beamlets 214, 216, and 218 of the primary charged particle beam 210, a primary projection optics system 220, an electric wafer stage 280, a wafer holder 282, multiple secondary charged particle beams 236, 238, and 240, a secondary optics system 242, and a charged particle detection device 244. The primary projection optics system 220 may include a beam separator 222, a deflection scan unit 226, and an objective lens 228. The charged particle detection device 244 may include detection sub-regions 246, 248, and 250.

[0031]

[0042] The charged particle source 202, gun aperture 204, focusing lens 206, source conversion unit 212, beam separator 222, deflection scan unit 226, and objective lens 228 may be aligned with the primary optical axis 260 of the device 104. The secondary optical system 242 and charged particle detection device 244 may be aligned with the secondary optical axis 252 of the device 104.

[0032]

[0043] The charged particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or other charge-carrying particles. In some embodiments, the charged particle source 202 may be an electron source. For example, the charged particle source 202 may include a cathode, an extractor, or an anode, and primary electrons can be emitted from the cathode and extracted or accelerated to form a primary charged particle beam 210 (in this case, a primary electron beam) having a crossover (virtual or real) 208. For simplicity of explanation without causing ambiguity, electrons are used as examples in some parts of this specification. However, it should be noted that in any embodiment of this disclosure, any charged particle, not limited to electrons, may be used. The primary charged particle beam 210 can be visualized as being emitted from the crossover 208. The gun aperture 204 can block surrounding charged particles from the primary charged particle beam 210 to reduce the Coulomb effect. The Coulomb effect may result in an enlargement of the probe spot size.

[0033]

[0044] The source conversion unit 212 may include an image-forming element array and a beam-limiting aperture array. The image-forming element array may include an array of micro-deflectors or microlenses. The image-forming element array can form multiple parallel images (virtual or real images) of the crossover 208 using multiple beamlets 214, 216, and 218 of the primary charged particle beam 210. The beam-limiting aperture array can limit the multiple beamlets 214, 216, and 218. Three beamlets 214, 216, and 218 are shown in Figure 2A, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the apparatus 104A may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in the range of 1 to 1000. In some embodiments, the first number of beamlets may be in the range of 200 to 500. In an exemplary embodiment, the apparatus 104A can generate 400 beamlets.

[0034]

[0045] The focusing lens 206 can focus the primary charged particle beam 210. The currents in the beamlets 214, 216, and 218 downstream of the source conversion unit 212 can be varied by adjusting the focusing force of the focusing lens 206 or by changing the radial size of the corresponding beam limiting aperture in the beam limiting aperture array. The objective lens 228 can focus the beamlets 214, 216, and 218 onto the wafer 230 for imaging, and can form a plurality of probe spots 270, 272, and 274 on the surface of the wafer 230.

[0035]

[0046] The beam separator 222 may be a Wien filter type beam separator that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, when applied, the force exerted by the electrostatic dipole field on the charged particles (e.g., electrons) of the beamlets 214, 216, and 218 may be substantially equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the charged particles. Thus, the beamlets 214, 216, and 218 can pass straight through the beam separator 222 with zero deflection angle. However, the total dispersion of the beamlets 214, 216, and 218 generated by the beam separator 222 may also be non-zero. The beam separator 222 can separate the secondary charged particle beams 236, 238, and 240 from the beamlets 214, 216, and 218 and guide the secondary charged particle beams 236, 238, and 240 to the secondary optical system 242.

[0036]

[0047] The deflection scanning unit 226 can deflect the beamlets 214, 216, and 218 to scan probe spots 270, 272, and 274 across the surface area of ​​wafer 230. In response to the incidence of beamlets 214, 216, and 218 onto probe spots 270, 272, and 274, secondary charged particle beams 236, 238, and 240 may be emitted from wafer 230. The secondary charged particle beams 236, 238, and 240 may contain charged particles (e.g., electrons) having an energy distribution. For example, the secondary charged particle beams 236, 238, and 240 may be secondary electron beams containing secondary electrons (energy less than 50 eV) and backscattered electrons (energy between 50 eV and the landing energy of beamlets 214, 216, and 218). The secondary optical system 242 can focus the secondary charged particle beams 236, 238, and 240 onto the detection subregions 246, 248, and 250 of the charged particle detection device 244. The detection subregions 246, 248, and 250 may be configured to detect the corresponding secondary charged particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, etc.) used to reconstruct an inspection image of structures on or beneath the surface area of ​​the wafer 230.

[0037]

[0048] The generated signals may represent the intensities of the secondary charged particle beams 236, 238, and 240 and may be provided to an image processing system 290 communicating with a charged particle detection device 244, a primary projection optics system 220, and an electric wafer stage 280. The movement speed of the electric wafer stage 280 may be synchronized and coordinated with beam deflection controlled by a deflection scan unit 226 so that the movement of scan probe spots (e.g., scan probe spots 270, 272, and 274) covers the region of interest on the wafer 230 in an orderly manner. Such synchronization and coordination parameters may be adjusted to accommodate different materials of the wafer 230. For example, different materials of the wafer 230 may have different resistive-capacitive properties that can result in different signal sensitivities to the movement of the scan probe spots.

[0038]

[0049] The intensities of the secondary charged particle beams 236, 238, and 240 may vary depending on the external or internal structure of the wafer 230, thus indicating whether or not the wafer 230 contains defects. Furthermore, as described above, the beamlets 214, 216, and 218 can generate secondary charged particle beams 236, 238, and 240 with varying intensities by projecting onto different locations on the upper surface of the wafer 230 or onto different sides of the local structure of the wafer 230. Therefore, the image processing system 290 can reconstruct an image that reflects the characteristics of the internal or external structure of the wafer 230 by mapping the intensities of the secondary charged particle beams 236, 238, and 240 to areas on the wafer 230.

[0039]

[0050] In some embodiments, the image processing system 290 may include an image acquirer 292, storage 294, and a controller 296. The image acquirer 292 may include one or more processors. For example, the image acquirer 292 may include a computer, server, mainframe host, terminal, personal computer, any kind of mobile computing device, or a combination thereof. The image acquirer 292 may be communicatively coupled to the charged particle detection device 244 of the beam tool 104A via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the internet, a wireless network, wireless radio, or a combination thereof. In some embodiments, the image acquirer 292 can receive signals from the charged particle detection device 244 and construct an image. In this way, the image acquirer 292 can acquire an inspection image of the wafer 230. The image acquirer 292 may also perform various post-processing functions such as contour generation and superimposition of indicators onto the acquired image. The image acquirer 292 may be configured to adjust the brightness and contrast of the acquired image. In some embodiments, the storage 294 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. The storage 294 may be coupled with the image acquirer 292 and may be used to store scanned raw image data as the original image and post-processed images. The image acquirer 292 and the storage 294 may be connected to the controller 296. In some embodiments, the image acquirer 292, the storage 294, and the controller 296 may be integrated as a single control unit.

[0040]

[0051] In some embodiments, the image acquisition unit 292 can acquire one or more inspection images of the wafer based on imaging signals received from the charged particle detection device 244. The imaging signals may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image containing multiple imaging areas. The single image may be stored in storage 294. The single image may be an original image that can be divided into multiple regions. Each region may contain one imaging area containing features of the wafer 230. The acquired image may contain multiple images of a single imaging area of ​​the wafer 230 sampled multiple times over a time series. The multiple images may be stored in storage 294. In some embodiments, the image processing system 290 may be configured to perform image processing steps using multiple images of the same location on the wafer 230.

[0041]

[0052] In some embodiments, the image processing system 290 may include a measurement circuit (e.g., an analog-to-digital converter) for obtaining the distribution of detected secondary charged particles (e.g., secondary electrons). The charged particle distribution data collected during the detection time window can be used in combination with the corresponding scan data of beamlets 214, 216, and 218 incident on the wafer surface to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 230, thereby revealing any defects that may be present in the wafer.

[0042]

[0053] In some embodiments, the charged particles may be electrons. When electrons from the primary charged particle beam 210 are projected onto the surface of the wafer 230 (e.g., probe spots 270, 272, and 274), the electrons from the primary charged particle beam 210 may penetrate the surface of the wafer 230 to a certain depth and interact with the particles of the wafer 230. Some electrons from the primary charged particle beam 210 may interact elastically with the material of the wafer 230 (e.g., in the form of elastic scattering or collision), and may be reflected or recoiled outward from the surface of the wafer 230. Elastic interactions conserve the total kinetic energy of the interacting objects (e.g., electrons from the primary charged particle beam 210), in which case the kinetic energy of the interacting objects is not converted into other forms of energy (e.g., heat, electromagnetic energy, etc.). Such reflected electrons produced by elastic interactions are sometimes called backscattered electrons (BSEs). Some electrons from the primary charged particle beam 210 may interact inelastically with the material of the wafer 230 (e.g., in the form of inelastic scattering or collision). Inelastic interactions do not conserve the total kinetic energy of the interacting objects; in this case, some or all of the kinetic energy of the interacting objects is converted into other forms of energy. For example, inelastic interactions can cause the kinetic energy of some electrons from the primary charged particle beam 210 to cause electron excitation and atomic transitions in the material. Such inelastic interactions may also generate electrons that emanate from the surface of the wafer 230, which are sometimes called secondary electrons (SEs). The yield or emission rate of BSEs and SEs depends, for example, on the material under inspection and the landing energy of the electrons from the primary charged particle beam 210 that land on the surface of the material. The energy of the electrons from the primary charged particle beam 210 can be partially provided by its accelerating voltage (e.g., the accelerating voltage between the anode and cathode of the charged particle source 202 in Figure 2A). The amounts of BSE and SE may be greater than or less than (or equal to) the amount of electrons injected by the primary charged particle beam 210.

[0043]

[0054] Another example of a charged particle beam apparatus is described with reference to Figure 2B. Beam tool 104B (also referred to herein as apparatus 104B) may be an example of beam tool 104 and may be similar to beam tool 104A shown in Figure 2A. However, unlike apparatus 104A, apparatus 104B may be a single-beam tool that scans one location on the wafer at a time using only one primary electron beam.

[0044]

[0055] As shown in Figure 2B, the apparatus 104B includes a wafer holder 136 supported by an electric stage 134 to hold the wafer 150 to be inspected. The beam tool 104B includes an electron emitter which may include a cathode 103, an anode 121, and a gun aperture 122. The beam tool 104B further includes a beam limiting aperture 125, a focusing lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 may be a modified SORIL lens which includes a pole piece 132a, a control electrode 132b, a deflector unit 132c, and an excitation coil 132d. In the detection or imaging process, the electron beam 161 emitted from the tip of the cathode 103 is accelerated by the voltage of the anode 121, passes through the gun aperture 122, the beam limiting aperture 125, and the focusing lens 126, and is focused to the probe spot 170 by the modified SORIL lens, where it can collide with the surface of the wafer 150. The probe spot 170 can be scanned across the surface of the wafer 150 by a deflector such as the deflector unit 132c or other deflectors in the SORIL lens. Secondary or scattered particles, such as secondary electrons or scattered primary electrons emitted from the wafer surface, can be collected by the detector 144 to determine the beam intensity, thereby allowing for the reconstruction of an image of the region of interest on the wafer 150.

[0045]

[0056] An image processing system 199 including an image acquirer 120, storage 130, and controller 109 can also be provided. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, server, mainframe host, terminal, personal computer, any type of mobile computing device, or a combination thereof. The image acquirer 120 can connect to the detector 144 of the beam tool 104B via a medium such as a conductor, optical fiber cable, portable storage medium, IR, Bluetooth, the Internet, wireless network, wireless device, or a combination thereof. The image acquirer 120 can receive signals from the detector 144 and construct an image. Thus, the image acquirer 120 can acquire an image of the wafer 150. The image acquirer 120 can also perform various post-processing functions such as image averaging, contour generation, and superimposition of indicators on the acquired image. The image acquirer 120 can be configured to perform adjustments such as brightness and contrast of the acquired image. The storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, or other types of computer-readable memory. The storage 130 can be coupled with the image acquirer 120 and used to store scanned raw image data as original images and post-processed images. The image acquirer 120 and the storage 130 can be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated as a single electronic control unit.

[0046]

[0057] In some embodiments, the image acquirer 120 can acquire one or more images of a sample based on imaging signals received from the detector 144. The imaging signals may correspond to a scanning operation for charged particle imaging. The acquired image may be a single image containing multiple imaging areas that may include various features of the wafer 150. The single image can be stored in the storage 130. Imaging can be performed based on imaging frames.

[0047]

[0058] The capacitor and illumination optics of an electron beam tool may include or be supplemented by an electromagnetic quadrupole electron lens. For example, as shown in Figure 2B, the electron beam tool 104B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses can be used to control the electron beam. For example, the first quadrupole lens 148 can be controlled to adjust the beam current, and the second quadrupole lens 158 can be controlled to adjust the beam spot size and beam shape.

[0048]

[0059] Figure 2B shows a charged particle beam apparatus that can use a single primary beam configured to generate secondary electrons by interacting with wafer 150. The detector 144 can be positioned along the optical axis 105, as in the embodiment shown in Figure 2B. The primary electron beam can be configured to move along the optical axis 105. Therefore, the detector 144 may include a hole in its center to allow the primary electron beam to pass through and reach wafer 150. Figure 2B shows an example of a detector 144 with a central opening, but in some embodiments, a detector positioned off-axis with respect to the optical axis through which the primary electron beam moves may be used. For example, as in the embodiment shown in Figure 2B described above, a beam separator 222 can be provided to guide the secondary electron beam toward the off-axis detector. The beam separator 222 may be configured to deflect the secondary electron beam toward an electron detection device 244, as shown in Figure 2A.

[0049]

[0060] Images generated by SCPM can be used for defect inspection. For example, a generated image capturing a test device region of a wafer can be compared to a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and may not contain known defects. If the difference between the generated image and the reference image exceeds an acceptable level, a potential defect can be identified. As another example, SCPM can scan multiple regions of a wafer, each containing a test device region designed similarly, and generate multiple images capturing those test device regions as they are being manufactured. These multiple images can be compared to each other. If the differences between the multiple images exceed an acceptable level, a potential defect can be identified.

[0050]

[0061] Referring here to Figure 3A, Figure 3A shows the configuration of the deflector and objective lens assembly according to an embodiment of the present disclosure. As shown in Figure 3A, the deflectors 309-1 and 309-2 can be placed in the magnetic field of the magnetic objective lens assembly 310, and the deflectors 309-1 and 309-2 may be implemented in a deflection scan unit (e.g., deflection scan unit 226 in Figure 2A) or as a deflector unit (e.g., deflector unit 132c in Figure 2B). The deflectors 309-1 and 309-2 can be configured to dynamically deflect the electron beam to scan a desired area on the surface of the sample 308. The dynamic deflection of the electron beam may cause the desired area or region of interest to be iteratively scanned, for example, in a raster scan pattern, to generate a secondary electron beam for sample inspection (e.g., 236, 238, and 240 in Figure 2A). The deflector 309-1 or 309-2 can be configured to deflect the electron beam in the X-axis or Y-axis direction. The X and Y axes used here form the Cartesian coordinates of an arbitrary reference frame, and the electron beam can propagate along the Z-axis or primary optical axis 304. In the diagrams of Figures 2A, 2B, or 3A, the X-axis refers to a horizontal or transverse axis extending along the width of the paper, and the Y-axis refers to a vertical axis extending in and out of the plane of the paper.

[0051]

[0062] Referring now to Figure 3B, which shows a diagram of a charged particle beam passing through a deflector according to an embodiment of the present disclosure. In some embodiments, the charged particle beam may be deflected as it passes through a region between a pair of electrodes 335 and 345 of the deflector (such as electrodes e2 and e4 in the subsequent Figure 3C). As shown in Figure 3B, the charged particle beam 320 can move along an axis 350. The axis 350 may be aligned with the Z-axis of the charged particle beam system. Electrodes 335 and 345 can be positioned on either side of axis 350. A voltage can be applied to electrodes 335 and 345. An electric field is formed between the electrodes, and the components of the electric field are substantially perpendicular to the direction of propagation of the charged particle beam 320. The charged particle beam 320 may be affected by the electric field as it passes through the resulting electric field. For example, its trajectory may be altered. A deflection scanning unit can use the deflector to deflect the beam and scan the beam over a region on a sample.

[0052]

[0063] Referring now to Figure 3C, which shows the configuration of electrodes for a deflector according to an embodiment of the present disclosure. Figure 3C shows a multi-pole structure with four electrodes e1 to e4, which can be configured to function in different ways based on the voltage applied to each electrode. A deflector (e.g., deflector 309-1 or 309-2 in Figure 3A) can be formed using electrodes e1 to e4. In some embodiments, a deflection voltage may be formed between opposing electrode pairs (e.g., a pair formed by electrodes e2 and e4, or a pair formed by electrodes e1 and e3). Combining multiple electrode pairs enables deflection in a two-dimensional plane. For example, a first electrode pair (e.g., electrodes e2 and e4) can operate to deflect the beam in the X direction, and a second electrode pair (e.g., electrodes e1 and e3) can operate to deflect the beam in the Y direction. The deflector may be located within the area of ​​the objective lens of the SEM system. The deflector can be used to dynamically guide the beam to a desired position on the sample surface. In some embodiments, there may be multiple beams that can be guided to multiple locations on the sample surface.

[0053]

[0064] As shown in Figure 3A, the deflection scan unit may include two deflectors 309-1 and 309-2 stacked in the Z direction and configured to work together to precisely manipulate the beam. In this configuration, precise and accurate operation of the deflectors becomes even more important, as even a small error in one or both deflectors could cause the beam trajectory to deviate further from the intended trajectory. While the deflection scan unit (e.g., the deflection scan unit 226 in Figure 2A) or the deflector unit (e.g., the deflector unit 132c in Figure 2B) is shown to comprise two deflectors 309-1 and 309-2, each having four electrodes e1 to e4, it should be noted that embodiments of this disclosure are not limited to the configurations shown in Figures 3A to 3C, and any number of deflectors with any number of electrodes can be used. It will also be understood that any pair of electrodes can be controlled to deflect the beam in any direction other than the X or Y directions.

[0054]

[0065] Referring here to Figure 4, Figure 4 shows an exemplary configuration of a deflection control unit 400 associated with charged particle beam deflectors (e.g., primary electron beam deflectors 309-1 and 309-2) according to an embodiment of the present disclosure. As shown, each primary electron beam deflector may be electronically driven by a corresponding driver system. For example, the deflection control unit 400 may comprise a driver system 425-1 associated with primary electron beam deflector 309-1 and a driver system 425-2 associated with primary electron beam deflector 309-2. As shown in Figure 4, deflector 309-1 can be implemented to have four electrodes 401-404, and deflector 309-2 can be implemented to have four electrodes 405-408.

[0055]

[0066] As shown in Figure 4, the deflection control unit 400 may further comprise a scan control unit 450. The scan control unit 450 may be configured to generate deflection signals 430-1 to 430-4 configured to be applied to primary electron beam deflectors 309-1 and 309-2. The deflection signals 430-1 to 430-4 may include voltage / current signals applied to the corresponding (one or more) electrodes of the primary electron beam deflectors. While Figure 4 shows that the deflection control unit 400 comprises a single scan control unit 450 configured to generate and supply deflection signals for multiple driver systems (e.g., 425-1 and 425-2), it should be understood that in embodiments of this disclosure, any number of scan control units 450 may be used, and a separate scan control unit may be used for each driver system.

[0056]

[0067] In some embodiments, the scan control unit 450 can generate multiple deflection signals corresponding to multiple electrodes 401-408 of deflectors 309-1 and 309-2. As shown in Figure 4, the scan control unit 450 can generate deflection signals 430-1-430-4 for operating electrodes 401-408 of deflectors 309-1 and 309-2. In some embodiments, the driver system (e.g., driver system 425-01 or 425-2) may include multiple DACs to convert the deflection signals (e.g., deflection signals 430-1-430-4) into analog deflection signals if the deflection signals are digital signals. In some embodiments, the driver system (e.g., driver system 425-1 or 425-2) may further include one or more power amplifiers configured to generate drive signals (e.g., drive signals 431-438) corresponding to the deflection signals (e.g., deflection signals 430-1-430-4). Although not shown, it should be understood that the driver system (e.g., driver system 425-1 or 425-2) may include other components and circuits, such as a variable gain amplifier, power supply, and timing circuitry, as necessary to manipulate the primary electron beam moving along the primary optical axis (e.g., primary optical axis 304 in Figure 3A). In some embodiments, the driver system 425-1 or 425-2 may also include circuits for calibration, offset and gain adjustment, scan pattern generation, or diagnostics, but these may not be described in this disclosure for the sake of brevity. In some embodiments, a pair of electrodes can be controlled to deflect the beam in a predetermined direction. For example, the first electrode pair 402 and 404 can be controlled to deflect the beam in the X direction, and the second electrode pair 401 and 403 can be controlled to deflect the beam in the Y direction. To deflect the beam in the X direction, drive signals 432 and 434 (e.g., +V) having the same absolute value and opposite polarity are used. X and V X A first electrode pair 402 and 404 can be subjected to a similar signal. Similarly, to deflect the beam in the Y direction, drive signals 431 and 433 (e.g., +V) having the same absolute value and opposite polarity can be applied. Y and -V Y) can be added to the second electrode pair 401 and 403. It will be understood that other electrode pairs (e.g., a third electrode pair 406 and 408 and a fourth electrode pair 405 and 407) can be controlled in a similar manner to deflect the beam in a specific direction.

[0057]

[0068] Referring here to Figure 5, Figure 5 shows an architecture of a deflector driver system with a pseudo-differential amplifier utilizing dual single-ended power amplifiers. In some embodiments, the driver system 500 may be the driver system 425-1 or 425-2 of Figure 4 for driving deflector electrodes, for example, deflector electrodes 401-408. The driver system 500 can be configured to receive a deflection signal and generate a high-voltage drive signal for the deflector electrodes. As shown in Figure 5, the driver system 500 may include a pattern generator 510 and a deflection driver 520.

[0058]

[0069] In some embodiments, the deflection pattern generator 510 may include one or more digital-to-analog converters (DACs) that convert (one or more) digital deflection signals into (one or more) analog deflection signals. Figure 5 shows that the deflection pattern generator 510 includes two DACs 511-1 and 511-2. As shown in Figure 5, the first DAC 511-1 is configured to receive a first digital deflection signal 501-1 and generate differential analog deflection signals 502-1 and 502-2. The first differential analog deflection signal 502-1 and the second differential analog deflection signal 502-2 may have the same absolute value but opposite polarity (e.g., +S and -S). In some embodiments, the first digital deflection signal 501-1 may be a signal for manipulating the beam in a specific direction (e.g., the X direction). The first differential analog deflection signal 502-1 and the second differential analog deflection signal 502-2 each have a value of +S X and -S XIt can have. Similarly, as shown in FIG. 5, the second DAC 511-2 is configured to receive the second digital deflection signal 501-2 and generate differential analog deflection signals 502-3 and 502-4. The second digital deflection signal 501-2 may be a signal for operating the beam in a different direction (e.g., the Y direction). The third and fourth differential analog deflection signals 502-3 and 502-4 can have values of +S Y and S Y respectively.

[0059]

[0070] As shown in FIG. 5, the pattern generator 510 may further include other components and circuits such as various amplifiers. For example, the pattern generator 510 can include transimpedance amplifiers 512-1 to 512-4 to convert the impedance of the analog deflection signals 502-1 to 502-4. In some embodiments, after the transimpedance amplifiers 512-1 to 512-4 convert the impedance, for example, from current to voltage, the analog deflection signals 502-1 to 502-4 can be in the form of +V X , -V X , +V Y , and -V Y respectively. As shown in FIG. 5, the pattern generator 510 can further include an additional amplifier 513 configured to amplify the deflection signal. The amplifier 513 can be configured to correct the common-mode voltage of the deflection signal transmitted to the deflection driver 520. As shown in FIG. 5, the amplifier 513 may be a fully differential amplifier that receives differential inputs and has differential outputs. By using a fully differential amplifier, the problem of EMI coupling along the transmission path can be reduced. In some embodiments, a portion of the deflection signal can be superimposed before being provided as an input to the amplifier 513. In some embodiments, a deflection signal with a positive polarity can be superimposed and provided as one differential input to the amplifier 513, and a deflection signal with a negative polarity can be superimposed and provided as another differential input to the amplifier 513. In FIG. 5, the first analog deflection signal 502-1 (+V X ) and the third analog deflection signal 502-3 (+VY ) is superimposed to form the first superimposed signal 503-1(+V X and +V Y The sum of the above is formed and provided as the first differential input to amplifier 513. Similarly, the second analog deflection signal 502-2(-V) is formed. X ) and the fourth analog deflection signal 502-4(-V Y ) is superimposed to create the second superimposed signal 503-2(-V X and -V Y The sum of the above is formed and provided as a second differential input to amplifier 513.

[0060]

[0071] As shown in Figure 5, after the deflection signals 502-1 to 502-4 are impedance-converted, superimposed, or amplified by the pattern generator 510, the deflection signals 502-1 to 502-4 can be provided to the deflection driver 520. In some embodiments, the deflection driver 520 may include a pseudo-differential power amplifier 515 configured to generate different high-voltage drive signals. As shown in Figure 5, the pseudo-differential power amplifier 515 may be implemented with two separate single-ended power amplifiers 515-1 and 515-2. In Figure 5, the first single-ended power amplifier 515-1 receives the first superimposed signal 503-1 (e.g., +V X and +V Y The total of the above is received, and the first superimposed drive signal 504-1 (e.g., +V OX and +V OY The second single-ended power amplifier 515-2 can be configured to output the second superimposed signal 503-2 (for example, -V). X and -V Y The system receives the sum of the two superimposed drive signals 504-2 (e.g., -V) and the second superimposed drive signal 504-2 (e.g., -V) OX and -V OYThey can be configured to output the sum of (V). In some embodiments, if the inputs to the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are differential signals with opposite polarity and the same absolute value, the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 can be configured to generate differential output signals with opposite polarity and the same absolute value. In Figure 5, the inputs to the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are differential signals with opposite polarity and the same absolute value (V X and V Y Since (the sum of) the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 can function as if they were a single differential amplifier producing differential output signals. In this regard, the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are collectively referred to as pseudo-differential amplifiers in this disclosure.

[0061]

[0072] In some embodiments, the output of the deflection driver 520 is a superimposed output signal and can therefore be split before being applied to the corresponding electrode. For example, using the first superimposed drive signal 504-1, the drive signal +V can be applied to the corresponding electrode, for example, electrode e2 in Figure 3C or electrode 402 in Figure 4, before being applied to the corresponding electrode. OX The drive signal +V is applied to electrode e1 in Figure 3C or electrode 401 in Figure 4. OY Before applying, the two drive signals +V OX and +V OY This can be generated. Similarly, the second superimposed drive signal 504-2 can be used to apply the drive signal V to the corresponding electrode, for example, electrode e4 in Figure 3C or electrode 404 in Figure 4, before it is applied to the corresponding electrode. OX The drive signal -V is applied to electrode e3 in Figure 3C or electrode 403 in Figure 4. OY Two drive signals -V before applying OX and -V OYThis can generate the following. As shown in Figure 5, the deflection driver 520 may further include another differential amplifier 514 to cancel or minimize common-mode noise injected along the path from the pattern generator 510 to the pseudo-differential power amplifier 515.

[0062]

[0073] While the driver system 500 is shown to be configured to generate drive signals for manipulating the beam in both the X and Y directions, it will be understood that the driver system 500 can be configured to generate drive signals for manipulating the beam in one direction. For example, the driver system 500 can be configured to generate drive signals for manipulating the beam in the X direction. In these embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified before being input to the power amplifiers 515-1 and 515-2 by considering the coordinates of the wafer on the wafer stage in comparison to the coordinates of the deflector electrodes. For example, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified to generate a differential signal representing the actual deflection control signal in the X direction. In some embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified based on the coordinates of the wafer on the wafer stage, the coordinates of the deflector electrodes, and the rotation angles of the wafer coordinates and the deflector electrode coordinates. In these embodiments, the outputs of power amplifiers 515-1 and 515-2 may be differential drive signals to electrodes controlled to deflect the beam in the X direction (e.g., the first electrode pair e2 and e4 in Figure 3C, or the first electrode pair 402 and 404 in Figure 4). Similarly, in some embodiments, an additional driver system similar to driver system 500 may be used to generate drive signals for manipulating the beam in the Y direction. In these embodiments, the outputs of the power amplifiers of the additional driver system may be differential drive signals to electrodes controlled to deflect the beam in the Y direction (e.g., the second electrode pair e1 and e3 in Figure 3C, or the second electrode pair 401 and 403 in Figure 4).

[0063]

[0074] Referring now to Figure 6, which shows a single-ended power amplifier circuit configuration. The single-ended power amplifier 600 may be either the first single-ended power amplifier 515-1 or the second single-ended power amplifier 515-2 in Figure 5. The single-ended power amplifier 600 may include an input stage 610, a bias stage 620, a gain stage 630, and an output stage 640. The bias stage 620 provides the single-ended power amplifier 600 with current to drive all the transistors included in the single-ended power amplifier 600. The current from the bias stage 620 is sent to the input stage 610. At the input stage 610, the first input signal 601-1 and the second input signal 601-2 are input to the input stage 610. As shown in Figure 6, the input stage 610 can be implemented by including various transistors such as Q1, Q2, Q6, Q7, Q10A, Q10B, and Q13, and is configured to measure the difference signal between two input signals 601-1 and 601-2 and send the difference signal to the gain stage 630. In the gain stage 630, the difference signal can be amplified by a predetermined gain. In some embodiments, the difference signal can be amplified to a high voltage greater than 100V in the gain stage 630. In some embodiments, a high voltage greater than 100V can be achieved by utilizing a cascaded number of transistors operating at lower voltages. Although not shown in Figure 6, the gain stage 630 may further include a phase compensation capacitor to prevent internal oscillation. The amplified difference signal proceeds to the output stage 640, which acts as a buffer to prevent the characteristics of the single-ended power amplifier 600 from fluctuating based on the influence of loads such as resistors connected to the output terminals. In the output stage 640, a high current can be supplied to improve the slew rate of the power amplifier. In Figure 6, the output stage 640 further includes a current limiter, which includes transistors Q12 and Q17, to protect the circuit from high current while improving the slew rate by using high current.As shown in Figure 6, power supplies +Vs and -Vs are supplied to the single-ended power amplifier circuit, and a single output signal 603 is taken from the output terminal OUT. The single-ended power amplifier 600 can be integrated into a single IC chip.

[0064]

[0075] Returning to Figure 5, the driver system 500 is implemented using a first single-ended power amplifier 515-1 and a second single-ended power amplifier 515-2, each constituting a single IC chip. Using separate IC chips inevitably results in element mismatches, even with the selection of the most accurate components and thorough optimization of the PCB design. Element mismatches further limit the common-mode rejection ratio (CMRR), leading to higher noise levels and lower image resolution, and further limiting signal linearity, resulting in higher image distortion. Furthermore, multi-chip implementation increases design complexity and extra circuit adjustment work, limiting mass production. Multi-chip implementation also suffers from lower design consistency between the two separate chips, and this design consistency makes troubleshooting problems caused by mismatches between the two chips difficult. In addition, the driver system 500, utilizing a pseudo-differential power amplifier, suffers from high noise levels, at least partially resulting from the low common-mode rejection ratio due to element mismatches between the two single-ended power amplifiers. Furthermore, because the two IC chips occupy limited space on the PCB, the deflection driver 520 is mounted on a separate PCB from the pattern generator 510, which includes multiple DACs 511-1 and 511-2. This leads to the mounting of additional components (e.g., amplifiers 513 and 514) on the PCB. The long signal transmission distance resulting from the use of two separate PCBs introduces additional noise into the system, potentially exacerbating the noise problems of the driver system 500. Consequently, the driver system 500 does not meet the noise standards required for current and next-generation systems, such as less than 2.5 nV / sqrt(Hz).

[0065]

[0076] Referring here to Figure 7, Figure 7 shows a driver system architecture with a fully differential power amplifier according to an embodiment of the present disclosure. In some embodiments, the driver system 700 may be the driver system 425-1 or 425-2 of Figure 4 for driving deflector electrodes, for example, deflector electrodes 401-408. The driver system 700 may be configured to receive a deflection signal and generate a high-voltage fully differential drive signal. According to some embodiments of the present disclosure, the driver system 700 may also include a pattern generator 710 and a deflection driver 720.

[0066]

[0077] According to some embodiments of this disclosure, the pattern generator 710 may include one or more DACs (e.g., DACs 511-1 and 511-2) that convert (one or more) digital deflection signals into (one or more) analog deflection signals. In some embodiments, the pattern generator 710 may further include transimpedance amplifiers 512-1 to 512-4 for converting the impedance of the analog deflection signals 502-1 to 502-4. As indicated by the same reference numerals, the DACs 511-1 and 511-2 and transimpedance amplifiers 512-1 to 512-4 of the pattern generator 710 in Figure 7 may be the same as or similar to the DACs 511-1 and 511-2 and transimpedance amplifiers 512-11 to 512-4 of the pattern generator 510 in Figure 5. Therefore, for the sake of brevity, redundant explanations regarding the operation and function of the DACs 511-1 and 511-2 and the transimpedance amplifiers 512-1 to 512-4 of the pattern generator 710 in Figure 7 are omitted here.

[0067]

[0078] According to some embodiments, the deflection driver 720 may include a fully differential power amplifier 715 configured to receive a differential input and generate a high-voltage differential output. As shown in Figure 7, the differential power amplifier 715 receives a first superimposed signal 503-1 (e.g., +V X and +V Y (total of) and the second superimposed signal 503-2 (for example, -V Xand -V Y The differential power amplifier 715 can be configured to receive the first superimposed drive signal 704-1 (e.g., +V) as a differential input. In some embodiments, the differential power amplifier 715 can be configured to receive the total of the first superimposed drive signals 704-1 (e.g., +V) as a differential input. OX and +V OY (total of) and the second superimposed drive signal 704-2 (e.g., -V OX and -V OY It can also be configured to output the sum of the two signals as a differential output. As shown in Figure 7, since the deflection driver 720 is positioned adjacent to the pattern generator 710 on the same PCB 701, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be provided to the differential power amplifier 715 without the need for an additional low-voltage fully differential amplifier. Furthermore, because the deflection driver 720 is positioned adjacent to the generator 710, common-mode noise that may be injected along the path between the deflection driver 720 and the pattern generator 710 can be minimized or reduced.

[0068]

[0079] In some embodiments, the output of the deflection driver 720 is a superimposed output signal and can therefore be split before being applied to the corresponding electrode. For example, using the first superimposed drive signal 704-1, the drive signal +V can be applied to the corresponding electrode, for example, electrode e2 in Figure 3C or electrode 402 in Figure 4, before being applied to the corresponding electrode. OX The drive signal +V is applied to electrode e1 in Figure 3C or electrode 401 in Figure 4. OY Before applying, the two drive signals +V OX and +V OY This can be generated. Similarly, the second superimposed drive signal 704-2 can be used to apply the drive signal V to the corresponding electrode, for example, electrode e4 in Figure 3C or electrode 404 in Figure 4, before it is applied to the corresponding electrode. OX The drive signal -V is applied to electrode e3 in Figure 3C or electrode 403 in Figure 4. OY Two drive signals -V before applying OX and -V OY It can generate [this].

[0069]

[0080] While the driver system 700 is shown to be configured to generate drive signals for manipulating the beam in both the X and Y directions, it will be understood that the driver system 700 can be configured to generate drive signals for manipulating the beam in one direction. For example, the driver system 700 can be configured to generate drive signals for manipulating the beam in the X direction. In these embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified before being input to the differential power amplifier 715 by considering the coordinates of the wafer on the wafer stage in comparison to the coordinates of the deflector electrodes. For example, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified to generate a differential signal that represents the actual deflection control signal in the X direction. In some embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified based on the coordinates of the wafer on the wafer stage, the coordinates of the deflector electrodes, and the rotation angles of the wafer coordinates and the deflector electrode coordinates. In these embodiments, the output of the differential power amplifier 715 may be a differential drive signal to electrodes controlled to deflect the beam in the X direction (e.g., the first electrode pair e2 and e4 in Figure 3C, or the first electrode pair 402 and 404 in Figure 4). Similarly, in some embodiments, an additional driver system similar to the driver system 700 can be used to generate a drive signal for manipulating the beam in the Y direction. In these embodiments, the output of the differential power amplifier of the additional driver system may be a differential drive signal to electrodes controlled to deflect the beam in the Y direction (e.g., the second electrode pair e1 and e3 in Figure 3C, or the second electrode pair 401 and 403 in Figure 4).

[0070]

[0081] Referring now to Figure 8, Figure 8 shows a fully differential power amplifier circuit configuration according to an embodiment of the present disclosure. In some embodiments, the differential power amplifier circuit 715 may be a fully differential power amplifier 715 included in the deflection driver 720 of Figure 7. According to some embodiments of the present disclosure, the differential power amplifier 715 may include an input stage 610, two bias stages 620 and 820, two gain stages 630 and 830, and two output stages 640 and 840. Similar to the single-ended power amplifier 600 of Figure 6, the input stage 610, the first bias stage 620, the first gain stage 630, and the first output stage 640 of Figure 8 may be configured to generate a first output 603-1 from among the differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, the input stage 610, the first bias stage 620, the first gain stage 630, and the first output stage 640 in Figure 8 amplify the difference signal between the two input signals 601-1 and 601-2 input to the input stage 610, thereby producing a positive output +V OIt can be configured to generate a second output 603-2 from among the differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, the input stage 610, second bias stage 820, second gain stage 830, and second output stage 840 in Figure 8 can be configured to generate a negative output -Vo by amplifying the difference signal between two input signals 601-1 and 601-2 input to the input stage 610. As indicated by the same reference numerals, the input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 in Figure 8 may be the same as or similar to the input stage 610, bias stage 620, gain stage 630, and output stage 640 in Figure 6. Furthermore, as shown in Figures 6 and 8, the second bias stage 820, second gain stage 830, and second output stage 840 of the differential power amplifier 715 in Figure 8 can be implemented by mirroring the first bias stage 620, first gain stage 630, and first output stage 640 with some modifications, thereby causing the second bias stage 820, second gain stage 830, and second output stage 840 to produce a second output 603-2 having the same absolute value as the first output signal 603-1 with opposite polarity. Thus, as explained with reference to Figure 6, the two differential outputs 603-1 and 603-2 can be high-voltage differential signals that meet industry-required standards, such as being greater than 100V.

[0071]

[0082] According to some embodiments of the present disclosure, the differential power amplifier 715 may further include a common-mode control circuit 810. According to some embodiments, the common-mode control circuit 810 may include an error amplifier 811. In some embodiments, the error amplifier 811 converts the common-mode voltages of the differential outputs 603-1 and 603-2 to a reference voltage V REFIt can be configured to compare with the following. As shown in Figure 8, the error amplifier 811 is coupled to the differential outputs 603-1 and 603-2 and configured to receive the common-mode voltage of the two differential outputs 603-1 and 603-2 as a feedback input via the first input terminal 812. In some embodiments, the common-mode control circuit 810 may further include two resistors 814 and 815. In Figure 8, the first resistor 814 is coupled between the first input terminal 812 and the first output terminal +OUT of the error amplifier 811, and the second resistor 815 is coupled between the first input terminal 812 and the second output terminal -OUT of the error amplifier 811. In some embodiments, the first resistor 814 and the second resistor 815 may have the same resistance value so that the common-mode voltage as the median of the two differential output signals 603-1 and 603-2 can be measured and input as a feedback input at the first input terminal 812. As shown in Figure 8, the error amplifier 811 uses the reference voltage V as a reference input via the second input terminal 813. REF It can be configured to receive the following. According to some embodiments of the present disclosure, the error amplifier 811 is configured to compare the feedback input with a reference input and output the difference 816 between the feedback input and the reference input. As shown in Figure 8, the difference 816 is provided to the differential power amplifier 715 and the output signals 603-1 and 603-2 are adjusted to cancel out the difference 816. For example, the output signals 603-1 and 603-2 can be adjusted according to the difference 816, thereby the common-mode voltages of the two output signals 603-1 and 603-2 are adjusted to cancel out the reference voltage V REF It can be equal to the reference voltage V. In some embodiments, the reference voltage V REFThe difference can be set to a value of 0V. As shown in Figure 8, the difference 816 can be supplied to the first gain stage 630 to adjust the first output signal 603-1 and to the second gain stage 830 to adjust the second output signal 603-2. In some embodiments, if a non-zero value is supplied to the gain stages 630 and 830 as the difference 816, the output signals 603-1 and 603-2 can be adjusted to cancel out the difference. In some embodiments, the common-mode control circuit 810 is a closed-loop feedback circuit and is configured to automatically adjust the output.

[0072]

[0083] According to some embodiments of this disclosure, the fully differential power amplifier 715 can be manufactured using high-voltage semiconductor manufacturing processes that support voltages greater than 100V. In some embodiments, the fully differential power amplifier 715 can be manufactured using high-voltage-resistant semiconductor materials such as gallium nitride and silicon carbide. In some embodiments, the fully differential power amplifier 715 can be manufactured without using complementary metal-oxide-semiconductor (CMOS), which is generally used for low-voltage devices. In some embodiments, the fully differential power amplifier 715 can be realized operating at voltages greater than 100V by utilizing a cascaded set of transistors, each operating at a lower voltage. According to some embodiments of this disclosure, the fully differential power amplifier 715 can be integrated onto a single IC chip, which eliminates the problem of element mismatch between two separate components. This allows the fully differential power amplifier 715 to exhibit an improved common-mode rejection ratio (CMSS) without the need to resolve the element mismatch problem. Because the fully differential power amplifier 715 is a true differential amplifier and not a pseudo-differential amplifier, the fully differential power amplifier 715, with its better element matching, can improve linearity, resulting in reduced image distortion. In the fully differential power amplifier 715, even-order distortion terms can be canceled out at the fully differential output. As shown in Figures 1 and 8, the fully differential power amplifier 715 is implemented to have two differential outputs using a common input stage (e.g., input stage 610), so the area occupied by the fully differential power amplifier 715 can be reduced compared to two single-ended power amplifiers. Therefore, the fully differential power amplifier 715 can be integrated into a single IC chip that can be mounted on the same PCB as the pattern generator 710, which prevents the inclusion of additional components (such as the additional amplifiers 513 and 514 in Figure 5) in the driver system 700. The reduction in components on the driver system 700 and the reduction in signal transmission distance can also lead to a reduction in system noise.According to some embodiments of this disclosure, the driver system 700 can meet noise criteria required for current and next-generation systems, such as less than 2.5 nV / sqrt(Hz), while the high-voltage drive signal meets requirements such as high voltage (greater than 100V), high speed (power bandwidth greater than 1 MHz), and slew rate (greater than 500 V / μs). If the drive signal is kept below 100V, it may not be possible to achieve industry scan rate requirements (e.g., 1.2 gigasamples / second) without sacrificing signal quality. For example, if a drive signal below 100V is used, 1.2 gigasamples / second can be achieved by using a more sensitive deflector, but ultimately the image resolution will be reduced. Therefore, in this disclosure, a higher voltage level can refer to a voltage level greater than 100V that can support industry scan rate requirements, e.g., 1.2 gigasamples / second, without sacrificing signal quality.

[0073]

[0084] Furthermore, according to some embodiments of this disclosure, the driver system 700 can provide greater design integrity and increased commonality of circuit components, which leads to simplified PCB design and benefits future RACK-based deflection driver designs. According to some embodiments of this disclosure, the increased commonality of circuit components reduces the volume of circuitry required to supply higher voltages than conventional systems. According to some embodiments of this disclosure, the driver system 700 can provide lower power consumption, which in turn simplifies heatsink design and helps achieve higher slew rates. According to some embodiments of this disclosure, the driver system 700 can provide a simplified circuit tuning strategy, which in turn improves production capacity for mass production. According to some embodiments of this disclosure, the common-mode control circuit 800 is also integrated into the same IC chip as the fully differential amplifier, which can improve slew rates compared to embodiments that have the feedback loop in the PCB area.

[0074]

[0085] Figure 9 is a flowchart illustrating an exemplary method for operating a deflector driver with a fully differential power amplifier according to embodiments of the present disclosure. The steps of Method 900 can be performed by a deflector driver system, for example, the driver system 700 of Figure 7, which includes a fully differential power amplifier 715. It will be understood that Method 900 as shown can be modified to change the order of the steps or to include additional steps.

[0075]

[0086] In step S910, a fully differential output is generated by the fully differential power amplifier 715. In some embodiments, the fully differential output may have an absolute value greater than 100V. In step S920, the common-mode voltage of the differential output of the differential amplifier is measured by the common-mode control circuit 810. In step S930, the difference between the common-mode voltage and the reference voltage is returned to the differential amplifier. In some embodiments, the difference can be provided to the gain stage of the differential amplifier. In step S940, the differential output can be adjusted based on the difference, thereby canceling the difference. In some embodiments, the adjusted fully differential output can be applied to multiple deflector electrodes to influence the charged particle beam of a charged particle inspection device based on the fully differential output.

[0076]

[0087] The processor of the controller (for example, controller 109 in Figure 1) may be provided with a non-temporary computer-readable medium that stores instructions for performing methods 900, including, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, focusing lens adjustment, charged particle source activation, beam deflection, and other operations. Common forms of non-temporary media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, compact disk read-only memory (CD-ROM), any other optical data storage media, any physical medium having a pattern of holes, random access memory (RAM), programmable read-only memory (PROM), and erasable programmable read-only memory (EPROM), FLASH-EPROM or any other flash memory, non-volatile random access memory (NVRAM), caches, registers, other memory chips or cartridges, and networked versions thereof.

[0077]

[0088] Embodiments can be further described using the following clauses. 1. A charged particle inspection device, A charged particle beam source configured to generate a primary charged particle beam for sample scanning, A deflector driver including a fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V, Multiple deflector electrodes coupled to a fully differential output and configured to influence the charged particle beam based on the fully differential output, A charged particle inspection device equipped with the following features. 2. The differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V, as described in Clause 1. 3. The apparatus according to Clause 1 or 2, wherein the deflector driver further includes multiple digital-to-analog converters (DACs) whose outputs are used to generate input differential signals for a fully differential amplifier, and the multiple DACs and the fully differential amplifier are mounted on a single printed circuit board. 4. The apparatus according to any one of the clauses 1 to 3, wherein the deflector driver further includes a common-mode control circuit configured to measure the common-mode voltage of the fully differential output of a fully differential amplifier and provide the fully differential amplifier with the difference between the common-mode voltage and a reference voltage, thereby adjusting the fully differential output of the differential amplifier based on the difference, and the fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip. 5. A fully differential amplifier is an apparatus as described in any of clauses 1 to 4, configured to operate with a power bandwidth greater than 1 MHz. 6. A fully differential amplifier is an apparatus as described in any of clauses 1 to 5, configured to operate at a slew rate greater than 500 V / μs. 7. A fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt(Hz), as described in any of the devices described in clauses 1 to 6. 8. A deflector driver for driving a deflector of a charged particle inspection device, the deflector driver comprising a fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V, wherein the fully differential output allows multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output. 9. A fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V, as described in Clause 8. 10. The deflector driver further comprises multiple digital-to-analog converters (DACs) whose outputs are used to generate input differential signals for a fully differential amplifier, and the multiple DACs and the fully differential amplifier are mounted on a single printed circuit board, as described in Clause 8 or 9. 11. The deflector driver further includes a common-mode control circuit configured to measure the common-mode voltage of the fully differential output of a fully differential amplifier and provide the fully differential amplifier with the difference between the common-mode voltage and a reference voltage, thereby adjusting the fully differential output of the fully differential amplifier based on the difference, wherein the fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip, as described in any of Clauses 8 to 10. 12. A fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz, as described in any of clauses 8 to 11 of the deflector driver. 13. A fully differential amplifier is configured to operate with a slew rate greater than 500 V / μs, as described in any of Clauses 8-12 of the deflector driver. 14. A fully differential amplifier is configured to operate with a noise level of less than 2.5 nV / sqrt(Hz) as described in any of clauses 8 to 13 of the deflector driver. 15. A method for operating a deflector driver for driving a deflector in a charged particle inspection apparatus, the method being: The fully differential amplifier included in the deflector driver generates a fully differential output with an absolute value greater than 100V, The common-mode control circuit included in the deflector driver measures the common-mode voltage of the fully differential output of the fully differential amplifier, and The common-mode control circuit provides the difference between the common-mode voltage and the reference voltage to a fully differential amplifier, Adjusting the fully differential output of the differential amplifier based on the difference and Includes, The tuned fully differential output allows the multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output. A method by which a fully differential amplifier and a common-mode control circuit are integrated into a single integrated circuit (IC) chip. 16. The method according to Clause 15, further comprising generating an input differential signal for a fully differential amplifier by utilizing multiple digital-to-analog converters (DACs) included in the deflector driver, wherein the multiple DACs and the fully differential amplifier are mounted on a single printed circuit board. 17. A fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V, according to the method of Clause 15 or 16. 18. A fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz, as described in any of clauses 15-17. 19. A fully differential amplifier is configured to operate at a slew rate greater than 500 V / μs, as described in any of clauses 15-18. 20. A fully differential amplifier is configured to operate with a noise level of less than 2.5 nV / sqrt(Hz) as described in any of clauses 15-19. 21. A deflector driver assembly, A fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V, A common-mode control circuit configured to measure the common-mode voltage of the fully differential output of a fully differential amplifier and to provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier. Equipped with, The fully differential amplifier is further configured to adjust the fully differential output of the differential amplifier based on the difference, and the adjusted fully differential output allows multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output, and the fully differential amplifier and common-mode control circuit are integrated into a single integrated circuit (IC) chip, forming a deflector driver assembly. 22. A deflector driver assembly as described in Clause 21, further comprising multiple digital-to-analog converters (DACs) configured to generate input differential signals for a fully differential amplifier, wherein the multiple DACs and the fully differential amplifier are mounted on a single printed circuit board. 23. A fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V, as described in Clause 21 or 22, for the deflector driver assembly. 24. A fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz, as described in any of the deflector driver assemblies in Clauses 21-23. 25. A fully differential amplifier is configured to operate at a slew rate greater than 500 V / μs, as described in any of the deflector driver assemblies in Clauses 21-24. 26. A fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt(Hz) in any of the deflector driver assemblies described in any of clauses 21 to 25.

[0078]

[0089] The block diagrams in the figures may illustrate possible architectures, functions, and operations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic diagram may represent a specific arithmetic or logical operation that can be performed using hardware such as an electronic circuit. A block may also represent a module, segment, or portion of code containing one or more executable instructions for performing a specified logical function. In some alternative embodiments, it should be understood that the functions shown in the blocks may be performed in a different order than shown in the figures. For example, two consecutively shown blocks may be executed or performed substantially simultaneously, or two blocks may be executed in reverse order, depending on the functions they relate to. Also, some blocks may be omitted. It should also be understood that each block and combination of blocks in the block diagram may be performed by a dedicated hardware-based system or by a combination of dedicated hardware and computer instructions for performing a specified function or action.

[0079]

[0090] It will be understood that the embodiments of this disclosure are not limited to the exact configurations described above and shown in the accompanying drawings, and that various modifications and changes may be made without departing from their scope. Although this disclosure has described various embodiments, other embodiments of the invention will become apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This specification and examples are to be considered merely illustrative, and the true scope and spirit of the invention are intended to be shown by the following claims.

Claims

1. A charged particle inspection device, A charged particle beam source configured to generate a primary charged particle beam for sample scanning, A deflector driver including a fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V, A plurality of deflector electrodes coupled to the fully differential output and configured to influence the charged particle beam based on the fully differential output, A charged particle inspection device equipped with the following features.

2. The apparatus according to claim 1, wherein the differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V.

3. The apparatus according to claim 1, wherein the deflector driver further includes a plurality of digital-to-analog converters (DACs) whose outputs are used to generate input differential signals for the fully differential amplifier, and the plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board.

4. The apparatus according to claim 1, wherein the deflector driver further includes a common-mode control circuit configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and to provide the fully differential amplifier with the difference between the common-mode voltage and a reference voltage so that the fully differential output of the differential amplifier is adjusted based on the difference, and the fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

5. The apparatus according to claim 1, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz.

6. The apparatus according to claim 1, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / μs.

7. The apparatus according to claim 1, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz).

8. A deflector driver for driving a deflector in a charged particle inspection device, the deflector driver comprising a fully differential amplifier configured to produce a fully differential output with an absolute value greater than 100V, the fully differential output enabling a plurality of deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output.

9. The deflector driver according to claim 8, wherein the fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V.

10. The deflector driver according to claim 8, further comprising a plurality of digital-to-analog converters (DACs) whose outputs are used to generate input differential signals for the fully differential amplifier, wherein the plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board.

11. The deflector driver according to claim 8, further comprising a common-mode control circuit configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and to provide the fully differential amplifier with the difference between the common-mode voltage and a reference voltage so that the fully differential output of the fully differential amplifier is adjusted based on the difference, wherein the fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

12. The deflector driver according to claim 8, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz.

13. The deflector driver according to claim 8, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / μs.

14. The deflector driver according to claim 8, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt(Hz).

15. A method for operating a deflector driver for driving a deflector in a charged particle inspection apparatus, wherein the method is: The deflector driver includes a fully differential amplifier which generates a fully differential output with an absolute value greater than 100V, The common-mode control circuit included in the deflector driver measures the common-mode voltage of the fully differential output of the fully differential amplifier, The common-mode control circuit provides the difference between the common-mode voltage and the reference voltage to the fully differential amplifier, Adjusting the fully differential output of the differential amplifier based on the aforementioned difference. Includes, The adjusted fully differential output allows the multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection apparatus based on the fully differential output. A method in which the fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

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