Plasma processing assembly for RF and PVT integration

Abstract

Embodiments of the present disclosure relate to systems and methods for processing a substrate in a plasma processing system. In one embodiment, a plasma processing system is provided, comprising: a high-frequency (RF) generator coupled to a substrate support base located in the plasma processing system and configured to supply an RF signal to the substrate support base; a pulsed voltage (PV) waveform generator coupled to the substrate support base and configured to supply a PV waveform to the substrate support base while the RF signal is being supplied to the substrate support base; and a high-voltage source coupled to a bias electrode of the plasma processing system and configured to supply a chucking voltage to a bias electrode located in the plasma processing system.

Description

Technical Field

[0001]

[0001] Embodiments of the present invention generally relate to systems and methods used in semiconductor device manufacturing. More specifically, the embodiments provided herein generally include systems and methods for processing a substrate within a plasma processing system.

Background Art

[0002]

[0002] Ensuring the fabrication of high aspect ratio features is one of the important technical challenges for next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process, to form high aspect ratio openings in a material layer (such as a dielectric layer) of a substrate. In a typical RIE plasma process, plasma is formed within a processing chamber, ions from the plasma are accelerated towards the surface of the substrate, and an opening is formed in the material layer disposed under the mask layer formed on the surface of the substrate.

[0003]

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a power electrode. In a capacitively coupled gas discharge, plasma is generated by using a radio frequency (RF) generator coupled to a power electrode disposed within an electrostatic chuck (ESC) assembly or another part of the processing chamber. Typically, an RF matching network (“RF matcher”) adjusts the RF waveform supplied from the RF generator to supply RF power to a 50Ω apparent load, thereby reducing reflected power and improving power supply efficiency. If the impedance of the load is not properly matched to the impedance of the source (e.g., the RF generator), a portion of the RF waveform may reflect and return in the opposite direction along the same transmission line.

[0004]

[0004] In addition, many plasma processes utilize a DC voltage pulse method to control the plasma sheath placed on the substrate being processed. During operation, the high DC voltage pulse is supplied by a high-voltage DC source used to supply a negative bias to the bias electrode, while the pulse voltage (PV) waveform is supplied by the PV waveform simultaneously generated at the bias electrode. The voltage supplied to the bias electrode is equal to the sum of the high DC voltage pulse and the PV waveform. The sum of the voltages on the bias electrode causes overshoot and droop in the combined waveform supplied to the bias electrode. The overshoot causes a high current (current spike) in the combined waveform and arc discharge due to the increase in the electric field generated at the edge of the bias electrode.

[0005]

[0005] Therefore, in the field of the art, there is a need for a plasma processing apparatus that can at least solve the problems outlined above. [Overview of the project]

[0006]

[0006] In one embodiment, a plasma processing system is provided that includes a high-frequency (RF) generator coupled to a substrate support base located within the plasma processing system and configured to supply an RF signal to the substrate support base; a pulse voltage (PV) waveform generator coupled to the substrate support base and configured to supply a PV waveform to the substrate support base while the RF signal is being supplied to the substrate support base; and a high-voltage source coupled to the bias electrode of the plasma processing system and configured to supply a chucking voltage to the bias electrode located with the plasma processing system.

[0007]

[0007] In another embodiment, a plasma processing system is provided which includes a high-frequency (RF) generator configured to generate an RF signal, a pulsed voltage (PV) waveform generator configured to generate a PV waveform, a high-voltage source configured to generate a chucking voltage, and a junction box coupled to the RF generator, the PV waveform generator, and the high-voltage source, the junction box being configured to receive the RF signal, the PV waveform, and the chucking voltage and to supply the RF signal and the PV waveform to a substrate support base of the plasma processing system and to supply the chucking voltage to a bias electrode of the plasma processing system.

[0008]

[0008] In another embodiment, the junction box includes a high-frequency (RF) filter coupled to an RF generator of the plasma processing system and configured to receive an RF signal from the RF generator, a pulsed voltage (PV) filter coupled to a PV waveform generator of the plasma processing system and configured to receive a PV waveform from the PV waveform generator, and a bias compensation module (BCM) coupled to a high-voltage supply of the plasma processing system and configured to receive a chucking voltage from the high-voltage supply, wherein the junction box is configured to transmit the RF signal and PV waveform to a substrate support base of the plasma processing chamber of the plasma processing system and to transmit a chucking voltage to the bias electrode of the plasma processing chamber.

[0009]

[0009] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings are only illustrative embodiments and should not be considered to limit the scope of the Disclosure, as other equally valid embodiments are also permitted. [Brief explanation of the drawing]

[0010] [Figure 1A]

[0010] This is a simplified schematic diagram of a plasma processing system according to one or more embodiments. [Figure 1B]

[0011] This is a schematic cross-sectional view of a plasma processing system that can be configured to perform one or more of the plasma processing methods described herein, according to one or more embodiments. [Figure 2]

[0012] This shows a voltage pulse supplied within a voltage waveform established on a substrate by supplying a voltage pulse to a bias electrode during plasma processing, according to one or more embodiments. [Figure 3A]

[0013] This is a schematic diagram of a bonding box for a plasma processing system according to one or more embodiments. [Figure 3B] This is a schematic diagram of a bonding box for a plasma processing system according to one or more embodiments. [Figure 3C] This is a schematic diagram of a bonding box for a plasma processing system according to one or more embodiments. [Figure 4]

[0014] This is a schematic diagram of an RF power supply system according to one or more embodiments. [Modes for carrying out the invention]

[0011]

[0015] For ease of understanding, the same reference numerals have been used to indicate identical elements common to the figures, where possible. It is intended that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

[0012]

[0016] Embodiments of this disclosure generally relate to systems used in semiconductor manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for reducing the current supplied to the bias electrodes of a plasma processing chamber in order to reduce the probability of arc discharge and increase the voltage margin supplied to the plasma processing chamber.

[0013]

[0017] Figure 1A is a schematic diagram of a plasma processing system. The plasma processing system 10 is configured for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. The plasma processing system 10 can also be used for other plasma-assisted processes, such as plasma-enhanced deposition processes (e.g., plasma chemical vapor deposition (PECVD), plasma physical vapor deposition (PEPVD), plasma atomic layer deposition (PEALD), plasma processing, plasma-based ion implantation, or plasma doping (PLAD). In one configuration, as shown in Figure 1A, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma can alternatively be generated by an inductively coupled source located above the processing area of ​​the plasma processing system 10.

[0014]

[0018] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a high-voltage supply source 173, a radio frequency (RF) generator 171, and an RF matcher 172 (e.g., an RF impedance matching network). The chamber lid 123 includes one or more side walls and a chamber base, which are configured to withstand the pressure and energy applied to them while the plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing.

[0015]

[0019] A gas supply system 182 coupled to the processing space 129 of the processing chamber 100 is configured to supply at least one processing gas from at least one gas processing source 119 to the processing space 129 of the processing chamber 100. The gas supply system 182 includes the processing gas source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 are configured to supply one or more processing gases to the processing space 129 of the processing chamber 100.

[0016]

[0020] The processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) and a lower electrode (e.g., a substrate support assembly 136) located within the processing space 129 of the processing chamber 100. The upper and lower electrodes face each other. In one embodiment, an RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to supply an RF signal for generating and maintaining a plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 can also be electrically coupled to the upper electrode. For example, the RF generator 171 can supply RF source power to an RF base plate in a cathode assembly (e.g., in the substrate support assembly 136) for plasma generation, while the upper electrode is grounded. The center frequency of the RF source power can range from 13.56 MHz to very high frequency bands such as 40 MHz, 60 MHz, 120 MHz, or 162 MHz. In some examples, the RF source power can also be supplied through the upper electrode. The RF source power can operate in continuous mode or pulsed mode. The RF power may have a pulse frequency ranging from 100 Hz to 10 kHz and a duty cycle ranging from 5% to 95%. The RF generator 171 has a frequency tuning function and can adjust the RF power frequency within a range of, for example, ±5% or ±10%. In some embodiments, the RF generator 171 switches the RF power frequency at a predetermined speed (e.g., 2 nanoseconds, 50 nanoseconds, etc.).

[0017]

[0021] The substrate support assembly 136 may be coupled to a high-voltage source 173 that supplies a chucking voltage to the substrate support assembly 136. The RF generator 171 and the high-voltage source 173 may be coupled to a junction box 178 positioned between the high-voltage source 173 and the substrate support assembly 136.

[0018]

[0022] The substrate support assembly 136 is coupled to an RF generator 171 configured to supply an RF signal to the processing space 129 of the processing chamber 100. The RF generator 171 is electrically coupled to a junction box 178 via an RF matcher 172. For example, the RF matcher 172 is an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing space 129 of the processing chamber 100) to optimize power supply efficiency. One or more RF filters (e.g., within the RF matcher 172 or the junction box 178) are designed to allow only power within a selected frequency range and to isolate the RF power supplies from each other. In some cases, the bandwidth of the RF filter must be greater than the frequency tuning range of the RF generator 171. The RF matcher 172 may or may not be included within the junction box 178.

[0019]

[0023] During plasma processing, the RF generator 171 supplies an RF signal to the substrate support assembly 136 via the junction box 178. From the substrate support assembly 136, the RF signal is applied to a load (e.g., gas) within the processing space 129 of the processing chamber 100. If the impedance of the load is not properly matched to the impedance of the source (e.g., the RF generator 171), a portion of the waveform may be reflected and return in the opposite direction. Therefore, in order to prevent a significant portion of the waveform from being reflected back, as the impedances of the source and the load change, an impedance match (e.g., a match point) is maintained by adjusting one or more components of the RF matcher 172.

[0020]

[0024] The RF matcher 172 is electrically coupled to the RF generator 171, the substrate support assembly 136, and a PV waveform generator 175. The RF matcher 172 is configured to receive a synchronization signal from either or both of the RF generator 171 and the PV waveform generator 175.

[0021]

[0025] The PV waveform generator 175 is used to supply a PV waveform and / or an adjusted voltage waveform, which is the sum of harmonic frequencies related to the waveform. The PV waveform generator 175 can output a synchronous TTL signal to the RF matcher 172. The PV waveform generator 175 and the RF generator 171 are coupled to the same electrode of the substrate support assembly 136 (e.g., the substrate support base 107 shown in FIG. 1B) via the bonding box 178. The high voltage supply source 173 is applied to the electrode of the substrate support (e.g., the bias electrode 104 shown in FIG. 1B) to chuck the wafer during the process for thermal control. In some cases, for edge uniformity control, a third electrode may exist at the edge of the substrate support assembly 136.

[0022]

[0026] The RF generator 171 and the PV waveform generator 175 are each directly coupled to the system controller 126. The system controller 126 synchronizes the generated respective RF signal and the PV waveform.

[0023]

[0027] FIG. 1B is a schematic detailed cross-sectional view of the plasma processing system 10. In one configuration, as shown in FIG. 1B, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma 101 can alternatively be generated by using an inductively coupled source disposed above the processing space 129 of the plasma processing system 10. In this configuration, a coil can be placed on top of the ceramic lid (vacuum boundary) of the processing chamber 100.

[0024]

[0028] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, an RF power system 189, and a system controller 126. As shown in Figure 1, the processing chamber 100 includes a chamber body 113 comprising a chamber lid 123, one or more side walls 122, and a chamber base 124. The chamber lid 123, one or more side walls 122, and the chamber base 124 collectively define the processing space 129. The one or more side walls 122 and the chamber base 124 generally include a material (such as aluminum, an aluminum alloy, or a stainless steel alloy) whose size and shape are determined to form a structural support for the elements of the processing chamber 100. The one or more side walls 122 and the chamber base 124 are configured to withstand the vacuum pressure and energy used to maintain the plasma 101 within the processing space 129 of the processing chamber 100. The substrate 103 is brought into the processing space 129 through one of the openings (not shown) in the side wall 122 and removed from the processing space 129. The opening is sealed with a slit valve (not shown) during the plasma processing of the substrate 103.

[0025]

[0029] The gas supply system 182, coupled to the processing space 129 of the processing chamber 100, includes a processing gas source 119 and a gas inlet 128 positioned through the chamber lid 123. The gas inlet 128 is configured to supply one or more processing gases from multiple processing gas sources 119 to the processing space 129.

[0026]

[0030] The processing chamber 100 further includes an upper electrode (e.g., a chamber lid 123) and a substrate support assembly 136 located within the processing space 129. As shown in Figure 1B, in one embodiment, a radio frequency (RF) generator 171 is electrically coupled to a lower electrode (e.g., a substrate support base 107) located within the substrate support assembly 136. The RF generator 171 is configured to supply an RF signal for generating and maintaining a plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 can also be electrically coupled to an upper electrode, such as the chamber lid 123.

[0027]

[0031] The substrate support assembly 136 includes a substrate support 105, a substrate support base 107, an insulating plate 111, a grounding plate 112, a plurality of lift pins 186, one or more substrate potential sensing assemblies 184, and a bias electrode 104. The substrate potential sensing assembly 184 includes a signal detection assembly 188 and one or more sensors 190. The substrate potential sensing assembly 184 is communicably connected to the system controller 126 via a communication line 165. The signal detection assembly 188 generally includes components configured to receive signals from the sensors 190 and form output signals that can be used by the system controller 126. The system controller 126 can then use the received output signals to display results or measurements performed by the sensors 190 and / or control the processing chamber 100 or a portion of the process performed therein. The system controller 126 can convert the output signals received from the sensors into meaningful plasma diagnostic signals that include, but are not limited to, Vdc (plasma voltage on the wafer), ion flux, or other parameters that can be used for improved control of chamber matching, fault detection, RF generator 171, and / or PV generator. One or more sensors 190 are coupled to the signal detection assembly 188 via one or more communication lines 158. Each lift pin 186 is positioned through a through hole 185 formed in the substrate support assembly 136 and is used to facilitate the movement of the substrate 103 to and from the substrate receiving surface 105A of the substrate support 105. The substrate support 105 is formed of a dielectric material. The dielectric material may include bulk sintered ceramic materials, corrosion-resistant metal oxides (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), yttrium oxide (Y2O3)), metal nitride materials (e.g., aluminum nitride (AIN), titanium nitride (TiN)), mixtures thereof, or combinations thereof.

[0028]

[0032] The substrate support base 107 is formed of a conductive material (e.g., aluminum, an aluminum alloy, or a stainless steel alloy). The substrate support base 107 is electrically insulated from the chamber base 124 by an insulating plate 111 and an earth plate 112 interposed between the insulating plate 111 and the chamber base 124. In some embodiments, the substrate support base 107 is configured to regulate the temperature of both the substrate support 105 and the substrate 103 placed on the substrate support 105 during substrate processing. In some embodiments, the substrate support base 107 includes one or more cooling channels (not shown) inside, which are in fluid communication with and fluidly coupled to cooling sources (not shown), such as a refrigerant source or substrate source with relatively high electrical resistance. In other embodiments, the substrate support 105 includes a heater (not shown) for heating the substrate support 105 and the substrate 103 placed on the substrate support 105.

[0029]

[0033] The bias electrode 104 is embedded in the dielectric material of the substrate support 105. Typically, the bias electrode 104 is formed of one or more conductive components. Conductive components typically include mesh, foil, plate, or a combination thereof. In some embodiments, the bias electrode 104 may function as a chuck electrode (i.e., an electrostatic chuck electrode) used to fix the substrate 103 to the substrate receiving surface 105A of the substrate support 105 (e.g., an electrostatic chuck). Generally, a structure such as parallel plates is formed by the bias electrode 104 and a layer of dielectric material placed between the bias electrode 104 and the substrate receiving surface 105A. The dielectric material may typically have an effective capacitance CE of about 5 nF to about 50 nF. Typically, the dielectric material layer (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between approximately 0.03 mm and approximately 5 mm, for example between approximately 0.1 mm and approximately 3 mm, for example between approximately 0.1 mm and approximately 1 mm, or even between approximately 0.1 mm and 0.5 mm. The bias electrode 104 is electrically coupled to a clamp network that supplies a chucking voltage. The clamp network includes a high voltage source 173 coupled to a bias compensation module (BCM) 178A in a junction box 178 positioned between the high voltage source 173 and the bias electrode 104.

[0030]

[0034] In some configurations, the substrate support assembly 136 further includes an edge control electrode 115. The edge control electrode 115 is formed from one or more conductive components. Conductive components typically include mesh, foil, plate, or a combination thereof. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104 and / or at a certain distance from the center of the bias electrode 104. Generally, in the case of a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. As shown in Figure 1B, the edge control electrode 115 is positioned within the region of the substrate support 105 and is biased using the output supplied from the high-voltage source 173. In one configuration, the edge control electrode 115 is biased by using a different PV waveform generator than the PV waveform generator 175 used for the bias electrode 104. In another configuration, the edge control electrode 115 is biased by splitting a portion of the signal supplied from the PV waveform generator 175 to the bias electrode 104.

[0031]

[0035] As shown in Figure 1B, the plasma processing system 10 includes a high-voltage source 173, a PV waveform generator 175, and a current source (not shown). In one example, the current source is included in the high-voltage source 173. In another example, the current source is separate from the high-voltage source 173. The RF power system 189 includes a radio frequency (RF) generator 171 and an RF matcher 172.

[0032]

[0036] In some embodiments, the junction box 178 is electrically coupled to one or more components of both the RF power system 189 and the high voltage source 173. The junction box 178 electrically isolates one or more components of the RF power system 189 and the high voltage source 173. Furthermore, as described above, the junction box 178 is configured to separate the high voltage source 173 and the PV waveform generator 175 to reduce the current supplied to the bias electrode 104, reduce arc discharge, enable a PV waveform with a higher voltage, and increase the voltage margin of the PV waveform generator 175 while maintaining the same etching rate. In one example, the junction box 178 directs the outputs of the RF generator 171 and the PV waveform generator 175 to the substrate support base 107 and the output of the high voltage source 173 to the bias electrode 104.

[0033]

[0037] In one example, the junction box 178 includes an RF filter 174, a BCM 178A, a pulse voltage (PV) filter 178B, a high-voltage module (HVM) filter 178C, and a sensor 190. In various embodiments, the junction box 178 is electrically coupled to an RF matcher 172, a high-voltage source 173, and a PV waveform generator 175. In other embodiments, the RF matcher 172 is contained within the junction box 178, and the junction box is directly electrically coupled to an RF generator 171.

[0034]

[0038] In some embodiments, the high-voltage source 173 is coupled to a bias electrode 104 located within a substrate support assembly 136. The high-voltage source 173 is configured to supply a chucking voltage to the bias electrode 104. The high-voltage source 173 is coupled to the bias electrode via a junction box 178. Power supply line 160A electrically connects the output of the high-voltage source 173 to a BCM 178A in the junction box 178. In one example, the BCM 178A is a circuit configured to maintain a stable chucking voltage and eliminate the effects of pulse-off. Power supply line 160B electrically connects the output of the BCM 178A to a high-voltage module (HVM) filter 178C in the junction box 178. In one example, the HVM filter 178C is configured to isolate the high-voltage source 173 from other signals generated within the processing chamber 100. For example, the HVM filter 178C is configured to isolate the high-voltage source 173 from signals generated by the RF generator 171 and the PV waveform generator 175. The HVM filter 178C can be any suitable filter that can protect the high-voltage source 173, such as a low-pass filter, high-pass filter, or band-pass filter. In one example, the HVM filter 178C is a low-pass filter.

[0035]

[0039] The power supply line 160C electrically connects the output of the HVM filter 178C to the bias electrode 104. The HVM filter 178C eliminates interference from RF and PV waveforms from returning to the high-voltage power source 173. In one configuration, the chucking voltage (i.e., static DC voltage) supplied by the high-voltage power source 173 is between approximately -5000V and approximately 5000V and is supplied using an electrical conductor (coaxial power supply line 160A to 160C, etc.).

[0036]

[0040] In some embodiments, the PV waveform generator 175 is coupled to the substrate support base 107. In one example, the PV waveform generator 175 is configured to supply a pulse voltage (PV) waveform to the substrate support base 107 in order to bias the substrate support assembly 136. The power supply line 161A electrically connects the output of the PV waveform generator 175 to the PV filter 178B in the junction box 178. In one example, the PV filter 178B is configured to isolate the PV waveform generator 175 from other signals generated within the processing chamber 100. For example, the PV filter 178B is configured to isolate the PV waveform generator 175 from signals generated by the RF generator 171 and the high-voltage supply source 173. The PV filter 178B can be any suitable filter that can protect the PV waveform generator 175, such as a low-pass filter, high-pass filter, or band-pass filter. In one example, the frequency of the PV waveform and the frequency of the PV filter 178B are the same. In another example, the frequencies of the PV waveform and the PV filter 178B are different. The power supply line 161B electrically connects the output of the PV filter 178B to output node n1.

[0037]

[0041] In some embodiments, the RF generator 171 is configured to supply an RF waveform (also known as an RF bias voltage signal) to bias a substrate support base 107 in order to generate and maintain plasma 101 within the processing space 129 of the processing chamber 100. A power supply line 163A electrically connects the output of the RF generator 171 to an RF matcher 172. The RF matcher 172 includes an RF matching network that adjusts the RF waveform supplied by the RF generator 171 to minimize reflected power and improve power supply efficiency. If the impedance of the load is not properly matched to the impedance of the source (e.g., the RF generator), some of the RF waveform may be reflected back in the reverse direction along the same transmission line. In other words, the RF matcher 172 is configured to receive the RF waveform from the RF generator 171, adjust / match the impedance of the load to the impedance of the generator to reduce reflected power and improve power supply efficiency, and supply the adjusted RF waveform to the processing chamber 100. The power supply line 163B electrically connects the output of the RF matcher 172 to the RF filter 174 in the junction box 178. In one example, the RF filter 174 is configured to isolate the RF generator 171 from other signals generated within the processing chamber 100. For example, the RF filter 174 is configured to isolate the RF generator 171 from signals generated by the PV waveform generator 175 and the high-voltage supply source 173. The RF filter 174 can be any suitable filter that can protect the RF generator 171, such as a low-pass filter, high-pass filter, or band-pass filter. In one example, the frequency of the RF signal and the frequency of the RF filter 174 are the same. In another example, the frequencies of the RF signal and the RF filter 174 are different.

[0038]

[0042] Power supply line 163C electrically connects the output of RF filter 174 to output node n1. Power supply line 164A electrically connects output node n1 to sensor 190. Power supply line 164B electrically connects the output of sensor 190 to substrate support base 107. Alternatively, sensor 190 and power supply line 164B are optional, and power supply line 164A is electrically connected to substrate support base 107. In one configuration, the RF waveform has a frequency range between approximately 100 kHz and approximately 200 MHz, for example, between 2 MHz and 40 MHz.

[0039]

[0043] Power supply lines 160-164B include conductors, including combinations of coaxial cables such as rigid coaxial cables and flexible coaxial cables connected in series, insulated high-voltage corona-resistant hookup wires, bare wires, metal rods, electrical connectors, and any combination of the above.

[0040]

[0044] A system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence used to process the substrate 103. The CPU is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated subprocessors. The memory 134 described herein, generally non-volatile memory, may include random-access memory, read-only memory, a hard disk drive, or other suitable form of local or remote digital storage. The support circuitry 135 is conventionally coupled to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supply, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are executable by the components in the plasma processing chamber 10.

[0041]

[0045] Typically, a program readable by the CPU 133 in the system controller 126 includes code. When executed by the CPU 133, this code performs tasks relating to the plasma processing scheme described herein. The program may include instructions used to control various hardware and electrical components within the plasma processing system 10 for performing various process tasks and various process sequences.

[0042]

[0046] Figure 2 shows two distinct voltage waveforms established on the substrate 103, which is placed on the substrate support surface 105A of the substrate support assembly 136 of the processing chamber 100, by supplying a PV waveform to the bias electrode 104 of the processing chamber 100. The first waveform (e.g., waveform 225) is an example of an uncompensated PV waveform formed on the substrate 103 during plasma processing. The second waveform (e.g., waveform 230) is an example of a compensated PV waveform established on the substrate 103 by applying a negative gradient waveform to the substrate support base 107 of the processing chamber 100 during the "ion current phase" portion of the PV waveform cycle using a current source. The compensated PV waveform can alternatively be established by applying a negative voltage ramp during the ion current phase of the PV waveform generated by the PV waveform generator 175.

[0043]

[0047] Waveforms 225 and 230 include two main stages, namely the ion current stage and the sheath collapse stage. Both parts of waveforms 225 and 230 (e.g., the ion current stage and the sheath collapse stage) can be established alternately and / or separately on the substrate 103 during plasma processing. Conventionally, at the start of the ion current stage, the supply of the negative portion (e.g., the ion current portion) of the PV waveform supplied to the substrate support base 107 by the PV waveform generator 175 causes a voltage drop on the substrate 103, thereby creating a high-voltage sheath on the substrate 103. The high-voltage sheath allows the positive ions generated by the plasma to be accelerated toward the biased substrate 103 during the ion current stage, and thus, in the case of an RIE process, the amount and characteristics of the etching process performed on the surface of the substrate 103 during plasma processing are controlled. In some embodiments, it is desirable that the ion current stage includes a region of the PV waveform that realizes a voltage on the substrate 103 that is stable or minimally fluctuating throughout the stage, as shown in Figure 2 by waveform 230. It should be noted that by supplying the PV waveform to the substrate support base 107 instead of the bias electrode 104, the voltage overshoot, ringing, and current spikes supplied to the bias electrode 104 of the plasma processing chamber 100 are reduced, thereby reducing arc discharge, enabling a PV waveform with a higher voltage, and increasing the voltage margin supplied to the plasma processing chamber 100 by the PV waveform generator 175.

[0044]

[0048] Figure 3A is a schematic diagram of a junction box 178 according to one or more embodiments. The junction box 178 may include an RF filter 174, a BCM 178A, a PV filter 178B, an HVM filter 178C, and a sensor 190. In one example, the junction box 178 receives inputs from an RF matcher 172, a PV waveform generator 175, and a high-voltage source 173. In another example, the RF matcher 172 is contained within the junction box 178, and the RF generator 171 is directly coupled to the junction box 178.

[0045]

[0049] The RF filter 174 is electrically coupled to the RF matcher 172. The PV filter 178B is electrically coupled to the PV waveform generator 175. The BCM 178A is electrically coupled to the high voltage source 173. The input of the sensor 190 is electrically coupled to the RF filter 174 and the PV filter 178B via the output node n1. The output of the sensor 190 is electrically coupled to the substrate support base 107. The input of the HVM filter 178C is electrically coupled to the BCM 178A. The output of the HVM filter 178C is electrically coupled to the bias electrode 104.

[0046]

[0050] Each filter is configured to isolate the corresponding signal generator from other signals provided and generated within the processing chamber. For example, the RF filter 174 is configured to block the RF generator 171 from signals generated by the PV waveform generator 175 and the high-voltage source 173 to avoid interference. The PV filter 178B is configured to block the PV waveform generator 175 from signals generated by the RF generator 171 and the high-voltage source 173 to avoid interference. The HVM filter 178C is configured to block the high-voltage source 173 from signals generated by the PV waveform generator 175 and the RF generator 171 to avoid interference.

[0047]

[0051] In one example, sensor 190 may include voltage and / or current sensors configured to measure the impedance or characteristics of the plasma processing system 10. Sensor 190 may include voltage and / or current sensors configured to measure the characteristics of RF signals and PV waveforms, such as voltage, current, phase, or harmonics. The sensor measurements may be used in feedback and feedforward algorithms for impedance matching. In one example, sensor 190 may be coupled to the RF matching controller 302 and / or PV waveform generator 175 of the RF matcher 172. In another example, sensor 190 is coupled to the RF matching controller 302, which provides readings from sensor 190 to the PV waveform generator 175 and / or system controller 126. In one example, based on the readings from sensor 190, the RF matching controller 302 adjusts the matching point of the RF matcher 172 so that the impedance of the output signal provided by the junction box 178 matches the impedance of the plasma processing chamber 100. In another example, based on readings from sensor 190, the PV waveform generator 175 adjusts the characteristics of the PV waveform, including but not limited to the rising and falling edges, duty cycle, and voltage of the PV waveform. In yet another example, sensor 190 communicates directly with system controller 126, which adjusts the PV and RF waveforms as appropriate via RF generator 171 and PV waveform generator 175 based on the sensor's return value. Based on readings from sensor 190, the RF generator adjusts the characteristics of the RF waveform, including but not limited to the power and / or pulsation of the RF waveform. In yet another example, sensor 190 is optional.

[0048]

[0052] Figure 3B is a schematic diagram of a junction box 178 according to one embodiment. In this example, the input of sensor 190 is electrically connected to the output of PV waveform generator 175. The output of sensor 190 is electrically connected to PV filter 178B. The outputs of both RF filter 174 and PV filter 178B are electrically connected to substrate support base 107 via output node n1.

[0049]

[0053] Figure 3C is a schematic diagram of a junction box 178 according to one embodiment. In one example, the junction box 178 includes a tuning circuit 191 electrically connected between the output of the BCM 178A and the bias electrode 104. The tuning circuit 191 is coupled to the bias electrode 104 via an HVM filter 178C. In one example, the tuning circuit 191 includes at least one variable capacitor and is configured to control the PV waveform and control overshoot on the substrate to ensure a high etching rate while maintaining stability.

[0050]

[0054] Figure 4 is a schematic diagram of an RF power supply system according to one or more embodiments. The RF matcher 172 includes an RF matching controller 402, an input sensor 418, an output sensor 417, a first RF filter 408, a second RF filter 410, a tuning circuit 412, an interlock 414, and a memory 416. The first RF filter 408 and the second RF filter 410 may be configured to block frequencies from other signals transmitted from the processing chamber 100 in order to avoid interference in the RF generator 171. For example, the first RF filter 408 and the second RF filter 410 may be low-pass filters, high-pass filters, or band-pass filters.

[0051]

[0055] The RF matcher 172 receives the RF waveform from the RF generator 171 and is configured to adjust the RF waveform to reduce reflected power and improve power supply efficiency. For the advantages described above, the RF matcher 172 supplies the adjusted RF waveform to the substrate support base 107 of the processing chamber 100 via the junction box 178. In some embodiments, as described above, the PV waveform generator 175 is configured to supply the PV waveform to the substrate support base 107 of the processing chamber 100 simultaneously with the adjusted RF waveform. The RF generator 171 and the PV waveform generator 175 are both communicably coupled and synchronized with the system controller 126. The synchronization signal may come from the system controller 126, the PV waveform generator 175, or the RF generator 171.

[0052]

[0056] The RF matching controller 402 may be communicatively coupled to an interlock 414, memory 416, tuning circuit 412, input sensor 418, output sensor 417, and optionally sensor 190 (Figures 3A and 3C). In some embodiments, the RF matching controller 402 also communicates with an electronic device including a display and user interface, such as a conventional computer (e.g., a user PC), which may optionally form part of a system controller 126. The RF matching controller 402 includes a central processing unit (CPU). The RF matching controller 402 is configured to control the tuning circuit 412 to change the impedance parameters of the RF matcher 172. The tuning circuit 412 described herein may be a T-network tuning circuit, a π (pi)-network tuning circuit, an L-network circuit, etc. The tuning circuit 412 may include at least one electrical component, such as a variable capacitor and / or inductor, which can be tuned by the RF matching controller 402 to change the impedance so that the RF waveform provided to the processing chamber 100 is optimized. Thus, a tuned RF signal is generated. The tuning circuit 412 has an input 412A directly or indirectly coupled to the input sensor 418, and an output 412B directly or indirectly coupled to the output sensor 417.

[0053]

[0057] Memory 416 can be programmed for long-term or short-term memory storage. Generally non-volatile memory, memory 416 as described herein may include random-access memory, read-only memory, hard disk drives, or other suitable forms of local or remote digital storage. Software instructions (programs) and data for instructing the processor in controller 402 may be coded and stored in memory 416. Software programs (or computer instructions) readable by controller 402 determine which tasks can be performed by components in the plasma processing system 10.

[0054]

[0058] Interlock 414 is implemented for safety purposes to control temperature switches, cable-in-place switches, and match-in-place switches, etc. Interlock 414 is released in the event of a failure, and an interlock signal is sent from the local microcontroller to both the user laptop and the system controller 126 to shut down the system.

[0055]

[0059] The output sensor 417 may include a voltage sensor and / or current sensor configured to measure impedance or characteristics of the plasma processing system 10 described above. In some embodiments, the output sensor 417 is optional if sensor 190 (Figures 3A and 3C) is included in the junction box 178. If sensor 190 is not included in the junction box 178, the output sensor 417 is included in the RF matcher 172. The output sensor 417 can be located between the RF matcher 172 and the junction box 178, or may be included in the junction box 178. In other words, the output sensor 417 and / or sensor 190 can be located anywhere between the output of the RF matcher 172 and the substrate support base 107. The input sensor 418 may include a voltage sensor and / or current sensor configured to measure characteristics of an RF waveform such as voltage, current, phase, or harmonics. In some cases, only one sensor may be used at the input of the RF matcher 172. The sensor measurements may be used in feedback and feedforward algorithms for impedance matching.

[0056]

[0060] Advantageously, as described above, the junction box 178 routes both the tuned RF waveform from the RF generator 171 and the PV waveform from the PV waveform generator 175 to the substrate support base 107. This effectively isolates the PV waveform generator 175 from the bias electrode 104, reduces the current supplied to the bias electrode 104, reduces arc discharge, enables a PV waveform with a higher voltage, and increases the voltage margin of the PV waveform generator 175 while maintaining the same etching rate.

[0057]

[0061] While the above description applies to embodiments of the present disclosure, other embodiments and additional embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure. The scope of the present disclosure is determined by the following claims.

Claims

1. A plasma processing system, A radio frequency (RF) generator, which is coupled to a substrate support base located within the plasma processing system and configured to supply an RF signal to the substrate support base, A pulse voltage (PV) waveform generator, which is coupled to the substrate support base and configured to supply a PV waveform to the substrate support base while the RF signal is supplied to the substrate support base, A high-voltage supply source, configured to be coupled to the bias electrode of the plasma processing system and to supply a chucking voltage to the bias electrode located within the plasma processing system, Plasma processing systems, including those mentioned above.

2. The plasma processing system according to claim 1, wherein the output of the RF generator is coupled to the substrate support base and configured to supply the RF signal to the substrate support base, the output of the PV waveform generator is coupled to the substrate support base and configured to supply the PV waveform to the substrate support base, and the output of the high voltage supply source is coupled to the bias electrode and configured to supply the chucking voltage to the bias electrode via a junction box.

3. The aforementioned joint box is A bias compensation module (BCM) is configured to be coupled to the high voltage supply source and to receive the chucking voltage from the high voltage supply source and stabilize the chucking voltage, A high-voltage module (HVM) filter, configured to be coupled to the output of the BCM and to receive the chucking voltage and provide the chucking voltage to the bias electrode, and The plasma processing system according to claim 2, including the following:

4. The aforementioned joint box is A bias compensation module (BCM) is configured to be coupled to the high voltage supply source and to receive the chucking voltage from the high voltage supply source and stabilize the chucking voltage, A tuning circuit, configured to be coupled to the output of the BCM and to control the PV waveform, A high-voltage module (HVM) filter, configured to be coupled to the output of the tuning circuit and to receive the chucking voltage and provide the chucking voltage to the bias electrode, The plasma processing system according to claim 2, including the following:

5. The plasma processing system according to claim 2, further comprising an RF matcher configured to be coupled to the RF generator, to receive the RF signal from the RF generator, to adjust the RF signal, and to provide the RF signal to the junction box.

6. The plasma processing system according to claim 5, wherein the bonding box includes an RF filter that is coupled to the output of the RF matcher and configured to receive the RF signal from the RF matcher and provide the RF signal to the substrate support base.

7. The plasma processing system according to claim 2, wherein the bonding box is coupled to the PV waveform generator and further includes a PV filter configured to receive the PV waveform from the PV waveform generator and provide the PV waveform to the substrate support base.

8. The aforementioned joint box is An RF filter configured to be coupled to an RF matching device, receive the RF signal from the RF matching device, and provide the RF signal to a sensor positioned between the RF matching device and the substrate support base, A PV filter configured to be coupled to the PV waveform generator, receive the PV waveform from the PV waveform generator, and provide the PV waveform to the sensor, wherein the sensor, located in the junction box, is coupled to the RF matching controller of the RF matching unit, and the PV filter is configured to measure the characteristics of the RF signal and the PV waveform and provide the measured characteristics to at least one of the RF matching controller and the PV waveform generator. The plasma processing system according to claim 5, including the following:

9. A plasma processing system, A radio frequency (RF) generator configured to generate RF signals, A pulse voltage (PV) waveform generator configured to generate PV waveforms, A high-voltage power source configured to generate a chucking voltage, A junction box, coupled to the RF generator, the PV waveform generator, and the high voltage supply source, wherein the junction box receives the RF signal, the PV waveform, and the chucking voltage, supplies the RF signal and the PV waveform to the substrate support base of the plasma processing system, and supplies the chucking voltage to the bias electrode of the plasma processing system. Plasma processing systems, including those mentioned above.

10. The aforementioned joint box is A bias compensation module (BCM) is coupled to the high voltage supply source and configured to receive the chucking voltage from the high voltage supply source and stabilize the chucking voltage, A high-voltage module (HVM) filter, which is coupled to the output of the BCM and configured to receive the chucking voltage and provide the chucking voltage to the bias electrode, and The plasma processing system according to claim 9, including the following:

11. The aforementioned joint box is A bias compensation module (BCM) is coupled to the high voltage supply source and configured to receive the chucking voltage from the high voltage supply source and stabilize the chucking voltage, A tuning circuit, which is coupled to the output of the BCM and configured to control the PV waveform, A high-voltage module (HVM) filter, which is coupled to the output of the tuning circuit and configured to receive the chucking voltage and provide the chucking voltage to the bias electrode, The plasma processing system according to claim 9, including the following:

12. The plasma processing system according to claim 9, further comprising an RF matcher coupled to the RF generator, configured to receive the RF signal from the RF generator, adjust the RF signal, and provide the RF signal to the junction box.

13. The plasma processing system according to claim 12, wherein the bonding box is coupled to the RF matching device and includes an RF filter configured to receive the RF signal from the RF matching device and provide the RF signal to the substrate support base.

14. The aforementioned joint box is An RF filter, which is coupled to the RF matching device and configured to receive the RF signal from the RF matching device and provide the RF signal to a sensor disposed between the RF matching device and the substrate support base, A PV filter, configured to be coupled to the PV waveform generator and to receive the PV waveform from the PV waveform generator and provide the PV waveform to the sensor, wherein the sensor is coupled to the RF matching controller of the RF matching unit and the PV filter, configured to measure the characteristics of the RF signal and the PV waveform and provide the measured characteristics to at least one of the RF matching controller and the PV waveform generator. The plasma processing system according to claim 12, including the following:

15. It is a connecting box, A high-frequency (RF) filter, which is coupled to an RF generator of a plasma processing system and configured to receive an RF signal from the RF generator, A pulse voltage (PV) filter, which is coupled to a PV waveform generator of the plasma processing system and configured to receive a PV waveform from the PV waveform generator, A bias compensation module (BCM) is configured to be coupled to a high voltage supply source of the plasma processing system and to receive a chucking voltage from the high voltage supply source, and the bonding box is configured to transmit the RF signal and the PV waveform to the substrate support base of the plasma processing chamber of the plasma processing system, and to transmit the chucking voltage to the bias electrode of the plasma processing chamber. A junction box, including a junction box.

16. The junction box according to claim 15, further comprising a high-voltage module (HVM) filter coupled to the output of the BCM and configured to receive the chucking voltage and provide the chucking voltage to the bias electrode.

17. A tuning circuit, which is coupled to the output of the BCM and configured to control the PV waveform, A high-voltage module (HVM) filter, which is coupled to the output of the tuning circuit and configured to receive the chucking voltage and provide the chucking voltage to the bias electrode, and The joining box according to claim 15, further comprising:

18. The bonding box according to claim 15, further comprising an RF filter coupled to an RF matcher of the plasma processing system, configured to receive the RF signal from the RF matcher and provide the RF signal to the substrate support base.

19. The bonding box according to claim 15, further comprising a PV filter coupled to a PV waveform generator of the plasma processing system, configured to receive the PV waveform from the PV waveform generator and provide the PV waveform to the substrate support base.

20. The aforementioned joint box is An RF filter, which is coupled to an RF matching device and configured to receive the RF signal from the RF matching device and provide the RF signal to a sensor positioned between the RF matching device and the substrate support base, A PV filter configured to be coupled to the PV waveform generator and to receive the PV waveform from the PV waveform generator and provide the PV waveform to the sensor, wherein the sensor is coupled to at least one of the RF matching controller of the RF matching unit, the PV waveform generator, and the system controller, and the sensor is configured to measure the characteristics of the RF signal and the PV waveform and provide the measured characteristics to at least one of the PV waveform generator, the RF matching controller, and the system controller. The joining box according to claim 15, including the following:

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