Self-adaptive large dynamic detection noise floor suppression system and control method thereof

Abstract

The invention discloses a self-adaptive large dynamic detection noise floor suppression system and a control method thereof. The system comprises a filtering selection front-end module, a detection synthesis module, a frequency measurement receiving module and an FPGA feedback control module. The method is composed of four main parts, namely a filtering selection front end, detection synthesis, frequency measurement receiving and FPGA feedback control. Wherein the filtering selection front end and the frequency measurement receiving end receive two groups of external radio frequency signals at the same time. And frequency measurement is carried out through a mature single-bit receiving scheme in frequency measurement receiving, and a result is sent to the feedback control module, so that switching of a filtering channel and suppression of a noise floor are realized. According to the invention, the broadband large dynamic DLVA detection sensitivity is obviously improved.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency signal detection technology, and in particular relates to an adaptive large dynamic range detection noise floor suppression system and its control method. Background Technology

[0002] Receiving and processing wideband RF signals is a common requirement for current receiving systems, especially when dealing with wideband signals with large dynamic range and narrow pulses. The signal-to-noise ratio (SNR) of logarithmic detection directly affects the receiver's detection capability. The latest large dynamic range logarithmic detection schemes directly use two sets of wideband SDLVAs (continuous detection logarithmic video amplifiers) and a pre-stage RF link to synthesize and splice wideband RF signals of different power levels. After circuit processing, a maximum detection sensitivity of approximately -76 dBm can be achieved in the Ku-band. However, the sensitivity is limited by the high noise floor inherent in the wideband signal and cannot be further improved. Summary of the Invention

[0003] The purpose of this invention is to provide an adaptive large dynamic range (DLVA) detection noise floor suppression system and its control method, which improves the detection sensitivity of wideband large dynamic range (DLVA).

[0004] To achieve the objectives of this invention, on the one hand, this invention provides an adaptive large dynamic range detection noise floor suppression system, including a filter selection front-end module, a detection synthesis module, a frequency measurement and receiving module, and an FPGA feedback control module;

[0005] The filtering selection front-end module is used for low-noise reception and selectable near-end narrowband filtering, followed by link power compensation, and then further suppression of noise floor through selectable far-end broadband filtering.

[0006] The detector synthesis module is used to receive two radio frequency signals from the filter selection module, then output a DC voltage signal through logarithmic detection, and finally synthesize them using an operational amplifier circuit.

[0007] The frequency measurement and receiving module is used to perform frequency measurement using a mature single-bit receiving scheme, and send the result to the FPGA feedback control module to realize the switching of the filtering channel and the suppression of noise floor.

[0008] The FPGA feedback control module is used to receive frequency information and system control commands from the frequency measurement receiver, and to control the switching of near-end and far-end filter bank channels and the selection of attenuation states.

[0009] The filtering selection front-end module includes three broadband low-noise amplifiers, a power divider, three attenuators, two single-pole multi-throw switches, a near-end switching filter chip, a digitally controlled attenuator, and a far-end switching filter chip. The RF signal first enters the broadband low-noise amplifier, then the power divider. One path goes through the attenuator and outputs to the next stage module, while the other path enters the second low-noise amplifier. After amplification, it enters the single-pole multi-throw switch, which provides a direct path through the near-end switching filter chip or the attenuator. It then passes through another switch to the digitally controlled attenuator, followed by the third low-noise amplifier and the far-end filter chip group, and finally outputs to the next stage.

[0010] The detection synthesis module is composed of two S-Ku band SDLVAs spliced ​​together, and is equipped with an operational amplifier synthesis circuit. The two SDLVAs are of the same model. The first SDLVA receives high-power radio frequency signals from the filter selection front-end module for detection, and the second SDLVA receives low-power radio frequency signals for detection. The two output DC voltage signals are finally fed into the operational amplifier synthesis circuit for single-channel output.

[0011] The frequency measurement receiving module adopts a single-bit frequency measurement receiver, which consists of a limiting amplification and frequency conversion module, an ADC analog-to-digital converter and a frequency measurement FPGA module. The limiting amplification and frequency conversion module processes the broadband radio frequency signal for down-conversion, and the ADC analog-to-digital converter converts the frequency-converted intermediate frequency signal into a digital signal, which is then fed into the frequency measurement FPGA module for FFT operation and data processing.

[0012] The FPGA feedback control module consists of an FPGA chip, peripheral circuits, and control lines. The FPGA chip receives frequency measurement signals and system control signals, converts them into control codes through a specific program, and outputs them to the control interface of the filter selection front-end module through the peripheral circuits and control lines.

[0013] On the other hand, the present invention also provides an automatic control method for implementing the above-mentioned adaptive large dynamic range detector noise floor suppression system, comprising the following steps:

[0014] Step 1: The filtering selection front-end module receives the broadband radio frequency signal from the antenna and operates in the initial state, in which the near-end filter bank is not enabled and is in a pass-through state, while the far-end filter bank is in the working state with the widest bandwidth.

[0015] Step 2: The detector synthesis module receives two signals from the filter selection front-end module and outputs the synthesized DC video signal as the initial output.

[0016] Step 3: The frequency measurement receiver uses another antenna to synchronously receive external radio frequency signals and perform frequency measurement. The result is sent to the FPGA feedback control module.

[0017] Step 4: The FPGA feedback control module receives frequency measurement information and system control signals, and controls the near-end filter bank, single-pole multi-throw switch, digitally controlled attenuator and far-end filter bank in the filter selection front-end module through program output control code, so that the filter selection front-end module works on the selected frequency band.

[0018] Step 5: After the control state is updated, the filter selection front-end module and the detector synthesis module continue to work and output the DC video signal after noise floor suppression;

[0019] Step 6: Based on changes in the external radio frequency signal, select whether to continue adaptive narrowband reception from step 3 or return to the initial working state in step 1 via system control commands.

[0020] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method described above for implementing a large dynamic range detector noise floor suppression system.

[0021] A non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the above-described method for implementing a large dynamic range detector noise floor suppression system.

[0022] A computer program product includes computer program instructions that, when executed on a computer, cause the computer to perform the method described above for implementing a large dynamic range detector noise floor suppression system.

[0023] Compared with the prior art, the significant advancement of the present invention is that it can effectively improve the detection sensitivity of large dynamic range detectors for specific narrowband signals, while also taking into account the ability to detect broadband signals; and it can adaptively control noise floor suppression according to external signals.

[0024] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0026] Figure 1 This is a basic structural principle block diagram of the present invention;

[0027] Figure 2 This is a specific circuit block diagram of the present invention. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] This invention provides an adaptive large dynamic range detector noise floor suppression system, combined with Figures 1-2 It includes a filter selection front-end module, a detector synthesis module, a frequency measurement and receiving module, and an FPGA feedback control module;

[0030] The filtering selection front-end module is used for low-noise reception and selectable near-end narrowband filtering, followed by link power compensation, and then further suppression of noise floor through selectable far-end broadband filtering.

[0031] The detector synthesis module is used to receive two radio frequency signals from the filter selection module, then output a DC voltage signal through logarithmic detection, and finally synthesize them using an operational amplifier circuit.

[0032] The frequency measurement and receiving module is used to perform frequency measurement using a mature single-bit receiving scheme, and send the result to the FPGA feedback control module to realize the switching of the filtering channel and the suppression of noise floor.

[0033] The FPGA feedback control module is used to receive frequency information and system control commands from the frequency measurement receiver, and to control the switching of near-end and far-end filter bank channels and the selection of attenuation states.

[0034] The filtering selection front-end module includes three broadband low-noise amplifiers, a power divider, three attenuators, two single-pole multi-throw switches, a near-end switching filter chip, a digitally controlled attenuator, and a far-end switching filter chip. The RF signal first enters the broadband low-noise amplifier, then the power divider. One path goes through the attenuator and outputs to the next stage module, while the other path enters the second low-noise amplifier. After amplification, it enters the single-pole multi-throw switch, which provides a direct path through the near-end switching filter chip or the attenuator. It then passes through another switch to the digitally controlled attenuator, followed by the third low-noise amplifier and the far-end filter chip group, and finally outputs to the next stage.

[0035] The detection synthesis module is composed of two S-Ku band SDLVAs (continuous detection logarithmic video amplifiers) spliced ​​together, and is equipped with an operational amplifier synthesis circuit. The two SDLVAs are of the same model. The first SDLVA receives high-power radio frequency signals from the filter selection front-end module for detection, and the second SDLVA receives low-power radio frequency signals for detection. The two output DC voltage signals are finally fed into the operational amplifier synthesis circuit for single-channel output.

[0036] The frequency measurement receiving module adopts a single-bit frequency measurement receiver, which consists of a limiting amplification and frequency conversion module, an ADC analog-to-digital converter and a frequency measurement FPGA module. The limiting amplification and frequency conversion module processes the broadband radio frequency signal for down-conversion, and the ADC analog-to-digital converter converts the frequency-converted intermediate frequency signal into a digital signal, which is then fed into the frequency measurement FPGA module for FFT operation and data processing.

[0037] The FPGA feedback control module consists of an FPGA chip, peripheral circuits, and control lines. The FPGA chip receives frequency measurement signals and system control signals, converts them into control codes through a specific program, and outputs them to the control interface of the filter selection front-end module through the peripheral circuits and control lines.

[0038] The front-end switching filter chipset uses several miniaturized filter chips covering the S-Ku band. Each chip has 4-5 selectable bandwidths. The three filter groups are spliced ​​together to achieve 12 narrowband near-end filtering segments, with a single chip achieving out-of-band rejection of up to 40dBc, while maintaining a small footprint. After the first filtering, a suitable filter bank is added to perform secondary filtering at the far end of the three filtering links, achieving four filtering segments and further suppressing the noise floor.

[0039] An automatic control method for implementing the above-mentioned adaptive large dynamic range detector noise floor suppression system includes the following steps:

[0040] Step 1: The filtering selection front-end module receives the broadband radio frequency signal from the antenna and operates in the initial state, in which the near-end filter bank is not enabled and is in a pass-through state, while the far-end filter bank is in the working state with the widest bandwidth.

[0041] Step 2: The detector synthesis module receives two signals from the filter selection front-end module and outputs the synthesized DC video signal as the initial output.

[0042] Step 3: The frequency measurement receiver uses another antenna to synchronously receive external radio frequency signals and perform frequency measurement. The result is sent to the FPGA feedback control module.

[0043] Step 4: The FPGA feedback control module receives frequency measurement information and system control signals, and controls the near-end filter bank, single-pole multi-throw switch, digitally controlled attenuator and far-end filter bank in the filter selection front-end module through program output control code, so that the filter selection front-end module works on the selected frequency band.

[0044] Step 5: After the control state is updated, the filter selection front-end module and the detector synthesis module continue to work and output the DC video signal after noise floor suppression;

[0045] Step 6: Based on changes in the external radio frequency signal, select whether to continue adaptive narrowband reception from step 3 or return to the initial working state in step 1 via system control commands.

[0046] Supplementary explanation of the principle of this invention:

[0047] Combination Figure 2 The filtering selection front end consists of a broadband low-noise amplifier, a single-pole multi-throw switch, switching filter chips, and a digitally controlled attenuator. Further, the filtering selection front end is mainly used for low-noise reception and selectable near-end narrowband filtering, followed by link power compensation. The link gains of the two power segments can adapt to the power input and splicing requirements of the subsequent SDLVA, while ensuring that the link noise figure of the low-power segment is as small as possible. First, the external broadband RF signal enters an LNA1 through antenna 1, and is split into two signals by a power divider PD. One signal directly passes through a fixed attenuator ATT1 and outputs to a subsequent SDLVA, serving as the large signal part in dynamic synthesis. The other signal serves as the small signal part in dynamic synthesis, determining the final detection sensitivity, and therefore requires more complex amplification and filtering to suppress the noise floor. The small signal passes through a temperature-compensated attenuator ATT2, a low-noise amplifier LNA2, and a single-pole four-throw switch SW1 before entering four different channels: near-end filter banks F1, F2, and F3, and a direct pass. The insertion loss of the above switching filter chips is approximately 9dB, requiring gain compensation. Four signals are output through a single-pole four-throw switch SW2, and then power-compensated by a digitally controlled attenuator ATT3 and a low-noise amplifier LNA3. They are then further reduced in noise by a secondary filtering selection channel composed of a remote switching filter chip F4, before finally being output to the subsequent SDLVA stage. The noise figure of the small-signal filtering channel in the entire filtering selection front-end can reach approximately 2.3, with a gain of approximately 30dB. The noise figure of the small-signal filtering channel is crucial for detection sensitivity. Considering the complexity of the link and control, this filtering selection front-end can be packaged in a SiP package to reduce its size.

[0048] Figure 2 The final output stage is a typical SDLVA (Signal-to-Large Dynamic Range) splicing circuit, where two SDLVAs handle the detection video outputs of small and large signals, respectively. These are then processed and output by a synthesis circuit. Wideband SDLVAs are currently mature products on the market. Furthermore, as mentioned earlier, the tangent sensitivity of the video detector logarithmic amplifier is determined by the RF bandwidth and the detection video bandwidth. The detection video bandwidth is generally a fixed value; by adaptively adjusting the RF front-end bandwidth and reducing the RF noise floor, the detection sensitivity can be improved by 3dB.

[0049] Figure 2The frequency measurement receiving link and FPGA feedback control loop receive the RF signal via antenna 2. The frequency measurement receiver is a single-bit receiver, employing currently mature methods for signal frequency measurement. Furthermore, the frequency measurement results are processed by a high-speed FPGA. Through preset control codes, the built-in switches of the filter banks F1, F2, F3, and F4 at the filter selection front end, as well as the digitally controlled attenuator and single-pole multi-throw switch, are automatically controlled. The preset control codes, through debugging, establish the correspondence between each segment of frequency measurement information, the filter channel, and the specific digitally controlled attenuation value. Furthermore, the direct-pass channel can serve as the default initial control state, representing a traditional instantaneous, wideband, high-dynamic-range reception state. The entire automatic control process can be actively intervened by external means to adapt to ever-changing reception requirements, ensuring reception flexibility.

[0050] Figure 2 Legend for the diagram: LNA1, LNA2, LNA3, low noise amplifiers; PD, power divider; SW1, single-pole four-throw switch; SW2, single-pole four-throw switch; ATT1, ATT4, fixed attenuators; ATT2, temperature-compensated attenuator; ATT3, digitally controlled attenuator.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An adaptive large dynamic detection noise floor suppression system, characterized by, The filter selection front-end module, the detection and synthesis module, the frequency measurement receiver module and the FPGA feedback control module are included. The filter selection front-end module is used for low-noise receiving and optional near-end narrow-band filtering, link power compensation, and further noise floor suppression through optional far-end wide-band filtering. The detection and synthesis module is used for receiving two-way radio frequency signals from the filter selection module, logarithmic detection and output of direct current voltage signals, and final synthesis using an operational amplifier circuit. The frequency measurement receiver module is used for frequency measurement through a mature single-bit receiving scheme, sending results to the FPGA feedback control module to realize filter channel switching and noise floor suppression. The FPGA feedback control module is used for receiving frequency information and system control instructions from the frequency measurement receiver, controlling near-end and far-end filter group channel switching and attenuation state selection.

2. An adaptive large dynamic detection noise floor suppression system as claimed in claim 1, wherein, The filter selection front-end module includes three wide-band low-noise amplifiers, a power divider, three attenuators, two single-pole multi-throw switches, a near-end switch filter chip, a digital attenuator, and a far-end switch filter chip. Radio frequency signals first enter the wide-band low-noise amplifier, then enter the power divider, one-way output to the next stage module through the attenuator, and the other way enters the second low-noise amplifier, then enters the single-pole multi-throw switch, passes through the near-end switch filter chip or the attenuator straight-through path, then enters the digital attenuator through a switch, and finally enters the third low-noise amplifier and the far-end filter chip set and is output to the next stage.

3. An adaptive large dynamic range detection noise floor suppression system as claimed in claim 1, wherein, The detection and synthesis module is composed of two SDLVA spliced in the S-Ku frequency band, and is equipped with an operational amplifier synthesis circuit. The two SDLVA are of the same type. The first SDLVA receives high-power radio frequency signals from the filter selection front-end module for detection, and the second SDLVA receives low-power radio frequency signals for detection. The two direct current voltage signals output are finally input into the operational amplifier synthesis circuit for single-way output.

4. The adaptive large dynamic detection noise floor suppression system of claim 1, wherein, The frequency measurement receiver module adopts a single-bit frequency measurement receiver, which is composed of an amplitude limiting amplification frequency conversion module, an ADC analog-digital converter, and a frequency measurement FPGA module. The amplitude limiting amplification frequency conversion module processes wide-band radio frequency signals for down-conversion. The ADC analog-digital converter converts the frequency-converted intermediate frequency signals into digital signals, which are then input into the frequency measurement FPGA module for FFT operation and data processing.

5. The adaptive large dynamic detection noise floor suppression system of claim 1, wherein, The FPGA feedback control module is composed of an FPGA chip, peripheral circuits and control lines. The FPGA chip receives frequency measurement signals and system control signals, converts them into control codes through a specific program, and outputs them to the control interface of the filter selection front-end module through the peripheral circuits and control lines.

6. An automatic control method for implementing the self-adapting large dynamic detection noise floor suppression system of any one of claims 1-5, characterized in that, The method includes the following steps: Step 1: The filter selection front-end module receives wide-band radio frequency signals from an antenna and works in an initial state, in which the near-end filter group is not enabled and is in a straight-through state, and the far-end filter group is in a state with the widest bandwidth. Step 2: The detection and synthesis module receives two-way signals from the filter selection front-end module and outputs a synthesized direct current video signal as an initial output. Step 3: A frequency measurement receiver uses another antenna to synchronously receive external radio frequency signals and performs frequency measurement, and the results are sent to the FPGA feedback control module. Step 4, the FPGA feedback control module receives frequency measurement information and system control signals, and controls the near-end filter group, single-pole multi-throw switch, digital attenuator and far-end filter group in the filter selection front-end module through program output control code, so that the filter selection front-end module works in the selected frequency band; Step 5, the filter selection front-end module and the detection and synthesis module continue to work after the control state is updated and output the direct current video signal after noise floor suppression; Step 6, according to the change of external radio frequency signals, whether to continue adaptive narrowband receiving work from step 3 or return to the initial working state in step 1 is selected through system control instructions.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the method as claimed in claim 6 when executing the program.

8. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions for causing the computer to execute the method as claimed in claim 6.

9. A computer program product comprising computer program instructions, characterised in that, When the computer program instructions run on the computer, the computer executes the method as claimed in claim 6.

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