Display panels and display devices

Abstract

This application discloses a display panel and a display device, the display panel comprising a first display area, a second display area, and a plurality of signal lines, wherein the first display area is provided with a plurality of first pixel circuits and a plurality of light-transmitting sections located between the plurality of first pixel circuits, the second display area is provided with a plurality of second pixel circuits, each of the plurality of signal lines is connected to a row of second pixel circuits, and at least two signal lines transmitting the same control signal are connected to the plurality of identical first pixel circuits.

Description

Technical Field

[0001] This application relates to the display field, and particularly to a display panel and a display device.

Background Art

[0002] In the Camera Under Panel (CUP) technology of an Organic Light-Emitting Diode (OLED) display panel, since the distribution density of pixel driving circuits in the under-panel imaging area is usually smaller than that in the display area, a part of the signal lines for transmitting control signals in the display area located on both sides of the under-panel imaging area is directly connected horizontally. Without avoiding the under-panel imaging area, this horizontally connected signal line occupies the area of a part of the light-transmitting area in the under-panel imaging area. As a result, there is a technical problem that the area of the light-transmitting area in the under-panel imaging area is reduced, and the infrared transmittance of the under-panel imaging area fails to reach the reference value.

Summary of the Invention

Problems to be Solved by the Invention

[0003] This application provides a display panel and a display device to improve the problem that the area of the light-transmitting area in the under-panel imaging area of a conventional display panel is relatively small.

Means for Solving the Problems

[0004] To solve the above problems, the technical solution provided in this application is as follows.

[0005] This application provides a display panel, and the display panel includes: A first display area, in which a plurality of first pixel circuits and a plurality of light-transmitting parts are provided, and a first display area where the plurality of light-transmitting parts are located between the plurality of first pixel circuits, and A second display area, the second display area being located around the first display area, and the second display area having a plurality of second pixel circuits, The system includes a plurality of signal lines, each of which is connected to a row of the second pixel circuit, and a plurality of signal lines, each transmitting the same control signal, where at least two of the signal lines are connected to a plurality of the same first pixel circuits.

[0006] The present invention further provides a display device, the display device including the display panel described above. [Brief explanation of the drawing]

[0007] [Figure 1] This is a first schematic diagram showing the display panel of the present invention. [Figure 2] This is the first configuration diagram showing region AA in Figure 1. [Figure 3] This is a second configuration diagram showing region AA in Figure 1. [Figure 4] This is an equivalent circuit diagram showing the second pixel circuit and the first pixel circuit in the display panel of the present invention. [Figure 5] This is a circuit diagram showing the first circuit in the display panel of the present invention. [Figure 6] This is a circuit diagram showing the second circuit in the display panel of the present invention. [Figure 7] This is a circuit diagram showing the third circuit in the display panel of the present invention. [Figure 8] A schematic diagram of the film layer relating to the display panel of the present invention. [Figure 9] This is a stacked film diagram relating to the second pixel circuit in the display panel of the present invention. [Figure 10] This is a stacked film layer diagram relating to the first pixel circuit in the display panel of the present invention. [Figure 11] This is a first film layer stacking diagram relating to the first main part and functional sub-part in region CC of Figure 1. [Figure 12] This is a second film layer stacking diagram relating to the first main part and the functional sub-part in region DD of Figure 11. [Figure 13]This is a diagram showing the third layer stacking of the first main part and the functional sub-part in region DD of Figure 11. [Figure 14] This is a connection diagram of the first main reset line and the first sub-reset line in region BB of Figure 1. [Figure 15] This is a connection diagram of the second main reset line and the second sub-reset line in region BB of Figure 1. [Figure 16] This is a connection diagram of the third main reset line and the third sub-reset line in region BB of Figure 1. [Modes for carrying out the invention]

[0008] The following describes the technical concepts in the embodiments of this application clearly and completely, with reference to the accompanying drawings of the embodiments. However, it is clear that the embodiments described are only a part of the embodiments of this application, and not all of them. All other embodiments that can be obtained by those skilled in the art without creative effort based on the embodiments of this application are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are intended to illustrate and explain the application only, and not to limit it.

[0009] Furthermore, please understand that the orientations and positional relationships indicated by terms such as "length," "width," "thickness," "top," "bottom," "front," "back," "left," "right," "inside," and "outside" in the description of this application are based on the orientations and positional relationships shown in the drawings, and do not suggest or imply that the referred device or element has a specific orientation or must be constructed and operated in a specific orientation. These terms are merely for the convenience of describing and simplifying the description of this application, and therefore should not be interpreted as limiting this application.

[0010] Furthermore, the terms "first" and "second" are used only for the purpose of description and are not to be construed as indicating or suggesting relative importance or implicitly specifying the number of recited technical features. Therefore, the features limited to "first" and "second" can include one or more features, either explicitly or implicitly. In the description of the present application, unless explicitly and specifically limited, "plurality" means two or more, and "at least one" means one, two, or more.

[0011] Referring to FIG. 1, the present application provides a display panel 100, which includes a first display area 300, a second display area 400 located around the first display area 300, and a non-display area 200 located on one side of the second display area 400.

[0012] In some embodiments of the present application, a plurality of signal lines connected to pixel circuits are provided in both the second display area 400 and the first display area 300. However, since a light-transmitting portion 300b is provided in the first display area 300, some signal lines may cross the light-transmitting portion 300b in the first display area 300 and occupy the area of the light-transmitting portion 300b. As a result, the effective light-transmitting area in the light-transmitting portion 300b is reduced, for example, the configuration shown in FIG. 2.

[0013] Referring to FIG. 3, a plurality of first pixel circuits 310 and a plurality of light-transmitting portions 300b located between the plurality of first pixel circuits 310 are provided in the first display area 300, and a plurality of second pixel circuits 410 are provided in the second display area 400. Each of the signal lines is connected to one row of the second pixel circuits 410, and at least two of the signal lines transmitting the same control signal are connected to a plurality of the same first pixel circuits 310.

[0014] By electrically connecting at least two signal lines that transmit the same control signal to a plurality of identical first pixel circuits 310, it is possible to avoid the signal lines directly crossing the first display area 300, reduce the area of the light-transmitting region occupied by the signal lines in the first display area 300, and thus increase the area of the light-transmitting region in the first display area 300.

[0015] Referring to FIG. 3, a plurality of functional sub-parts 300a and a plurality of light-transmitting parts 300b located between the plurality of functional sub-parts 300a may be provided in the first display area 300. Each functional sub-part 300a includes a plurality of first pixel circuits 310 and one sub-signal line group 320. One sub-signal line group 320 is connected to the corresponding plurality of first pixel circuits 310, and each sub-signal line group 320 includes at least one sub-signal line.

[0016] Referring to FIG. 3, a plurality of first main parts 400a may be provided in the second display area 400. Each first main part 400a includes a plurality of second pixel circuits 410 arranged along at least two rows in the first direction X and at least two main signal line groups 420. One main signal line group 420 is connected to the corresponding row of second pixel circuits 410, and each main signal line group 420 includes at least one main signal line. And one functional sub-part 300a corresponds to one first main part 400a.

[0017] For example, in the functional sub-part 300a and the first main part 400a corresponding to the functional sub-part 300a, at least two main signal lines that transmit the same control signal in the first main part 400a are electrically connected to a parallel connection node with one sub-signal line that transmits the same control signal in the functional sub-part 300a. Thereby, it is possible to avoid the main signal lines that transmit the same control signal in the first main part 400a from crossing the functional sub-part 300a, which is equivalent to increasing the area of the light-transmitting region in the functional sub-part 300a.

[0018] Furthermore, since there are multiple main signal lines that transmit different control signals in the signal lines that cross the first display area 300, the present invention can avoid the light-transmitting portion 300b in the first display area 300 by electrically connecting the corresponding main signal line that transmits at least one type of control signal to the corresponding sub-signal line.

[0019] The display panel 100 may include multiple first display areas 300, and the shape of each first display area 300 in plan view is not limited to a circle, rectangle, or rounded rectangle. For example, in the configuration of Figure 1, the display panel 100 may include one first display area 300.

[0020] In the configuration shown in Figure 3, the first display area 300 is provided with multiple first main sections 400a on both sides in the first direction X.

[0021] Furthermore, one first main unit 400a corresponds to one functional sub-unit 300a, and one first main unit 400a has at least two rows of second pixel circuits 410, while one functional sub-unit 300a has only one row of first pixel circuits 310. Therefore, in order to increase the light transmittance of the first display area 300, the present invention reduces the number of rows of first pixel circuits 310 in the first display area 300. For example, in the configuration shown in Figure 3, one first main unit 400a has two rows of second pixel circuits 410, and one functional sub-unit 300a has one row of first pixel circuits 310, meaning that one row of first pixel circuits 310 corresponds to two rows of second pixel circuits 410.

[0022] Furthermore, since the number of rows in the first pixel circuit 310 in the first display area 300 is reduced, the number of light-emitting elements connected to the first pixel circuit 310 is reduced, and consequently the resolution of the first display area 300 is no longer lower than the resolution of the second display area 400. For this reason, the present invention may increase the number of light-emitting elements connected to the first pixel circuit 310 in order to improve the difference in resolution between the first display area 300 and the second display area 400.

[0023] For example, the first display area 300 may include a plurality of first light-emitting elements 330, and the second display area 400 further includes a plurality of second light-emitting elements 430, and one second pixel circuit 410 is electrically connected to one second light-emitting element 430, and one first pixel circuit 310 is electrically connected to two first light-emitting elements 330. In the first display area 300, the resolution of the first display area 300 is increased by electrically connecting one first pixel circuit 310 to two first light-emitting elements 330.

[0024] Furthermore, since one first pixel circuit 310 is electrically connected to two first light-emitting elements 330, the light-emitting elements do not occupy a relatively large area of ​​the light-transmitting portion 300b, and therefore the area of ​​the first light-emitting element 330 in this application is smaller than the area of ​​the second light-emitting element 430.

[0025] Furthermore, in order that the arrangement of the first pixel circuits 310 in the first display area 300 does not occupy a relatively large area of ​​the light-transmitting portion 300b, the multiple first pixel circuits 310 in this application are arranged in the form of pixel cells 340, with two adjacent pixel cells 340 spaced apart, and each first pixel circuit 310 has the same configuration. For example, in the configurations of Figures 11 to 13, one pixel cell 340 may include three clustered first pixel circuits 310, and the six first light-emitting elements 330 connected to each pixel cell 340 may be light-emitting elements with two red emission colors, two green emission colors, and two blue emission colors.

[0026] The plurality of pixel cells 340 in this application may have two arrangement methods. In the first arrangement method, the plurality of pixel cells 340 are arranged in an array along a first direction X and a second direction Y, that is, the plurality of pixel cells 340 are arranged to form rows and columns in the first direction X and the second direction Y, that is, each sub-control line may be connected to one row of first pixel circuits 310. Alternatively, the plurality of pixel cells 340 in this application are arranged along the first direction X to form a plurality of pixel cell rows, and two adjacent rows of pixel cells 340 are offset from each other, that is, each sub-control line may be connected to two offset rows of first pixel circuits 310.

[0027] Furthermore, in order to increase the area of ​​the light-transmitting portion 300b, the area of ​​each first pixel circuit 310 is smaller than the area of ​​each second pixel circuit 410, which corresponds to a further reduction in the area occupied by the first pixel circuit 310 in the first display area 300.

[0028] Referring to Figures 11 to 13, the second display area 400 is provided with a plurality of second pixel circuits 410, and in the first main part 400a, two adjacent second pixel circuits 410 arranged along the first direction X are provided symmetrically with respect to the center line of the two adjacent second pixel circuits 410 as the axis. That is, the present invention provides two adjacent second pixel circuits 410 symmetrically, and ensures that the configuration of the second pixel circuits 410 in the same row is the same, so as not to limit the invention to a compact type.

[0029] Referring to Figures 11 to 13, since one row of first pixel circuits 310 corresponds to two rows of second pixel circuits 410, the present invention may provide the first pixel circuit 310 of this row in a corresponding row between the two rows of second pixel circuits 410. For example, the extension of the boundary line of two adjacent rows of second pixel circuits 410 coincides with the median line parallel to the first direction X in the corresponding first pixel circuit 310, or the value of the difference between this extension and its center is within a predetermined range.

[0030] Although the number of first pixel circuits 310 in the first display area 300 of this application has been reduced, the area occupied by the first pixel circuits 310 has been reduced, so the sum of the second pixel circuits 410 and the first pixel circuits 310 in one row of pixel circuits in this application has not been reduced. For example, in a second display area 400 where no first pixel circuits 310 are provided, the number of second pixel circuits 410 in one row is a0, and in a sub-pixel row where the first pixel circuits 310 are provided, the number of second pixel circuits 410 in this sub-pixel row is a1 and the number of first pixel circuits 310 is a2, then the sum of a1 and a2 in this application is equal to a0.

[0031] Similarly, since two first light-emitting elements 330 can be connected to one first pixel circuit 310 of the present invention, the area of ​​the light-emitting region in the first display region 300 of the present invention is reduced, but the number of light-emitting units per unit area in the first display region 300 is equal to the number of light-emitting units per unit area in the second display region 400.

[0032] The first display area 300 may also correspond to a sensor. The sensor receives light incident from the light-transmitting portion 300b in the first display area 300 and forms a corresponding voltage or current signal, etc. For example, the sensor may include a fingerprint recognition sensor, a camera, a structural light sensor, a time-of-flight sensor, a distance sensor, a light sensor, etc. The sensor collects signals through the light-transmitting portion 300b and enables the display panel 100 to implement solutions such as under-screen fingerprint recognition, under-screen camera, under-screen face recognition, and under-screen distance detection.

[0033] The first light-emitting element 330 and the second light-emitting element 430 of this application may both be organic light-emitting diodes, mini LEDs, micro LEDs, conventional-sized LEDs, or other light sources.

[0034] Furthermore, the angle between the first direction X and the second direction Y in this application is greater than 0 and 90° or less. For example, the first direction X in this application may be the horizontal direction from the non-display area 200 toward the display area, the second direction Y may be the vertical direction, and the angle between the first direction X and the second direction Y may be 90°.

[0035] The technical proposal of this application will be explained below, along with specific examples.

[0036] Referring to Figures 1 and 3, a bonding pad 500 is provided below the second display area 400. The bonding pad 500 may be connected to an external circuit, and the bonding pad 500 transmits signals input from the external circuit to the data wiring, driving the display panel 100 to display the screen. For example, the bonding pad 500 may be bonded to a chip or flip-chip thin film, etc., in order to provide power and drive signals to the display panel 100.

[0037] In this embodiment, both the second pixel circuit 410 and the first pixel circuit 310 may be pixel circuits such as 7T1C, 7T2C, 8T2C, 8T3C, or 8T4C. In the following embodiment, an 8T2C pixel circuit will be described as an example.

[0038] Referring to Figure 4, both the second pixel circuit 410 and the first pixel circuit 310 may include a switching transistor T2, a drive transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boost capacitor Cboost, and a storage capacitor Cst. The storage capacitor Cst includes a first pole plate Cst1 and a second pole plate Cst2, and the boost capacitor Cboost includes a third pole plate and a fourth pole plate.

[0039] Referring to Figure 4, the first electrode of switching transistor T2 is connected to the data signal line Data, the second electrode of switching transistor T2 is connected to the first node A1, and the gate of switching transistor T2 receives the switching control signal Pscan1. The first electrode of driving transistor T1 is connected to the first node A1, the second electrode of driving transistor T1 is connected to the second node B1, and the gate of driving transistor T1 is connected to the third node Q1. The first electrode of compensating transistor T3 is connected to the third node Q1, the second electrode of compensating transistor T3 is connected to the second node B1, and the gate of compensating transistor T3 receives the compensation control signal Nscan1. The first electrode of the first reset transistor T4 receives the first reset signal Vi1, the second electrode of the first reset transistor T4 is connected to the third node Q1, and the gate of the first reset transistor T4 receives the first reset control signal Nscan2. The first electrode of the second reset transistor T7 is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7 is connected to the fourth node, i.e., the anode of the light-emitting element, and the gate of the second reset transistor T7 receives the second reset control signal Pscan2. The first electrode of the third reset transistor T8 receives the third reset signal Vi3, and the second electrode of the third reset transistor T8 is connected to the first node A1, and the gate of the third reset transistor T8 receives the third reset control signal. The first electrode of the first light-emitting transistor T5 is connected to the high-potential line VDD, and the second electrode of the first light-emitting transistor T5 is connected to the first node A1, and the gate of the first light-emitting transistor T5 receives the light-emitting control signal EM. The first electrode of the second light-emitting transistor T6 is connected to the second node B1, and the second electrode of the second light-emitting transistor T6 is connected to the fourth node D1, and the gate of the second light-emitting transistor T6 receives the light-emitting control signal EM. The third electrode plate of the boost capacitor Cboost is connected to the third node Q1, and the fourth electrode plate of the boost capacitor Cboost is connected to the gate of the switching transistor T2. The first electrode plate of the storage capacitor Cst is connected to the third node Q1, and the second electrode plate of the storage capacitor Cst is connected to the high-potential line VDD. The cathode of the light-emitting element is connected to the low-potential line VSS.

[0040] In this embodiment, the high-potential line VDD is used to provide a high-level constant voltage to the second pixel circuit 410 or the first pixel circuit 310, and the low-potential line VSS is used to provide a low-level constant voltage to the second pixel circuit 410 or the first pixel circuit 310.

[0041] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 may be either P-type or N-type transistors. The compensation transistor T3 and the first reset transistor T4 may be the other of P-type or N-type transistors. This application describes the case where the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 are P-type transistors, and the compensation transistor T3 and the first reset transistor T4 are N-type transistors as an example.

[0042] In this embodiment, the capacitance value of the boost capacitor Cboost is smaller than that of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain stability regarding the potential of the third node Q1, so the capacitance value of the storage capacitor Cst is relatively large. For example, the capacitance value range of the storage capacitor Cst may be 45fF to 55fF, and the capacitance value range of the boost capacitor Cboost may be 5fF to 15fF.

[0043] In this embodiment, the first electrode may be either the source or the drain, and the second electrode may be the other of the source or the drain.

[0044] Referring to Figures 1 and 3, the non-display area 200 may include two non-display sub-sections 210 located on either side of the second display area 400. Each of the two non-display sub-sections 210 is provided with a gate drive circuit, and the output terminal of the gate drive circuit is connected to at least one of the signal lines.

[0045] In this embodiment, the gate drive circuit may include gate circuits that output different control signals. The type of gate circuit in the non-display area 200 relates to the second pixel circuit 410 or the first pixel circuit 310. For example, the second pixel circuit 410 or the first pixel circuit 310 requires a compensation control signal Nscan1, a first reset control signal Nscan2, a second reset control signal Pscan2, a light emission control signal EM, and a switching control signal Pscan1. Therefore, in the non-display area 200 of this application, it is necessary to install five types of gate circuits that output the above-mentioned control signals.

[0046] In the configurations shown in Figures 3 and 9, the second display area 400 may contain the main compensation control line 421, the first main reset control line 422, the second main reset control line 423, the main light emission control line 424, the main switching control line 425, the first main reset line 426, the second main reset line 427, and the third main reset line 428, which constitute the main signal line group 420.

[0047] In the configurations shown in Figures 3 and 10, the first display area 300 may contain a sub-compensation control line 321, a first sub-reset control line 322, a second sub-reset control line 323, a sub-light emission control line 324, a sub-switching control line 325, a first sub-reset line 326, a second sub-reset line 327, and a third sub-reset line 328, which constitute the sub-signal line group 320.

[0048] In this embodiment, the sub-compensation control line 321 and the main compensation control line 421 are used to transmit the compensation control signal Nscan1, the first sub-reset control line 322 and the first main reset control line 422 are used to transmit the first reset control signal Nscan2, the second sub-reset control line 323 and the second main reset control line 423 are used to transmit the second reset control signal Pscan2, the sub-light emission control line 324 and the main light emission control line 424 are used to transmit the light emission control signal EM, the sub-switching control line 325 and the main switching control line 425 are used to transmit the switching control signal Pscan1, the first main reset line 426 and the first sub-reset line 326 are used to transmit the first reset signal Vi1, the second main reset line 427 and the second sub-reset line 327 are used to transmit the second reset signal Vi2, and the third main reset line 428 and the third sub-reset line 328 are used to transmit the third reset signal Vi3.

[0049] In the configuration shown in Figure 3, the non-display area 200 may include a plurality of first gate circuits 210 arranged and cascaded along the second direction Y, a plurality of second gate circuits 220 arranged and cascaded along the second direction Y, a plurality of third gate circuits 230 arranged and cascaded along the second direction Y, a plurality of fourth gate circuits 240 arranged and cascaded along the second direction Y, and a plurality of fifth gate circuits 240 arranged and cascaded along the second direction Y.

[0050] Referring to Figure 3, the first gate circuits 210 are provided on both sides of the second display area 400 and are used to transmit the compensation control signal Nscan1, with one first gate circuit 210 connected to two main compensation control lines 421. In addition, the one-stage first gate circuit 210 of this application is used to output the compensation control signal Nscan1 to two rows of second pixel circuits 410, that is, two rows of second pixel circuits 410 require one-stage first gate circuit 210.

[0051] Referring to Figure 3, the second gate circuits 220 are provided on both sides of the second display area 400, and the second gate circuits 220 and the first gate circuits 210 are arranged along the second direction Y. The second gate circuits 220 are used to transmit the first reset control signal Nscan2, and one second gate circuit 220 is connected to two adjacent first main reset control lines 422. In addition, the one-stage second gate circuit 220 of the present invention is used to output the first reset control signal Nscan2 to two rows of second pixel circuits 410, that is, two rows of second pixel circuits 410 require one-stage second gate circuit 220.

[0052] Referring to Figure 3, the fifth gate circuit 240 is provided on both sides of the second display area 400 and is located between the second display area 400 and the first gate circuit 210, and between the second display area 400 and the second gate circuit 220, and is used to transmit the switching control signal Pscan1. One fifth gate circuit 240 is connected to two adjacent main switching control lines 425, and together, one stage of the fifth gate circuit 240 of this application is used to output the switching control signal Pscan1 to one row of second pixel circuits 410, that is, one row of second pixel circuits 410 requires one stage of the fifth gate circuit 240.

[0053] In the configuration shown in Figure 3, each non-display sub-section 210 is provided with a first gate circuit 210, a second gate circuit 220, and a fifth gate circuit 240. That is, the first gate circuit 210, the second gate circuit 220, and the fifth gate circuit 240 of this application are driven simultaneously from both sides.

[0054] Referring to Figure 3, the third gate circuit 230 is located on the first side of the second display area 400 and on the side of the first gate circuit 210 away from the second display area 400, and is used to transmit the second reset control signal Pscan2, and one third gate circuit 230 is connected to two adjacent second main reset control lines 423. At the same time, the one-stage fourth gate circuit 240 of the present invention is used to output the compensation control signal Nscan1 to the two rows of second pixel circuits 410, that is, the two rows of second pixel circuits 410 require one-stage third gate circuit 230.

[0055] Referring to Figure 3, the fourth gate circuit 240 is located on the second side of the second display area 400 and away from the second display area 400 of the first gate circuit 210, and is used to transmit the light emission control signal EM, and one fourth gate circuit 240 is connected to two adjacent main light emission control lines 424. In addition, the one-stage fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two rows of second pixel circuits 410, that is, the two rows of second pixel circuits 410 require one-stage fourth gate circuit 240.

[0056] In this invention, only the third gate circuit 230 is provided in one of the non-display sub-sections 210, and only the fourth gate circuit 240 is provided in the other non-display sub-section 210; that is, the third gate circuit 230 and the fourth gate circuit 240 are driven from one side.

[0057] Furthermore, since the first reset signal Vi1, the second reset signal Vi2, and the third reset signal Vi3 are all constant voltages, they do not need to be controlled by corresponding gate circuits, and the corresponding constant voltage sources can be connected directly.

[0058] In this embodiment, the first gate circuit 210, second gate circuit 220, third gate circuit 230, fourth gate circuit 240, and fifth gate circuit 240 of the present application may be gate circuits of mTnC. In the following embodiment, the case in which the first gate circuit 210 and the second gate circuit 220 are first circuits of 16T5C, the third gate circuit 230 and the fourth gate circuit 240 are second circuits of 13T3C, and the fifth gate circuit 240 is a third circuit of 8T3C will be described as an example.

[0059] Referring to Figure 5, the first circuit 21 may include a stage transmission circuit 211, an output circuit 212, a stage transmission frequency divider circuit 213, and an output frequency divider circuit 214.

[0060] Referring to Figure 5, the stage transmission circuit 211 includes a stage transmission receiving circuit 2111 and a stage transmission output circuit 2112. The stage transmission receiving circuit 2111 is used to receive the stage transmission signal generated from the first circuit 21 of the previous stage, and the stage transmission output circuit 2112 is electrically connected to the stage transmission receiving circuit 2111 by control nodes P1 and Q1, and is used to output the stage transmission signal of the current stage to the first circuit 21 of the next stage based on the signals from control node P1 and control node Q1.

[0061] Referring to Figure 5, the output circuit 212 is electrically connected to control nodes P1 and Q1 in the stage transmission circuit 211. The output circuit 212 outputs a gate control signal based on the frequency division control signal FD, the signals from control nodes P1 and Q1, and the output circuit 212 is electrically connected to the clock signal line. The clock signal lines connected to the first circuit 21 of two adjacent stages are different.

[0062] Referring to Figure 5, one end of the output frequency divider circuit 214 is connected to the output circuit 212 at control node S1, and the other end of the output frequency divider circuit 214 is connected to the stage transmission circuit 211 at one of control nodes P1 and Q1. The output frequency divider circuit 214 controls the signal transmission between one of control nodes P1 and Q1 and the output circuit 212 based on the signal from one of control nodes P1 and Q1 and the frequency division control signal FD.

[0063] Referring to Figure 5, the stage transmission frequency divider circuit 213 is electrically connected to the stage transmission receiving circuit 2111 by control node R1 and electrically connected to the stage transmission output circuit 2112 by control node P1 or control node Q1. Based on the frequency division control signal FD, it controls the signal of either control node P1 or control node Q1 to control the stage transmission output circuit 2112 to output the stage transmission signal of the current stage.

[0064] Referring to Figure 5, the output frequency divider circuit 214 includes the 18th transistor T18A and the 20th transistor T20A, the gate of the 18th transistor T18A being connected to the first frequency divider signal line FDL1, the source of the 18th transistor T18A being electrically connected to control node P1 or control node Q1, and the drain of the 18th transistor T18A being electrically connected to control node S1. The gate of the 20th transistor T20A being electrically connected to control node Z1 of the stage transmission circuit 211, the source of the 20th transistor T20A being electrically connected to the first frequency divider signal line FDL1, and the drain of the 20th transistor T20A being electrically connected to the gate of the 18th transistor T18A.

[0065] Referring to Figure 5, the stage transmission frequency divider circuit 213 includes a 17th transistor T17A, the gate of the 17th transistor T17A is electrically connected to the second frequency divider signal line FDL2, the source of the 17th transistor T17A is electrically connected to the stage transmission receiver circuit 2111 by control node R1, and the drain of the 17th transistor T17A is electrically connected to control node P1 or control node Q1.

[0066] Referring to Figure 5, the stage transmission output circuit 2112 includes a 10th transistor T10A and a 9th transistor T9A. The gate of the 10th transistor T10A is electrically connected to control node P1, the source of the 10th transistor T10A is electrically connected to a high-level source VGH, and the drain of the 10th transistor T10A is electrically connected to the stage transmission output terminal OUT, which outputs the stage transmission signal in the first circuit 21. The gate of the 9th transistor T9A is electrically connected to control node Q1, the source of the 9th transistor T9A is electrically connected to a low-level source VGL, and the drain of the 9th transistor T9A is electrically connected to the stage transmission output terminal OUT.

[0067] Referring to Figure 5, the output circuit 212 includes a 22nd transistor T22A and a 21st transistor T21A, the gate of the 22nd transistor T22A being electrically connected to control node S1, the source of the 22nd transistor T22A being electrically connected to the high-potential line VGH, and the drain of the 22nd transistor T22A being connected to the first output terminal OUT1. The gate of the 21st transistor T21A being electrically connected to control node P1 or control node Q1, the source of the 21st transistor T21A being electrically connected to the low-level source VGL, and the drain of the 21st transistor T21A being connected to the first output terminal OUT1.

[0068] Referring to Figure 5, the stage transmission receiving circuit 2111 includes a third transistor T3A, to which a first clock signal XCK is applied to the gate of the third transistor T3A, the source of the third transistor T3A is connected to the first input terminal IN1, and the drain of the third transistor T3A is connected to the control node D1.

[0069] Referring to Figure 5, the stage transmission receiver circuit 2111 includes a fourth transistor T4A, a fifth transistor T5A, and sixth transistors T6A and seventh transistors T7A installed in series. The gate of the fifth transistor T5A is electrically connected to the drain of the third transistor T3A, a first clock signal XCK is applied to the source of the fifth transistor T5A, a first clock signal XCK is applied to the gate of the fourth transistor T4A, a low-level source VGL is applied to the source of the fourth transistor T4A, the drain of the fourth transistor T4A is electrically connected to the gate of the sixth transistor T6A and the drain of the fifth transistor T5A, the drain of the sixth transistor T6A is electrically connected to the source of the seventh transistor T7A, a second clock signal CK is applied to both the source of the sixth transistor T6A and the gate of the seventh transistor T7A, and the drain of the seventh transistor T7A is electrically connected to the control node R1.

[0070] Referring to Figure 5, the stage transmission receiving circuit 2111 includes a 13th transistor T13A, a first capacitor C1A, and first transistors T1A and T2A installed in series. A control signal is applied to the gate of the 13th transistor T13A (electrically connected to the control line CL), a high-level source VGH is applied to the source of the 13th transistor T13A, the drain of the 13th transistor T13A is electrically connected to the control node Q1, the gate of the first transistor T1A is electrically connected to the drain of the fourth transistor T4A, a high-level source VGH is applied to the source of the first transistor T1A, the drain of the first transistor T1A is electrically connected to the source of the second transistor T2A, a second clock signal CK is applied to the drain of the second transistor T2A, the stage transmission signal generated from the first circuit 21 of the previous stage is also applied to the gate of the second transistor T2A, and the first capacitor C1A is electrically connected between the gate and drain of the second transistor T2A.

[0071] Referring to Figure 5, the stage transmission receiving circuit 2111 includes an eleventh transistor T11A, a second capacitor C2A, and a twelfth transistor T12A, and the stage transmission output circuit 2112 may further include a third capacitor C3A electrically connected between the gate and source of the tenth transistor T10A. The gates of both the eleventh transistor T11A and the twelfth transistor T12A can be kept on by applying a low-level source VGL. The source and drain of the eleventh transistor T11A are electrically connected to the drain of the fourth transistor T4A and the gate of the sixth transistor T6A, respectively, the second capacitor C2A is electrically connected between the gate and drain of the sixth transistor T6A, and the source and drain of the twelfth transistor T12A are electrically connected to the drain of the third transistor T3A and the control node Q1, respectively.

[0072] Referring to Figure 5, the stage transmission receiver circuit 2111 includes an eighth transistor T8A, the gate of which is connected to control node Z1, the drain of the 19th transistor T19A is connected to a high-level source VGH, and the source of the 19th transistor T19A is connected to control node S1.

[0073] Referring to Figure 5, the first circuit further includes a 19th transistor T19A, the gate of which is connected to control node Z1, the drain of the 8th transistor T8A, the high-level source VGH, and the source of which is connected to control node P1.

[0074] Referring to Figure 5, the stage transmission receiver circuit 2111 includes a 14th transistor T14A and a 16th transistor T16A. The source of the 14th transistor T14A is electrically connected to the first input terminal IN1, the first clock signal XCK is applied to the gate of the 14th transistor T14A, and the drain of the 14th transistor T14A is electrically connected to the gate of the second transistor T2A. Both the gate and source of the 16th transistor T16A are electrically connected to the gate of the second transistor T2A, and the drain of the 16th transistor T16A is electrically connected to the control node Q1.

[0075] Referring to Figure 5, the stage transmission receiving circuit 2111 includes a 15th transistor T15A, and a low-level source VGL may be applied to the gate of the 15th transistor T15A, and the source and drain of the 15th transistor T15A may be electrically connected to the drain of the 14th transistor T14A and the gate of the 2nd transistor T2A, respectively.

[0076] Referring to Figure 5, the first circuit 21 further includes a first coupling capacitor C4A and a second coupling capacitor C5A. One end of the first coupling capacitor C4A is connected to a high-potential line Vgh, and the other end of the first coupling capacitor C4A is connected to the gate of the 22nd transistor T22A. One end of the second coupling capacitor C5A is connected to a high-potential line Vgh, and the other end of the second coupling capacitor C5A is connected to the gate of the 18th transistor T18A.

[0077] In Figure 5, the first output terminal OUT1 is used to output either the compensation control signal Nscan1 or the first reset control signal Nscan2.

[0078] Referring to Figure 6, the second circuit 22 may also include a receiving circuit 221 and an export circuit 222. The receiving circuit 221 is used to receive the stage transmission signal generated from the second circuit 22 of the previous stage, and the export circuit 222 is electrically connected to the receiving circuit 221 by control nodes P2 and Q2, and is used to output a control signal for the current stage, such as a light emission control signal or a second reset control signal, based on the signals from control node P2 and control node Q2.

[0079] Referring to Figure 6, the export circuit 222 includes a 10th transistor T10B and a 9th transistor T9B, the gate of the 10th transistor T10B is electrically connected to control node P2, the source of the 10th transistor T10B is electrically connected to high-level source VGH, and the drain of the 10th transistor T10B is electrically connected to the second output terminal OUT2 in the second circuit 22. The gate of the 9th transistor T9B is electrically connected to control node Q2, the source of the 9th transistor T9B is electrically connected to low-level source VGL, and the drain of the 9th transistor T9B is electrically connected to the second output terminal OUT2.

[0080] Referring to Figure 6, the receiving circuit 221 includes a third transistor T3B, to which a first clock signal XCK is applied to the gate of the third transistor T3B, the source of the third transistor T3B is connected to the second input terminal IN2, and the drain of the third transistor T3B is connected to the control node D2.

[0081] Referring to Figure 6, the receiving circuit 221 includes a fourth transistor T4B, a fifth transistor T5B, a sixth transistor T6B, and a seventh transistor T7B. The gate of the fifth transistor T5B is electrically connected to the drain of the third transistor T3B. A first clock signal XCK is applied to the source of the fifth transistor T5B. A first clock signal XCK is applied to the gate of the fourth transistor T4B. A low-level source VGL is applied to the source of the fourth transistor T4B. The drain of the fourth transistor T4B is electrically connected to the gate of the sixth transistor T6B and the drain of the fifth transistor T5B. The drain of the sixth transistor T6B is electrically connected to the source of the seventh transistor T7B. A second clock signal CK is applied to both the source of the sixth transistor T6B and the gate of the seventh transistor T7B. The drain of the seventh transistor T7B is electrically connected to the control node P2.

[0082] Referring to Figure 6, the receiving circuit 221 includes a 13th transistor T13B, a first capacitor C1B, a first transistor T1B, and a second transistor T2B. A control signal is applied to the gate of the 13th transistor T13B (electrically connected to the control line CL), a high-level source VGH is applied to the source of the 13th transistor T13B, the drain of the 13th transistor T13B is electrically connected to the control node D2, the gate of the first transistor T1B is electrically connected to the drain of the fourth transistor T4B, a high-level source VGH is applied to the source of the first transistor T1B, the drain of the first transistor T1B is electrically connected to the source of the second transistor T2B, a second clock signal CK is applied to the drain of the second transistor T2B, the stage transmission signal generated from the second circuit 22 of the previous stage is also applied to the gate of the second transistor T2B, and the first capacitor C1B is electrically connected between the gate and drain of the second transistor T2B.

[0083] Referring to Figure 6, the receiving circuit 221 includes an eleventh transistor T11B, a second capacitor C2B, and a twelfth transistor T12B, and the export circuit 222 may further include a third capacitor C3B electrically connected between the gate and source of the tenth transistor T10B. The gates of both the eleventh transistor T11B and the twelfth transistor T12B can be kept on by applying a low-level source VGL. The source and drain of the eleventh transistor T11B are electrically connected to the drain of the fourth transistor T4B and the gate of the sixth transistor T6B, respectively. The second capacitor C2B is electrically connected between the gate and drain of the sixth transistor T6B, and the source and drain of the twelfth transistor T12B are electrically connected to control node D2 and control node Q2, respectively.

[0084] Referring to Figure 6, the receiving circuit 221 includes an eighth transistor T8B, the gate of the eighth transistor connected to control node D2, the drain of the eighth transistor T8B connected to a high-level source VGH, and the source of the eighth transistor T8B connected to control node P2.

[0085] In Figure 6, the second output terminal OUT2 is used to output the second reset control signal Pscan2 or the light emission control signal EM.

[0086] Referring to Figure 7, the three types of circuits 23 may include a first transistor T1C, a second transistor T2C, a third transistor T3C, a fourth transistor T4C, a fifth transistor T5C, a sixth transistor T6C, a seventh transistor T7C, an eighth transistor T8C, a first capacitor C1C, and a second capacitor C2C.

[0087] Referring to Figure 7, the gate of the seventh transistor T7C is electrically connected to control node P3, the source of the seventh transistor T7C is electrically connected to the high-level source VGH, and the drain of the seventh transistor T7C is electrically connected to the third output terminal OUT3 in the third circuit 23. The gate of the sixth transistor T6C is electrically connected to control node Q3, the source of the sixth transistor T6C is connected to the second clock signal CK, and the drain of the sixth transistor T6C is electrically connected to the third output terminal OUT3. At the same time, both ends of the first capacitor C1C are connected to control node Q3 and the third output terminal OUT3, respectively, and both ends of the second capacitor C2C are connected to control node Q3 and the third output terminal OUT3, respectively.

[0088] Referring to Figure 7, the first clock signal XCK is applied to the gate of the third transistor T3C, the source of the third transistor T3C is connected to the third input terminal IN3, and the drain of the third transistor T3C is connected to the control node D3.

[0089] Referring to Figure 7, the gate of the fifth transistor T5C is electrically connected to control node D3, the first clock signal XCK is applied to the source of the fifth transistor T5C, the first clock signal XCK is applied to the gate of the fourth transistor T4C, the low-level source VGL is applied to the source of the fourth transistor T4C, and the drain of the fourth transistor T4C is electrically connected to control node P3 and the drain of the fifth transistor T5C.

[0090] Referring to Figure 7, the gate of the first transistor T1C is electrically connected to control node P3, a high-level source VGH is applied to the source of the first transistor T1C, the drain of the first transistor T1C is electrically connected to the source of the second transistor T2C, the drain of the second transistor T2C is connected to control node D3, and a second clock signal CK is applied to the gate of the second transistor T2C.

[0091] Referring to Figure 7, the gate of the eighth transistor T8C is connected to the low-level source VGL, and the source and drain of the eighth transistor T8C are connected to control node D3 and control node Q3, respectively.

[0092] In Figure 7, the third output terminal OUT3 is used to output the switching control signal Pscan1.

[0093] The film layer configurations relating to the second pixel circuit 410, the first pixel circuit 310, and the five gate circuits of this application will be described below with reference to the pixel configuration shown in Figure 4.

[0094] Referring to Figure 8, the first display area 300, the second display area 400, and the non-display area 200 of the display panel 100 may each include a base substrate 110 and an array driving layer 120 provided on the base substrate 110. In the second display area 400 and the first display area 300, the display panel 100 may be provided with a pixel definition layer (not shown) on the array driving layer 120, a light-emitting element layer (not shown) installed on the same layer as the pixel definition layer, and a sealing layer (not shown) provided on the pixel definition layer. The following description will mainly focus on the film layer configuration of the array driving layer 120.

[0095] In this embodiment, the base substrate 110 supports each layer provided on the base substrate 110. When the display panel 100 is a bottom-emission light-emitting display device or a double-sided emission light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emission light-emitting display device, not only a transparent base substrate but also a translucent or opaque base substrate may be used.

[0096] In this embodiment, the base substrate 110 is used to support each film layer provided on the base substrate 110. The base substrate 110 may be made from an insulating material such as glass, quartz, or polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or curled. Examples of flexible materials for flexible substrates include, but are not limited to, polyimide (PI).

[0097] In this embodiment, the base substrate 110 may include a first flexible base 111, a first barrier layer 112, a second flexible base 113, and a second barrier layer 114, which are stacked and installed. The first flexible base 111 and the second flexible base 113 may be formed from the same material, for example, polyimide. The first barrier layer 112 and the second barrier layer 114 may be formed from an inorganic material, for example, containing at least one of SiOx and SiNx.

[0098] In this embodiment, the first flexible base 111 is formed by coating a support substrate with a polymer material and curing the polymer material. The second flexible base 113 is formed by coating the first flexible base 111 with the same material and curing the material, and is formed in the same manner as the first flexible base 111. Both the first flexible base 111 and the second flexible base 113 may be formed to have a thickness of approximately 8 μm to approximately 12 μm. Furthermore, when the base substrate 110 is formed from the first flexible base 111 and the second flexible base 113, micropores, cracks, etc., formed during the manufacturing process of the first flexible base 111 are covered by the second flexible base 113, thereby eliminating the aforementioned defects.

[0099] Referring to Figure 8, the array driving layer 120 may include a plurality of thin-film transistors. The thin-film transistors may be etch-stop type, back-channel etching type, or may be divided into configurations such as bottom-gate thin-film transistors and top-gate thin-film transistors depending on the position of the gate and active layer, or may be divided into N-type thin-film transistors and P-type thin-film transistors depending on the function of the thin-film transistors. Here, the thin-film transistors in Figure 8 are not configuration diagrams relating to any of the transistors in Figure 4, but merely schematic diagrams relating to each film layer of the display panel 100 of this application.

[0100] Referring to Figure 8, the array drive layer 120 includes a light-shielding layer 121 provided on the base substrate 110, a buffer layer 122 provided on the light-shielding layer 121, a first active layer 123 provided on the buffer layer 122, a first gate insulating layer 124 provided on the first active layer 123, a first gate layer 125 provided on the first gate insulating layer 124, a second gate insulating layer 126 provided on the first gate insulating layer 126, a third gate insulating layer 128 provided on the second gate layer 127, and a third gate The material may also include a second active layer 129 provided on the gate insulating layer 128, a fourth gate insulating layer 130 provided on the second active layer 129, a third gate layer 131 provided on the fourth gate insulating layer 130, a first inter-gate insulating layer 132 provided on the third gate layer 131, a first source-drain layer 133 provided on the first inter-gate insulating layer 132, a second inter-gate insulating layer 134 provided on the first source-drain layer 133, a second source-drain layer 135 provided on the second inter-gate insulating layer 134, and a flat layer 136 provided on the second source-drain layer 135.

[0101] Referring to Figure 8, the light-shielding layer 121 is provided on the second barrier layer 114 and is used to shield external light from entering the thin-film transistor from the bottom. The material of the light-shielding layer 121 may be a black light-shielding material, such as a black light-shielding metal or a black organic material.

[0102] Referring to Figure 8, the buffer layer 122 is provided on the light-shielding layer 121 and is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may consist of a compound comprising nitrogen, silicon, and oxygen, for example, a single layer of silicon oxide film, or a silicon oxide-silicon nitride laminated structure.

[0103] Referring to Figure 8, the first active layer 123 may be provided on the buffer layer 122, and the second active layer 129 may be provided on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 may be indium gallium zinc oxide semiconductor, amorphous silicon, or low-temperature polysilicon. For example, in this application, the material of the first active layer 123 may be low-temperature polysilicon, and the material of the second active layer 129 may be indium gallium zinc oxide semiconductor.

[0104] Referring to Figure 8, the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first inter-gate insulating layer 132, the second inter-gate insulating layer 134, and the third inter-gate insulating layer 136 are each provided on the corresponding metal or semiconductor layer, with the metal or semiconductor layers of different layers being placed apart. The materials of the first gate insulating layer 124, the second gate insulating layer 126, the first inter-gate insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the second inter-gate insulating layer 134 may consist of an inorganic material with a nitrogen-oxygen-silicon combination, or a planar organic material.

[0105] Referring to Figure 8, the first gate layer 125, the second gate layer 127, and the third gate layer 131 are each provided on a corresponding insulating layer, and the materials of the first gate layer 125, the second gate layer 127, and the third gate layer 131 may be copper, molybdenum, or a molybdenum-titanium alloy, etc. The material of the three gate layers of this application may be molybdenum.

[0106] Referring to Figure 8, the first source-drain layer 133 is provided on the first inter-insulating layer 132, and the second source-drain layer 135 is provided on the second inter-insulating layer 134. The materials of the first source-drain layer 133 and the second source-drain layer 135 may be copper, molybdenum, molybdenum-titanium alloy, or a three-layer metal such as titanium-aluminum-titanium. The materials of the two source-drain layers in this application may also be titanium-aluminum-titanium.

[0107] Referring to Figure 8, the flat layer 136 is laid across the entire layer to ensure the flatness of the film layer of the array drive layer 120. The material of the flat layer 136 may consist of an inorganic material of nitrogen-oxygen-silicon combination, or an organic material having flatness.

[0108] Referring to Figures 9 and 10, Figure 9 is a partial film layer stacking diagram relating to the first main part 400a of the present application, and Figure 10 is a partial film layer stacking diagram relating to the functional sub-part 300a of the present application.

[0109] In the configuration shown in Figure 9, the first gate layer 125 may include a second main reset control line 423, a main light emission control line 424, a main switching control line 425, and a first main reset line 426. The second main reset control line 423, the main light emission control line 424, the main switching control line 425, and the first main reset line 426 all extend along a first direction. The first main reset line 426, the main switching control line 425, the main light emission control line 424, and the second main reset control line 423 are arranged along a second direction Y and spaced apart from each other.

[0110] In the configuration of Figure 10, the first gate layer 125 may include a second sub-reset control line 323, a sub-light emission control line 324, a sub-switching control line 325, and a first sub-reset line 326. The second sub-reset control line 323, the sub-light emission control line 324, the sub-switching control line 325, and the first sub-reset line 326 all extend along a first direction. The first sub-reset line 326, the sub-switching control line 325, the sub-light emission control line 324, and the second sub-reset control line 323 are arranged along a second direction Y and spaced apart from each other.

[0111] Referring to Figure 9, the second gate layer 127 includes a third main reset line 428, a first portion of the main compensation control line 421, and a first portion of the first main reset control line 422. The third main reset line 428, the first portion of the main compensation control line 421, and the first portion of the first main reset control line 422 all extend along a first direction. The first portion of the first main reset control line 422, the first portion of the main compensation control line 421, and the third main reset line 428 are arranged along a second direction Y and spaced apart from each other. The third main reset line 428 is located on the side of the second main reset control line 423 away from the main light emission control line 424.

[0112] Referring to Figure 10, the second gate layer 127 includes a third sub-reset line 328, a first portion of a sub-compensation control line 321, and a first portion of a first sub-reset control line 322. The third sub-reset line 328, the first portion of the sub-compensation control line 321, and the first portion of the first sub-reset control line 322 all extend along a first direction. The first portion of the first sub-reset control line 322, the first portion of the sub-compensation control line 321, and the third sub-reset line 328 are arranged along a second direction Y and spaced apart from each other. The third sub-reset line 328 is located on the side of the second sub-reset control line 323 away from the sub-light emission control line 324.

[0113] Referring to Figure 9, the third gate layer 131 includes a second reset signal Vi2, a second portion of the main compensation control line 421, and a second portion of the first main reset control line 422. The third main reset line 428, the first portion of the main compensation control line 421, and the first portion of the first main reset control line 422 all extend along the first direction. The first portion of the first main reset control line 422, the first portion of the main compensation control line 421, and the second reset signal Vi2 are arranged along the second direction Y and spaced apart from each other. The second reset signal Vi2 and the second main reset control line 423 overlap at least partially. In addition, the second and first parts of the main compensation control line 421 overlap at least partially, the second and first parts of the first main reset control line 422 overlap at least partially, the main compensation control line 421 is provided between the main switching control line 425 and the main light emission control line 424, and the first main reset control line 422 is provided between the main switching control line 425 and the first main reset line 426.

[0114] Referring to Figure 10, the third gate layer 131 includes a second reset signal Vi2, a second portion of the sub-compensation control line 321, and a second portion of the first sub-reset control line 322. The third sub-reset line 328, the first portion of the sub-compensation control line 321, and the first portion of the first sub-reset control line 322 all extend along the first direction. The first portion of the first sub-reset control line 322, the first portion of the sub-compensation control line 321, and the second reset signal Vi2 are arranged along the second direction Y and spaced apart from each other. The second reset signal Vi2 and the second sub-reset control line 323 overlap at least partially. In addition, the second and first parts of the sub-compensation control line 321 overlap at least partially, the second and first parts of the first sub-reset control line 322 overlap at least partially, the sub-compensation control line 321 is provided between the sub-switching control line 325 and the sub-light emission control line 324, and the first sub-reset control line 322 is provided between the sub-switching control line 325 and the first sub-reset line 326.

[0115] Referring to Figures 9 and 10, the first active layer 123 includes the switching active portion of the switching transistor T2, the driving active portion of the driving transistor T1, the second reset active portion of the second reset transistor T7, the third reset active portion of the third reset transistor T8, the first light-emitting active portion of the first light-emitting transistor T5, and the second light-emitting active portion of the second light-emitting transistor T6. The second active layer 129 includes the compensation active portion of the compensation transistor T3 and the first reset active portion of the first reset transistor T4.

[0116] Referring to Figures 9 and 10, the first source-drain layer 133 is primarily used to form the source and drain of at least some of the transistors in the second pixel circuit 410 and the first pixel circuit 310.

[0117] Referring to Figures 9 and 10, the second source-drain layer 135 includes a data signal line Data, a high-level line VDD, and a fan-out wiring FIAA. In the configuration of Figure 9, the data signal line Data is provided between two second pixel circuits 410, and the fan-out wiring is provided between two data signal lines Data. In the configuration of Figure 10, the data signal line Data is provided on one side of each first pixel circuit 310, and the high-level line VDD is provided between two adjacent data signal lines Data.

[0118] Referring to Figures 1 and 3, the second display area 400 further includes a second main section 400b. The second main section 400b is provided with a plurality of second pixel circuits 410 arranged along a first direction X in multiple rows, and since the plurality of rows of second pixel circuits 410 in the second main section 400b do not traverse the first display area 300, the five main signal lines in the second main section 400b can extend along the first direction X from one non-display sub-section 210 to the other non-display sub-section 210 of the display panel 100. On the other hand, with respect to the multi-row second pixel circuit 410 in the first main unit 400a, if the main signal lines in the two main signal line groups 420 of the first main unit 400a are arranged in the same way as the five main signal lines in the second main unit 400b in order to install the light-transmitting section 300b in the first display area 300, then there will be one main signal line group 420 in the first main unit 400a that overlaps with the light-transmitting section 300b in the first display area 300. As a result, the area of ​​the light-transmitting section 300b will be reduced, and the proportion of the area of ​​the light-transmitting section 300b in the first display area 300 will decrease.

[0119] Accordingly, the present invention reduces the number of main signal lines crossing the light-transmitting section 300b and, consequently, increases the area ratio of the light-transmitting section 300b in the first display area 300 by having at least one main signal line from one main signal line group 420 of the first main section 400a connected to a main signal line in another main signal line group 420 that transmits the same control signal, and also electrically connected to a sub-signal line in the functional sub-section 300a that transmits the same control signal.

[0120] For example, in a functional sub-unit 300a and a first main unit 400a corresponding to the functional sub-unit 300a, at least two main compensation control lines 421 in the first main unit 400a are electrically connected to one sub-compensation control line 321 in the functional sub-unit 300a at the first parallel connection node M1. And / or, at least two first main reset control lines 422 in the first main unit 400a are electrically connected to one first sub-reset control line 322 in the functional sub-unit 300a at the second parallel connection node M2. And / or, at least two second main reset control lines 423 in the first main unit 400a are electrically connected to one second sub-reset control line 323 in the functional sub-unit 300a at the third parallel connection node M3. And / or, at least two main light emission control lines 424 in the first main section 400a are electrically connected to one sub-light emission control line 324 in the functional sub-section 300a at the fourth parallel connection node M4.

[0121] That is, in the configurations of Figures 3 and 12, one main compensation control line 421 in the first main unit 400a is directly connected to the sub-compensation control line 321 in the corresponding functional sub-unit 300a, and another main compensation control line 421 in the first main unit 400a is connected to the sub-compensation control line 321 of the functional sub-unit 300a at the first parallel connection node M1. And / or, one first main reset control line 422 in the first main unit 400a is directly connected to the first sub-reset control line 322 in the corresponding functional sub-unit 300a, and another first main reset control line 422 in the first main unit 400a is connected to the first sub-reset control line 322 of the functional sub-unit 300a at the second parallel connection node M2. And / or, this corresponds to one second main reset control line 423 in the first main unit 400a being directly connected to the second sub-reset control line 323 in the corresponding functional sub-unit 300a, and another second main reset control line 423 in the first main unit 400a being connected to the second sub-reset control line 323 of the functional sub-unit 300a at the third parallel connection node M3. And / or, this corresponds to one main light emission control line 424 in the first main unit 400a being directly connected to the sub-light emission control line 324 in the corresponding functional sub-unit 300a, and another main light emission control line 424 in the first main unit 400a being connected to the sub-light emission control line 324 of the functional sub-unit 300a at the fourth parallel connection node M4.

[0122] Referring to Figures 3 and 11 to 13, in order to increase the area ratio of the light-transmitting portion 300b in the first display area 300, the two main compensation control lines 421 in the first main section 400a of the present invention are both electrically connected to the sub-compensation control line 321 in the corresponding functional sub-section 300a, the two first main reset control lines 422 in the first main section 400a are both electrically connected to the first sub-reset control line 322 in the corresponding functional sub-section 300a, the two second main reset control lines 423 in the first main section 400a are both electrically connected to the second sub-reset control line 323 in the corresponding functional sub-section 300a, and the two main light emission control lines 424 in the first main section 400a are both electrically connected to the sub-light emission control line 324 in the corresponding functional sub-section 300a.

[0123] Note that the number of stacked film layers in Figures 11 and 13 is the same, and both include the first gate layer 125, the second gate layer 127, and the third gate layer 131. The difference between Figure 11 and Figure 13 is that the enlarged areas shown are different. Figure 12 includes all the metallic conductive layers of the display panel 100 array drive layer.

[0124] Referring to Figures 11 to 13, the plurality of pixel cells 340 include a first pixel cell 340a and a second pixel cell 340b, the first pixel cell 340a is installed adjacent to the first main unit 400a, and the second pixel cell 340b is installed adjacent to the first pixel cell 340a, and both the first pixel cell 340a and the second pixel cell 340b include a plurality of first pixel circuits 310.

[0125] In this embodiment, since the proportion of the unit area of ​​the first light-emitting element 330 in the second display area 400 is larger than the proportion of the unit area of ​​the second light-emitting element 430 in the first display area 300, in order to minimize the display difference in the transition area between the second display area 400 and the first display area 300, the present invention makes the distance between the first main part 400a and the first pixel cell 340a smaller than the distance between the first pixel cell 340a and the second pixel cell 340b.

[0126] In addition, the distance between the first main unit 400a and the first pixel cell 340a is smaller than the distance between the first pixel cell 340a and the second pixel cell 340b, while the connection between the two main signal lines and the one sub-signal line needs to occupy a certain amount of space. Therefore, the first parallel connection node M1 of this application may be located between the first main unit 400a and the first pixel cell 340a, or between the first pixel cell 340a and the second pixel cell 340b, and the second parallel connection node M2 ​​is The third parallel connection node M3 may be located between the first main unit 400a and the first pixel cell 340a, or between the first pixel cell 340a and the second pixel cell 340b, and the fourth parallel connection node M4 may be located between the first main unit 400a and the first pixel cell 340a, or between the first pixel cell 340a and the second pixel cell 340b.

[0127] Referring to Figures 11 to 13, the first parallel connection node M1, the third parallel connection node M3, and the fourth parallel connection node M4 are all located between the first pixel cell 340a and the second pixel cell 340b, while the second parallel connection node M2 ​​is located between the first main unit 400a and the first pixel cell 340a.

[0128] Furthermore, since the first parallel connection node M1, the second parallel connection node M2, the third parallel connection node M3, and the fourth parallel connection node M4 are all located in the first display area 300, multiple extension lines need to be installed in the first display area 300 in order to electrically connect the main signal line to the sub-signal line.

[0129] Referring to Figures 11 to 13, the functional sub-section 300a further includes a first extending segment 351, a second extending segment 352, a third extending segment 353, and a fourth extending segment 354, all located around the first pixel cell 340a. The second extending segment 352 is located between the first main section 400a and the first pixel cell 340a, while the first extending segment 351, the third extending segment 353, and the fourth extending segment 354 extend toward the side away from the first main section 400a.

[0130] In this embodiment, one end of the first extended segment 351 is electrically connected to a main compensation control line 421 in the first main section 400a, and the other end of the first extended segment 351 is electrically connected to a sub-compensation control line 321 in the region where the first parallel connection node M1 is located. One end of the second extended segment 352 is electrically connected to a first main reset control line 422 in the first main section 400a, and the other end of the second extended segment 352 is electrically connected to a first sub-reset control line 322 in the region where the second parallel connection node M2 ​​is located. One end of the third extended segment 353 is electrically connected to a second main reset control line 423 in the first main section 400a, and the other end of the third extended segment 353 is electrically connected to a second sub-reset control line 323 in the region where the third parallel connection node M3 is located. One end of the fourth extended segment 354 is electrically connected to a main light emission control line 424 in the first main section 400a, and the other end of the fourth extended segment 354 is electrically connected to a sub-light emission control line 324 in the region where the fourth parallel connection node M4 is located.

[0131] In this embodiment, both the first extending segment 351 and the main compensation control line 421 of the present application are located in the same metal layer, while the main compensation control line 421 has a first portion located in the second gate layer 127 and a second portion located in the third gate layer 131. Similarly, the present application has a first extending segment 351 located in the second gate layer 127 and a first extending segment 351 located in the third gate layer 131. Furthermore, the two first extending segments 351 in different layers both extend toward the side away from the first main part 400a and at least partially overlap, and together the two first parallel connection nodes M1 are both located between the first pixel cell 340a and the second pixel cell 340b.

[0132] Similarly, the present invention has a second extending segment 352 located in the second gate layer 127 and a second extending segment 352 located in the third gate layer 131. Furthermore, the second extending segment 352 located in the second gate layer 127 is located between the first main section 400a and the first pixel cell 340a, while the second extending segment 352 located in the third gate layer 131 extends toward the side away from the first main section 400a and is located around the first pixel cell 340a, that is, the two second parallel connection nodes M2 are one located between the first main section 400a and the first pixel cell 340a and the other located between the first pixel cell 340a and the second pixel cell 340b.

[0133] In this embodiment, both the third extended segment 353 and the second main reset control line 423 are located in the first gate layer 125, and both the fourth extended segment 354 and the main light emission control line 424 are located in the first gate layer 125.

[0134] Referring to Figures 11 to 13, the two first extended segments 351 in different layers are both located in close proximity to the first pixel cell 340a, the fourth extended segment 354 is located on the side of the first extended segment 351 away from the first pixel cell 340a, the third extended segment 353 is located on the side of the fourth extended segment 354 away from the first pixel cell 340a, and the second extended segment 352 located in the third gate layer 131 is located between the first extended segment 351 and the first pixel cell 340a, which are located in two different layers, respectively.

[0135] Since multiple sub-signal lines are provided between the first pixel cell 340a and the second pixel cell 340b, when the first extended segment 351, the second extended segment 352, the third extended segment 353, and the fourth extended segment 354 are electrically connected to their corresponding sub-signal lines, a technical problem arises in which control lines transmitting different control signals are short-circuited.

[0136] Referring to Figure 12, the functional sub-section 300a further includes a first vertical segment 361 extending along the second direction Y, a second vertical segment 362, a third vertical segment 363, a fourth vertical segment 364, a fifth vertical segment 365, and a sixth vertical segment 366. The first vertical segment 361, the third vertical segment 363, the fourth vertical segment 364, the fifth vertical segment 365, and the sixth vertical segment 366 are provided between the first pixel cell 340a and the second pixel cell 340b, and the second vertical segment 362 is provided between the first pixel cell 340a and the first main section 400a.

[0137] Referring to Figure 12, the first extended segment 351 located in the second gate layer 127 is electrically connected to the sub-compensation control line 321 located in the second gate layer 127 by the first longitudinal segment 361, the second extended segment 352 located in the second gate layer 127 is electrically connected to the first sub-reset control line 322 located in the second gate layer 127 by the second longitudinal segment 362, and the third extended segment 353 is electrically connected to the second sub-reset control line 323 by the third longitudinal segment 363. The fourth extending segment 354 is electrically connected to the sub-light emission control line 324 by the fourth longitudinal segment 364, the first extending segment 351 located in the third gate layer 131 is electrically connected to the sub-compensation control line 321 located in the third gate layer 131 by the fifth longitudinal segment 365, and the second extending segment 352 located in the third gate layer 131 is electrically connected to the first sub-reset control line 322 located in the third gate layer 131 by the sixth longitudinal segment 366.

[0138] In this embodiment, the first vertical segment 361 and the sixth vertical segment 366 partially overlap. Therefore, in this application, the sixth vertical segment 366 is provided on the second source-drain layer 135, while the first vertical segment 361, the second vertical segment 362, the third vertical segment 363, the fourth vertical segment 364, and the fifth vertical segment 365 are all located on the first source-drain layer 133.

[0139] Note that Figure 12 is merely one embodiment of the present invention, and if the distance between the first pixel cell 340a and the second pixel cell 340b is insufficient to install the five vertical segments, the five vertical segments may be installed on the side of the second pixel cell 340b that is away from the first pixel cell 340a.

[0140] Referring to Figures 3 and 12, each sub-signal line group 320 of the present invention further includes a sub-switching control line 325, and each main signal line group 420 further includes a main switching control line 425. The sub-switching control lines 325 and the main switching control line 425 are used to transmit a switching control signal Pscan1, that is, the sub-switching control lines 325 and the main switching control line 425 are mainly used to turn on a switching transistor that transmits a data signal.

[0141] In this embodiment, in the functional sub-unit 300a and the first main unit 400a corresponding to the functional sub-unit 300a, a single main switching control line 425 in the first main unit 400a is electrically connected to a single sub-switching control line 325 in the functional sub-unit 300a.

[0142] For example, in the configuration shown in Figure 3, one main switching control line 425 in one first main section 400a of the present invention is electrically connected to a corresponding sub-switching control line 325. Another main switching control line 425 in the first main section 400a is installed in isolation from the sub-switching control line 325 in the corresponding functional sub-section 300a and is directly electrically connected to the main switching control line 425 in the corresponding first main section 400a on the other side of the first display area 300.

[0143] Furthermore, since the main switching control line 425 is located in the first main section 400a, this invention requires that a connection segment connecting the two main switching control lines 425 located in the same row be installed in the first display area 300.

[0144] Referring to Figure 12, the functional sub-section 300a further includes at least one electrical connection segment 371 provided around a plurality of first pixel circuits 310 in the same row. The electrical connection segment 371 is installed in isolation from the sub-switching control line 325, and one end of the electrical connection segment 371 is electrically connected to a single main switching control line 425 installed in isolation from the five sub-signal lines in the first main section 400a.

[0145] In this embodiment, the electrical connection segment 371 is provided on the outermost edge of a plurality of pixel cells 340. At the same time, since the electrical connection segment 371 needs to be connected to the main switching control line 425 in the first main section 400a located in the first gate layer 125, and the first main reset line 426 located in the first gate layer 125 needs to be electrically connected to the first sub-reset line 326 provided between the electrical connection segment 371 and the pixel cell 340, a bridge metal structure is required to electrically connect the electrical connection segment 371 and the main switching control line 425. Similarly, since the first pixel circuit 310 corresponds to the region between two rows of second pixel circuits 410, that is, in the first main section 400a, the main switching control line 425 electrically connected to the sub-switching control line 325 is not located on the same straight line, the sub-switching control line 325 and the main switching control line 425 similarly require a bridge metal structure to electrically connect the two.

[0146] Referring to Figure 12, the functional sub-section 300a includes a first bridge segment 372 and a second bridge segment 373. The first bridge segment 372 electrically connects a single main switching control line 425, which is installed insulated from the sub-switching control line 325, to an electrical connection segment 371. The second bridge segment 373 electrically connects a single main switching control line 425 to the sub-switching control line 325. The first bridge segment 372 extends along a first direction, a portion of the second bridge segment 373 extends along a second direction Y, the second bridge segment 373 is located between the second longitudinal segment 362 and the first pixel cell 340a, and both the first bridge segment 372 and the second bridge segment 373 are located in the first source-drain layer 133.

[0147] In this embodiment, the plurality of signal lines include a plurality of reset lines used to transmit reset signals to the first pixel circuit 310 and the second pixel circuit 410, the plurality of reset lines extending only in the first direction X within the first display area 300, and the plurality of reset lines forming a grid structure within the second display area 400.

[0148] For example, referring to Figure 12, the plurality of signal lines may include at least two first main reset lines 426, at least two second main reset lines 427, and at least two third main reset lines 428 located within the second display area. One first main reset line 426 is connected to a first reset transistor T4 of a row of second pixel circuits 410 arranged along a first direction X, one second main reset line 427 is connected to a second reset transistor T7 of a row of second pixel circuits 410 arranged along a first direction X, and one third main reset line 428 is connected to a third reset transistor T8 of a row of second pixel circuits 410 arranged along a first direction X.

[0149] Referring to Figure 12, the plurality of signal lines further include a first sub-reset line 326, a second sub-reset line 327, and a third sub-reset line 328 located within the first display area, wherein the first sub-reset line 326 is connected to a first reset transistor T4 of a row of first pixel circuits 310 arranged along a first direction X, the second sub-reset line 327 is connected to a second reset transistor T7 of a row of first pixel circuits 310 arranged along a first direction X, and the third sub-reset line 328 is connected to a third reset transistor T8 of a row of first pixel circuits 310 arranged along a first direction X.

[0150] In this embodiment, in the functional sub-unit 300a and the first main unit 400a corresponding to the functional sub-unit 300a, at least two first main reset lines 426 in the first main unit 400a are electrically connected to one first sub-reset line 326 in the functional sub-unit 300a at the fifth parallel connection node M5, at least two second main reset lines 427 in the first main unit 400a are electrically connected to one second sub-reset line 327 in the functional sub-unit 300a at the sixth parallel connection node M6, and at least two third main reset lines 428 in the first main unit 400a are electrically connected to one third sub-reset line 328 in the functional sub-unit 300a at the seventh parallel connection node M7.

[0151] In this embodiment, since two main reset lines need to be electrically connected to corresponding sub-reset lines that transmit the same reset signal, the functional sub-section 300a of the present invention further includes a fifth extending segment 355, a sixth extending segment 356, and a seventh extending segment 357, wherein the fifth extending segment 355 and the seventh extending segment 357 are provided around the first pixel cell 340a, and the sixth extending segment 356 is provided between the first pixel cell 340a and the first main section 400a.

[0152] In this embodiment, one end of the fifth extending segment 355 is electrically connected to a first main reset line 426 in the first main section 400a, and the other end of the fifth extending segment 355 is electrically connected to a first sub-reset line 326 in the area where the fifth parallel connection node M5 is located. One end of the sixth extending segment 356 is electrically connected to a second main reset line 427 in the first main section 400a, and the other end of the sixth extending segment 356 is electrically connected to a second sub-reset line 327 in the area where the sixth parallel connection node M6 is located. One end of the seventh extending segment 357 is electrically connected to a third main reset line 428 in the first main section 400a, and the other end of the seventh extending segment 357 is electrically connected to a third sub-reset line 328 in the area where the seventh parallel connection node M7 is located.

[0153] Referring to Figure 12, the first main reset line 426 and the first sub-reset line 326 are located in the first gate layer 125, the second main reset line 427 and the second sub-reset line 327 are located in the third gate layer 131, and the third main reset line 428 and the third sub-reset line 328 are located in the second gate layer 127. On the other hand, when connecting a main reset line to a corresponding sub-reset line, a metal layer traversing the same layer is required. Therefore, the fifth extended segment 355, the sixth extended segment 356, and the seventh extended segment 357 of this application are all manufactured using the metal of the first source-drain layer 133.

[0154] In this embodiment, the fifth extending segment 355 may be installed between the first main portion 400a and the second vertical segment 362, and both the sixth extending segment 356 and the seventh extending segment 357 are provided around the first pixel cell 340a.

[0155] Since the first reset signal Vi1, the second reset signal Vi2, and the third reset signal Vi3 are all constant voltage signals, this invention forms a mesh structure by connecting reset lines that transmit the same reset signal in parallel.

[0156] Referring to Figures 14 to 16, the second display area 400 further includes a plurality of first connection segments 441, a plurality of second connection segments 442, and a plurality of third connection segments 443. The plurality of first connection segments 441, a plurality of second connection segments 442, and a plurality of third connection segments 443 are arranged along a first direction X and extend along a second direction Y.

[0157] In this embodiment, each first connection segment 441 is electrically connected to a plurality of first main reset lines 426, and the plurality of first connection segments 441 and the plurality of first main reset lines 426 form a mesh structure. Each second connection segment 442 is electrically connected to a plurality of second main reset lines 427, and the plurality of second connection segments 442 and the plurality of second main reset lines 427 form a mesh structure. Each third connection segment 443 is electrically connected to a plurality of third main reset lines 428, and the plurality of third connection segments 443 and the plurality of third main reset lines 428 form a mesh structure.

[0158] The second main section 400b is similarly provided with multiple first main reset lines 426, multiple second main reset lines 427, and multiple third main reset lines 428. The main reset lines that transmit the same reset signal in the first main section 400a and the second main section 400b are all electrically connected to connection segments that extend in the vertical direction, forming a corresponding mesh structure. This reduces the impedance of the reset lines and improves the technical problem of the reset line voltage signal being attenuated by the effects of resistance and capacitors.

[0159] Referring to Figures 14 to 16, the multiple first connection segments 441, multiple second connection segments 442, and multiple third connection segments 443 are spaced apart along the first direction X, and the number of first connection segments 441 is less than the number of second connection segments 442, and the number of third connection segments 443 is less than the number of second connection segments 442. For example, there is a spacing of the width of eight second pixel circuits 410 between two adjacent first connection segments 441, a spacing of the width of four second pixel circuits 410 between two adjacent second connection segments 442, and a spacing of the width of eight second pixel circuits 410 between two adjacent third connection segments 443.

[0160] In this embodiment, the second reset signal Vi2 is used to reset the potential of the anode in the light-emitting element. However, if the potential of the anode in the light-emitting element is not accurate, there is a technical problem that brightness unevenness is likely to occur at low gradation levels. In this application, by installing a relatively large number of second connection segments 442, the mesh structure formed by multiple second connection segments 442 and multiple second main reset lines 427 becomes denser, further reducing the impedance of the multiple second main reset lines 427 and reducing the influence of resistors and capacitors on the voltage signal transmitted to the second main reset lines 427.

[0161] In Figures 14 to 16, each bright line in the horizontal and vertical directions represents only one wiring, and the two horizontal lines in the drawings are the boundary lines in the width direction of the corresponding wiring.

[0162] The following comparisons will be made with the transmittance of the present application based on relevant comparative examples. Specifically, these are shown in the table below. TIFF2026528869000002.tif187159

[0163] As can be seen from the table above, if the design is not based on this proposed technology, the transmittance of the first display area 300 is 17.5%.

[0164] On the other hand, in Comparative Example 1, when two compensation control lines transmitting the compensation control signal Nscan1 are connected in parallel to the first display area 300, the transmittance in the first display area 300 increased from 17.5% to 18.5%.

[0165] In Comparative Example 2, when two compensation control lines transmitting the compensation control signal Nscan1 and two light emission control lines transmitting the light emission control signal EM are connected in parallel to the first display area 300, the transmittance in the first display area 300 increased from 18.5% to 19.5%.

[0166] In Comparative Example 3, when two compensation control lines transmitting the compensation control signal Nscan1, two light emission control lines transmitting the light emission control signal EM, and two first reset lines transmitting the first reset signal Vi1 are connected in parallel to the first display area 300, the transmittance in the first display area 300 increased from 19.5% to 20.5%.

[0167] In Comparative Example 4, when two compensation control lines transmitting the compensation control signal Nscan1, two light emission control lines transmitting the light emission control signal EM, two first reset control lines transmitting the first reset control signal Nscan2, two second reset control lines transmitting the second reset control signal Pscan2, two first reset lines transmitting the first reset signal Vi1, two second reset lines transmitting the second reset signal Vi2, and two third reset lines transmitting the third reset signal Vi3 were connected in parallel to the first display area 300, the transmittance in the first display area 300 increased from 20.5% to 24.5%.

[0168] It should be noted that the comparative examples described above are merely illustrative examples of the present invention, and the transmittance values ​​are approximate; the transmittance of actual products will have some degree of error compared to the above values.

[0169] The present invention further includes a display device, which includes the display panel described above. The display device may be a product or component having a display function, such as a mobile phone, tablet, television, display, laptop computer, digital photo frame, or navigation system.

[0170] In the embodiments described above, each embodiment has its own focus, and for parts not explained in detail in one embodiment, one can refer to the descriptions in other embodiments.

[0171] Although the technical solutions provided in the embodiments of this application have been described in detail above, this specification describes the principles and embodiments of this application by applying specific examples, and the descriptions of the embodiments above are intended to aid in understanding the technical solutions of this application and their core concept. Those skilled in the art will understand that it is still possible to modify the technical solutions described in each of the embodiments described above, or to replace some of their technical features with equivalent ones, and that such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of each embodiment of this application.

Claims

1. A first display area, wherein a plurality of first pixel circuits and a plurality of light-transmitting sections are provided within the first display area, and the plurality of light-transmitting sections are located between the plurality of first pixel circuits in the first display area, A second display area, the second display area being located around the first display area, and the second display area having a plurality of second pixel circuits, A plurality of signal lines, each of which is connected to a row of the second pixel circuit, and a plurality of signal lines, each of which transmits the same control signal, is connected to a plurality of the same first pixel circuits, Display panel.

2. The display panel further includes a non-display area provided on the side of the second display area away from the first display area, and a gate drive circuit is provided within the non-display area. Here, the output terminal of the gate drive circuit is connected to at least one of the signal lines. The display panel according to claim 1.

3. Both the first pixel circuit and the second pixel circuit are, A switching transistor wherein the gate of the switching transistor receives a switching control signal, A drive transistor connected to the switching transistor at the first node, A compensation transistor, wherein the compensation transistor is connected to the drive transistor at a second node, and the gate of the compensation transistor receives a compensation control signal. A first reset transistor, wherein the first reset transistor is connected to the compensation transistor and the drive transistor at the third node, and the gate of the first reset transistor receives a first reset control signal. A second reset transistor, the second reset transistor is connected at the fourth node, and the gate of the second reset transistor is connected to the second reset transistor that receives the second reset control signal, A third reset transistor, wherein the third reset transistor is connected to the switching transistor at the first node, and the gate of the third reset transistor is a third reset transistor that receives the second reset control signal, A first light-emitting transistor, wherein the first light-emitting transistor is connected to the switching transistor at the first node, and the gate of the first light-emitting transistor receives a light-emitting control signal, Here, the multiple signal lines are used to transmit at least one of the compensation control signal, the first reset control signal, the second reset control signal, and the light emission control signal. The display panel according to claim 2.

4. The gate drive circuit is, A first gate circuit provided on both sides of the second display area and used to transmit compensation control signals, A second gate circuit is provided on both sides of the second display area, is arranged along the second direction with the first gate circuit, and is used to transmit the first reset control signal. A third gate circuit is provided on the first side of the second display area, located on the side of the first gate circuit away from the second display area, and is used to transmit a second reset control signal. A fourth gate circuit is provided on the second side of the second display area, located on the side of the first gate circuit away from the second display area, and is used to transmit light emission control signals. A fifth gate circuit is provided on both sides of the second display area, located between the second display area and the first gate circuit, and between the second display area and the second gate circuit, and is used to transmit switching control signals. Here, the plurality of signal lines include a main compensation control line located within the second display area, a first main reset control line, a second main reset control line, a main light emission control line, and a main switching control line, one of the first gate circuits is connected to two of the main compensation control lines, one of the second gate circuits is connected to two adjacent first main reset control lines, one of the third gate circuits is connected to two of the second main reset control lines, one of the fourth gate circuits is connected to two of the main light emission control lines, and one of the fifth gate circuits is connected to one of the main switching control lines. The display panel according to claim 3.

5. The plurality of signal lines further include a sub-compensation control line located within the first display area, a first sub-reset control line, a second sub-reset control line, and a sub-light emission control line. Here, at least two of the main compensation control lines are electrically connected to one of the sub-compensation control lines at the first parallel connection node, and / or At least two of the first main reset control lines are electrically connected to one of the first sub-reset control lines at the first parallel connection node, and / or At least two of the second main reset control lines are electrically connected to one of the second sub-reset control lines at the first parallel connection node, and / or At least two of the main light emission control lines are electrically connected to one of the sub-light emission control lines at the first parallel connection node. The display panel according to claim 4.

6. The plurality of signal lines further include sub-switching control lines located within the first display area, and one of the main switching control lines is electrically connected to one of the sub-switching control lines. The display panel according to claim 5.

7. Within the first display area, at least one electrical connection segment is further provided around a plurality of the first pixel circuits in the same row, and the electrical connection segment is installed in isolation from the sub-switching control line. Here, one end of the electrical connection segment is electrically connected to a single main switching control line that is installed in isolation from the sub-switching control line in the second display area. The display panel according to claim 6.

8. Within the first display area, there are multiple pixel cells formed by combining multiple first pixel circuits, and there are gaps between the multiple pixel cells. Here, the plurality of pixel cells include a first pixel cell and a second pixel cell, the first pixel cell is installed adjacent to the second display area, the second pixel cell is installed adjacent to the first pixel cell, and both the first pixel cell and the second pixel cell include a plurality of the first pixel circuits. The first parallel connection node is located between the second display area and the first pixel cell, or between the first pixel cell and the second pixel cell; the second parallel connection node is located between the second display area and the first pixel cell, or between the first pixel cell and the second pixel cell; the third parallel connection node is located between the second display area and the first pixel cell, or between the first pixel cell and the second pixel cell; and the fourth parallel connection node is located between the second display area and the first pixel cell, or between the first pixel cell and the second pixel cell. The display panel according to claim 5.

9. The distance between the second display area and the first pixel cell is smaller than the distance between the first pixel cell and the second pixel cell. The display panel according to claim 8.

10. The first parallel connection node, the third parallel connection node, and the fourth parallel connection node are all located between the first pixel cell and the second pixel cell, and the second parallel connection node is located between the second display area and the first pixel cell. The display panel according to claim 8.

11. Within the first display area, a first extending segment, a second extending segment, a third extending segment, and a fourth extending segment are provided, located around the first pixel cell. The second extending segment is located between the second display area and the first pixel cell, and the first extending segment, the third extending segment and the fourth extending segment extend toward the side away from the second display area. Here, one end of the first extended segment is electrically connected to one of the main compensation control lines in the second display area, and the other end of the first extended segment is electrically connected to the sub-compensation control line in the area where the first parallel connection node is located. One end of the second extended segment is electrically connected to one of the first main reset control lines in the second display area, and the other end of the second extended segment is electrically connected to the first sub-reset control line in the area where the second parallel connection node is located. One end of the third extended segment is electrically connected to one of the second main reset control lines in the second display area, and the other end of the third extended segment is electrically connected to the second sub-reset control line in the area where the third parallel connection node is located. One end of the fourth extended segment is electrically connected to one of the main light emission control lines in the second display area, and the other end of the fourth extended segment is electrically connected to the sub-light emission control line in the area where the fourth parallel connection node is located. The display panel according to claim 8.

12. The first extended segment is installed in close proximity to the first pixel cell, the fourth extended segment is located on the side of the first extended segment away from the first pixel cell, and the third extended segment is located on the side of the fourth extended segment away from the first pixel cell. The display panel according to claim 11.

13. Each pixel cell includes three of the first pixel circuits, and the configuration of each of the first pixel circuits is the same. Here, in the second display area, two adjacent second pixel circuits arranged along the first direction are arranged symmetrically with respect to the centerlines of the two adjacent second pixel circuits. The display panel according to claim 8.

14. The area of ​​the first pixel circuit is smaller than the area of ​​the second pixel circuit. The display panel according to claim 1.

15. The plurality of signal lines include a plurality of reset lines used to transmit reset signals to the first pixel circuit and the second pixel circuit, the plurality of reset lines extending only in a first direction within the first display area, and the plurality of reset lines forming a grid structure within the second display area. The display panel according to any one of claims 1 to 14.

16. The multiple reset lines include a first main reset line, a second main reset line, and a third main reset line, all located within the second display area. The first main reset line is used to transmit a first reset signal and is connected to the first reset transistor of the second pixel circuit; the second main reset line is used to transmit a second reset signal and is connected to the second reset transistor of the second pixel circuit; the third main reset line is used to transmit a third reset signal and is connected to the third reset transistor of the second pixel circuit. The multiple reset lines include a first sub-reset line, a second sub-reset line, and a third sub-reset line located within the first display area. The first sub-reset line is used to transmit the first reset signal and is connected to the first reset transistor of the first pixel circuit; the second sub-reset line is used to transmit the second reset signal and is connected to the second reset transistor of the first pixel circuit; the third sub-reset line is used to transmit the third reset signal and is connected to the third reset transistor of the first pixel circuit. Here, at least two of the first main reset lines are electrically connected to one of the first sub-reset lines at the fifth parallel connection node, at least two of the second main reset lines are electrically connected to one of the second sub-reset lines at the sixth parallel connection node, and at least two of the third main reset lines are electrically connected to one of the third sub-reset lines at the seventh parallel connection node. The display panel according to claim 15.

17. The second display area is, A plurality of first connection segments arranged along the first direction and extending along the second direction, each of the plurality of first connection segments being electrically connected to a plurality of first main reset lines, and the plurality of first connection segments and the plurality of first main reset lines forming a mesh structure. A plurality of second connection segments arranged along the first direction and extending along the second direction, each of the plurality of second connection segments being electrically connected to a plurality of second main reset lines, and the plurality of second connection segments and the plurality of second main reset lines form a mesh structure. The present invention further includes a plurality of third connection segments arranged along the first direction and extending along the second direction, each of which is electrically connected to a plurality of third main reset lines, and the plurality of third connection segments and the plurality of third main reset lines form a mesh structure. Here, the multiple first connecting segments, the multiple second connecting segments, and the multiple third connecting segments are installed at intervals along the first direction, the number of first connecting segments is less than the number of second connecting segments, and the number of third connecting segments is less than the number of second connecting segments. The display panel according to claim 16.

18. There is a spacing of eight widths of the second pixel circuits between two adjacent first connection segments, a spacing of four widths of the second pixel circuits between two adjacent second connection segments, and a spacing of eight widths of the second pixel circuits between two adjacent third connection segments. The display panel according to claim 17.

19. Within the first display area, A fifth extending segment provided around the first pixel cell, wherein one end of the fifth extending segment is electrically connected to one of the first main reset lines in the second display area, and the other end of the fifth extending segment is electrically connected to the first sub-reset line in the area where the fifth parallel connection node is located, A sixth extending segment provided between the first pixel cell and the second display area, wherein one end of the sixth extending segment is electrically connected to a second main reset line in the second display area, and the other end of the sixth extending segment is electrically connected to a second sub-reset line in the area where the sixth parallel connection node is located, A seventh extending segment is provided around the first pixel cell, wherein one end of the seventh extending segment is electrically connected to one of the third main reset lines in the second display area, and the other end of the seventh extending segment is electrically connected to the third sub-reset line in the area where the seventh parallel connection node is located. The display panel according to claim 16.

20. Includes a display panel according to any one of claims 1 to 19, Display device.

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