Semiconductor device and clock control method

Abstract

To shorten a time for a semiconductor device to operate in a low frequency.SOLUTION: A clock unit outputs a clock signal of a first frequency. A detection unit detects occurrence of power supply noise and end of the power supply noise. A control unit drops, in a case where the occurrence of the power supply noise is detected, a frequency of the clock signal from the first frequency to a second frequency. Then, the control unit determines a frequency return time according to a noise occurrence time from the occurrence of the power supply noise to the end of the power supply noise, and returns the frequency of the clock signal from the second frequency to the first frequency based on the frequency return time.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a clock control technique. [Background technology]

[0002] Due to an increase in current consumption in LSIs (Large Scale Integration) such as processors, the change in current when the computation load fluctuates also becomes large, which can result in very large power supply noise. When the power supply voltage drops due to power supply noise, the delay time of the internal circuit of the LSI increases. The LSI is an example of a semiconductor device.

[0003] Fig. 1 shows an example of an LSI. The LSI in Fig. 1 includes a clock driver 101, a flip-flop (FF) 102, a logic circuit 103, and a FF 104. The clock driver 101 supplies a clock signal to the FF 102 and the FF 104, and the FF 102 outputs a data signal to the logic circuit 103 in accordance with the clock signal.

[0004] The logic circuit 103 performs a logical operation using the data signal output from the FF 102, and outputs the data signal resulting from the operation to the FF 104. The delay time of the data signal input to the FF 104 is the sum of the delay time Td at the normal power supply voltage and the delay time ΔTd increased due to a drop in the power supply voltage.

[0005] Fig. 2 shows an example of a clock signal and a data signal in the LSI of Fig. 1. The clock signal represents the clock signal output from the clock driver 101, and the clock cycle represents the cycle of the clock signal. The output data represents the data signal output from the FF 102, and the input data represents the data signal input to the FF 104.

[0006] In LSI design, a margin is added to the clock cycle so that the increased delay time ΔTd satisfies the timing constraints. In this example, ΔTd is added as a clock cycle margin so that Td + ΔTd fits within the clock cycle.

[0007] When the power supply noise is large, the clock cycle margin also becomes large. When the clock cycle margin in a processor becomes large, the frequency of the clock signal decreases, which hinders the improvement of the processor's operating speed and reduction of power consumption. Therefore, in recent processors, a small value is adopted as the clock cycle margin, and a technique is sometimes applied to avoid timing errors by lowering the frequency of the clock signal when the occurrence of power supply noise is detected.

[0008] In relation to the control of clock signals caused by power supply noise, a control program is known that suppresses the occurrence of timing errors caused by power supply noise without increasing the frequency of clock frequency drops (see, for example, Patent Document 1). Electronic circuits that can quickly change the oscillation frequency in response to power supply noise are also known (see, for example, Patent Document 2). Semiconductor devices that can quickly change voltage changes such as large voltage drops that occur during sudden load fluctuations are also known (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2020-98545 A [Patent Document 2] JP 2017-17671 A [Patent Document 3] JP 2017-58911 A Summary of the Invention [Problem to be solved by the invention]

[0010] Reducing the frequency of the clock signal when power supply noise occurs reduces the performance of the processor while it is operating with the lower frequency clock signal.

[0011] This problem is not limited to processors, but occurs in various semiconductor devices that operate in accordance with a clock signal.

[0012] In one aspect, the present invention aims to reduce the time during which a semiconductor device operates at a low frequency. [Means for solving the problem]

[0013] In one embodiment, the semiconductor device includes a clock unit, a detection unit, and a control unit. The clock unit outputs a clock signal of a first frequency. The detection unit detects occurrence of power supply noise and convergence of the power supply noise.

[0014] When occurrence of power supply noise is detected, the control unit reduces the frequency of the clock signal from a first frequency to a second frequency, determines a frequency recovery time according to a noise occurrence time from the occurrence of the power supply noise to the convergence of the power supply noise, and recovers the frequency of the clock signal from the second frequency to the first frequency based on the frequency recovery time. Effect of the Invention

[0015] According to one aspect, the time during which a semiconductor device operates at a low frequency can be shortened. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing an LSI. [Diagram 2] FIG. 2 is a diagram illustrating a clock signal and a data signal in an LSI. [Diagram 3] 11 is a timing chart of clock control in a comparative example. [Figure 4] FIG. 11 is a configuration diagram of a circuit that performs clock control in a comparative example. [Diagram 5]11 is a timing chart of clock control when maximum power supply noise occurs in the comparative example. [Figure 6] 11 is a timing chart of clock control when small noise with a short period occurs in the comparative example. [Figure 7] 1 is a configuration diagram of a semiconductor device according to an embodiment; [Figure 8] 1 is a flowchart of clock control. [Figure 9] FIG. 1 is a first hardware configuration diagram of an LSI. [Figure 10] FIG. 1 is a first hardware configuration diagram of a clock control circuit. [Figure 11] FIG. 13 is a diagram showing a candidate time table. [Figure 12] 11 is a timing chart of clock control when small, short-period noise occurs in an LSI. [Figure 13] FIG. 11 is a diagram illustrating a first clock control. [Figure 14] 1 is a flowchart of a first clock control. [Figure 15] FIG. 2 is a second hardware configuration diagram of the clock control circuit. [Figure 16] FIG. 11 is a diagram illustrating a second clock control. [Figure 17] 11 is a flowchart of a second clock control. [Figure 18] FIG. 2 is a second hardware configuration diagram of the LSI. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, the embodiments will be described in detail with reference to the drawings.

[0018] 3 is a timing chart showing an example of clock control for lowering the frequency of the clock signal when the occurrence of power supply noise is detected in a processor of the comparative example. CLK represents the clock signal, and the CLK frequency represents the frequency of the clock signal. The normal speed corresponds to the frequency F0 of the clock signal in normal operation of the LSI, the low speed corresponds to a frequency FL lower than the normal speed, and the medium speed corresponds to a frequency between the normal speed and the low speed.

[0019] The normal voltage represents the power supply voltage in normal operation of the processor, and the limit voltage represents the lower limit of the power supply voltage at which the processor can operate at the normal CLK frequency. If the power supply voltage is lower than the limit voltage, it becomes difficult for the processor to operate at the frequency F0.

[0020] At the start of operation, the CLK frequency is F0, and the processor operates at normal speed. At time t1, power supply noise occurs, and at time t2, the power supply voltage drops to the limit voltage. At this point, control is performed to change the CLK frequency to FL, and the processor operates at a slower speed. This increases the timing margin of the clock signal, preventing timing errors from occurring.

[0021] After that, the power supply voltage drops further, and then starts to rise due to the reduction in power supply noise. Then, at time t3, the power supply noise converges and the power supply voltage reaches the limit voltage. Then, control is performed to gradually increase the CLK frequency, and the processor operates at medium speed. The convergence of the power supply noise means that the power supply noise disappears. The noise generation time, which is the time from when the power supply noise occurs to when it converges, is the time from time t2 to time t3.

[0022] During operation at medium speed, the CLK frequency increases stepwise from FL and finally returns to F0, and the processor operates at the normal speed again. At time t4, the power supply voltage reaches the normal voltage.

[0023] Fig. 4 shows an example of the configuration of a circuit that performs the clock control of Fig. 3 in a processor of a comparative example. The circuit of Fig. 4 includes a detection circuit 401, a control circuit 402, and a clock circuit 403. The detection circuit 401 includes a comparison circuit 411, and detects the occurrence and convergence of power supply noise. The clock circuit 403 can dynamically change the frequency of the clock signal.

[0024] 4(a) shows an example of control for changing the CLK frequency to FL at time t2. The comparator circuit 411 compares the power supply voltage of the processor with the limit voltage, and outputs a noise occurrence signal 421 indicating the occurrence of power supply noise to the control circuit 402 when the power supply voltage becomes lower than the limit voltage.

[0025] When the control circuit 402 receives the noise generating signal 421, it outputs a frequency down signal 422, which indicates an instruction to change the CLK frequency to FL, to the clock circuit 403. When the clock circuit 403 receives the frequency down signal 422, it changes the CLK frequency to FL and outputs a clock signal. This changes the operating speed of the processor from the normal speed to a low speed.

[0026] 4(b) shows an example of control for gradually increasing the CLK frequency at time t3. The comparator circuit 411 compares the power supply voltage of the processor with the limit voltage, and when the power supply voltage reaches the limit voltage, outputs a noise convergence signal 431 indicating the convergence of the power supply noise to the control circuit 402.

[0027] When the control circuit 402 receives the noise convergence signal 431, it starts a frequency recovery control for increasing the CLK frequency stepwise from FL to F0. In the frequency recovery control, the control circuit 402 outputs a frequency increase signal 432, which indicates an instruction to increase the CLK frequency by a predetermined value, to the clock circuit 403 at predetermined time intervals.

[0028] Each time the clock circuit 403 receives the frequency up signal 432, it increases the CLK frequency by a predetermined value and outputs a clock signal. This causes the operating speed of the processor to change from low speed to medium speed. When the frequency up signal 432 is received a predetermined number of times, the CLK frequency returns to F0, and the operating speed of the processor changes from medium speed to normal speed.

[0029] A sudden increase in the CLK frequency is accompanied by a large current fluctuation, which may cause power supply noise to occur again. In this case, the power supply noise that has occurred is detected and the CLK frequency is reduced again. Therefore, instead of increasing the CLK frequency suddenly, it is possible to avoid a further reduction in the CLK frequency by gradually increasing it from FL to F0.

[0030] 5 is a timing chart showing an example of clock control when maximum power supply noise occurs in a processor of a comparative example. Hereinafter, the maximum power supply noise may be referred to as maximum noise.

[0031] At the start of operation, the power supply voltage is a normal voltage and the CLK frequency is F0. At time t11, power supply noise occurs, causing the power supply voltage to fall below the limit voltage, and the CLK frequency is changed to FL.

[0032] After that, the power supply voltage further drops, and then starts to rise due to the reduction in power supply noise, and at time t12, the power supply noise converges and the power supply voltage reaches the limit voltage. Then, control is performed to gradually increase the CLK frequency, and at time t13, the CLK frequency returns to F0.

[0033] In this case, the noise occurrence time is several μs (microseconds) from time t11 to time t12, and the frequency recovery time, which is the time it takes for the CLK frequency to return from FL to F0, is several μs from just after time t12 to time t13. The frequency recovery time is set to several μs, taking into account the voltage recovery time when maximum noise occurs, so that the CLK frequency does not drop again.

[0034] However, in a multi-core processor, the maximum noise occurs when all cores start operating at the same time. In this case, a large noise with a long period occurs, but the frequency with which all cores start operating at the same time is low, so the maximum noise occurs less frequently.

[0035] On the other hand, when several cores start operating at the same time, the power supply noise is a small noise with a short period. In this case, the voltage recovery time is less than several hundred ns (nanoseconds), which is shorter than the voltage recovery time when the maximum noise occurs.

[0036] 6 is a timing chart showing an example of clock control when short-period small noise occurs in a processor of a comparative example. At the start of operation, the power supply voltage is a normal voltage and the CLK frequency is F0. At time t21, power supply noise occurs and the CLK frequency is changed to FL. Then, at time t22, the power supply noise converges and control is performed to gradually increase the CLK frequency, and at time t23, the CLK frequency returns to F0.

[0037] In this case, the noise occurrence time is several ns from time t21 to time t22, and the frequency recovery time is several μs from just after time t22 to time t23. Since the frequency recovery time is set based on the voltage recovery time when the maximum noise occurs, even if the noise occurrence time is short, it takes a long time for the CLK frequency to recover from FL to F0.

[0038] When a small, short-period noise occurs, the power supply voltage recovers in a short time, but the processor operates at a frequency lower than F0 for a long time, unnecessarily reducing the processor's performance.

[0039] In the electronic circuit of Patent Document 2, the oscillation frequency can be changed at high speed in response to power supply noise, but the frequency recovery time is not optimized.

[0040] Fig. 7 shows an example of the configuration of a semiconductor device according to an embodiment. A semiconductor device 701 in Fig. 7 includes a detection unit 711, a control unit 712, and a clock unit 713. The clock unit 713 outputs a clock signal.

[0041] Fig. 8 is a flowchart showing an example of clock control performed by the semiconductor device 701 of Fig. 7. First, the detection unit 711 detects the occurrence of power supply noise (step 801), and the control unit 712 reduces the frequency of the clock signal from a first frequency to a second frequency (step 802).

[0042] Next, the detection unit 711 detects the convergence of the power supply noise (step 803), and the control unit 712 determines a frequency recovery time according to the noise occurrence time from the occurrence of the power supply noise to the convergence of the power supply noise (step 804). Then, the control unit 712 recovers the frequency of the clock signal from the second frequency to the first frequency based on the frequency recovery time (step 805).

[0043] According to the semiconductor device 701 of FIG. 7, the time during which the semiconductor device 701 operates at a low frequency can be shortened.

[0044] Fig. 9 shows a first hardware configuration example of an LSI corresponding to the semiconductor device 701 of Fig. 7. The LSI 901 of Fig. 9 includes a clock control circuit 911, an internal circuit 912, and an I / O (Input / Output) circuit 913. These components are hardware circuits. The LSI 901 may be a processor.

[0045] The internal circuit 912 performs logical operations. The I / O circuit 913 receives data used in the logical operations from the outside, outputs the received data to the internal circuit 912, and outputs the operation result output from the internal circuit 912 to the outside. The clock control circuit 911 generates a clock signal and outputs it to the internal circuit 912 via a signal line 922. At this time, the clock control circuit 911 detects the power supply voltage of the internal circuit 912 via a signal line 921, and controls the frequency of the clock signal based on the detected power supply voltage.

[0046] Fig. 10 shows a first example of a hardware configuration of the clock control circuit 911 of Fig. 9. The clock control circuit 911 of Fig. 10 includes a detection circuit 1011, a control circuit 1012, a clock circuit 1013, a counter 1014, and a register 1015.

[0047] The clock circuit 1013 can dynamically change the frequency of the clock signal. The clock circuit 1013 may include a phase locked loop (PLL), a delay locked loop (DLL), or a switch that switches the frequency of the clock signal.

[0048] The detection circuit 1011, the control circuit 1012, and the clock circuit 1013 correspond to the detection unit 711, the control unit 712, and the clock unit 713 in FIG. 7, respectively.

[0049] The register 1015 stores a candidate time table. The candidate time table includes candidate times associated with a plurality of time ranges. The candidate times associated with each time range are candidates for the frequency recovery time. The register 1015 is an example of a storage unit. When power supply noise occurs, the counter 1014 counts the noise occurrence time and outputs a count value "count."

[0050] Fig. 11 shows an example of a candidate time table. The candidate time table in Fig. 11 includes N+1 entries (N is an integer equal to or greater than 1), and each entry includes an item number, a condition, and a candidate time. The item number is identification information of the entry, and the condition is a judgment condition for the count that indicates the noise occurrence time.

[0051] num_i (i=0 to N) is a threshold for count, and time_i is a candidate time. time_i (i=1 to N) is longer than time_(i-1). The candidate time for each entry is associated with the condition for that entry.

[0052] For example, the condition for the 0th entry is that count is less than or equal to num_0. The condition for the i-th entry (i=1 to N-1) is that count is greater than num_(i-1) and less than or equal to num_i. The condition for the Nth entry is that count is greater than num_(N-1).

[0053] The condition of each entry represents the time range to which the count belongs, and the longer the noise occurrence time represented by the count, the longer the candidate time corresponding to the time range to which the count belongs.

[0054] The detection circuit 1011 detects the power supply voltage of the internal circuit 912 via the signal line 921, and detects the occurrence of power supply noise from the detected power supply voltage. Then, the detection circuit 1011 outputs a noise occurrence signal indicative of the occurrence of power supply noise to the control circuit 1012.

[0055] The control circuit 1012 controls the frequency of the clock signal by utilizing the correlation between the power supply noise occurrence time and the period and magnitude of the power supply noise. When the control circuit 1012 receives the noise occurrence signal, it outputs a frequency reduction signal to the clock circuit 1013, which indicates an instruction to change the frequency of the clock signal to a frequency FL for low-speed operation. Then, the control circuit 1012 starts measuring the noise occurrence time by instructing the counter 1014 to start a counting operation.

[0056] Upon receiving the frequency down signal, the clock circuit 1013 changes the frequency of the clock signal to FL, and outputs the clock signal to the internal circuit 912 via the signal line 922. The counter 1014 starts counting the noise generation time.

[0057] Next, the detection circuit 1011 detects the convergence of the power supply noise from the power supply voltage detected via the signal line 921. Then, the detection circuit 1011 outputs to the control circuit 1012 a noise convergence signal indicating the convergence of the power supply noise.

[0058] When the control circuit 1012 receives the noise convergence signal, it instructs the counter 1014 to stop the counting operation, and acquires the count from the counter 1014. Then, the control circuit 1012 uses the acquired count as the noise occurrence time to determine the frequency recovery time.

[0059] The control circuit 1012 accesses the candidate time table stored in the register 1015 and acquires the candidate time associated with the time range including the acquired count from among the multiple candidate times included in the candidate time table. This makes it possible to select the frequency recovery time according to the noise occurrence time.

[0060] Next, the control circuit 1012 starts frequency return control using the acquired candidate time as a frequency return time. In the frequency return control, the control circuit 1012 controls the clock circuit 1013 so that the frequency of the clock signal increases stepwise from FL to a normal operation frequency F0 during the frequency return time. F0 is an example of a first frequency, and FL is an example of a second frequency.

[0061] The control circuit 1012 determines a time interval ΔT and a frequency increment ΔF so that the time it takes for the frequency of the clock signal to change from FL to F0 coincides with the frequency recovery time and the frequency gradually increases from FL to F0. Then, the control circuit 1012 outputs a frequency increase signal, which indicates an instruction to increase the frequency by ΔF, to the clock circuit 1013 at intervals of ΔT.

[0062] Every time the clock circuit 1013 receives a frequency increase signal, it increases the frequency of the clock signal by ΔF and outputs the clock signal to the internal circuit 912 via the signal line 922. Then, after the frequency recovery time has elapsed, the frequency of the clock signal returns to F0. By increasing the frequency in stages, it is possible to prevent a further drop in frequency due to reoccurring power supply noise.

[0063] The conditions and candidate times to be set in the candidate time table can be obtained by a prior simulation. However, the accuracy of the conditions and candidate times can be increased if the conditions and candidate times are determined while evaluating them during operation of the LSI 901. Therefore, it is preferable to set the conditions and candidate times in the candidate time table from outside the clock control circuit 911.

[0064] In addition, since the number of periods of power supply noise to be considered in clock control is determined by the number and height of impedance peaks in the power supply system, it is desirable to determine the number of entries in the candidate time table according to these values. The frequency recovery time can be further optimized by setting the conditions and candidate times in the candidate time table so that a frequency recovery time corresponding to the number and height of the impedance peaks can be selected.

[0065] Fig. 12 is a timing chart showing an example of clock control when short-period small noise occurs in the LSI 901 of Fig. 9. The CLK frequency represents the frequency of the clock signal output by the clock circuit 1013. A region 1201 of the graph showing the change in power supply voltage is enlarged and shown below.

[0066] At the start of operation, the power supply voltage is a normal voltage and the CLK frequency is F0. At time t31, power supply noise occurs and the CLK frequency is changed to FL. Then, at time t32, the power supply noise converges and control is performed to gradually increase the CLK frequency, and at time t33, the CLK frequency returns to F0.

[0067] In this case, the noise occurrence time is a short time from time t31 to time t32, and the frequency recovery time is several hundred ns from just after time t32 to time t33. Since a short frequency recovery time is selected in accordance with the short noise occurrence time, the CLK frequency recovers to F0 in a shorter time than in the clock control of FIG.

[0068] Fig. 13 shows an example of a first clock control performed by the clock control circuit 911 of Fig. 10. The detection circuit 1011 of Fig. 13 includes a comparison circuit 1311.

[0069] 13(a) shows an example of control for changing the CLK frequency to FL when power supply noise occurs. A comparator circuit 1311 compares the power supply voltage of the internal circuit 912 with a limit voltage, and outputs a noise occurrence signal 1321 indicating the occurrence of power supply noise to the control circuit 1012 when the power supply voltage becomes lower than the limit voltage.

[0070] When the control circuit 1012 receives the noise generating signal 1321, it outputs a frequency down signal 1322, which indicates an instruction to change the CLK frequency to FL, to the clock circuit 1013, and instructs the counter 1014 to start a counting operation. When the clock circuit 1013 receives the frequency down signal 1322, it changes the CLK frequency to FL and outputs a clock signal. As a result, the operating speed of the LSI 901 changes from the normal speed to a low speed.

[0071] 13(b) shows an example of control for gradually increasing the CLK frequency when short-period small noise has converged. A comparator circuit 1311 compares the power supply voltage of the internal circuit 912 with a limit voltage, and when the power supply voltage reaches the limit voltage, outputs a noise convergence signal 1331 indicating the convergence of the power supply noise to the control circuit 1012.

[0072] When the control circuit 1012 receives the noise convergence signal 1331, it instructs the counter 1014 to stop the counting operation, and acquires a count indicating a short noise occurrence time from the counter 1014. Then, the control circuit 1012 acquires, in the candidate time table stored in the register 1015, a short candidate time associated with a time range including the acquired count.

[0073] Next, the control circuit 1012 determines ΔT and ΔF using the acquired short candidate time as the frequency recovery time, and starts frequency recovery control. In the frequency recovery control, the control circuit 1012 outputs a frequency increase signal 1332 indicating an instruction to increase the CLK frequency by ΔF to the clock circuit 1013 at intervals of ΔT.

[0074] Every time the clock circuit 1013 receives the frequency increase signal 1332, it increases the CLK frequency by ΔF and outputs the clock signal to the internal circuit 912. This causes the operating speed of the LSI 901 to change from low speed to medium speed, and the LSI 901 operates at the medium speed for a short frequency recovery time. When the frequency recovery time has elapsed, the CLK frequency returns to F0, and the operating speed of the LSI 901 changes from medium speed to normal speed.

[0075] 13(c) shows an example of control for gradually increasing the CLK frequency when the long-period large noise has converged. The comparator circuit 1311 compares the power supply voltage of the internal circuit 912 with the limit voltage, and when the power supply voltage reaches the limit voltage, outputs a noise convergence signal 1341 indicating the convergence of the power supply noise to the control circuit 1012.

[0076] When the control circuit 1012 receives the noise convergence signal 1341, it instructs the counter 1014 to stop the counting operation, and acquires a count indicating a long noise occurrence time from the counter 1014. Then, the control circuit 1012 acquires a long candidate time associated with a time range including the acquired count in a candidate time table stored in the register 1015.

[0077] Next, the control circuit 1012 determines ΔT and ΔF using the acquired long candidate time as the frequency recovery time, and starts frequency recovery control. In the frequency recovery control, the control circuit 1012 outputs a frequency increase signal 1342 indicating an instruction to increase the CLK frequency by ΔF to the clock circuit 1013 at intervals of ΔT.

[0078] Every time the clock circuit 1013 receives the frequency increase signal 1332, it increases the CLK frequency by ΔF and outputs the clock signal to the internal circuit 912. This causes the operating speed of the LSI 901 to change from low speed to medium speed, and the LSI 901 operates at the medium speed for a long frequency recovery time. When the frequency recovery time has elapsed, the CLK frequency returns to F0, and the operating speed of the LSI 901 changes from medium speed to normal speed.

[0079] 10, the frequency recovery time can be selected from a plurality of candidate times according to the noise occurrence time from when the power supply noise occurs until it converges. This makes it possible to select an appropriate frequency recovery time according to the period and magnitude of the power supply noise, and shortens the time during which the LSI 901 operates at medium speed. By reducing the time during which the LSI 901 operates at medium speed, the time during which the LSI 901 operates at normal speed increases, improving the performance of the LSI 901.

[0080] Fig. 14 is a flowchart showing an example of a first clock control performed by the clock control circuit 911 of Fig. 10. First, the detection circuit 1011 detects the occurrence of power supply noise from the power supply voltage of the internal circuit 912, and outputs a noise occurrence signal to the control circuit 1012 (step 1401).

[0081] Next, the control circuit 1012 outputs a frequency down signal to the clock circuit 1013 based on the received noise occurrence signal, and the clock circuit 1013 changes the frequency of the clock signal to FL based on the received frequency down signal (step 1402). Then, the control circuit 1012 instructs the counter 1014 to start a counting operation, and the counter 1014 starts counting the noise occurrence time (step 1403).

[0082] Next, the detection circuit 1011 detects the convergence of the power supply noise from the power supply voltage of the internal circuit 912, and outputs a noise convergence signal to the control circuit 1012 (step 1404).

[0083] Next, the control circuit 1012 instructs the counter 1014 to stop counting based on the received noise convergence signal, and the counter 1014 stops counting the noise occurrence time (step 1405). Then, the control circuit 1012 obtains the count from the counter 1014 (step 1406).

[0084] Next, the control circuit 1012 sets 0 to the control variable i indicating the entry of the candidate time table (step 1407), and obtains num_i included in the condition from the i-th entry having the item number "i" (step 1408).Then, the control circuit 1012 compares count obtained from the counter 1014 with num_i (step 1409).

[0085] If count is equal to or less than num_i (step 1409, YES), the control circuit 1012 obtains time_i from the i-th entry (step 1410), and performs frequency recovery control using time_i as the frequency recovery time (step 1411).

[0086] On the other hand, if count is greater than num_i (step 1409, NO), the control circuit 1012 increments i by 1 (step 1412) and compares i with N (step 1413). If i is less than N (step 1413, NO), the control circuit 1012 repeats the processes from step 1408 onwards.

[0087] On the other hand, if i has reached N (step 1413, YES), the control circuit 1012 obtains time_N from the Nth entry (step 1414), and performs frequency recovery control using time_N as the frequency recovery time (step 1415).

[0088] Fig. 15 shows a second hardware configuration example of the clock control circuit 911 of Fig. 9. The clock control circuit 911 of Fig. 15 has a configuration in which the register 1015 is deleted from the clock control circuit 911 of Fig. 10 and the control circuit 1012 is replaced with a control circuit 1511. The control circuit 1511 corresponds to the control unit 712 of Fig. 7.

[0089] The operations of the detection circuit 1011, the clock circuit 1013, and the counter 1014 are similar to those of the clock control circuit 911 in FIG.

[0090] When the control circuit 1511 receives the noise occurrence signal from the detection circuit 1011, it outputs a frequency down signal indicating an instruction to change the frequency of the clock signal to the frequency FL for low-speed operation to the clock circuit 1013. Then, the control circuit 1511 instructs the counter 1014 to start a counting operation.

[0091] When the control circuit 1511 receives the noise convergence signal from the detection circuit 1011, it instructs the counter 1014 to stop the counting operation and acquires the count from the counter 1014. Then, the control circuit 1511 uses the acquired count as X to calculate the frequency recovery time TR by the following equation.

[0092] TR=a n X n +a n-1 X n-1 +···+a1X 1 +a0(1)

[0093] The right-hand side of equation (1) is an n-th degree polynomial of X (n is an integer equal to or greater than 1), and TR increases as X increases.

[0094] Next, the control circuit 1511 performs frequency recovery control to increase the frequency of the clock signal stepwise from FL to F0, using the calculated TR as the frequency recovery time.

[0095] Coefficient a in Equation (1) n The values ​​of the coefficient a1 and the constant term a0 can be obtained by a prior simulation. However, the coefficient a n The accuracy of the coefficient a1 and the constant term a0 can be improved by determining them while evaluating them. nIt is desirable to be able to set the values ​​of the coefficient a1 and the constant term a0.

[0096] In addition, the coefficient a is used to calculate the frequency recovery time corresponding to the number and height of the impedance peaks in the power supply system. n By setting the values ​​of coefficient a1 and constant term a0, the frequency recovery time can be further optimized.

[0097] Fig. 16 shows an example of a second clock control performed by the clock control circuit 911 of Fig. 15. The comparator circuit 1311 compares the power supply voltage of the internal circuit 912 with a limit voltage, and outputs a noise convergence signal 1611 indicating the convergence of the power supply noise to the control circuit 1511 when the power supply voltage reaches the limit voltage.

[0098] When the control circuit 1511 receives the noise convergence signal 1611, it instructs the counter 1014 to stop the counting operation, and acquires a count indicating the noise occurrence time from the counter 1014. Then, the control circuit 1511 uses the acquired count as X to calculate TR by the formula (1).

[0099] Next, the control circuit 1511 determines ΔT and ΔF using the calculated TR as the frequency recovery time, and starts frequency recovery control. In the frequency recovery control, the control circuit 1511 outputs a frequency increase signal 1612, which indicates an instruction to increase the CLK frequency by ΔF, to the clock circuit 1013 at intervals of ΔT.

[0100] Every time the clock circuit 1013 receives the frequency increase signal 1612, it increases the CLK frequency by ΔF and outputs the clock signal to the internal circuit 912. This changes the operating speed of the LSI 901 from low speed to medium speed, and the LSI 901 operates at the medium speed during the frequency recovery time. When the frequency recovery time has elapsed, the CLK frequency returns to F0, and the operating speed of the LSI 901 changes from medium speed to normal speed.

[0101] 15, the frequency recovery time can be calculated according to the noise occurrence time from when the power supply noise occurs until it converges. This makes it possible to select an appropriate frequency recovery time according to the period and magnitude of the power supply noise, and shortens the time during which the LSI 901 operates at medium speed. By reducing the time during which the LSI 901 operates at medium speed, the time during which the LSI 901 operates at normal speed increases, improving the performance of the LSI 901.

[0102] Fig. 17 is a flowchart showing an example of the second clock control performed by the clock control circuit 911 of Fig. 15. The processes of steps 1701 to 1706 are similar to the processes of steps 1401 to 1406 of Fig. 14.

[0103] When the count is acquired from the counter 1014, the control circuit 1511 calculates TR by equation (1) using the acquired count as X (step 1707). Then, the control circuit 1511 performs frequency recovery control using the calculated TR as a frequency recovery time (step 1708).

[0104] Fig. 18 shows a second hardware configuration example of an LSI corresponding to the semiconductor device 701 of Fig. 7. The LSI 1801 of Fig. 18 is a multi-core processor and includes cores 1811-1 to 1811-4 and an I / O circuit 1812. These components are hardware circuits. The cores 1811-j (j=1 to 4) include clock control circuits 1821-j.

[0105] The core 1811-j performs arithmetic processing. The I / O circuit 1812 receives data used in the arithmetic processing from the outside, outputs the received data to the core 1811-j, and outputs the arithmetic result output from the core 1811-j to the outside. The clock control circuit 1821-j generates a clock signal used by the core 1811-j. The clock control circuit 1821-j has a configuration similar to that of the clock control circuit 911 shown in FIG. 10 or FIG. 15, for example, and performs similar clock control.

[0106] The configurations of the LSI in Fig. 1, the semiconductor device 701 in Fig. 7, the LSI 901 in Fig. 9, and the LSI 1801 in Fig. 18 are merely examples, and some of the components may be omitted or changed depending on the use or conditions of the LSI or the semiconductor device. For example, the number of cores 1811-j included in the LSI 1801 in Fig. 18 may be 1 to 3, or may be 5 or more. The configurations of the clock control circuits 911 in Figs. 10 and 15 are merely examples, and some of the components may be omitted or changed depending on the configuration or conditions of the LSI.

[0107] The clock signal and data signal in Fig. 2 are merely examples, and the clock signal and data signal change depending on the LSI. The timing charts in Fig. 3, Fig. 5, Fig. 6, and Fig. 12 are merely examples, and the timing chart of the clock control changes depending on the LSI and power supply noise. The clock control shown in Fig. 4, Fig. 13, and Fig. 16 are merely examples, and the clock control changes depending on the LSI and power supply noise.

[0108] The flowcharts of Fig. 8, Fig. 14, and Fig. 17 are merely examples, and some processes may be omitted or changed depending on the configuration or conditions of the LSI or semiconductor device. The candidate time table of Fig. 11 is merely an example, and conditions and candidate times in other formats may be used. Equation (1) is merely an example, and the control circuit 1511 may calculate the frequency recovery time TR using another calculation formula.

[0109] Although the disclosed embodiments and their advantages have been described in detail, it will be appreciated that those skilled in the art may make various modifications, additions and omissions therein without departing from the scope of the invention as clearly set forth in the claims.

[0110] The following notes are further disclosed regarding the embodiment described with reference to FIGS. (Appendix 1) a clock unit that outputs a clock signal of a first frequency; A detection unit that detects an occurrence of power supply noise and a convergence of the power supply noise; a control unit that, when occurrence of the power supply noise is detected, reduces a frequency of the clock signal from the first frequency to a second frequency, determines a frequency recovery time according to a noise occurrence time from occurrence of the power supply noise to convergence of the power supply noise, and recovers the frequency of the clock signal from the second frequency to the first frequency based on the frequency recovery time; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the control unit controls the clock unit so that the frequency of the clock signal increases stepwise from the second frequency to the first frequency during the frequency recovery time. (Appendix 3) A storage unit that stores candidate times associated with each of the plurality of time ranges, The semiconductor device according to claim 1 or 2, wherein the control unit uses, as the frequency recovery time, a candidate time associated with a time range including the noise occurrence time, among the candidate times associated with each of the plurality of time ranges, to recover the frequency of the clock signal from the second frequency to the first frequency. (Appendix 4) The semiconductor device according to claim 1 or 2, wherein the control unit calculates the frequency recovery time by using the noise occurrence time, and uses the calculated frequency recovery time to recover the frequency of the clock signal from the second frequency to the first frequency. (Appendix 5) Detects power supply noise and Reducing the frequency of the clock signal from a first frequency to a second frequency; Detecting convergence of the power supply noise; determining a frequency recovery time according to a noise occurrence time from the occurrence of the power supply noise to the convergence of the power supply noise; restoring the frequency of the clock signal from the second frequency to the first frequency based on the frequency recovery time; 2. A clock control method comprising: (Appendix 6) 6. The clock control method according to claim 5, wherein the process of returning the frequency of the clock signal from the second frequency to the first frequency includes a process of controlling the frequency of the clock signal so that the frequency of the clock signal increases stepwise from the second frequency to the first frequency during the frequency return time. (Appendix 7) The clock control method according to claim 5 or 6, characterized in that the process of restoring the frequency of the clock signal from the second frequency to the first frequency includes a process of using, as the frequency restoration time, a candidate time associated with a time range including the noise occurrence time, among candidate times associated with each of a plurality of time ranges, to restore the frequency of the clock signal from the second frequency to the first frequency. (Appendix 8) 7. The clock control method according to claim 5, wherein the process of returning the frequency of the clock signal from the second frequency to the first frequency includes a process of calculating the frequency return time using the noise generation time, and a process of returning the frequency of the clock signal from the second frequency to the first frequency using the calculated frequency return time. [Explanation of symbols]

[0111] 101 Clock Driver 102, 104 FF 103 Logic Circuits 401, 1011 Detection circuit 402, 1012, 1511 Control circuit 403, 1013 Clock Circuit 411, 1311 comparison circuit 421, 1321 Noise generating signal 422, 1322 Frequency reduction signal 431, 1331, 1341, 1611 Noise-converged signals 432, 1332, 1342, 1612 frequency rising signal 701 Semiconductor Devices 711 Detection unit 712 Control Unit 713 Clock section 901, 1801 LSI 911, 1821-1 to 1821-4 Clock control circuit 912 Internal circuit 913, 1812 I / O circuit 921, 922 signal line 1014 Counter 1015 Register 1201 area 1811-1~1811-4 Core

Claims

1. a clock unit that outputs a clock signal of a first frequency; A detection unit that detects an occurrence of power supply noise and a convergence of the power supply noise; a control unit that, when occurrence of the power supply noise is detected, reduces a frequency of the clock signal from the first frequency to a second frequency, determines a frequency recovery time according to a noise occurrence time from occurrence of the power supply noise to convergence of the power supply noise, and recovers the frequency of the clock signal from the second frequency to the first frequency based on the frequency recovery time; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the control unit controls the clock unit so that the frequency of the clock signal increases stepwise from the second frequency to the first frequency during the frequency recovery time.

3. A storage unit that stores candidate times associated with each of the plurality of time ranges, 3. The semiconductor device according to claim 1, wherein the control unit uses, among the candidate times associated with each of the plurality of time ranges, a candidate time associated with a time range including the noise occurrence time as the frequency recovery time, to recover the frequency of the clock signal from the second frequency to the first frequency.

4. 3. The semiconductor device according to claim 1, wherein the control unit calculates the frequency recovery time by using the noise occurrence time, and uses the calculated frequency recovery time to recover the frequency of the clock signal from the second frequency to the first frequency.

5. A detection unit detects the occurrence of power supply noise, The control unit reduces the frequency of the clock signal output from the clock unit from the first frequency to the second frequency, The detection unit detects convergence of the power supply noise, the control unit determines a frequency recovery time in accordance with a noise occurrence time from the occurrence of the power supply noise to the convergence of the power supply noise; the control unit restores the frequency of the clock signal from the second frequency to the first frequency based on the frequency restoration time.

2. A clock control method comprising:

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