Gate Driver

Abstract

To provide a gate drive device which can detect a short-circuit state even just after of a gate on of a semiconductor switching element, and can be utilized as a failsafe of a dead time shortening control such as a feedback to a setting dead time which is over-shortened.SOLUTION: A gate drive device that performs a driving control by applying a gate driving signal by a control circuit provided in accordance with each gate driving type semiconductor switching element, comprises: a differential circuit that detects a time change amount of a current in the semiconductor switching element; and a comparison circuit that outputs a detection signal when the time change amount in a returning period of a recover current in the time change amount of a current detected by the differential circuit is a predetermined level or more. The control circuit determines whether or not it is in a short-circuit state on the basis of an on-off command and the detection signal from the comparison circuit, and performs the driving control of the semiconductor switching element by the gate driving signal to which a dead time is adjusted and set on the basis of a result of the determination.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a gate drive device. [Background technology]

[0002] In recent years, some gate drive devices such as inverters that have semiconductor switching elements in the upper and lower arms to supply power to a load use SiCMOS transistors as the semiconductor switching elements. When using a body diode in a SiCMOS transistor, the on-voltage is high, resulting in large losses, and degradation of the body diode during conduction can also be an issue.

[0003] Therefore, synchronous rectification is used to reduce losses and the stress on the elements by shortening the time that the body diode is energized.With synchronous rectification control, it is necessary to set a dead time DT (Dead Time) between the opposing arm OFF and the own arm ON to prevent the upper and lower arms from shorting out, and it is necessary to shorten the dead time to reduce inverter losses.

[0004] One method for shortening the dead time is to measure the actual dead time and feed it back to control the motor for the next time. However, in practice, there is a concern that control variations or failures could cause short circuits in the upper and lower arms.

[0005] However, on the other hand, a recovery current due to the body diode flows when the arm is turned on, which can cause a large current to flow even in normal conditions. To avoid this, a method is sometimes adopted in which a mask period is set up to prevent false detection of a short circuit immediately after turning on the device, and a short circuit is detected when the detection threshold is exceeded after the mask period has elapsed.

[0006] However, with this method, it is not possible to detect short circuits during the mask period, making it impossible to detect short circuits at the moment of turn-on or immediately afterwards, and there remains the issue that minute short-circuit currents cannot be detected when the dead time is made too short. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] WO2018 / 193527 publication Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention has been made in consideration of the above circumstances, and its object is to provide a gate drive device that can detect a short-circuit state even immediately after the gate of a gate-driven semiconductor switching element is turned on, and that can be used as a fail-safe for dead-time shortening control, such as by providing feedback to a set dead-time that is too shortened. [Means for solving the problem]

[0009] The gate drive device according to claim 1 is a gate drive device in which gate drive type semiconductor switching elements are arranged in upper and lower arms to supply power to a load, and drive control is performed by providing gate drive signals to the semiconductor switching elements by control circuits provided corresponding to each of the semiconductor switching elements based on an on / off command signal, the gate drive device comprising: a differentiation circuit that detects a time change in current of the semiconductor switching elements; and a gate drive circuit that detects a time change in the current detected by the differentiation circuit when a time change in the recovery period of a recovery current is equal to or greater than a predetermined level. Comparison to output detection signal a control circuit for controlling the on / off command signal and the above comparison From the circuit Based on the detection signal, it is determined whether or not the upper and lower arms are in a short-circuit state. The semiconductor switching element is driven and controlled by a gate drive signal in which the dead time is adjusted based on the gate drive signal.

[0010] By adopting the above-mentioned configuration, when the control circuit turns on the semiconductor switching element corresponding to itself, the current flowing through the semiconductor switching element is differentiated by the differentiation circuit to detect the amount of change over time, and it is determined whether the amount of change over time in the recovery period of the recovery current is equal to or greater than a predetermined level. The decision It is determined.

[0011] If the time change amount is not equal to or greater than the predetermined level, it is determined that a short circuit has not occurred and the dead time is set appropriately, and if the time change amount is equal to or greater than the predetermined level, it is determined that a short circuit has occurred and the dead time is adjusted and set. As a result, the semiconductor switching element of the opposing arm is turned on at the timing at which the dead time is adjusted.

[0012] This makes it possible to quickly determine the short-circuit state immediately after the gate is turned on within this period without setting a mask period immediately after the gate is turned on, and it is possible to suppress the short-circuit energy to a degree that does not damage the semiconductor switching elements.It can also be used as a fail-safe for dead-time shortening control, such as feedback for a dead-time setting that is too short, and it is possible to shorten the dead time as much as possible.

[0013] Furthermore, since the return slope of the recovery current of the semiconductor switching element is detected by a differential circuit, it is possible to eliminate the need to set a mask period and prevent erroneous detection of overcurrent that occurs when only the current value of the semiconductor switching element is monitored. [Brief description of the drawings]

[0014] [Figure 1] Electrical configuration diagram showing the first embodiment [Diagram 2] Timing chart showing the first embodiment [Diagram 3] FIG. 1 is an explanatory diagram showing the operation of the first embodiment. [Figure 4] Electrical configuration diagram showing the second embodiment [Diagram 5] Timing chart showing the second embodiment [Figure 6] Electrical configuration diagram showing the third embodiment [Figure 7] Timing chart showing the third embodiment [Figure 8] Electrical configuration diagram showing the fourth embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] (First embodiment) A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. In Fig. 1 showing the electrical configuration, the upper and lower arms are composed of N-channel type SiCMOS transistors (hereinafter simply referred to as MOS transistors) 1a and 1b which are semiconductor switching elements connected in series. The MOS transistor 1a is arranged in the lower arm, and the MOS transistor 1b is arranged in the upper arm. The MOS transistors 1a and 1b have body diodes 2a and 2b, respectively. The common connection point of the MOS transistors 1a and 1b is connected to an inductor 3 which is a load.

[0016] Gate drive control of the MOS transistors 1a and 1b is performed by gate drive devices 10A and 10B, respectively. Both gate drive devices 10A and 10B have the same configuration, and hereinafter, the configuration of gate drive device 10A is indicated with the subscript a, and the configuration of gate drive device 10B is indicated with the subscript b. The gate drive devices 10A and 10B are given on-off command signals Sx1 and Sx2, respectively, from the microcomputer 4, and output short circuit detection signals Ss1 and Ss2 to the microcomputer 4. The configuration of the gate drive device 10A will be described below as a representative example.

[0017] The gate driver 10A includes a control circuit 11a, a sense element 12a for detecting current, a current monitor 13a, a drive circuit 20a, a differentiation circuit 30a, and a comparison circuit 40a. The control circuit 11a receives an on / off command signal Sx1 with an adjusted dead time from the microcomputer 4, and outputs a drive signal to the drive circuit 20a in response to the signal to drive the MOS transistor 1a. The control circuit 11a also functions as a determination unit that, when a high-level detection signal is received from the comparison circuit 40a, determines whether or not a short circuit has occurred and outputs a short circuit detection signal Ss1 to the microcomputer 4.

[0018] The sense element 12a can be used when it is built into the MOS transistor 1a, or when it is not built in, it is provided as a current detection element, and is configured to pass a minute current set to a predetermined ratio to the current flowing through the MOS transistor 1a and the body diode 2a. The drain and gate of the sense element 12a are commonly connected to the MOS transistor 1a, and the current flowing through the source is detected by a current monitor 13a.

[0019] The drive circuit 20a includes a P-channel MOS transistor 21a for ON drive, an N-channel MOS transistor 22a for OFF drive, and resistors 23a and 24a. The source of the MOS transistor 21a is connected to a drive power supply VCC1, the drain is connected to the gate of the MOS transistor 1a via the resistor 23a, and a drive signal is applied from the control circuit 11a. The source of the MOS transistor 22a is connected to a drive power supply VEE1, the drain is connected to the gate of the MOS transistor 1a via the resistor 24a, and a drive signal is applied from the control circuit 11a.

[0020] The differentiating circuit 30a includes a differential amplifier 31a, a resistor 32a, and a capacitor 33a. A voltage signal corresponding to the current value of the MOS transistor 1a is input from the current monitor 13a to an inverting input terminal of the differential amplifier 31a via a differentiation capacitor 33a. A resistor 32a is connected between the inverting input terminal and the output terminal of the differential amplifier 31a, and a DC power supply VEE1 is connected to the non-inverting input terminal. The differential amplifier 31a is composed of a high-speed response operational amplifier so that it can perform an amplifying operation following a change in the current of the MOS transistor 1a.

[0021] The differentiation circuit 30a outputs a signal obtained by differentiating the current of the MOS transistor 1a, i.e., the voltage signal from the current monitor 13a that monitors the current of the MOS transistor 1a, from the output terminal. In other words, the differentiation circuit 30a outputs a signal corresponding to the amount of change in the current value of the MOS transistor 1a over time. The amount of change in the current of the MOS transistor 1a over time is detected as the speed at which the current increases or decreases, i.e., the gradient on the time axis.

[0022] The comparison circuit 40a includes a comparator 41a and a reference power supply 42a. The comparator 41a receives the output signal from the differentiation circuit 30a at its inverting input terminal, and receives a threshold voltage Vth1 from the reference power supply 42a at its non-inverting input terminal. The threshold voltage Vth is a voltage indicating a predetermined negative level for detecting the presence or absence of a short circuit, and outputs a high-level detection signal to the control circuit 11a when the negative signal level input from the differentiation circuit 30a, i.e., the amount of change over time in the return of the recovery current, becomes equal to or less than the threshold voltage Vth.

[0023] Next, the operation of the above configuration will be described with reference to FIGS. Figure 2 is a timing chart showing the signal changes at each part. Along the time axis, period (A) is when sufficient dead time (DT) is secured, period (B) is when DT is insufficient and a short circuit occurs, and period (C) is when DT is adjusted after a short circuit is detected.

[0024] FIG. 2 also shows on / off command signals Sx1, Sx2 and gate voltages Vgs1, Vgs2, and illustrates the operation of the gate driver 10A that occurs when the MOS transistor 1a is turned on relative to the off timing of the MOS transistor 1b.

[0025] In response to an on / off command signal given from the outside, the microcomputer 4 gives on / off command signals Sx1, Sx2, in which the DT between the upper and lower arm MOS transistors 1a, 1b has been adjusted, to the gate drive devices 10A, 10B, respectively. At time t0, the on / off command signal Sx2 for the MOS transistor 1b turns off, and then, at time t1, when a predetermined DT has elapsed, the on / off command signal Sx1 for the MOS transistor 1a turns on.

[0026] When a gate drive signal is applied to the gate of the MOS transistor 1a from the drive circuit 20a, the gate voltage Vgs1 rises, and when it reaches the threshold voltage, the drain current starts to flow, which is detected by the current monitor 13a. Immediately after the MOS transistor 1a is turned on, a recovery current is superimposed, so that after reaching a peak value, the current drops during the return period. If the DT is set appropriately, the return of the recovery current at this time has a slope below a certain level, i.e., the amount of change over time is below a certain level.

[0027] Figure 3 shows how the slope of the recovery current return waveform is a slope α below a certain level when DT is sufficient, and a slope β above a certain level when DT is zero. Since the slope of the recovery current return waveform is the differential value, it is possible to determine whether DT is insufficient by determining whether the differential value is above a certain level.

[0028] At this time, the change in the current of the MOS transistor 1a is detected by the differential circuit 30a. As shown in Fig. 2, the change is a large positive value during the period when the current increases immediately after the transistor is turned on, and is a negative value during the recovery current return period, and then becomes zero when the current value becomes constant.

[0029] In the case of (A) where DT is sufficiently secured, the negative detection value generated by the differentiation circuit 30a during the recovery current return period does not become equal to or lower than the threshold voltage Vth, so the comparison circuit 40a does not output a detection signal. After this, when the MOS transistor 1a turns off, the current value drops sharply and a large negative value is output from the differentiation circuit 30a. This causes the comparison circuit 40a to output a detection signal.

[0030] Even if the detection signal input from the comparison circuit 40a is at a high level, the control circuit 11a does not output the short circuit detection signal Ss1 unless the on / off command signal is on. As a result, the control circuit 11a does not output the short circuit detection signal Ss1 to the microcomputer 4.

[0031] Next, a description will be given of the case (B) in which DT is set to approximately zero. This is the case in which the on / off command signal Sx1 is output to the MOS transistor 1a at approximately the same timing as the time t2 when the MOS transistor 1b is turned off.

[0032] In this case, the MOS transistor 1a is turned on while the MOS transistor 1b is not completely turned off. Therefore, a large current flows through the MOS transistor 1a, and the return current of the recovery current also becomes a large negative value. As a result, the detection signal from the differentiation circuit 30a exceeds the threshold voltage Vth in the comparison circuit 40a, and a high-level detection signal is output at time t3.

[0033] On the other hand, in the control circuit 11a, since a high-level detection signal is input from the comparison circuit 40a while the on / off command signal Sx1 is in the on state, it is determined that a short circuit has occurred, and the control circuit 11a generates a short circuit detection signal Ss1 and outputs it to the microcomputer 4.

[0034] The microcomputer 4 adjusts and sets DT based on the input of the short circuit detection signal Ss1, then adjusts and sets the DT of the on / off command signal Sx2 to be given to the gate drive device 10B, and thereafter lengthens the DT of the on / off command signal Sx1 to be given to the gate drive device 10A. This makes it possible to immediately prevent a short circuit from occurring.

[0035] In this embodiment, a differentiation circuit 30a is provided that differentiates the current of the MOS transistor 1a, and a short-circuit state is detected when the amount of change in current over time during the recovery current return period is a negative value that drops below the threshold voltage Vth, and the dead time is adjusted and set.

[0036] This makes it possible to quickly determine the short-circuit state immediately after the gates of the MOS transistors 1a and 1b are turned on within this period without providing a mask period, and to suppress the short-circuit energy to an extent that does not damage the MOS transistors 1a and 1b. It can also be used as a fail-safe for dead-time reduction control, such as feedback for a dead-time setting that is too short, and makes it possible to reduce the dead-time as much as possible.

[0037] Furthermore, since the return slope of the recovery current of the MOS transistors 1a, 1b is detected by the differential circuits 30a, 30b, it is possible to eliminate the need to provide a mask period and to prevent erroneous detection of overcurrent, which occurs when short-circuit detection of the MOS transistors 1a, 1b is performed by monitoring only the current value.

[0038] Second embodiment 4 and 5 show the second embodiment, and the following describes the differences from the first embodiment. In this embodiment, the gate drivers 110A and 110B include control circuits 111a and 111b, respectively.

[0039] 4, the microcomputer 4 outputs on / off command signals Sx1 and Sx2 with no DT adjustment to the respective control circuits 111a and 111b. When the control circuit 111a detects a short circuit in the MOS transistor 1a that controls the gate drive, the control circuit 111a outputs a short circuit detection signal Ss1 to the control circuit 111b via the insulating element 5a. When the control circuit 111b detects a short circuit in the MOS transistor 1b that controls the gate drive, the control circuit 111b outputs a short circuit detection signal Ss2 to the control circuit 111a via the insulating element 5b.

[0040] Each of the control circuits 111a, 111b is configured to adjust and set DT based on the input short circuit detection signals Ss2, Ss1 to perform on / off drive control for the MOS transistors 1a, 1b that perform gate drive control without going through the microcomputer 4. Next, the operation of the above configuration will be described with reference to FIG.

[0041] Fig. 5 is a timing chart showing the change in signals at each part, and shows the same state as Fig. 2. In this embodiment, the microcomputer 4 does not adjust the DT between the upper and lower arm MOS transistors 1a, 1b, and the signal drives the two transistors alternately to turn on and off at the same timing.

[0042] In the gate drive device 110A, the control circuit 111a sets a predetermined DT in response to the on / off command signal Sx1 received from the microcomputer 4, and applies a gate drive signal from the drive circuit 20a to the gate of the MOS transistor 1a to drive it on.

[0043] As described above, when the drain current of the MOS transistor 1a starts to flow, this is detected by the current monitor 13a. When DT is set appropriately, the recovery current of the MOS transistor 1a returns with a slope equal to or smaller than a certain value, i.e., the amount of change over time is equal to or smaller than a certain value. When DT is sufficiently secured (A), the negative detection value generated by the differentiation circuit 30a during the period when the recovery current returns does not become equal to or smaller than the threshold voltage Vth, so the comparison circuit 40a does not output a detection signal.

[0044] Next, in the case of (B) where DT is set to almost zero, a large current flows through the MOS transistor 1a, and the return current of the recovery current also becomes a large negative value. As a result, the detection signal from the differentiation circuit 30a exceeds the threshold voltage Vth in the comparison circuit 40a, and a high-level detection signal is output at time t3.

[0045] On the other hand, in the control circuit 111a, since a high-level detection signal is input from the comparison circuit 40a during the period in which the on / off command signal Sx1 is in the on state, it is determined that a short-circuit state has occurred, and the control circuit 111a generates a short-circuit detection signal Ss1 and outputs it to the control circuit 111b of the upper arm gate drive device 11B.

[0046] Furthermore, the control circuit 111a adjusts and sets DT to be longer based on the detection of a short circuit, and at the next on timing, the MOS transistor 1a is turned on at a timing where an appropriate DT is set for the on / off command signal Sx1. This makes it possible to immediately prevent a short circuit from occurring. Therefore, in the second embodiment as well, the same effects as those in the first embodiment can be obtained.

[0047] In the above embodiment, the DT of the device itself is adjusted based on the detection of a short circuit obtained from the current of the MOS transistor 1a that it controls. However, the DT may be adjusted at the next ON timing of the MOS transistor 1b in the control circuit 111b on the gate drive device 110B side of the opposing arm based on the short circuit detection signal Ss1 obtained at this time.

[0048] In other words, in the gate driver 110A, when the short circuit detection signal Ss2 is provided from the gate driver 110B, the DT when the MOS transistor 1a is turned on may be adjusted based on this short circuit detection signal Ss2.

[0049] Third embodiment 6 and 7 show the third embodiment, and the following describes the differences from the first embodiment. In this embodiment, the gate drivers 210A and 210B include control circuits 211a and 211b, respectively.

[0050] 6, the current monitors 13a, 13b are configured to output a voltage signal corresponding to the detected current value to the differential circuits 30a, 30b as well as to the control circuits 211a, 211b. In this embodiment, in order to ensure accuracy in determining whether the MOS transistors 1a, 1b are in a short-circuit state, the control circuits 211a, 211b also use the current value level as a determination factor in addition to the detection results from the comparison circuits 40a, 40b.

[0051] FIG. 7 shows the changes in gate voltage Vgs and current value before and after ON driving for each of the MOS transistors 1a, 1b in the own arm and the opposing arm when DT is short and a short circuit occurs.

[0052] As shown in the figure, for example, when the MOS transistor of the own arm is on and the MOS transistor of the opposing arm is off, if the timing of both is approximately the same, that is, when DT is close to zero, the peak of the recovery current increases depending on the degree of the short circuit, and by using the current value at this time as a factor in determining whether or not there is a short circuit, and combining this with the change in slope from the recovery return, more accurate short circuit detection can be performed. Also, by detecting the degree of short circuit, it is possible to vary the amount of DT adjustment setting depending on the degree of short circuit.

[0053] Therefore, according to the third embodiment as well, it is possible to obtain the same effects as the above-described embodiments, and it is also possible to perform a short circuit detection operation and an adjustment setting of DT with higher accuracy.

[0054] (Fourth embodiment) 8 shows the fourth embodiment, and the following describes the differences from the first embodiment. In this embodiment, current monitor sense elements 12a and 12b are not provided, and the currents of the MOS transistors 1a and 1b are directly detected by current monitors 14a and 14b. Therefore, the fourth embodiment can also provide the same effects as the first embodiment.

[0055] (Other embodiments) The present invention is not limited to the above-described embodiment, but can be applied to various embodiments without departing from the spirit of the present invention, and can be modified or expanded as follows, for example.

[0056] In the above embodiment, a SiCMOS transistor is used as the gate-driven semiconductor switching element. However, the MOS transistor may be an ordinary silicon transistor, or an IGBT (Insulated Gate Bipolar Transistor) may be used.

[0057] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0058] In the drawing, 1a and 1b are MOS transistors (semiconductor switching elements), 2a and 2b are body diodes, 3 is an inductor (load), 4 is a microcontroller (general control unit), 10A, 10B, 110A, 110B, 210A, 210B are gate driving devices, 11a, 11b, 111a, 111b, 211a, 211b are control circuits, 12a, 12b are sense elements, 13a, 13b, 14a, 14b are current monitors, 20a, 20b are drive circuits, 30a, 30b are differential circuits, 31a, 31b are differential amplifiers, 33a, 33b are capacitors, and 40a, 40b are comparison circuits.

Claims

1. A gate drive device in which gate drive type semiconductor switching elements are arranged in upper and lower arms to supply power to a load, and drive control is performed by applying a gate drive signal to the semiconductor switching elements by control circuits (11a, 11b, 111a, 111b, 211a, 211b) provided corresponding to each of the semiconductor switching elements based on an on / off command signal, A differential circuit (30a, 30b) for detecting a time change in current of the semiconductor switching element; a comparison circuit (40a, 40b) that outputs a detection signal when a time change amount during a recovery period of the recovery current, among the time changes of the current detected by the differentiation circuit, is equal to or greater than a predetermined level; The control circuit determines whether or not the upper and lower arms are in a short-circuited state based on the on / off command signal and the detection signal from the comparison circuit, and drives and controls the semiconductor switching elements with a gate drive signal that adjusts and sets a dead time based on the result of the determination.

2. 2. The gate drive device according to claim 1, wherein the control circuit outputs a determination result as to whether or not the short-circuit state exists to an integrated control unit (4) that controls the semiconductor switching elements of the upper and lower arms in an integrated manner, and inputs the on / off command signal, the dead time of which is adjusted by the integrated control unit, to drive and control the semiconductor switching elements.

3. 2. The gate drive device according to claim 1, wherein the control circuit inputs the on / off command signal, the dead time of which is not adjusted, from an integrated control unit (4) that collectively controls the semiconductor switching elements of the upper and lower arms, and shares the determination result of whether or not the short-circuit state exists between the control circuits of the upper and lower arms to adjust and set the dead time and generate a gate drive signal.

4. 4. The gate drive device according to claim 1, wherein the control circuit determines whether or not the short circuit state occurs based on a current value of the semiconductor switching element in addition to the on / off command signal and the detection signal from the comparison circuit.

5. 4. The gate driver according to claim 1, wherein the semiconductor switching element includes a sense element, and a current through the semiconductor switching element is detected based on a current through the sense element.

Images