Solar Cells and Photovoltaic Modules

Abstract

SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of solar cells and provide solar cells and photovoltaic modules. The solar cell includes a first polysilicon doped layer and a second polysilicon doped layer on opposite sides of a substrate, the first polysilicon doped layer is doped with an N-type doping element, and the surface of the first polysilicon doped layer has a first roughness, the second polysilicon doped layer is doped with a P-type doping element, and the surface of the second polysilicon doped layer has a second roughness, the second roughness being smaller than the first roughness. The solar cell includes a first electrode and a second electrode, the first electrode is electrically connected to the first polysilicon doped layer through a first passivation layer, and the second electrode is electrically connected to the second polysilicon doped layer through a second passivation layer. The solar cell and photovoltaic module provided in the embodiments of the present application can improve the photoelectric conversion efficiency of the solar cell.

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present application relate to the field of solar cells, and in particular to solar cells and photovoltaic modules. [Background technology]

[0002] Currently, with the depletion of fossil energy, solar cells are being used more and more widely as a new alternative energy source. A solar cell is a device that converts the light energy of the sun into electrical energy. A solar cell uses the principle of photovoltaic power to generate carriers and extract them at electrodes, thereby contributing to the effective use of electrical energy.

[0003] At present, solar cells mainly include IBC (Interdigitated Back Contact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated Emitter and Real Cells) and heterojunction cells, etc. By installing different film layers and limiting their functionality, the optical loss can be reduced, and the recombination of photogenerated carriers on and inside the silicon substrate can be reduced, thereby improving the photoelectric conversion efficiency of solar cells.

[0004] However, currently, the photoelectric conversion efficiency of solar cells is still poor. Summary of the Invention [Problem to be solved by the invention]

[0005] In the embodiments of the present application, a solar cell and a photovoltaic module are provided that are advantageous in improving at least the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided, the solar cell including: a substrate having a first surface and a second surface opposite to each other; a first dielectric layer located on the first surface and a first polysilicon doped layer located on the first dielectric layer; a second dielectric layer located on the second surface and a second polysilicon doped layer located on the second dielectric layer; a first passivation layer located on the first polysilicon doped layer and a second passivation layer located on the second polysilicon doped layer; and a first electrode and a second electrode; The first polysilicon doped layer is doped with an N-type doping element, a surface of the first polysilicon doped layer remote from the first dielectric layer has a first roughness, the second polysilicon doped layer is doped with a P-type doping element, wherein a surface of the second polysilicon doped layer remote from the second dielectric layer has a second roughness, the second roughness being smaller than the first roughness, the first electrode is electrically connected to the first polysilicon doped layer through the first passivation layer, and the second electrode is electrically connected to the second polysilicon doped layer through the second passivation layer.

[0007] In some embodiments, the first polysilicon doped layer includes a plurality of first silicon crystal grains, surfaces of the plurality of first silicon crystal grains forming a surface of the first polysilicon doped layer having the first roughness, the second polysilicon doped layer includes a plurality of second silicon crystal grains, surfaces of the plurality of second silicon crystal grains forming a surface of the second polysilicon doped layer having the second roughness, and a grain size of the first silicon crystal grains is smaller than a grain size of the second silicon crystal grains.

[0008] In some embodiments, the grain size range of the first silicon crystal grains includes 10 nm to 300 nm.

[0009] In some embodiments, the second silicon crystal grains have a grain size ranging from 100 nm to 900 nm.

[0010] In some embodiments, the shape of the first silicon crystal grains comprises spherical grains or quasi-spherical grains.

[0011] In some embodiments, the shape of the second silicon crystalline grains includes sheets, plates, or grains.

[0012] In some embodiments, a radial dimension of the first silicon crystal grain is smaller than a radial dimension of the second silicon crystal grain, and a height of the first silicon crystal grain is greater than a height of the second silicon crystal grain.

[0013] In some embodiments, the solar cell includes alternating electrode and non-electrode regions, the first dielectric layer and the first polysilicon doped layer being located in the electrode regions, the first passivation layer being located in the electrode regions and the non-electrode regions, the first surface opposite the electrode regions having a first textured structure, the first dielectric layer covering the first textured structure, the first surface opposite the non-electrode regions having a second textured structure, and the first passivation layer further covering the second textured structure.

[0014] In some embodiments, a minimum distance between the first texture structure and the second surface is a first distance and a minimum distance between the second texture structure and the second surface is a second distance, the first distance being greater than the second distance.

[0015] In some embodiments, the solar cell includes alternating electrode and non-electrode regions, the second dielectric layer and the second polysilicon doped layer are located in the electrode regions, the second passivation layer is located in the electrode regions and the non-electrode regions, the second surface opposite the electrode regions has a first textured structure, the second dielectric layer covers the first textured structure, the second surface opposite the non-electrode regions has a second textured structure, and the second passivation layer covers the second textured structure.

[0016] In some embodiments, a minimum distance between the first texture structure and the first surface is a first distance and a minimum distance between the second texture structure and the first surface is a second distance, the first distance being greater than the second distance.

[0017] In some embodiments, the difference between the first distance and the second distance is in the range of 0.5 to 10 μm.

[0018] In some embodiments, the first surface of the substrate further comprises a third texture structure, the third texture structure being interposed at the boundary between the non-electrode region and the electrode region, a portion of the third texture structure including a first side and a second side, the first side facing the electrode region, and the first dielectric layer covering the first side and the second side facing the non-electrode region, and a radial length of the first side being smaller than a radial length of the second side.

[0019] In some embodiments, the third texture structures include prismatic structures, pyramidal structures or tetrahedral structures.

[0020] In some embodiments, at least one of the first texture structure or the second texture structure comprises a platform protrusion structure or a pyramid texture structure.

[0021] In some embodiments, the first surface is a front surface and the substrate is doped with an N-type doping element.

[0022] In some embodiments, the average thickness of the first polysilicon doped layer is less than or equal to the average thickness of the second polysilicon doped layer.

[0023] In some embodiments, a material of at least one of the first dielectric layer or the second dielectric layer includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0024] According to some embodiments of the present application, in another aspect of the present embodiment, a photovoltaic module is further provided, the photovoltaic module including a cell string in which solar cells in any of the above-mentioned embodiments are connected by a connecting member, an encapsulation layer for covering a surface of the cell string, and a cover plate for covering a surface of the encapsulation layer remote from the cell string. Effect of the Invention

[0025] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0026] In the solar cell provided in the embodiment of the present application, the solar cell includes a first polysilicon doped layer and a second polysilicon doped layer, the first polysilicon doped layer is located on a first surface, and the second polysilicon doped layer is located on a second surface, and the recombination current of the cell is reduced to the maximum extent by designing a full passivation contact cell structure, and the open-circuit voltage of the cell is increased. In addition, in the process of manufacturing the full passivation contact cell, there is no design of a high-temperature diffusion layer, and the first polysilicon doped layer and the second polysilicon doped layer are used as carrier transport layers to eliminate the influence of the recombination current of the diffusion layer, and the open-circuit voltage of the cell is increased. The first polysilicon doped layer is doped with an N-type doping element, and the surface of the first polysilicon doped layer has a first roughness, and the second polysilicon doped layer is doped with a P-type doping element, and the surface of the second polysilicon doped layer has a second roughness, and the second roughness is smaller than the first roughness. Thus, based on the difference in the morphology of the first polysilicon doped layer and the second polysilicon doped layer, for the first polysilicon doped layer with higher roughness, the surface of the first polysilicon doped layer can enhance the internal reflection of incident light and reduce the optical loss of the solar cell, the first polysilicon doped layer can further increase the contact area between the first electrode and the first polysilicon doped layer, and improve the contact performance and welding tensile strength of the first polysilicon doped layer. For the second polysilicon doped layer with low roughness, the surface of the second polysilicon doped layer is smooth, the uniformity of the second passivation layer deposited thereon is good, and the passivation performance of the second passivation layer is good, which can improve the recombination defect problem of the solar cell. [Brief description of the drawings]

[0027] One or more embodiments are illustratively described in the figures in the corresponding accompanying drawings, but these illustrative descriptions are not intended to limit the embodiments, and unless otherwise specified, the figures in the accompanying drawings are not limited to scale. In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the drawings that need to be used in the embodiments are briefly introduced below, but obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative labor. [Figure 1] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Diagram 2] FIG. 2 is a diagram showing a cross-sectional structure along the A1-A2 cross section of FIG. [Diagram 3] FIG. 3 is a scanning electron micrograph of the first polysilicon doped layer in a solar cell provided in one embodiment of the present application. [Figure 4] FIG. 4 is a scanning electron micrograph of the second polysilicon doped layer in a solar cell provided in one embodiment of the present application. [Diagram 5] FIG. 5 is a diagram showing the structure of a solar cell provided in another embodiment of the present application. [Figure 6] FIG. 6 is a diagram showing a cross-sectional structure along the A1-A2 cross section of FIG. [Figure 7] FIG. 7 is a diagram showing the structure of a solar cell provided in another embodiment of the present application. [Figure 8] FIG. 8 is a diagram showing a cross-sectional structure along the A1-A2 cross section of FIG. [Figure 9] FIG. 9 is a local enlarged view of C in FIG. [Figure 10] FIG. 10 is a first scanning electron micrograph of the boundary between the electrode region and the non-electrode region in FIG. [Figure 11] FIG. 11 is a second type of scanning electron micrograph of the boundary between the electrode region and the non-electrode region in FIG. [Figure 12] FIG. 12 is a diagram showing the structure of a photovoltaic module provided in another embodiment of the present application. [Figure 13] FIG. 13 is a diagram showing a cross-sectional structure along the M1-M2 cross section of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] As can be seen from the background art, currently, the photoelectric conversion efficiency of solar cells is poor.

[0029] The embodiment of the present application provides a solar cell and a photovoltaic module, the solar cell includes a first polysilicon doped layer and a second polysilicon doped layer, the first polysilicon doped layer is located on a first surface, and the second polysilicon doped layer is located on a second surface, and the recombination current of the cell is reduced to the maximum extent and the open-circuit voltage of the cell is increased by designing a full passivation contact cell structure. In addition, in the process of manufacturing the full passivation contact cell, there is no design of a high-temperature diffusion layer, and the first polysilicon doped layer and the second polysilicon doped layer are used as carrier transport layers to eliminate the influence of the recombination current of the diffusion layer and increase the open-circuit voltage of the cell. The first polysilicon doped layer is doped with an N-type doping element, and the surface of the first polysilicon doped layer has a first roughness, and the second polysilicon doped layer is doped with a P-type doping element, and the surface of the second polysilicon doped layer has a second roughness, and the second roughness is smaller than the first roughness. Thus, based on the difference in the morphology of the first polysilicon doped layer and the second polysilicon doped layer, for the first polysilicon doped layer with higher roughness, the surface of the first polysilicon doped layer can enhance the internal reflection of incident light and reduce the optical loss of the solar cell, the first polysilicon doped layer can further increase the contact area between the first electrode and the first polysilicon doped layer, and improve the contact performance and welding tensile strength of the first polysilicon doped layer. For the second polysilicon doped layer with low roughness, the surface of the second polysilicon doped layer is smooth, the uniformity of the second passivation layer deposited thereon is good, and the passivation performance of the second passivation layer is good, which can improve the recombination defect problem of the solar cell.

[0030] Hereinafter, each embodiment of the present application will be described in detail in conjunction with the drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in the embodiments of the present application in order to allow the reader to better understand the present application, the technical solution claimed for protection in the embodiments of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0031] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application, FIG. 2 is a diagram showing the cross-sectional structure along the A1-A2 section of FIG. 1, FIG. 3 is a scanning electron microscope photograph of a first polysilicon doped layer in a solar cell provided in one embodiment of the present application, and FIG. 4 is a scanning electron microscope photograph of a second polysilicon doped layer in a solar cell provided in one embodiment of the present application.

[0032] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell for improving photoelectric conversion efficiency is provided, as shown in Figures 1 and 2. The solar cell includes a substrate 100, and has a first surface 11 and a second surface 12 that are disposed opposite to each other.

[0033] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, and may be, for example, silicon or germanium. Here, the elemental semiconductor material may be in a monocrystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a monocrystalline state and an amorphous state is called a microcrystalline state), and for example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0034] In some embodiments, the material of the substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, materials such as silicon germanium, silicon carbide, gallium arsenide, indium gallide, perovskites, cadmium telluride, copper indium selenide, etc. The substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0035] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. In the N-type semiconductor substrate, an N-type doping element is doped, which may be any of the group V elements, such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In the P-type semiconductor substrate, an P-type doping element is doped, which may be any of the group III elements, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0036] In some embodiments, the first surface 11 of the substrate 100 may be the front surface and the second surface 12 may be the back surface, or the first surface 11 of the substrate 100 may be the back surface and the second surface 12 may be the front surface, i.e., the solar cell is a single-sided cell, the front surface is used as the light receiving surface to receive incident light, and the back surface is used as the backlight surface. In some embodiments, the solar cell is a double-sided cell, i.e., both the first surface and the second surface of the substrate may be used as the light receiving surface to receive incident light. Here, the backlight surface can also receive incident light, but the efficiency of receiving incident light is weaker than the efficiency of receiving incident light of the light receiving surface.

[0037] In the solar cells shown in Figures 2, 6 and 8, the first side of the substrate is the front side and the second side of the substrate is the back side, i.e., by making improvements on the front side of the solar cell, the parasitic absorption on the front side of the solar cell is reduced, and by making improvements on the back side of the solar cell, the passivation performance on the back side of the solar cell is improved. In the solar cells shown in Figures 2, 6 and 8, the side facing up of the substrate is the light receiving side, and the side facing down of the substrate is the backlight side.

[0038] In addition, the solar cells shown in Figures 2, 6 and 8 are described as examples in which the first surface of the substrate is the front surface and the second surface of the substrate is the back surface, and some embodiments of the present application further provide solar cells in which the first surface is the back surface and the second surface is the front surface.

[0039] As shown in FIG. 2, the solar cell includes a first dielectric layer 111 located on a first surface 11 and a first polysilicon doped layer 112 located on the first dielectric layer 111, the first polysilicon doped layer 112 is doped with an N-type doping element, and a surface of the first polysilicon doped layer 112 away from the first dielectric layer 111 has a first roughness.

[0040] In some embodiments, the material of the first dielectric layer 111 includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0041] In some embodiments, the first dielectric layer 111 may include a first tunnel dielectric layer, and a passivation contact structure is formed between the first tunnel dielectric layer and the first polysilicon doped layer 112, and the first polysilicon doped layer 112 can form a band bending at the surface of the substrate 100, and the first tunnel dielectric layer creates an asymmetric offset in the band at the surface of the substrate 100, and the potential barrier for the majority carriers in the carriers is lower than the potential barrier for the minority carriers in the carriers. Thus, the majority carriers can easily pass through the first tunnel dielectric layer to perform quantum tunneling, but the minority carriers cannot easily pass through the first tunnel dielectric layer, thereby realizing selective transport of carriers.

[0042] In addition, the first tunnel dielectric layer exerts a chemical passivation effect. Specifically, since there are interface state defects at the interface between the substrate 100 and the first tunnel dielectric layer, the interface state density at the front surface of the substrate 100 increases, and the increase in the interface state density promotes the recombination of photogenerated carriers, increases the backing factor, short circuit current, and open circuit voltage of the solar cell, and enhances the photoelectric conversion efficiency of the solar cell. By arranging the first tunnel dielectric layer to be located at the first surface 11 of the substrate 100, the first tunnel dielectric layer exerts a chemical passivation effect on the surface of the substrate 100. Specifically, the dangling bonds of the substrate 100 are saturated, the defect state density of the substrate 100 is reduced, and the recombination center of the substrate 100 is reduced, thereby reducing the recombination speed of carriers.

[0043] The first polysilicon doped layer 112 exerts a field passivation effect. Specifically, it forms an electrostatic field on the surface of the substrate 100 toward the inside of the substrate 100, and the minority carriers escape from the interface, thereby reducing the minority carrier concentration, lowering the carrier recombination rate at the interface of the substrate 100, increasing the open circuit voltage, short circuit current and backing factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0044] The first polysilicon doped layer 112 may be doped with the same type of doping element as the substrate 100, for example, the type of doping element of the substrate 100 is N-type.

[0045] The concentration of the doping element in the first polysilicon doped layer 112 is greater than the concentration of the doping element in the substrate 100, thereby forming a sufficiently high potential barrier at the surface of the substrate 100 to allow majority carriers in the substrate 100 to pass through the first tunnel dielectric layer and reach the first polysilicon doped layer 112.

[0046] In some embodiments, the first polysilicon doped layer 112 may be doped with a different type of doping element than the substrate 100, for example, if the type of doping element in the substrate 100 is P-type, the type of doping element in the first polysilicon doped layer 112 may be N-type. In this way, a PN junction is established between the first polysilicon doped layer 112 and the substrate, and new hole-electron pairs are formed when sunlight shines on the PN junction, and the built-in electric field of the PN junction causes the photo-generated holes to flow to the P region and the photo-generated electrons to flow to the N region, generating a current when the circuit is turned on.

[0047] In some embodiments, the thickness of the first tunnel dielectric layer is 0.5 nm to 5 nm. The thickness range of the first tunnel dielectric layer is 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. If the thickness of the first tunnel dielectric layer is within any of the above ranges, the thickness of the first tunnel dielectric layer is thin, and majority carriers can easily pass through the first tunnel dielectric layer to perform quantum tunneling, but minority carriers have difficulty passing through the first tunnel dielectric layer, so that selective transport of carriers can be realized. In some embodiments, the thickness of the first polysilicon doped layer 112 is 10 nm to 300 nm. Optionally, the thickness of the first polysilicon doped layer 112 is 10 nm to 60 nm, or 60 nm to 130 nm, or 130 nm to 250 nm, or 250 nm to 300 nm.

[0048] As shown in FIG. 3, the first polysilicon doped layer 112 includes a plurality of first silicon crystal grains 1121, and the surfaces of the plurality of first silicon crystal grains 1121 constitute the surface of the first polysilicon doped layer 112 having a first roughness.

[0049] In the process of forming the first polysilicon doped layer 112, silicon atoms are arranged in a number of crystal nuclei in the form of a diamond lattice, and these crystal nuclei grow into crystal grains with different crystal plane orientations, and these crystal grains are combined to crystallize into polycrystalline silicon. Here, the first silicon crystal grains refer to the crystal grains with different crystal plane orientations that constitute the polycrystalline silicon.

[0050] From the scanning electron microscope photograph in Figure 3, the surface morphology of the first polysilicon doped layer 112 can be intuitively observed. The first polysilicon doped layer 112 is composed of a plurality of first silicon crystal particles 1121, and the unevenness of the plurality of first silicon crystal particles 1121 forms the uneven surface of the first polysilicon doped layer 112, and thus the surface of the first polysilicon doped layer 112 has a first roughness.

[0051] In some embodiments, the grain size of the first silicon crystal grains 1121 may be in the range of 10 nm to 300 nm. The grain size of the first silicon crystal grains 1121 may be in the range of 10 nm to 53 nm, 53 nm to 95.3 nm, 95.3 nm to 138.2 nm, 138.2 nm to 200.6 nm, 200.6 nm to 248 nm, or 248 nm to 300 nm. The grain size of the first silicon crystal grains 1121 is in any of the above ranges so that the roughness of the surface formed by the first silicon crystal grains 1121 is large. When the grain size of the first silicon crystal grains 1121 is in any of the above ranges, the stability between the first silicon crystal grains 1121 is good, and the first polysilicon doped layer 112 is less likely to deform in crystallinity. In addition, when the grain size of the first silicon crystal grains 1121 is within the above range, the stress of the first polysilicon doped layer 112 on the first dielectric layer 111 and the first passivation layer is reduced, and the film layer performance between the first polysilicon doped layer 112 and the first dielectric layer 111 and between the first polysilicon doped layer 112 and the first passivation layer can be improved.

[0052] In some embodiments, the shape of the first silicon crystal grains 1121 includes a grain shape, which has fewer grain boundaries between the grains and larger spaces between the grain boundaries compared to the block structure, so that the N-type doping element in the first polysilicon doped layer 112 can migrate through the spaces between the grain boundaries and finally be collected in the first electrode.

[0053] In some embodiments, the particulates include spherical or quasi-spherical particulates.

[0054] The shape of the first silicon crystal particle including the shape of the second silicon crystal particle described below is observed by an inspection means having a magnification such as an electric microscope or an optical microscope, and includes a scanning electron microscope (SEM) or an atomic force microscope (AFM) in which the electric microscope is a typical measurement means. FIG. 3 is a micro-morphological photograph of the first silicon crystal particle taken by a scanning electron microscope, and as can be seen from FIG. 3, the first silicon crystal particle has a particle shape that is equal in length in three dimensions. FIG. 4 is a micro-morphological photograph of the second silicon crystal particle taken by a scanning electron microscope, and as can be seen from FIG. 4, the second silicon crystal particle has a sheet shape that extends in two dimensions.

[0055] As shown in FIG. 2, the solar cell includes a second dielectric layer 121 located on a second surface and a second polysilicon doped layer 122 located on the second dielectric layer 121, the second polysilicon doped layer 122 being doped with a P-type doping element, where a surface of the second polysilicon doped layer 122 away from the second dielectric layer 121 has a second roughness, and the second roughness is smaller than the first roughness.

[0056] In some embodiments, the material of the second dielectric layer 121 includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0057] In some embodiments, the second dielectric layer 121 may include a second tunnel dielectric layer, and a passivation contact structure is formed between the second tunnel dielectric layer and the second polysilicon doped layer 122, and the second polysilicon doped layer 122 can form a band bending at the surface of the substrate 100, and the second tunnel dielectric layer can cause an asymmetric offset in the band at the surface of the substrate 100, so that the potential barrier for the majority carriers in the carriers is lower than the potential barrier for the minority carriers in the carriers. Therefore, the majority carriers can easily perform quantum tunneling through the tunnel dielectric layer, but the minority carriers have difficulty in passing through the tunnel dielectric layer, so that selective transport of carriers can be realized.

[0058] In addition, the second tunnel dielectric layer exerts a chemical passivation effect. Specifically, since there are interface state defects at the interface between the substrate 100 and the second tunnel dielectric layer, the interface state density at the back surface of the substrate 100 increases, and the increase in the interface state density promotes the recombination of photogenerated carriers, increases the backing factor, short circuit current and open circuit voltage of the solar cell, and improves the photoelectric conversion efficiency of the solar cell. By arranging the second tunnel dielectric layer so as to be located at the second surface 12 of the substrate 100, the second tunnel dielectric layer exerts a chemical passivation effect on the front surface of the substrate 100. Specifically, the dangling bonds of the substrate 100 are saturated, the defect state density of the substrate 100 is reduced, and the recombination center of the substrate 100 is reduced, thereby reducing the recombination speed of the carriers.

[0059] The second polysilicon doped layer 122 exerts a field passivation effect, specifically, it forms an electrostatic field on the surface of the substrate 100 toward the inside of the substrate 100, and causes minority carriers to escape from the interface, thereby reducing the minority carrier concentration, decreasing the carrier recombination rate at the interface of the substrate 100, increasing the open circuit voltage, short circuit current and backing factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0060] The second polysilicon doped layer 122 may be doped with the same type of doping element as the substrate 100, for example, the type of doping element of the substrate 100 is P-type.

[0061] The concentration of the doping element in the second polysilicon doped layer 122 is greater than the concentration of the doping element in the substrate 100, forming a sufficiently high potential barrier at the surface of the substrate 100 to allow majority carriers in the substrate 100 to pass through the second tunnel dielectric layer and reach the second polysilicon doped layer 122.

[0062] In some embodiments, the thickness of the second tunnel dielectric layer is 0.5 nm to 5 nm. The thickness range of the second tunnel dielectric layer is 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. If the thickness of the second tunnel dielectric layer is within any of the above ranges, the thickness of the second tunnel dielectric layer is thin, and majority carriers can easily pass through the second tunnel dielectric layer to perform quantum tunneling, but minority carriers have difficulty passing through the second tunnel dielectric layer, so that selective transport of carriers can be realized.

[0063] 2, in some embodiments, the first polysilicon doped layer 112 and the substrate 100 are doped with doping elements of different conductivity types, forming a PN junction between the first polysilicon doped layer 112 and the substrate 100, with the first polysilicon doped layer 112 serving as an emitter. In some embodiments, the second polysilicon doped layer 122 and the substrate are doped with doping elements of different conductivity types, forming a PN junction between the second polysilicon doped layer 122 and the substrate 100, with the second polysilicon doped layer 122 serving as an emitter.

[0064] FIG. 5 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, and FIG. 6 is a diagram showing a cross-sectional structure along the A1-A2 cross section of FIG.

[0065] In some embodiments, as shown in FIG. 6, the second dielectric layer 221 may include an intrinsic dielectric layer, forming a heterojunction structure between the intrinsic dielectric layer and the substrate, where the intrinsic dielectric layer can have a good passivation effect on the substrate surface, greatly avoid carrier recombination, and achieve a high minority carrier lifetime and open circuit voltage.

[0066] The material of the intrinsic dielectric layer includes intrinsic amorphous silicon, intrinsic microcrystalline silicon, intrinsic silicon oxide, intrinsic nanocrystalline silicon or intrinsic silicon carbide. The thickness of the intrinsic dielectric layer can be selected in the range of 2 μm to 10 μm, preferably 5 μm. In some cases, due to the influence of the diffusion or doping process conditions of other film layers to be manufactured later, the intrinsic dielectric layer may contain a small amount of doping element, but the intrinsic dielectric layer having a small amount of doping element is still regarded as an intrinsic type dielectric layer.

[0067] In some embodiments, the thickness range of the second polysilicon doped layer 222 is 20 nm to 500 nm, and further, the thickness range of the second polysilicon doped layer 222 is 200 nm to 400 nm. The thickness range of the second polysilicon doped layer 222 may be 20 nm to 103 nm, 103 nm to 139 nm, 139 nm to 161 nm, 161 nm to 218 nm, 218 nm to 298 nm, or 298 nm to 500 nm.

[0068] In some embodiments, as shown in FIG. 6, the solar cell further includes a transparent conductive layer 202 located on a surface of the second polysilicon doped layer 222, and a second electrode is in electrical contact with the transparent conductive layer 202.

[0069] In some embodiments, the material of the transparent conductive layer 202 may include at least one of tin-doped indium oxide (ITO), aluminum-doped zinc oxide (AZO), cerium-doped indium oxide, and tungsten-doped indium oxide.

[0070] In the solar cell shown in FIG. 6, in some embodiments, the first polysilicon doped layer 212 and the substrate 200 are doped with doping elements of different conductivity types, and a PN junction is formed between the first polysilicon doped layer 212 and the substrate 200, with the first polysilicon doped layer 212 as the emitter. In some embodiments, the second polysilicon doped layer 222 and the substrate 200 are doped with doping elements of different conductivity types, and a PN junction is formed between the second polysilicon doped layer 222 and the substrate 200, with the second polysilicon doped layer 222 as the emitter. Here, a PN junction is formed between the second polysilicon doped layer 222 and the substrate 200. An intrinsic dielectric layer is inserted between the PN junction as a buffer layer, and the intrinsic dielectric layer has a good passivation effect on the surface of the substrate 200, which can largely avoid carrier recombination and achieve a high minority carrier lifetime and open circuit voltage.

[0071] As shown in Figures 2 and 4, the second polysilicon doped layer 122 includes a plurality of second silicon crystal grains 1221, the surfaces of the plurality of second silicon crystal grains 1221 form a surface of the second polysilicon doped layer 122 having a second roughness, and the grain size of the first silicon crystal grains 1121 is smaller than the grain size of the second silicon crystal grains 1221.

[0072] In some embodiments, the "roughness" in the "first roughness and second roughness" refers to the arithmetic mean of the absolute values ​​of the vertical deviations of the peaks and valleys in a sampled length from the average horizontal line, with the average horizontal line being set at one sampled length. Roughness can be measured by a comparative method, a light section method, an interferometric method, and a probe scanning method.

[0073] In some embodiments, the grain size of the second silicon crystal grains 1221 is in the range of 100 nm to 900 nm. The grain size of the second silicon crystal grains 1221 may be 100 nm to 250 nm, 250 nm to 360 nm, 360 nm to 490 nm, 490 nm to 584 nm, 584 nm to 610 nm, 610 nm to 790 nm, or 790 nm to 900 nm. When the grain size of the second silicon crystal grains 1221 is within any of the above ranges, the grain boundaries between the second silicon crystal grains 1221 are small, and carriers can easily pass through the second polysilicon doped layer 122, thereby increasing the carrier migration speed and contributing to improving the battery efficiency.

[0074] In some embodiments, the shape of the second silicon crystal grains 1221 includes a sheet, a plate, or a grain. The micro-morphology of the second silicon crystal grains shown in FIG.

[0075] 3 and 4 are the surface morphology of the first polysilicon doped layer 112 and the surface morphology of the second polysilicon doped layer 122 at the same magnification. As can be seen from FIG. 3 and FIG. 4, the surface of the first polysilicon doped layer 112 is rougher than the surface of the second polysilicon doped layer 122, that is, the first roughness is greater than the second roughness. Thus, based on the difference in the morphology of the first polysilicon doped layer 112 and the second polysilicon doped layer 122, for the first polysilicon doped layer 112 with higher roughness, the surface of the first polysilicon doped layer 112 can enhance the internal reflection of incident light and reduce the optical loss of the solar cell. In addition, the first polysilicon doped layer 112 can increase the contact area between the first electrode and the first polysilicon doped layer 112, thus improving the contact performance and welding tensile strength of the first polysilicon doped layer 112. For the second polysilicon doped layer 122 with low roughness, the surface of the second polysilicon doped layer 122 is smooth, the uniformity of the second passivation layer deposited thereon is good, and the passivation performance of the second passivation layer is good, which can improve the recombination defect problem of the solar cell.

[0076] In some embodiments, the grain size of the first silicon crystal grains 1121 being smaller than the grain size of the second silicon crystal grains 1221 includes a radial dimension of the first silicon crystal grains 1121 being smaller than a radial dimension of the second silicon crystal grains 1221 and a height of the first silicon crystal grains 1121 being larger than a height of the second silicon crystal grains 1221. As a result, the roughness of the first polysilicon doped layer 112 formed of the first silicon crystal grains 1121 is larger than the roughness of the second polysilicon doped layer 122 formed of the second silicon crystal grains 1221.

[0077] Here, the radial one-dimensional dimension of the first silicon crystal grain 1121 refers to the average line length (or diameter) of the first silicon crystal grain 1121. The height of the first silicon crystal grain 1121 refers to the distance between the side of the first silicon crystal grain 1121 closer to the first dielectric layer 111 and the side of the first silicon crystal grain 1121 farther from the first dielectric layer 111.

[0078] Similarly, the radial one-dimensional dimension of the second silicon crystal grain 1221 refers to the average line length (or diameter) of the second silicon crystal grain 1221. The height of the second silicon crystal grain 1221 refers to the distance between the side of the second silicon crystal grain 1221 closer to the second dielectric layer 121 and the side of the second silicon crystal grain 1221 farther from the second dielectric layer 121.

[0079] In some embodiments, the shape of the first silicon crystal grains 1121 is a three-dimensionally isometric grain shape, and the height of the first silicon crystal grains 1121 is equal to the average line length of the first silicon crystal grains 1121, and the shape of the second silicon crystal grains 1221 is a two-dimensionally elongated sheet shape, and the height of the second silicon crystal grains 1221 is smaller than the average line length of the second silicon crystal grains 1221. The height of the second silicon crystal grains 1221 is the line length in the non-extending surface direction.

[0080] Here, the size of the crystal grains is called the crystal grain size. Commonly used methods of expression include the number of crystal grains per unit volume (ZV), the number of crystal grains per unit area (ZS), or the average line length or diameter of the crystal grains. The average line length of the crystal grains refers to the line length of the extension surface in the extension direction of the crystal grains. The crystal grain size in the embodiments of the present application may be the average line length of the crystal grains.

[0081] In some embodiments, the average thickness of the first polysilicon doped layer 112 is equal to or less than the average thickness of the second polysilicon doped layer 122. This allows the first polysilicon doped layer 112 located on the front side to have a small average thickness, thereby reducing the parasitic absorption of the first polysilicon doped layer 112 for the incident light irradiated to the front side, and the second polysilicon doped layer 122 located on the back side to have a large average thickness, thereby reducing the risk of the second electrode burning through the second polysilicon doped layer 122 and diffusing the P-type doping element into the substrate due to the second polysilicon doped layer 122 being too thin, and avoids the problem of the P-type doping element of the second polysilicon doped layer 122 accumulating at the substrate interface to form a "dead layer", thereby improving the carrier transport efficiency and reducing the generation of carrier recombination centers.

[0082] As shown in FIG. 2, the solar cell includes a first passivation layer 113 covering a surface of the first polysilicon doped layer 112 remote from the first dielectric layer 111, a second passivation layer 123 covering a surface of the second polysilicon doped layer 122 remote from the second dielectric layer 121, a first electrode 114 located on the first passivation layer 113 and electrically connected to the first polysilicon doped layer 112 through the first passivation layer 113, and a second electrode 124 located on the second passivation layer 123 and electrically connected to the second polysilicon doped layer 122 through the second passivation layer 123.

[0083] In some embodiments, the first passivation layer 113 may be a single layer structure or a laminated structure, and the material of the first passivation layer 113 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, aluminum oxide, etc.

[0084] In some embodiments, the second passivation layer 123 may be a single layer structure or a laminate structure, and the material of the second passivation layer 123 may be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0085] In some embodiments, the materials of the first passivation layer 113 and the second passivation layer 123 are the same, and the first passivation layer 113 and the second passivation layer 123 can be manufactured in the same process step.

[0086] In some embodiments, the pitch range between the first electrodes 114 in the first direction X is 0.5 mm to 2 mm. The pitch range between the first electrodes 114 in the first direction X is 0.5 mm to 0.8 mm, 0.8 mm to 1.15 mm, 1.15 mm to 1.28 mm, 1.28 mm to 1.46 mm, 1.46 mm to 1.68 mm, 1.68 mm to 1.84 mm, or 1.84 mm to 2 mm.

[0087] In some embodiments, the range of the width of the first electrode 114 in the first direction X is 5 μm to 50 μm. The range of the width of the first electrode 114 in the first direction X is 5 μm to 9 μm, 9 μm to 14 μm, 14 μm to 23 μm, 23 μm to 34 μm, 34 μm to 42 μm, 42 μm to 45 μm, 45 μm to 48 μm, or 48 μm to 50 μm.

[0088] In some embodiments, the first electrode 114 may be formed by sintering a burn-through paste. A method for forming the first electrode 114 includes printing a metal paste on a surface of a portion of the first passivation layer 113 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste, and the metal paste includes a highly corrosive component such as glass powder. Thus, during sintering, the corrosive component corrodes the first passivation layer 113, and the metal paste penetrates the first passivation layer 113 and electrically contacts the first polysilicon doped layer 112.

[0089] In some embodiments, the orthogonal projections of the second electrodes 124 on the second surface and the orthogonal projections of the first electrodes 114 on the second surface overlap, and the pitch between the second electrodes in the first direction X is between 0.5 mm and 2 mm. The width of the second electrodes 124 in the first direction X ranges from 5 μm to 50 μm.

[0090] In some embodiments, the second electrode 124 may be formed by sintering a burn-through paste. A method for forming the second electrode 124 includes printing a metal paste on a surface of a portion of the second passivation layer 123 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste, and the metal paste includes a highly corrosive component such as glass powder. Thus, during sintering, the corrosive component corrodes the first passivation layer 123, and the metal paste penetrates the first passivation layer 123 and electrically contacts the first polysilicon doped layer 122.

[0091] As shown in FIG. 6, the method of forming the second electrode 224 includes printing a metal paste on a surface of a portion of the second passivation layer 223 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste, and the metal paste includes a highly corrosive component such as glass powder. Thus, the corrosive component corrodes the first passivation layer 223 during sintering, and the metal paste penetrates the first passivation layer 223 to electrically contact the transparent conductive layer 202.

[0092] In some embodiments, the materials of the first electrode 114 and the second electrode 124 are the same, and the first electrode 114 and the second electrode 124 can be manufactured in the same process step.

[0093] In some embodiments, as shown in FIG. 2 , the first surface 11 of the substrate 100 includes an original texture structure 13, where the first surface 11 is a surface having a concave-convex structure, which can increase the internal reflection of incident light and improve the light utilization rate of the solar cell, thereby enhancing the photoelectric conversion efficiency of the cell.

[0094] In some embodiments, the original texture structure 13 includes a plurality of protruding structures 101, and the shape of the protruding structures may include a pyramidal shape, a parabolic shape, or an ellipsoidal shape.

[0095] In some embodiments, as shown in FIG. 2, the first surface is the front surface, and the substrate is doped with N-type doping elements, and the N-type cell has the advantages of higher conversion rate, lower temperature coefficient, higher bifacial rate, and longer carrier life than the P-type cell. The first polysilicon doped layer 112 is located on the front surface of the solar cell, and the second polysilicon doped layer 122 is located on the back surface of the solar cell, and the doping types of the second polysilicon doped layer 122 and the substrate are different, and a PN junction is formed between the substrate and the second polysilicon doped layer 122, so that the normal front contact cell can be replaced with a back contact cell to reduce the recombination efficiency of the incident light on the front surface and reduce the recombination defects of the substrate. The first roughness of the first polysilicon doped layer 112 is large, so that the unevenness degree of the front surface is large, and the incident light can be largely reflected, which can increase the internal reflectance of the solar cell and improve the photoelectric conversion efficiency of the solar cell. The second roughness of the second polysilicon doped layer 122 is small, which can improve the film layer performance of the second passivation layer deposited thereon, enhance the passivation performance of the second passivation layer, and improve the efficiency of the battery.

[0096] Regarding the substrate 200, the first passivation layer 213, the first dielectric layer 211, the first polysilicon doped layer 212, the original texture structure 23, the protrusion structure 201, the first electrode 214, the first surface 21, and the second surface 22 in Fig. 6 above, reference can be made to the descriptions of the substrate 100, the first passivation layer 113, the first dielectric layer 111, the first polysilicon doped layer 112, the original texture structure 13, the protrusion structure 101, the first electrode 114, the first surface 11, and the second surface 12 in Fig. 2. Here, the description is omitted.

[0097] In the solar cell provided in the embodiment of the present application, the solar cell includes a first polysilicon doped layer 112 and a second polysilicon doped layer 122, the first polysilicon doped layer 112 is located on a first surface, and the second polysilicon doped layer 122 is located on a second surface, and the full passivation contact cell structure is designed to reduce the cell recombination current to the maximum extent and increase the open circuit voltage of the cell. In addition, in the process of manufacturing the full passivation contact cell, there is no design of a high temperature diffusion layer, and the first polysilicon doped layer 112 and the second polysilicon doped layer 122 are used as carrier transport layers to eliminate the influence of the recombination current of the diffusion layer and improve the open circuit voltage of the cell. The first polysilicon doped layer 112 is doped with an N-type doping element, and the surface of the first polysilicon doped layer 112 has a first roughness, and the second polysilicon doped layer 122 is doped with a P-type doping element, and the surface of the second polysilicon doped layer 122 has a second roughness, and the second roughness is smaller than the first roughness. Thus, based on the difference in the morphology of the first polysilicon doped layer 112 and the second polysilicon doped layer 122, for the first polysilicon doped layer 112 with higher roughness, the surface of the first polysilicon doped layer 112 can enhance the internal reflection of incident light and reduce the optical loss of the solar cell, and the first polysilicon doped layer 112 can further increase the contact area between the first electrode and the first polysilicon doped layer 112, and improve the contact performance and welding tensile strength of the first polysilicon doped layer 112. For the second polysilicon doped layer 122 with lower roughness, the surface of the second polysilicon doped layer 122 is smooth, the uniformity of the second passivation layer deposited thereon is good, and the passivation performance of the second passivation layer is good, which can improve the recombination defect problem of the solar cell.

[0098] FIG. 7 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, FIG. 8 is a diagram showing the cross-sectional structure along the A1-A2 section of FIG. 7, FIG. 9 is a locally enlarged view of C in FIG. 8, FIG. 10 is a first type of scanning electron microscope photograph of the boundary between the electrode region and the non-electrode region in FIG. 8, and FIG. 11 is a second type of scanning electron microscope photograph of the boundary between the electrode region and the non-electrode region in FIG. 8.

[0099] In addition, some other embodiments of the present application further provide a solar cell, which is different from the above-mentioned embodiments in that the solar cell provided in some other embodiments of the present application includes an electrode region and a non-electrode region, and a first surface facing the electrode region has a first texture structure, and a first surface facing the non-electrode region has a second texture structure. Descriptions of the same parts as the above-mentioned embodiments will be omitted here.

[0100] As shown in FIG. 8, the solar cell includes a substrate 300, a first dielectric layer 311 located on the first surface 31, a first polysilicon doped layer 312 located on the first dielectric layer 311, a second dielectric layer 321 located on the second surface 32, a second polysilicon doped layer 322 located on the second dielectric layer 321, a first passivation layer 313 located on the first polysilicon doped layer 312, a second passivation layer 323 located on the second polysilicon doped layer 322, a first electrode 314, and a second electrode 324. The substrate 300 has a first surface 31 and a second surface 32 opposite to each other. The first polysilicon doped layer 312 is doped with an N-type doping element. a surface of the polysilicon doped layer 312 away from the first dielectric layer 311 has a first roughness, and the second polysilicon doped layer 322 is doped with a P-type doping element, wherein a surface of the second polysilicon doped layer 322 away from the second dielectric layer 321 has a second roughness, the second roughness being smaller than the first roughness; a first electrode 314 is located on the first passivation layer 313, the first electrode 314 penetrates the first passivation layer 313 and is in electrical contact with the first polysilicon doped layer 312; a second electrode 324 is located on the second passivation layer 323, and the second electrode 324 penetrates the second passivation layer 323 and is in electrical contact with the second polysilicon doped layer 322.

[0101] As shown in FIG. 8 or FIG. 10, the solar cell includes alternating electrode regions 2 and non-electrode regions 1, where a first dielectric layer 311 and a first polysilicon doped layer 312 are located in the electrode regions, and a first passivation layer 313 is located in the electrode regions 2 and the non-electrode regions 1.

[0102] In some embodiments, the electrode region 2 refers to a region in the substrate 300 that faces the first electrode 314 or the second electrode 324 in the thickness direction of the substrate 300, or a region where the orthogonal projection of the first electrode 314 on the substrate 300 is located, or a region where the orthogonal projection of the second electrode 324 on the substrate 300 is located. Conversely, a region in the substrate 300 where the first electrode 314 and the second electrode 324 do not face each other is the non-electrode region 1. The area of ​​the electrode region 2 is equal to or larger than the area of ​​the orthogonal projection of the first electrode 314 or the second electrode 324 on the substrate 300, thereby ensuring that the contact region of the first electrode 314 or the second electrode 324 is the electrode region 2.

[0103] In some embodiments, the width of the electrode region is 1 to 5 times the width of the first electrode, and if the width of the electrode region is too large, it will affect the integrity and uniformity of the film in the non-electrode region 1, reduce the internal reflection of light, and be detrimental to improving the carrier surface recombination rate and the photoelectric conversion efficiency of the solar cell. Here, the perpendicular bisector of the electrode region may overlap with the central axis of the first electrode or may deviate from it by ±5% to the left or right.

[0104] In some embodiments, the first surface 31 facing the electrode region 2 has a first textured structure 35, a first dielectric layer 311 covers the first textured structure 35, and the first surface 31 facing the non-electrode region 1 has a second textured structure 34, and a first passivation layer 313 further covers the second textured structure 34.

[0105] In some embodiments, the minimum distance between the first texture structure 35 and the second surface 32 is a first distance, and the minimum distance between the second texture structure 34 and the second surface 32 is a second distance, and the first distance is greater than the second distance.

[0106] Here, the minimum distance between the first texture structure and the second surface refers to the distance between the second surface and a portion of the first texture structure that is closest to the second surface 32. The minimum distance between the second texture structure and the second surface refers to the distance between the second surface and a portion of the second texture structure that is closest to the second surface 32.

[0107] In some embodiments, the difference between the first distance and the second distance is in the range of 0.5 to 10 μm. The difference between the first distance and the second distance may be 0.5 μm to 2 μm, 2 μm to 3.8 μm, 3.8 μm to 6.9 μm, 6.9 μm to 7.6 μm, 7.6 μm to 8.3 μm, or 8.3 μm to 10 μm.

[0108] In some embodiments, the first texture structure 35 includes a plurality of first protrusion structures 304 arranged at intervals, and there is no limitation on the arrangement of the plurality of first protrusion structures 304 in practical applications. Because the first dielectric layer 311 and the first polysilicon doped layer 312 are thin, the first dielectric layer 311 and the first polysilicon doped layer 312 can have the form of the first protrusion structures.

[0109] 8, the second texture structure 34 includes a plurality of second protrusion structures 303. In practical applications, the arrangement of the plurality of second protrusion structures 303 is not limited.

[0110] In some embodiments, at least one of the first texture structure 35 or the second texture structure 34 includes a platform protrusion structure or a pyramid texture structure.

[0111] In some embodiments, the solar cell includes alternating electrode and non-electrode regions, a second dielectric layer and a second polysilicon doped layer located in the electrode regions, a second passivation layer located in the electrode regions and the non-electrode regions, a second opposing surface of the electrode regions having a first textured structure, the second dielectric layer covering the first textured structure, a second opposing surface of the non-electrode regions having a second textured structure, and the second passivation layer covering the second textured structure.

[0112] In some embodiments, a minimum distance between the first texture structure and the first surface is a first distance and a minimum distance between the second texture structure and the first surface is a second distance, the first distance being greater than the second distance.

[0113] In some embodiments, as shown in Figures 9 and 10, the surface of the substrate 300 further comprises a third texture structure 36, the third texture structure 36 being interposed at the boundary between the non-electrode region 1 and the electrode region 2, and some of the third texture structures 36 include a first side 315 and a second side 325, the first side 315 facing the electrode region 2, and the first dielectric layer 311 covers the first side 315, the second side 325 facing the non-electrode region 1, and the radial length of the first side 315 is smaller than the radial length of the second side 325.

[0114] As shown in FIG. 11, the third texture structure 36 includes a plurality of third protrusion structures 305 arranged in a cross-like manner. In addition to the discrete third protrusion structures 305, the third texture structure 36 further includes a fine protrusion structure 345, so that the incident light incident on the boundary between the electrode region and the non-electrode region at different angles is more likely to be absorbed by the substrate 300 through the third protrusion structure 305 and / or the fine protrusion structure 345 by at least one reflection, and is more likely to be reflected to the non-electrode region 1 through the third protrusion structure 305 and / or the fine protrusion structure 345 by at least one reflection and absorbed by the non-electrode region 1, which contributes to increasing the absorptivity of the incident light on the first surface 31. By improving the serious carrier recombination problem in the electrode region 2 and improving the absorptivity of the incident light on the first surface 31, the photoelectric conversion efficiency of the solar cell can be improved.

[0115] In some embodiments, the third texture structures 36 include prismatic structures, pyramidal structures, or tetrahedral structures.

[0116] Hereinafter, the embodiments of the present application will be described in more detail with reference to the drawings.

[0117] In some embodiments, as shown in FIG. 11, the micro-projection structure 345 includes at least one of a prismatic structure, a second pyramidal structure, or a triangular plate structure that is inclined toward the electrode region 2 .

[0118] 11 shows an example in which the micro-protrusion structure 345 includes three structures, namely, a prismatic structure inclined toward the electrode region 2, a second pyramid structure, and a triangular plate-like structure, but in actual applications, for the third texture structure 36 in the same region, the micro-protrusion structure 345 may include only one or two of the second pyramid structure inclined toward the electrode region 2, a triangular plate-like structure, and a prismatic structure. Furthermore, the micro-protrusion structure 345 may be an irregular grain structure in addition to being one of the prismatic structure inclined toward the electrode region 2, the second pyramid structure, and a triangular plate-like structure.

[0119] 11, the one-dimensional dimension of the bottom of the micro-protrusion structure 345 includes any one of the length, width, and diagonal length of the orthogonal projection pattern on the substrate 300 of the bottom of the micro-protrusion structure 345. Also, in FIG. 10, the orthogonal projection pattern on the substrate 300 of the bottom of the micro-protrusion structure 345 is taken as an example to be a regular rectangle. In this case, the one-dimensional dimension of the bottom of the micro-protrusion structure 345 is any one of the length, width, and diagonal length of the regular rectangle.

[0120] In practical applications, the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 may be an irregular polygon. In this case, the length, width or diagonal length of the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 is not absolute, but is an artificially defined one-dimensional dimension to represent the bottom of the micro-protrusion structure 345. For example, if the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 is an irregular rectangle, the length of the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 is defined as the length of the longest side of the irregular rectangle, the width of the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 is defined as the length of the shortest side of the irregular rectangle, and the diagonal length of the orthogonal projection pattern on the substrate 300 at the bottom of the micro-protrusion structure 345 is defined as the length of the longest diagonal of the irregular rectangle, but it can be understood that the above is only an example and can be flexibly defined according to actual needs.

[0121] In addition, the orthogonal projection pattern of the bottom of the micro-protrusion structure 345 on the substrate 300 may be an irregular rectangle, other irregular polygon, circle, or irregular shape close to circle. In this case, the one-dimensional dimension of the bottom of the micro-protrusion structure 345 can be obtained by selecting a number of different specific area regions on the bottom of the micro-protrusion structure 345, the specific area regions can be flexibly defined according to actual needs, and calculating the average value of the length, width, diagonal, or diameter of the different specific area regions.

[0122] As shown in FIG. 11, the orthogonal projection pattern of the bottom of the third protrusion structure 305 on the substrate 300 is generally a regular rectangle. In this case, the one-dimensional dimension of the bottom of the third protrusion structure 305 is either the length, width or diagonal length of the regular rectangle. In practical applications, the orthogonal projection pattern of the bottom of the third protrusion structure 305 on the substrate 300 may be an irregular rectangle. In this case, the definition of the one-dimensional dimension is similar to that of the orthogonal projection pattern of the bottom of the micro-protrusion structure 345 on the substrate 300 when the pattern is an irregular rectangle, so the description will be omitted here.

[0123] In addition, the one-dimensional dimension of the bottom of the different third protrusion structures 305 may be different or the same, but the one-dimensional dimension of the bottom of the third protrusion structure 305 is within a certain numerical range. The one-dimensional dimension of the bottom of the different micro-protrusion structures 345 may be different or the same, but the one-dimensional dimension of the bottom of the third protrusion structure 305 is also within a certain numerical range. The one-dimensional dimension of the bottom of the micro-protrusion structure 345 being smaller than the one-dimensional dimension of the bottom of the third protrusion structure 305 means that the average value of the one-dimensional dimension of the bottom of the multiple micro-protrusion structures 345 is smaller than the average value of the one-dimensional dimension of the bottom of the multiple third protrusion structures 305.

[0124] The specific features of the prismatic structure will be described in detail below.

[0125] In some embodiments, as shown in Fig. 11, the prismatic structures are located on the side of the third protrusion structure 305. There are two ways in which the prismatic structures are arranged on the side of the third protrusion structure 305: one prismatic structure is located on the side of one third protrusion structure 305; and multiple prismatic structures are attached to the same side of one third protrusion structure 305, and each prismatic structure is in contact with and connected to the side.

[0126] 11, some prismatic structures are located in some regions close to the electrode region 2 at the boundary. For example, the prismatic structures are located between the third protruding structure 305 and the electrode region 2.

[0127] In some other embodiments, the multiple prismatic structures are sequentially arranged along a direction away from the side surface of the third protrusion structure 305. For example, among the multiple prismatic structures, only the prismatic structure closest to the side surface of the third protrusion structure 305 is in contact with and connected to the side surface of the third protrusion structure 305.

[0128] In addition, the multiple prismatic structures located on the same boundary are at least one of the three embodiments described above, that is, the multiple prismatic structures located on the same boundary may each have the characteristics of the prismatic structures in the three embodiments described above, or may have the characteristics of the prismatic structures in any two of the embodiments described above, or may have the characteristics of the prismatic structures in any one of the embodiments described above.

[0129] The specific features of the second pyramid structure are explained in detail below.

[0130] In some embodiments, the base of the second pyramid structure is in contact with and connected to the base of the third protruding structure 305. In some cases, multiple second pyramid structures can be surrounded around the base of the same third protruding structure 305, with the bases of each second pyramid structure in contact with and connected to the base of the third protruding structure 305.

[0131] In some other embodiments, at least one second pyramid structure is located between two adjacent third protrusion structures 305. In other words, the bottom of the second pyramid structure is not in contact with and connected to the bottom of the third protrusion structure 305.

[0132] In addition, the second pyramid structure located on the same boundary is at least one of the second pyramid structures of the two embodiments described above, i.e., the multiple second pyramid structures located on the same boundary may each have the characteristics of the second pyramid structure in the two embodiments described above, or may have the characteristics of the second pyramid structure in any one of the embodiments described above.

[0133] Specific features of the triangular plate structure will be described in detail below.

[0134] In some cases, one triangular plate structure is located on a side of one third protrusion structure 305. In some cases, multiple triangular plate structures are attached to the same side of one third protrusion structure 305, and each triangular plate structure is in contact with and connected to the side.

[0135] In some other embodiments, a plurality of triangular plate structures are sequentially arranged along a direction away from the side surface of the third protrusion structure 305. For example, among the plurality of triangular plate structures, only the triangular plate structure closest to the side surface of the third protrusion structure 305 is in contact with and connected to the side surface of the third protrusion structure 305.

[0136] In addition, the triangular plate-like structures located on the same boundary are at least one of the triangular plate-like structures of the two embodiments described above, i.e., multiple triangular plate-like structures located on the same boundary may each have the characteristics of the triangular plate-like structures in the two embodiments described above, or may have the characteristics of the triangular plate-like structures in any one of the embodiments described above.

[0137] In some embodiments, the third protruding structures 305 are located in some areas closer to the boundary than the non-electrode regions 1. In other words, there are more representative third protruding structures 305 in some areas closer to the boundary than the non-electrode regions 1.

[0138] As described above with respect to the third texture structure 36 at the boundary in each of the embodiments, there is a variety in the structure of the third texture structure 36. In some cases, the same boundary may have a plurality of fine-protrusion structures 345 in addition to the third protrusion structure 305, and the specific features of the plurality of fine-protrusion structures 345 at different boundaries may be different, for example, one of two adjacent boundaries may have a prismatic structure inclined toward the electrode region 2 and a second pyramid structure, and the other may have a second pyramid structure and a triangular plate structure.

[0139] 10, the third texture structure further includes a first prismatic structure 335, and along the inclination direction of the first prismatic structure 335, a first length of the third protrusion structure 305 is longer than a second length of the first prismatic structure 335, and at least a part of the first prismatic structure 335 is located on a side of the third protrusion structure 305 away from the electrode region 2. This contributes to further increasing the probability that the incident light incident on the boundary is absorbed by the boundary or the non-electrode region 1.

[0140] 10, the first length of the third protrusion structure 305 is defined as the inclination length of the shortest third protrusion structure 305 among the plurality of third protrusion structures 305, and the second length of the first prismatic structure 335 is defined as the inclination length of the longest first prismatic structure 335 among the plurality of first prismatic structures 335. Based on this, the first length of the third protrusion structure 305 being longer than the second length of the first prismatic structure 335 means that the inclination length of the shortest third protrusion structure 305 among the plurality of third protrusion structures 305 is longer than the inclination length of the longest first prismatic structure 335 among the plurality of first prismatic structures 335.

[0141] In practical application, the first length of the third protrusion structure 305 may be defined as the average value of the inclination lengths of the plurality of third protrusion structures 305, and the second length of the first prismatic structure 335 may be defined as the average value of the inclination lengths of the plurality of first prismatic structures 335. On this basis, the first length of the third protrusion structure 305 being greater than the second length of the first prismatic structure 335 refers to the average value of the inclination lengths of the plurality of third protrusion structures 305 being greater than the average value of the inclination lengths of the plurality of first prismatic structures 335.

[0142] In some embodiments, as shown in FIG. 10 , the arrangement manner of the second rectangular prism structures 335 on the side of the third protrusion structure 305 away from the electrode region 2 includes two situations: one second rectangular prism structure 335 is located on the side of one third protrusion structure 305 away from the electrode region 2, and multiple first rectangular prism structures 335 are located on the side of the same second rectangular prism structure 335 away from the electrode region 2, and each first rectangular prism structure 335 is in contact with and connected to the side.

[0143] 10, a plurality of first prismatic structures 335 are sequentially arranged along a direction away from the side surface of the third protrusion structure 305. For example, among the plurality of first prismatic structures 335, only the first prismatic structure 335 closest to the side surface of the third protrusion structure 305 is in contact with and connected to the side surface of the third protrusion structure 305.

[0144] In some embodiments, as shown in FIG. 10, the third texture structure 36 may include first pyramid structures, with at least some of the first pyramid structures located in some areas of the boundary.

[0145] Here, the one-dimensional dimension of the bottom of the third protrusion structure is larger than the one-dimensional dimension of the bottom of the first protrusion structure, and the one-dimensional dimension of the bottom of the first protrusion structure is larger than the one-dimensional dimension of the bottom of the second protrusion structure.

[0146] Note that the one-dimensional dimensions of the bottom of the first protrusion structure and the one-dimensional dimensions of the bottom of the second protrusion structure are both similar to the definition of the one-dimensional dimensions of the bottom of the third protrusion structure in one embodiment of the present application, so we will not explain them here.

[0147] In addition, the one-dimensional dimensions of the bottoms of the different first protrusion structures may be different or the same, but the one-dimensional dimensions of the bottoms of the first protrusion structures are within a numerical range. The one-dimensional dimensions of the bottoms of the different second protrusion structures may be different or the same, but the one-dimensional dimensions of the bottoms of the second protrusion structures are also within a numerical range. Based on this, the one-dimensional dimensions of the bottoms of the third protrusion structure being larger than the one-dimensional dimensions of the bottoms of the first protrusion structures means that the average value of the one-dimensional dimensions of the bottoms of the third protrusion structures is larger than the average value of the one-dimensional dimensions of the bottoms of the first protrusion structures. The one-dimensional dimensions of the bottoms of the first protrusion structures being larger than the one-dimensional dimensions of the bottoms of the second protrusion structures means that the average value of the one-dimensional dimensions of the bottoms of the first protrusion structures having a first polysilicon doped layer on the surface is larger than the average value of the one-dimensional dimensions of the bottoms of the second protrusion structures located in the non-electrode region 1.

[0148] Furthermore, in one embodiment of the present application, there are no limitations on the relationship in size between the one-dimensional dimension of the bottom of the second protrusion structure and the one-dimensional dimension of the bottom of the first protrusion structure, nor are there any limitations on the relationship in size between the one-dimensional dimension of the bottom of the second protrusion structure and the one-dimensional dimension of the bottom of the second protrusion structure.

[0149] FIG. 12 is a diagram showing the structure of a photovoltaic module provided in another embodiment of the present application, and FIG. 13 is a diagram showing a cross-sectional structure along the M1-M2 cross section of FIG.

[0150] Correspondingly, according to some embodiments of the present application, some other embodiments of the present application provide a photovoltaic module that can include the solar cell of the above-mentioned embodiment. The same parts as those of the above-mentioned embodiment will not be described here.

[0151] As shown in FIG. 12, the photovoltaic module includes a cell string in which solar cells 40 in any of the above-mentioned embodiments are connected by connecting members 406, a sealing layer 47 for covering a surface of the cell string, and a cover plate 48 for covering a surface of the sealing layer 47 remote from the cell string.

[0152] Specifically, in some embodiments, the battery cells are electrically connected by a connection member 406, and the connection member 406 and the main grid 405 of the battery cell can be welded. FIG. 12 shows only the positional relationship between one solar cell, that is, the arrangement direction of the electrodes with the same polarity of the battery cells is the same, or the electrodes with positive polarity of each battery cell are arranged toward the same side, so that the connection member connects the different sides of two adjacent battery cells, respectively. In some embodiments, the battery cells may have electrodes with different polarities facing the same side, that is, when the electrodes of the adjacent battery cells are arranged in the order of the first polarity, the second polarity, and the first polarity, respectively, the connection member connects the two adjacent battery cells on the same side.

[0153] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap.

[0154] In some embodiments, a weld is formed between the connection member and a sub-grid in the battery cell, and the sub-grid includes a first electrode 414 and a second electrode 424 .

[0155] In some embodiments, the encapsulation layer includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covering one of the front side or the back side of the solar cell, and the second encapsulation layer covering the other of the front side or the back side of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer may be an organic encapsulation film, such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0156] Before the lamination process, there is a boundary between the first sealing layer and the second sealing layer, and after the lamination process, when the photovoltaic module is formed, the concept of the first sealing layer and the second sealing layer no longer exists; in other words, the first sealing layer and the second sealing layer are integrated to form sealing layer 47.

[0157] In some embodiments, the cover plate 48 may be a cover plate with a light-transmitting function, such as a glass cover plate, a plastic cover plate, etc. Specifically, the surface of the cover plate 48 facing the encapsulation layer 47 may be an uneven surface, which can increase the utilization rate of the incident light. The cover plate 48 includes a first cover plate and a second cover plate, where the first cover plate faces the first encapsulation layer and the second cover plate faces the second encapsulation layer. Alternatively, the first cover plate faces one side of the solar cell, and the second cover plate faces the other side of the solar cell.

[0158] Accordingly, based on several embodiments of the present application, one embodiment of the present application further provides a solar cell manufacturing method for manufacturing the solar cell provided in the above-mentioned embodiments, and the same or corresponding technical features as those of the above-mentioned embodiments will not be described here.

[0159] Here, the method for manufacturing a solar cell shown in FIG. 8 is taken as an example.

[0160] The manufacturing method includes providing a substrate and performing a polishing process on both sides of the substrate placed opposite each other, where the polishing process is used to reduce surface defects of the substrate.

[0161] In some embodiments, the substrate includes spaced apart electrode and non-electrode regions.

[0162] The method includes performing a texture forming process on one side of the substrate such that the substrate forms an original texture structure on the one side. The texture forming process includes chemical etching, for example, washing the substrate with a mixed solution of potassium hydroxide and hydrogen peroxide solution, and specifically, controlling the concentration ratio of the potassium hydroxide and hydrogen peroxide solutions to form the original texture structure having a desired morphology. In some embodiments, the original texture structure can be formed by a method such as laser etching, mechanical method, or plasma etching. In laser etching, the parameters of the laser process can be controlled to obtain the original texture structure having a desired morphology.

[0163] The manufacturing method includes sequentially forming a first passivation film and a first doped conductive film on a surface of a substrate, where the first passivation film covers the original texture structure, and the first doped conductive film covers a surface of the first passivation film.

[0164] The method includes sequentially forming a second dielectric layer and a second doped conductive film on the other side of the substrate.

[0165] In some embodiments, the first doped conductive film and the second doped conductive film may be crystallized simultaneously, in which a surface of the first doped conductive film remote from the first passivation film has a first roughness and a surface of the second doped conductive film remote from the second passivation film has a second roughness, and the crystallized second doped conductive film is a second polysilicon doped layer.

[0166] In some embodiments, the crystallization process includes an annealing process or laser activation.

[0167] The manufacturing method includes performing a shaping process on the first passivation film, the first doped conductive film and the substrate in the non-electrode region, where the shaping process is used to remove the first passivation film and the first doped conductive film in the non-electrode region, where the remaining first passivation film is a first dielectric layer and the remaining first doped conductive film is a first polysilicon doped layer.

[0168] In some embodiments, the method further includes forming a mask layer on the surface of the first doped conductive film in the electrode region before performing the shaping process, so as to reduce etching damage to the first polysilicon doped layer caused by the shaping process. The material of the mask layer includes organic wax, metal, or silicon dioxide mask. The mask layer is formed using a printing process.

[0169] In some embodiments, after forming the first polysilicon doped layer, the mask layer can be removed by an etching process, which can be one of a dry etching process, a wet etching process, or a laser etching process.

[0170] In some embodiments, during the shaping process, the original texture structure located in the non-electrode area is converted into a second texture structure, the original texture structure located in the boundary between the non-electrode area and the electrode area is converted into a third texture structure, and the original texture structure located in the electrode area is the first texture structure.

[0171] In some embodiments, the shaping process includes a wet etching process or a laser etching process. The process parameters for the wet etching process include a reaction solution including an acid solution and a reaction time of 50-550 s.

[0172] In some embodiments, the wet etching process includes the steps of: (1) using a mixed acid solution containing HF, HNO3, and H2SO4, with mass concentrations of 10-25%, 5-10%, and 2-4%, respectively, to pattern and act on the surface of the non-metallic region using a screen printing method, with an acting volume of 0.05-0.8 mL / cm2 The duration of the reaction is 50 to 550 s, and (2) after the reaction, the solution is washed twice with alternating deionized water / low-concentration alkaline solution (0.5 to 1% NaOH) / low-concentration HCl (2.5 to 3.5%).

[0173] The method includes forming a first passivation layer overlying a surface of the substrate in a non-electrode region and a surface of the first polysilicon doped layer.

[0174] The manufacturing method includes forming electrodes arranged sequentially along a first direction, each electrode located in an electrode region, the electrode burn-through the first passivation layer to make electrical contact with the first polysilicon doped layer.

[0175] In some embodiments, a method of manufacturing includes forming a first passivation layer covering a surface of the first polysilicon doped layer remote from the first dielectric layer and a second passivation layer covering a surface of the second polysilicon doped layer remote from the second dielectric layer, and forming a first electrode located in the first passivation layer and penetrating the first passivation layer in electrical contact with the first polysilicon doped layer, and a second electrode located in the second passivation layer and penetrating the second passivation layer in electrical contact with the second polysilicon doped layer.

[0176] Although the present application has been disclosed as above in the preferred embodiment, it does not limit the scope of the claims, and since a person skilled in the art can make some possible variations and modifications without departing from the idea of ​​the present application, the scope of protection of the present application should be in accordance with the scope defined by the claims of the present application. In addition, the examples and drawings of the present specification are merely examples, and do not cover the entire scope of protection provided by the claims of the present application.

[0177] Those skilled in the art will understand that the above embodiments are specific examples for implementing the present application, but various changes in form and details are possible in practice without departing from the spirit and scope of the present application. Since any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, the scope of protection of the present application should be based on the scope limited by the claims.

Claims

1. a substrate having a first surface and a second surface disposed opposite to each other; a first dielectric layer overlying the first surface and a first polysilicon doped layer overlying the first dielectric layer; a second dielectric layer located on the second surface and a second polysilicon doped layer located on the second dielectric layer; a first passivation layer overlying the first polysilicon doped layer and a second passivation layer overlying the second polysilicon doped layer; a first electrode and a second electrode, the first polysilicon doped layer is doped with an N-type doping element, and a surface of the first polysilicon doped layer remote from the first dielectric layer has a first roughness; the second polysilicon doped layer is doped with a P-type doping element, wherein a surface of the second polysilicon doped layer remote from the second dielectric layer has a second roughness, the second roughness being smaller than the first roughness; the first electrode is electrically connected to the first polysilicon doped layer through the first passivation layer, and the second electrode is electrically connected to the second polysilicon doped layer through the second passivation layer; The solar cell includes alternating electrode and non-electrode regions, the first dielectric layer and the first polysilicon doped layer being located in the electrode regions, the first passivation layer being located in the electrode regions and the non-electrode regions, the first surface opposite the electrode regions having a first textured structure, the first dielectric layer covering the first textured structure, the first surface opposite the non-electrode regions having a second textured structure, and the first passivation layer further covering the second textured structure; a minimum distance between the first texture structure and the second surface is a first distance, a minimum distance between the second texture structure and the second surface is a second distance, the first distance being greater than the second distance; the first surface of the substrate further comprises a third texture structure, the third texture structure being interposed at a boundary between the non-electrode region and the electrode region, a portion of the third texture structure including a first side and a second side, the first side facing the electrode region, the first dielectric layer covering the first side, the second side facing the non-electrode region, and a radial length of the first side being smaller than a radial length of the second side; A solar cell characterized by:

2. the first polysilicon doped layer includes a plurality of first silicon crystal grains, the surfaces of the plurality of first silicon crystal grains constitute a surface of the first polysilicon doped layer having the first roughness; the second polysilicon doped layer includes a plurality of second silicon crystal grains, the surfaces of the plurality of second silicon crystal grains constitute a surface of the second polysilicon doped layer having the second roughness; and the grain size of the first silicon crystal grains is smaller than the grain size of the second silicon crystal grains; The solar cell according to claim 1 .

3. The range of the grain size of the first silicon crystal grains includes 10 nm to 300 nm; The solar cell according to claim 2 .

4. The range of the crystal grain size of the second silicon crystal grains includes 100 nm to 900 nm; The solar cell according to claim 2 .

5. The shape of the first silicon crystal grains includes spherical grains or quasi-spherical grains. The solar cell according to claim 2 .

6. The shape of the second silicon crystal grains includes a sheet shape or a particle shape. The solar cell according to claim 2 .

7. a radial one-dimensional dimension of the first silicon crystal grain is smaller than a radial one-dimensional dimension of the second silicon crystal grain, and a height of the first silicon crystal grain is larger than a height of the second silicon crystal grain; The solar cell according to claim 2 .

8. The difference between the first distance and the second distance is in the range of 0.5 to 10 μm. The solar cell according to claim 1 .

9. The third texture structure includes a prism structure, a pyramid structure, or a tetrahedron structure. The solar cell according to claim 1 .

10. At least one of the first texture structure or the second texture structure comprises a pyramidal texture structure. The solar cell according to claim 1 .

11. the first surface is a front surface, and the substrate is doped with an N-type doping element; The solar cell according to claim 1 .

12. the average thickness of the first polysilicon doped layer is less than or equal to the average thickness of the second polysilicon doped layer; 2. The solar cell according to claim 1 ,

13. A material of at least one of the first dielectric layer or the second dielectric layer includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide; The solar cell according to claim 1 .

14. A cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 13 with a connecting member; a sealing layer for covering a surface of the cell string; a cover plate for covering a surface of the sealing layer remote from the cell string. A photovoltaic module comprising:

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