How synapse circuits work

Abstract

Provided is a driving method of a simplified synapse circuit. When a first pre-spike pulse precedes a first post-spike pulse, a second pre-spike pulse from an input circuit 20a is used as a time window in which writing of a connection weight is permitted, and the first post-spike pulse from a neuron circuit 17 is used as a writing pulse of a writing timing control for the connection weight. When the first post-spike pulse precedes the first pre-spike pulse, a second post-spike pulse from the neuron circuit 17 is used as a time window, and the first pre-spike pulse from the input circuit 20a is used as a writing pulse. The second pre-spike pulse and the second post-spike pulse are respectively synchronized with the first pre-spike pulse and the first post-spike pulse to be output.

Description

[Technical field]

[0001] The present invention relates to a method for driving a synapse circuit. [Background technology]

[0002] A neural network that processes information on a computer by modeling the mechanism of a biological brain is known. In addition, research on the constituent elements and circuits of a neural network is being conducted in order to realize the neural network using semiconductor elements and the like. Various models of neural network circuit devices have been proposed. For example, in one model, neurons are connected to each other via a synapse circuit, and the synapse circuit has a synapse connection weight that represents the strength of the connection. When the integrated value of the voltage of a pulse input from another neuron to one neuron and the connection weight reaches a predetermined threshold, the neuron fires and transmits a pulse to the next neuron.

[0003] In neural networks, when storing synaptic connection weights in synapse circuits, learning is performed based on a synapse model that has, for example, Spike Timing Dependent Synaptic Plasticity (hereinafter referred to as STDP). In STDP, synaptic connection weights based on the time difference between a pulse from a pre-neuron circuit connected in the front stage of the synapse circuit and a pulse from a post-neuron circuit connected in the rear stage are stored in the synapse circuit.

[0004] On the other hand, as a nonvolatile memory element, for example, a resistive random access memory (ReRAM) having a resistance change type memory element whose electric resistance changes due to a giant electric field induced resistance change, a phase change random access memory, etc. are known. A neural network circuit device that stores synaptic connection weights in such a nonvolatile memory element is known (for example, see Non-Patent Documents 1 to 3). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] GW Burr, P. Narayanan, RM Shelby, S. Sidler, I. Boybat, C. di Nolfo, and Y. Leblebici, IEDM, pp. 4.4.1-4.4.4, 2015. [Non-Patent Document 2] M. Chu; B. Kim; S. Park; H. Hwang; M. Jeon; B.-H. Lee; B.-G. Lee, IEEE Trans. IE, Vol. 62, Issue 4, pp. 2410-2419, 2015. [Non-Patent Document 3] SP Adhikari; H. Kim; RK Budhathoki; C. Yang; LO Chua, IEEE Trans. CAS, Vol. 62, Issue 1, pp. 215-223, 2015. Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, when learning based on STDP, it is necessary to write the synaptic connection weights of the synapse circuit according to the lead-in and lead-out time of each pulse, but this requires complex control, which leads to problems such as increased power consumption and large-scale circuits. For this reason, a simplified driving method for storing synaptic connection weights is desired.

[0007] The present invention has been made in consideration of the above circumstances, and has an object to provide a simplified method for driving a synapse circuit. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention provides a method for driving a synapse circuit, which has a weight memory section for storing either a first connection weight or a second connection weight as a synaptic connection weight, connected between a pre-neuron circuit and a post-neuron circuit, and outputs a weighted pre-spike pulse obtained by weighting a pre-spike pulse input from the pre-neuron circuit with the synaptic connection weight to the post-neuron circuit, and writes the synaptic connection weight based on the lead time and pulse time difference between the pre-spike pulse and the post-spike pulse output from the post-neuron circuit, comprising: inputting a first time window pulse from either the pre-neuron circuit or the post-neuron circuit to the synapse circuit, the first time window pulse defining a first time window for allowing the writing of the synaptic connection weight to the weight memory section when the pre-spike pulse precedes the post-spike pulse; A first write pulse having a pulse width shorter than the first time window pulse, which is a timing for writing the synaptic connection weight to the weight memory unit, is input to the synapse circuit, a second time window pulse defining a second time window for allowing the writing of the synaptic connection weight to the weight memory unit when the post-spike pulse precedes the pre-spike pulse is input to the synapse circuit from either the pre-neuron circuit or the post-neuron circuit, and a second write pulse having a pulse width shorter than the second time window pulse, which is a timing for writing the synaptic connection weight to the weight memory unit, is input to the synapse circuit from the other circuit, and the weight memory unit performs a write operation when the first time window pulse and the first write pulse are input to the synapse circuit simultaneously and when the second time window pulse and the second write pulse are input to the synapse circuit simultaneously. Effect of the Invention

[0009] According to the present invention, for each of the cases where a postspike pulse precedes a prespike pulse and where a prespike pulse precedes a postspike pulse, a time window pulse permitting writing of a synaptic connection weight is input to the synapse circuit from either the pre-neuron circuit or the post-neuron circuit, and a short write pulse serving as the write timing of the synaptic connection weight is input to the synapse circuit from the other circuit, so that the weight memory section performs a write operation when these are input to the synapse circuit simultaneously, thereby simplifying the drive for storing synaptic connection weights based on STDP. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an outline of a neural network circuit device according to a first embodiment. [Diagram 2] 13 is a graph showing the relationship between the pulse time difference ΔT between the first post-spike pulse and the first pre-spike pulse and the coupling weight. [Diagram 3] FIG. 2 is a circuit diagram showing a configuration of a synapse circuit. [Figure 4] FIG. 2 is a block diagram showing an example of a configuration of a main part of a main body of a neuron circuit. [Diagram 5] 4 is a timing chart showing various signals in a recognition mode. [Figure 6] 13 is a timing chart showing various signals in the learning mode when a first pre-spike pulse precedes. [Figure 7] 13 is a timing chart showing various signals in the learning mode when preceded by a first post-spike pulse. [Figure 8] FIG. 11 is a block diagram showing an outline of a neural network circuit device according to a second embodiment. [Figure 9] FIG. 11 is a circuit diagram showing a configuration of a synapse circuit according to a second embodiment. [Figure 10] 13 is a timing chart showing various signals in a learning mode in the case where a first pre-spike pulse precedes in the second embodiment. [Figure 11] 13 is a timing chart showing various signals in a learning mode in the case where a first post-spike pulse precedes in the second embodiment. [Figure 12] 13 is a timing chart showing various signals in a learning mode in the case where a first pre-spike pulse precedes in the third embodiment. [Figure 13] 13 is a timing chart showing various signals in a learning mode in the case where a first post-spike pulse precedes in the third embodiment. [Figure 14] FIG. 13 is a block diagram showing a configuration of a main part of a fourth embodiment in which a synapse circuit is composed of a plurality of weight storage units. [Figure 15] 13 is a timing chart showing various signals in a learning mode in the fourth embodiment. [Figure 16] FIG. 11 is a circuit diagram showing an example of a load memory unit using one MTJ element. [Figure 17] FIG. 11 is a circuit diagram showing an example of a load memory unit using a three-terminal MTJ element. [Figure 18] FIG. 13 is a circuit diagram showing an example in which a load memory unit has an SRAM configuration. [Figure 19] FIG. 13 is a circuit diagram showing another example in which the load memory unit has an SRAM configuration. [Figure 20] FIG. 11 is a circuit diagram showing an example of outputting a current signal as a weighted pre-spike pulse. [Figure 21] FIG. 11 is a circuit diagram showing an example in which a weight memory unit to which a selection signal is input outputs a current signal as a weighted pre-spike pulse. [Figure 22] FIG. 11 is a circuit diagram showing an example in which a weight memory unit using one MTJ element outputs a current signal as a weighted pre-spike pulse. [Figure 23] FIG. 11 is a circuit diagram showing an example in which a weight memory unit using a three-terminal MTJ element outputs a current signal as a weighted pre-spike pulse. [Figure 24] FIG. 11 is a circuit diagram showing an example in which a weight storage unit having an SRAM configuration outputs a current signal as a weighted pre-spike pulse. [Diagram 25]FIG. 11 is a circuit diagram showing another example in which a weight storage unit having an SRAM configuration outputs a current signal as a weighted pre-spike pulse. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [First embodiment] In Fig. 1, a neural network circuit device 10 according to the first embodiment has a plurality of synapse circuits 11 arranged in a matrix. Each synapse circuit 11 has a weight storage section 14 and a selection section 15. A plurality of neuron circuits 17 are provided in the neural network circuit device 10, and a plurality of synapse circuits 11 are provided corresponding to each neuron circuit 17. In this example, a neuron circuit 17 is provided at the end of each column 16 of the synapse circuits 11 in the column direction (the vertical direction in Fig. 1), and one column of synapse circuits 11 corresponds to one neuron circuit 17. The neuron circuit 17 has a main body section 18 and a bit line driver 19.

[0012] Corresponding to each column 16 of the synapse circuits 11, bit lines BL, BLB, a first post-spike line POLa, and a second post-spike line POLb are respectively extended in the column direction. The bit lines BL and BLB are connected to each weight memory unit 14 and a bit line driver 19 in the corresponding column 16. The first post-spike line POLa and the second post-spike line POLb are connected to each selection unit 15 and a main unit 18 in the corresponding column 16. An output line OL is provided for each weight memory unit 14, and each weight memory unit 14 is connected to the main unit 18 of the neuron circuit 17 in the column 16 in which it is arranged by the output line OL.

[0013] Corresponding to each row of the synapse circuit 11, a power line PL for supplying a power supply voltage to the weight memory unit 14, a grounded source line SL, a pre-spike line PrL, and a word line WL are respectively extended in the row direction (left and right direction in the figure). The power line PL, the source line SL, and the pre-spike line PrL are respectively connected to each weight memory unit 14 in the corresponding row. The pre-spike line PrL and the word line WL are respectively connected to each selection unit 15 in the corresponding row. The voltage supplied from the power line PL is about half the magnitude (=|ΔVB| / 2) of the bit line potential difference ΔVB generated between the bit line BL and the bit line BLB, as described later. The front stage 20 is provided with an input circuit 20a for each row. The pre-spike line PrL of each row is connected to the input circuit 20a via an inverter 20b, and the word line WL is directly connected to the input circuit 20a.

[0014] The neural network circuit device 10 refers to a model of synapses having spike timing dependent synaptic plasticity (hereinafter referred to as STDP). The input circuit 20a in the neural network circuit device 10 is provided as a pre-neuron circuit and corresponds to a pre-neuron. The neuron circuit 17 is provided as a post-neuron circuit and corresponds to a post-neuron. The input circuit 20a outputs a first pre-spike pulse as a pre-spike pulse, and the neuron circuit 17 outputs a first post-spike pulse as a post-spike pulse. The first pre-spike pulse is output at a timing corresponding to the firing timing of the pre-neuron, and the first post-spike pulse is output at a timing corresponding to the firing timing of the post-neuron. The synapse circuits 11 correspond to synapses that synapse-connect a pre-neuron and a post-neuron, and store synaptic connection weights (hereinafter simply referred to as connection weights).

[0015] The STDP has a property that, when focusing on one synapse, the connection weight with the synapse located between the pre-neuron and the post-neuron changes depending on the timing when the pre-neuron and the post-neuron connected before and after the synapse fire and output a spike pulse. In the neural network circuit device 10, when the first pre-spike pulse precedes the first post-spike pulse and when the pulse time difference ΔT between the first post-spike pulse and the first pre-spike pulse is within a preset specified time Tw, the connection weight of the synapse circuit 11 is updated. In this example, the synapse circuit 11 stores the first connection weight as the connection weight when the former of the first pre-spike pulse and the first post-spike pulse precedes, and stores the second connection weight as the connection weight when the latter precedes.

[0016] In the following explanation, the pulse time difference ΔT is defined as the magnitude of the time difference between the first postspike pulse and the first prespike pulse, but when distinguishing between positive and negative, it is defined as positive when the first prespike pulse precedes the first postspike pulse, and negative when the first postspike pulse precedes the first prespike pulse.

[0017] In this example, the weight of the first connection weight is relatively large and the weight of the second connection weight is relatively small. That is, as shown in Fig. 2, the connection weight of the synapse circuit 11 becomes a large first connection weight when the first pre-spike pulse is input to the synapse circuit 11 within a period of time Tw counting back from the time when the first post-spike pulse is output from the neuron circuit 17 connected to the synapse circuit 11, and becomes a small second connection weight when the first pre-spike pulse is input to the synapse circuit 11 within a period of time Tw from the time when the first post-spike pulse is output. Therefore, in this example, when updating the connection weight, it is different from the general symmetric STDP and asymmetric STDP in which the connection weight is gradually increased or decreased by increasing the pulse time difference ΔT.

[0018] The neural network circuit device 10 has a recognition mode and a learning mode. The recognition mode is a mode in which a signal corresponding to an image to be processed, such as image recognition, is input from the front-stage unit 20 to the neural network circuit device 10, and an output from each neuron circuit 17 is obtained as a processing result corresponding to the result of image recognition, and the connection weights stored in each synapse circuit 11 are used in the learning mode. The learning mode is an operation mode in which a signal based on a previously prepared image is input from the front-stage unit 20 to the neural network circuit device 10, and the connection weights stored in each synapse circuit 11 are updated.

[0019] The input circuit 20a of the front-stage section 20 has a pulse generator that generates a first prespike pulse and a second prespike pulse synchronized with the first prespike pulse, and outputs the first prespike pulse to the prespike line PrL and the second prespike pulse to the word line WL. In this example, the first prespike pulse in the synapse circuit 11 is active low, and the first prespike pulse from the input circuit 20a is output to the prespike line PrL via an inverter 20b. The first prespike pulse is output in both the recognition mode and the learning mode, but the second prespike pulse is output only in the learning mode.

[0020] In the learning mode, the first prespike pulse also functions as a second write pulse used to control the write timing of the coupling weight when the first postspike pulse precedes the first prespike pulse. The pulse width of this first prespike pulse is shorter than that of the second prespike pulse. As will be described later, in a configuration in which the weights are stored in the weight memory unit 14 using an MTJ element, the pulse width of the first prespike pulse can be set to 10 nsec or less.

[0021] The second pre-spike pulse is used as a time window that allows writing of a coupling weight to the synapse circuit 11 in the case where the first pre-spike pulse precedes the first post-spike pulse in the learning mode, and is the first time window pulse in this example. Writing is allowed while the second pre-spike pulse is input to the synapse circuit 11. This second pre-spike pulse has the same pulse width as the specified time Tw. In this example, the second pre-spike pulse starts to be output simultaneously with the first pre-spike pulse, but it can also be delayed from the first pre-spike pulse. When the second pre-spike pulse is output with a delay from the first pre-spike pulse, the generation timing of the second post-spike pulse, which will be described later, and the timing of changing the potential of the bit lines BL / BLB are also delayed in the same way.

[0022] In the learning mode, the first post-spike pulse output from the neuron circuit 17 also functions as a first write pulse used to control the write timing of the coupling weight when the first pre-spike pulse precedes the first post-spike pulse. The pulse width of this first post-spike pulse is shorter than that of the second pre-spike pulse. As with the first pre-spike pulse, in a configuration in which the weights are stored in the weight memory unit 14 using an MTJ element, the pulse width of the first post-spike pulse can be set to 10 nsec or less.

[0023] The second post-spike pulse is output from the neuron circuit 17 in synchronization with the first post-spike pulse. In this example, the output of the second post-spike pulse starts simultaneously with the first post-spike pulse. This second post-spike pulse is used as a time window that allows writing of a connection weight to the synapse circuit 11 in the case where the first post-spike pulse precedes the first pre-spike pulse in the learning mode, and is the second time window pulse in this example. Like the second pre-spike pulse, writing is allowed while the second post-spike pulse is input to the synapse circuit 11. This second pre-spike pulse has the same pulse width as the specified time Tw.

[0024] As will be described later, the synapse circuit 11 performs a write operation of the connection weight when the second post-spike pulse and the first pre-spike pulse are input simultaneously and when the first post-spike pulse and the second pre-spike pulse are input simultaneously.

[0025] In response to the input of the first prespike pulse, the weight memory unit 14 of the synapse circuit 11 outputs a voltage signal Vpre as a weighted prespike pulse weighted by the stored connection weights to the main body 18 of the neuron circuit 17 via an output line OL.

[0026] The main body 18 of the neuron circuit 17 generates a first post-spike pulse in response to the sum of the voltage levels of the voltage signals Vpre from the weight memories 14 in the row 16 in which it is arranged becoming equal to or greater than a predetermined threshold. In the recognition mode, the main body 18 outputs the first post-spike pulse to the first post-spike line POLa, and in the learning mode, it outputs the first post-spike pulse and also outputs a second post-spike pulse synchronized with the first post-spike pulse to the second post-spike line POLb. The first post-spike pulse is also sent to a synapse circuit provided between the neuron circuit 17 and a neuron circuit in the next stage, for example.

[0027] In the learning mode, the bit line driver 19 of the neuron circuit 17 controls the potentials of the bit lines BL and BLB in synchronization with the generation of the first post-spike pulse of the main body 18 in the same neuron circuit 17. Specifically, the bit line driver 19 makes the potential VB1 of the bit line BL higher than the potential VB2 of the bit line BLB (makes the bit line potential difference ΔVB (=VB1-VB2) positive) for a period almost equal to the pulse width of the first post-spike pulse at the same time as the first post-spike pulse, and then makes a current flow from the bit line BL to the bit line BLB via the weight memory 14, and then makes the potential VB2 of the bit line BLB higher than the potential VB1 of the bit line BL (makes the bit line potential difference ΔVB negative) so that a current flows from the bit line BLB to the bit line BL via the weight memory 14. When a specified time Tw has elapsed since the generation of the first post-spike pulse, the bit line potential difference ΔVB is set to 0V. In this example, when the bit line potential difference ΔVB is positive, the potential of the bit lines BL and BLB is a first potential, and when the bit line potential difference ΔVB is negative, the potential of the bit lines BL and BLB is a second potential.

[0028] In the learning mode, the selection unit 15 of the synapse circuit 11 generates a selection signal based on the first pre-spike pulse, the second pre-spike pulse, the first post-spike pulse, and the second post-spike pulse when the pulse time difference ΔT between the first post-spike pulse and the first pre-spike pulse is within a specified time Tw. The weight memory unit 14 stores a coupling weight based on the potential difference between the bit lines BL and BLB at the timing when the selection signal is input.

[0029] 3, the weight storage unit 14 of the synapse circuit 11 has inverters 21 and 22, a pair of MOS transistors 23 and 24 as transfer gates, and a MOS transistor 25. The inverter 21 is composed of an MTJ element (magnetic tunnel junction element) 31 and a MOS transistor 32 connected in series, and the inverter 22 is composed of an MTJ element 33 and a MOS transistor 34 connected in series. The MOS transistors 23, 24, 32, and 34 are N-type MOSFETs, and the MOS transistor 25 is a P-type MOSFET. In this example, the MOS transistors 32 and 34 are MOS transistors for inverters.

[0030] The MTJ element 31 has a structure in which a magnetization fixed layer 31a and a magnetization free layer 31b are stacked with an insulating film 31c sandwiched therebetween. The magnetization fixed layer 31a has a fixed magnetization direction. The magnetization free layer 31b can change its magnetization direction by passing a write current of a predetermined threshold value or more through the MTJ element 31, and the magnetization direction is determined by the direction of the write current. As is well known, the MTJ element 31 has a low resistance value when the magnetization directions of the magnetization fixed layer 31a and the magnetization free layer 31b are in a parallel state where the magnetization directions are the same, and has a high resistance value when the magnetization free layer 31b is in an antiparallel state where the magnetization direction of the magnetization fixed layer 31a is opposite to that of the magnetization free layer 31b. The MTJ element 31 is in a parallel state when a write current is passed from the magnetization fixed layer 31a to the magnetization free layer 31b, and is in an antiparallel state when a write current is passed in the opposite direction.

[0031] The MTJ element 33 also has a laminated configuration of a magnetization fixed layer 33a, a magnetization free layer 33b, and an insulating film 33c. Similar to the MTJ element 31, the magnetization direction of the magnetization free layer 33b can be changed by a write current, and the resistance value changes between the parallel and anti-parallel states.

[0032] The load memory unit 14 stores the coupling loads in a non-volatile manner by the MTJ elements 31 and 33. When one of the MTJ elements 31 and 33 is in a parallel state, the other is in an anti-parallel state. In this example, when the first coupling load is stored, the MTJ element 31 is in an anti-parallel state and the MTJ element 33 is in a parallel state, and when the second coupling load is stored, the MTJ element 31 is in a parallel state and the MTJ element 33 is in an anti-parallel state. Compared to other ReRAMs, phase change memories, etc., the MTJ elements 31 and 33 are advantageous elements in that they can be rewritten at high speed, have a significantly large maximum number of rewrites, and can be learned many times.

[0033] In the inverter 21, the magnetization free layer 31b of the MTJ element 31 is connected to the drain of the MOS transistor 32, and in the inverter 22, the magnetization free layer 33b of the MTJ element 33 is connected to the drain of the MOS transistor 34. The magnetization fixed layers 31a and 33a of the MTJ elements 31 and 33 are connected to a power supply line PL via a MOS transistor 25. The sources of the MOS transistors 32 and 34 are grounded via a source line SL.

[0034] A connection node SN between the MTJ element 31, which is the output end of the inverter 21, and the MOS transistor 32 is connected to the gate of the MOS transistor 34, which is the input end of the inverter 22, and a connection node SNB between the MTJ element 33, which is the output end of the inverter 22, and the MOS transistor 34 is connected to the gate of the MOS transistor 32, which is the input end of the inverter 21. As a result, the inverters 21 and 22 are cross-coupled to form a flip-flop, and the MOS transistors 32 and 34 form a differential pair.

[0035] The connection node SN is connected to a bit line BL via a MOS transistor 23, and the connection node SNB is connected to a bit line BLB via a MOS transistor 24. The gates of the MOS transistors 23 and 24 are connected to a selection unit 15 and are turned on and off by a selection signal from the selection unit 15. The selection unit 15 and the MOS transistors 23 and 24 form a write unit.

[0036] When the bit line potential difference ΔVB is positive and the MOS transistors 23 and 24 are turned on, a write current flows through a path from the bit line BL to the bit line BLB via the connection node SN, the MTJ element 31, the MTJ element 33, and the connection node SNB, and the MTJ element 31 is in the antiparallel state and the MTJ element 33 is in the parallel state. Conversely, when the bit line potential difference ΔVB is negative and the MOS transistors 23 and 24 are turned on, a write current flows through a path from the bit line BLB to the bit line BL via the connection node SNB, the MTJ element 33, the MTJ element 31, and the connection node SN, and the MTJ element 31 is in the parallel state and the MTJ element 33 is in the antiparallel state.

[0037] The potential (voltage) of the connection node SNB is outputted to the output line OL as a voltage signal Vpre via a capacitor 36 as an output circuit section. That is, one electrode of the capacitor 36 is connected to the connection node SNB, and the other electrode is connected to the main body 18 of the neuron circuit 17 via the output line OL. As described later, the capacitor 36 is connected to a control gate CG (see FIG. 4) in the main body 18. The capacitor 36 is provided to prevent the generation of a conductive current between the weight memory sections 14 of the synapse circuits 11 that are capacitively coupled to the same floating gate FG (see FIG. 4) via the control gate CG. For the capacitor 36, for example, a MOS capacitor using the gate capacitance of a transistor may be used.

[0038] The substantial coupling capacitance between the load memory unit 14 and the floating gate FG is determined by the capacitance of the capacitor 36 and the coupling capacitance of the control gate CG to the floating gate FG. The substantial coupling capacitance between the load memory unit 14 and the floating gate FG can also be made different, and by doing so, for example, the voltage signal Vpre can be weighted. Furthermore, an output circuit unit may be connected to the connection node SN instead of the connection node SNB.

[0039] The MOS transistor 25 is a switching element for power gating in the recognition mode, and is also a switching element for signal driving, i.e., as a readout section that outputs the voltage signal Vpre. The MOS transistor 25 is turned on when its gate is connected to the pre-spike line PrL and a first pre-spike pulse is output as an input signal. When the MOS transistor 25 is turned on, the inverters 21 and 22, i.e., the MOS transistors 32 and 34 constituting a differential pair, receive power from the power line PL and operate. As a result, in response to the first pre-spike pulse, the voltage of the connection node SNB, which is the output end of the inverter 22, is output to the output line OL as the voltage signal Vpre. The voltage signal Vpre is relatively high in the case of the first coupling load, i.e., when the MTJ element 31 is in an anti-parallel state and the MTJ element 33 is in a parallel state, and is relatively low in the case of the second coupling load, i.e., when the MTJ element 31 is in a parallel state and the MTJ element 33 is in an anti-parallel state.

[0040] The selection unit 15 makes the selection signal active (H level) when the first pre-spike pulse is output while the second post-spike pulse is output, or when the second pre-spike pulse is output while the first post-spike pulse is output, by a combination of the logic circuits 15a to 15c. As a result, the selection signal becomes active and the MOS transistors 23, 24 are turned on only when the pulse time difference ΔT between the first post-spike pulse and the first pre-spike pulse is within the specified time Tw.

[0041] 4, the main body 18 has a MOS transistor 41 which is a P-type MOSFET, a MOS transistor 42 which is an N-type MOSFET, an inverter 43, and a pulse generator 44. The pulse generator 44 generates a first post-spike pulse and a second post-spike pulse. Note that the first post-spike pulse and the second post-spike pulse can be generated by using a pulse generator whose pulse waveform, output timing, delay time, etc. can be controlled as the pulse generator 44 of the main body 18.

[0042] MOS transistors 41 and 42 as neuron MOS transistors are connected in series to form an inverter. That is, the drains of the MOS transistors 41 and 42 are connected to each other, the source of the MOS transistor 41 is connected to a power supply (voltage VDD), and the source of the MOS transistor 42 is grounded. The input terminal of the inverter 43 is connected to the connection node of the MOS transistors 41 and 42, and when the connection node becomes the ground potential (0V), its output logic is inverted from L level to H level. The pulse generator 44 generates a first post-spike pulse and a second post-spike pulse in response to the output of the inverter 43 changing from L level to H level.

[0043] The MOS transistors 41 and 42 share a common floating gate FG. The MOS transistors 41 and 42 are provided with a plurality of control gates CG that are capacitively coupled to the floating gate FG. The control gates CG of the main body 18 are provided corresponding to the respective weight memories 14 in the column 16 in which the main body 18 is arranged, and each control gate CG is connected to an output line OL from the corresponding weight memory 14. The MOS transistors 41 and 42 are controlled to be on or off by the potential of the floating gate FG, and when one is on, the other is off.

[0044] The potential of the floating gate FG is determined by the voltage of the voltage signal Vpre applied to each control gate CG and the coupling capacitance between each control gate CG and the floating gate FG. In this example, the coupling capacitance of each control gate CG to the floating gate FG is the same. Therefore, the sum of the voltages applied to each control gate CG can be used to control the MOS transistors 41, 42 so that one is turned on and the other is turned off. Note that the main body 18 may be configured to generate a first post-spike pulse and a second post-spike pulse based on the sum of the voltages of the voltage signals Vpre from the synapse circuits 11 to which it is connected.

[0045] Next, the operation of the above configuration will be described. In the recognition mode, as shown in Fig. 5, a first pre-spike pulse is output from each input circuit 20a to the pre-spike line PrL via the inverter 20b at a timing according to the contents of the processing of the front-stage section 20. In this recognition mode, since a second pre-spike pulse is not output, the selection section 15 does not output a selection signal.

[0046] Focusing on one synapse circuit 11, when a first prespike pulse is input to that synapse circuit 11 via the prespike line PrL to which it is connected, the MOS transistor 25 in the weight memory unit 14 turns on. When this MOS transistor 25 turns on, a current from the power line PL flows through the MTJ element 31 and the MTJ element 33, and the inverters 21 and 22 operate. Thus, in the recognition mode, the weight memory unit 14 is effective in suppressing power consumption because a current flows only while the MOS transistor 25 is on.

[0047] For example, when the coupling weight stored in the synapse circuit 11 is the first coupling weight, that is, when the MTJ element 31 has a high resistance and the MTJ element 33 has a low resistance, a potential difference occurs in which the potential of the connection node SNB is higher than the potential of the connection node SN. This potential difference is amplified by the action of the cross-coupled inverters 21 and 22, and the potential difference becomes stable in a large state. Conversely, when the coupling weight stored in the synapse circuit 11 is the second coupling weight, that is, when the MTJ element 31 has a low resistance and the MTJ element 33 has a high resistance, a potential difference occurs in which the potential of the connection node SNB is lower than the potential of the connection node SN, and the potential difference is amplified by the action of the cross-coupled inverters 21 and 22, and the potential difference becomes stable in a large state.

[0048] The potential difference between the connection nodes SN and SNB is amplified and stabilized by the differential pair of MOS transistors 32 and 34, so the time required for stabilization is very short, thereby enabling high-speed operation.

[0049] The current flowing through the MTJ elements 31 and 33 when the MOS transistor 25 is turned on is adjusted to a value that does not change their magnetization states. In reality, the magnetization directions of the magnetization free layers 31b and 33b change while the current is flowing, but the change is so slight that it does not affect the generation of the desired potential difference at the connection nodes SN and SNB. The slight magnetization directions of the magnetization free layers 31b and 33b return to their original magnetization directions when the current is stopped.

[0050] As described above, the potentials of the connection nodes SN and SNB change according to the coupling weights stored in the synapse circuit 11. As a result, when the synapse circuit 11 stores the first coupling weight, a high voltage signal Vpre is output to the output line OL connected to the connection node SNB via the capacitor 36, and when the synapse circuit 11 stores the second coupling weight, a low voltage signal Vpre is output. The voltage signal Vpre from the synapse circuit 11 is applied to the control gate CG of the main body 18 via the output line OL. When the MOS transistor 25 is turned off, the capacitor 36 is discharged and the voltage of the voltage signal Vpre decreases, but since the capacitor 36 discharges through the MTJ elements 31 and 33 and the MOS transistors 32 and 34, the voltage of the voltage signal Vpre gradually decreases and does not immediately become 0V.

[0051] Focusing on one neuron circuit 17, the voltage of the voltage signal Vpre output from each synapse circuit 11 in the column 16 in which it is arranged is applied to the corresponding control gate CG. Of course, no voltage is applied to the control gate CG from a synapse circuit 11 to which no first pre-spike pulse is input. When the voltage signal Vpre is applied to each control gate CG as described above and the potential of the floating gate FG reaches the threshold, the MOS transistor 41 is turned off and the MOS transistor 42 is turned on. As a result, the output of the inverter 43 is inverted from the L level to the H level, and the first post-spike pulse is output from the pulse generator 44. If the potential of the floating gate FG does not reach the threshold, the MOS transistor 41 is not turned off and the MOS transistor 42 is not turned on, so that the first post-spike pulse is not output.

[0052] As described above, a first post-spike pulse is output from the neuron circuit 17 provided for each column 16 according to the timing of the first pre-spike pulse output from the front-stage section 20 to the pre-spike line PrL of each row and the connection weight stored in each synapse circuit 11. In the recognition mode, the first post-spike pulse is sent to a synapse circuit provided between the neuron circuit 17 and, for example, the neuron circuit in the next stage.

[0053] In the recognition mode, the weighting applied to the pre-spike is transmitted from the weight memory section 14 to the main section 18 as the magnitude of the voltage of the voltage signal Vpre, and the sum of these voltages is obtained by the capacitively coupled control gate CG and floating gate FG. Therefore, a first post-spike pulse equivalent to the post-spike pulse resulting from the product-sum operation is obtained without providing an arithmetic circuit for calculating the product-sum of the coupling weight and the pre-spike pulse.

[0054] Also, since only an extremely small current flows to charge the control gate CG (actually the capacitor 36), low-power operation is possible. In the load memory unit 14, the two MTJ elements 31 and 33 are always written with opposite resistance states. Therefore, when the voltage signal Vpre is output, a current flows through one (low resistance) MTJ element, and almost no current flows through the other (high resistance) MTJ element. The direction of the current flowing through one (low resistance) MTJ element is the direction of the write current that makes the MTJ element low resistance. Therefore, neither the high resistance MTJ element nor the low resistance MTJ element will experience read disturbance in which the magnetization direction is reversed by the current flowing when the voltage signal Vpre is output.

[0055] Next, the learning mode will be described. In the learning mode, as in the recognition mode, a first pre-spike pulse is output from each input circuit 20a to the pre-spike line PrL at a timing according to the content of the processing of the front-stage section 20. In this learning mode, when the first pre-spike pulse is output, the load memory section 14 operates to output a voltage signal Vpre, as in the recognition mode.

[0056] In this learning mode, a second prespike pulse with a pulse width Tw is output from the input circuit 20a to the word line WL in synchronization with the first prespike pulse, as shown in Figures 6 and 7. Note that Figure 6 shows the case where the first prespike pulse precedes the first postspike pulse, and Figure 7 shows the case where the first postspike pulse precedes the first prespike pulse, and both show the case where the pulse time difference ΔT between the first prespike pulse and the first postspike pulse is within the specified time Tw.

[0057] As in the cognitive mode, synapse circuit 11 to which the first prespike pulse has been input via prespike line PrL outputs a voltage signal Vpre corresponding to the coupling weight stored in its weight memory unit 14 to main unit 18 arranged in the same column 16. When the voltage of voltage signal Vpre is applied to control gate CG of main unit 18 and the potential of floating gate FG reaches a threshold value, MOS transistor 41 is turned off and MOS transistor 42 is turned on. As a result, a first postspike pulse is output from pulse generator 44 to first postspike line POLa. Also, in synchronization with the first postspike pulse, a second postspike pulse having a pulse width Tw is output from main unit 18 to second postspike line POLb.

[0058] Furthermore, simultaneously with the output of the first post-spike pulse, the bit line potential difference ΔVB is made positive for a period substantially equal to the pulse width of the first post-spike pulse by the bit line driver 19, and then the bit line potential difference ΔVB is made negative. Then, when a specified time Tw has elapsed since the generation of the first post-spike pulse, the bit line potential difference ΔVB is made 0 V.

[0059] As described above, the second pre-spike pulse begins to be output simultaneously with the first pre-spike pulse, and has the same pulse width as the specified time Tw. Therefore, for example, as shown in Fig. 6, if the first pre-spike pulse is input to synapse circuit 11 within a period preceding the time Tw from the timing at which the first post-spike pulse is output, the first post-spike pulse is input to selection unit 15 of that synapse circuit 11 while the second pre-spike pulse is being input. As a result, a selection signal is output from selection unit 15 to weight memory 14 almost simultaneously with the first post-spike pulse, and MOS transistors 23 and 24 in weight memory 14 are each turned on during the period in which bit line potential difference ΔVB is positive.

[0060] When the MOS transistors 23 and 24 are turned on as described above, the potential of the bit line BL is higher than that of the bit line BLB, so that a write current flows from the bit line BL through the MOS transistor 23, the MTJ element 31, the MTJ element 33, and the MOS transistor 24 to the bit line BLB. This causes the MTJ element 31 to have a high resistance and the MTJ element 33 to have a low resistance. As a result, the synapse circuit 11 enters a state in which the first coupling weight is stored.

[0061] In this way, when the pulse time difference ΔT is equal to or less than the specified time Tw and the first pre-spike pulse precedes the first post-spike pulse, MOS transistor 25 turns on simultaneously with MOS transistors 23 and 24. Meanwhile, as described above, the voltage of power supply line PL is set to about |ΔVB| / 2. For this reason, even if MOS transistor 25 turns on simultaneously with MOS transistors 23 and 24, a potential difference occurs between the bit line BL and the power supply line PL, and between the power supply line PL and the bit line BLB, so that a write current flows as described above, and the first coupling weight is stored by MTJ elements 31 and 33.

[0062] On the other hand, the second post-spike pulse begins to be output simultaneously with the first post-spike pulse, and has the same pulse width as the specified time Tw. Therefore, as shown in Fig. 7, if a first pre-spike pulse is input to synapse circuit 11 within the period from when the first post-spike pulse is output until the specified time Tw has elapsed, the first pre-spike pulse is input to selection unit 15 of that synapse circuit 11 while the second post-spike pulse is being input. As a result, a selection signal is output from selection unit 15 to weight memory 14 almost simultaneously with the first pre-spike pulse, so that MOS transistors 23 and 24 in weight memory 14 are each turned on during the period when bit line potential difference ΔVB is negative.

[0063] When the MOS transistors 23 and 24 are turned on as described above, the potential of the bit line BLB is higher than that of the bit line BL, so that a write current flows from the bit line BLB through the MOS transistor 24, the MTJ element 33, the MTJ element 31, and the MOS transistor 23 to the bit line BL. This causes the MTJ element 31 to have a low resistance and the MTJ element 33 to have a high resistance. As a result, the synapse circuit 11 is in a state in which the second coupling weight is stored.

[0064] If the first prespike pulse precedes the first postspike pulse by more than time Tw, the first postspike pulse is input to a selection section 15 to which the second prespike pulse has not been input. If the first postspike pulse precedes the first prespike pulse by more than time Tw, the first prespike pulse is input to a selection section 15 to which the second postspike pulse has not been input. In these cases, no selection signal is generated, so the weight memory section 14 does not write the connection weights.

[0065] In the above manner, each synapse circuit 11 has its connection weight rewritten, and when a first pre-spike pulse is input after the rewriting, it outputs a voltage signal Vpre according to the new connection weight to the neuron circuit 17 in the same manner as described above. Furthermore, when the potential of the floating gate FG reaches a threshold value, the neuron circuit 17 outputs a first post-spike pulse and a second post-spike pulse in the same manner as described above. Then, in each synapse circuit 11, when a first pre-spike pulse is input within each period of time Tw before and after the timing when the first post-spike pulse is input, the connection weight is rewritten again. In this manner, the connection weight of each synapse circuit 11 is updated, and the final one is held in each synapse circuit 11.

[0066] As described above, in the learning mode, a write current is passed to change the magnetization state of the MTJ elements 31 and 33, but the time required to alternate between the parallel state and the antiparallel state of the MTJ elements 31 and 33 (hereinafter referred to as the rewrite time) is very short, enabling high-speed operation. For example, the rewrite time of the MTJ elements 31 and 33 is about 1 / 10 of that of ReRAM.

[0067] As described above, in both the recognition mode and the learning mode, the neural network circuit device 10 can operate at high speed and low power, and has a more optimal configuration. In addition, the time window that allows the writing of the connection weight is determined by using the second prespike pulse from the input circuit 20a as the first time window pulse when the first prespike pulse precedes the first postspike pulse, and by using the second postspike pulse from the neuron circuit 17 as the second time window pulse when the first postspike pulse precedes the first prespike pulse, respectively. The control of the writing timing of the connection weight is determined by using the first postspike pulse from the neuron circuit 17 as the first write control pulse when the first prespike pulse precedes the first postspike pulse, and by using the first prespike pulse from the input circuit 20a as the second write control pulse when the first postspike pulse precedes the first prespike pulse, respectively. This makes it possible to simplify the driving of the synapse circuit based on STDP. In addition, the driving based on STDP can be realized with a simple circuit configuration.

[0068] In addition, the connection weights stored in the synapse circuit may be binary, being either a first connection weight, which has a relatively large weight, or a second connection weight, which has a relatively small weight, or may be multi-valued, being one of three or more connection weights with different weights.

[0069] When the connection weights stored in the synapse circuits are multi-valued, for example, each synapse circuit is provided with a plurality of (e.g., M) storage units each consisting of a weight storage section and a selection section, and each weight storage section is configured to store either the first connection weight or the second connection weight, as described above. The pulse widths of the second post-spike pulses input to the selection sections in one synapse circuit are made to differ from each other within time Tw (Tw is a specified time), and similarly, the pulse widths of the second pre-spike pulses are made to differ from each other within time Tw (Tw is a specified time). As a result, the number of weight storage sections to which selection signals are input increases or decreases depending on the length of the pulse time difference ΔT between the first post-spike pulse and the first pre-spike pulse.

[0070] Focusing on one synapse circuit, when the first prespike pulse precedes the first postspike pulse, the smaller the pulse time difference ΔT, the greater the number of weight memories into which the first connection weight is written, and the greater the pulse time difference ΔT, the fewer the number of weight memories into which the first connection weight is written. Conversely, when the first postspike pulse precedes the first prespike pulse, the smaller the pulse time difference ΔT, the greater the number of weight memories into which the second connection weight is written, and the greater the pulse time difference ΔT, the fewer the number of weight memories into which the second connection weight is written. As a result, one synapse circuit can store M+1 types of connection weights corresponding to states in which the first connection weight is stored in 0 to M weight memories (the second connection weight is stored in the weight memories that do not store the first connection weight).

[0071] In this case too, when the first pre-spike pulse is output as an input signal, each weight memory unit outputs to the main unit a voltage or current corresponding to the stored connection weight. In response to the input of the first pre-spike pulse, one synapse circuit outputs to the main unit each voltage or current corresponding to the connection weight stored in that weight memory unit. Since the main unit operates based on the sum of the input voltages or currents, it also operates based on the sum of the voltages or currents from one synapse circuit, and as a result, it outputs to the main unit one of the M+1 types of connection weights stored in the synapse circuit.

[0072] [Second embodiment] In the second embodiment, the time window is controlled only by the signal from the pre-neuron circuit, and the timing of writing the connection weight is controlled only by the signal from the post-neuron circuit. The second embodiment is the same as the first embodiment except for the details described below, and the same components are denoted by the same reference numerals and their detailed description is omitted.

[0073] 8, a neural network circuit device 60 according to the second embodiment has the same configuration as the neural network circuit device according to the first embodiment, but does not have the first and second post-spike lines. The main body 18 of the neuron circuit 17 sends the first post-spike only to the synapse circuit provided between the neuron circuit of the next stage. The main body 18 does not output the second post-spike.

[0074] Also, in the learning mode, bit line driver 19 controls the potentials of bit lines BL and BLB to make the bit line potential difference ΔVB positive in a pulsed manner at the same time as the first post-spike pulse for a time substantially equal to the pulse width of the first post-spike pulse, and to make the bit line potential difference ΔVB negative in a pulsed manner for a time substantially equal to the pulse width of the first post-spike pulse after a time Tw has elapsed since the generation of the first post-spike pulse. In this example, this pulsed positive change in bit line potential difference ΔVB functions as a first write pulse, and the pulsed negative change in bit line potential difference ΔVB functions as a second write pulse.

[0075] Furthermore, the synapse circuit 11 is composed only of a weight storage section 64, to which the power supply line PL, source line SL, bit lines BL, BLB, pre-spike line PrL, and word line WL are connected.

[0076] As shown in Fig. 9, the gates of the MOS transistors 23 and 24 constituting the weight memory unit 64 are connected to the word line WL. Therefore, the MOS transistors 23 and 24 are turned on while the second pre-spike pulse is being output. The configuration of the weight memory unit 64 is the same as that of the weight memory unit of the first embodiment, except for the connection of these MOS transistors 23 and 24. Note that the operation of the weight memory unit 64 and the operation of the neural network circuit device 60 in the recognition mode are the same as those of the first embodiment.

[0077] In the neural network circuit device 60 configured as described above, the second prespike pulse from the input circuit as a preneuron circuit defines the time window when the first prespike pulse precedes the first postspike pulse and when the first postspike pulse precedes the first prespike pulse. Therefore, in this example, the second prespike pulse is the common time window pulse.

[0078] 10 and 11, in the learning mode, simultaneously with generation of a first post-spike pulse from main unit 18, bit line driver 19 makes the bit line potential difference ΔVB positive for a time period substantially equal to the pulse width of the first post-spike pulse, and then sets it to "0 V." After this, when time Tw has elapsed since generation of the first post-spike pulse, the bit line potential difference ΔVB is made negative for a time period substantially equal to the pulse width of the first post-spike pulse, and then sets it to "0 V."

[0079] The pulse width of the second pre-spike pulse output simultaneously with the first pre-spike pulse is time Tw. For this reason, for example, as shown in Fig. 10, if the first pre-spike pulse precedes the first post-spike pulse and the pulse time difference ΔT between them is within the specified time Tw, the bit line potential difference ΔVB becomes positive during the period in which the MOS transistors 23 and 24 are turned on by the second pre-spike pulse. As a result, the write current flows from the bit line BL through the MOS transistor 23, the MTJ element 31, the MTJ element 33, and the MOS transistor 24 to the bit line BLB. As a result, the MTJ element 31 becomes high resistance, the MTJ element 33 becomes low resistance, and the weight memory unit 64 becomes in a state in which the first coupling weight is stored.

[0080] Also, the pulse width of the second pre-spike pulse outputted simultaneously with the first pre-spike pulse is time Tw, and the bit line potential difference ΔVB becomes negative after a delay of time Tw from the first post-spike pulse. For this reason, for example, as shown in FIG. 11, if the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT between them is within the specified time Tw, the bit line potential difference ΔVB becomes negative during the period when the MOS transistors 23 and 24 are turned on by the second pre-spike pulse. As a result, the write current flows from the bit line BLB through the MOS transistor 24, the MTJ element 33, the MTJ element 31, and the MOS transistor 23 to the bit line BL. As a result, the MTJ element 31 becomes low resistance, and the MTJ element 33 becomes high resistance, and the synapse circuit 11 enters a state in which the second coupling weight is stored.

[0081] When the first pre-spike pulse precedes the first post-spike pulse by more than time Tw, and when the first post-spike pulse precedes the first pre-spike pulse by more than time Tw, the bit line potential difference ΔVB becomes positive or negative outside the period in which the second pre-spike pulse is input to the weight memory unit 64. In this case, therefore, the weight memory unit 64 does not perform the operation of writing the coupling weight.

[0082] In the second embodiment, the time window for allowing the writing of the coupling weight is defined by using the second pre-spike pulse from the input circuit 20a as a common time window pulse, and the control of the timing for writing the coupling weight is defined by using the positive change in the pulse-like bit line potential difference ΔVB as the first write pulse and the negative change in the pulse-like bit line potential difference ΔVB as the second write pulse, so that the driving of the synapse circuit based on STDP can be simplified. Moreover, the driving based on STDP can be realized with a simple circuit configuration.

[0083] [Third embodiment] In the third embodiment, the time window is controlled only by the signal from the post-neuron circuit side, and the timing of writing the coupling weight is controlled only by the signal from the pre-neuron circuit side, which is the opposite of the second embodiment. As will be described in detail below, the third embodiment is the same as the second embodiment except for the change in the bit line potential difference ΔVB by the bit line driver and the pulse width of the second pre-spike pulse. For the neural network circuit device and synapse circuit, refer to Figures 8 and 9, and the substantially same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0084] In the third embodiment, the input circuit 20a of the neural network circuit device 60 outputs a second prespike pulse delayed by a time Tw from the first prespike pulse, as shown in Figures 12 and 13. In this example, the second prespike pulse has the same pulse width as the first prespike pulse. The second prespike pulse is a common write pulse when the first prespike pulse precedes the first postspike pulse and when the first postspike pulse precedes the first prespike pulse.

[0085] Also, in the learning mode, the bit line driver 19 makes the bit line potential difference ΔVB positive in a pulsed manner almost simultaneously with the first post-spike pulse, maintains this bit line potential difference ΔVB for a period of time Tw, and then makes the bit line potential difference ΔVB negative in a pulsed manner that continues for a period of time Tw. In this example, the pulsed change in the positive bit line potential difference ΔVB is the first time window pulse, and the pulsed change in the negative bit line potential difference ΔVB is the second time window pulse.

[0086] In this example, the second pre-spike pulse is output with a delay of time Tw from the first pre-spike pulse, and the bit line potential difference ΔVB becomes positive almost simultaneously with the first post-spike pulse, and this positive bit line potential difference ΔVB continues for time Tw. Therefore, for example, as shown in Fig. 12, if the first pre-spike pulse precedes the first post-spike pulse and the pulse time difference ΔT is within the specified time Tw, the second pre-spike pulse turns on MOS transistors 23 and 24 during the period when the bit line potential difference ΔVB is positive. As a result, MTJ element 31 becomes high resistance, and MTJ element 33 becomes low resistance, and weight memory unit 64 enters a state in which the first coupling weight is stored.

[0087] Also, the second pre-spike pulse is outputted with a delay of time Tw from the first pre-spike pulse, and the bit line potential difference ΔVB becomes negative with a delay of time Tw from the first post-spike pulse, and the negative bit line potential difference ΔVB continues for time Tw. Therefore, for example, as shown in Fig. 13, if the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT is within the specified time Tw, the second pre-spike pulse turns on the MOS transistors 23 and 24 during the period when the bit line potential difference ΔVB is negative. This causes the MTJ element 31 to have a low resistance, and the MTJ element 33 to have a high resistance. As a result, the synapse circuit 11 enters a state in which the second coupling weight is stored.

[0088] According to the third embodiment, it is possible to simplify the driving of the synapse circuit based on STDP, as in the second embodiment, and by extension, it is possible to realize the driving based on STDP with a simple circuit configuration.

[0089] [Fourth embodiment] In the fourth embodiment, a synapse circuit is composed of multiple weight storage units, and the connection weights stored in the synapse circuit are changed in stages according to the pulse time difference between the first post-spike pulse and the first pre-spike pulse. Note that, except for the details described below, the fourth embodiment is the same as the third embodiment, and substantially the same components are denoted by the same reference numerals and detailed description thereof is omitted.

[0090] In this example, as shown in FIG. 14, the synapse circuit 11 has a plurality of, in this example, four, weight storage units 64A-64D arranged in the column direction. The weight storage units 64A-64D have the same configuration as the weight storage unit 64 (see FIG. 9) of the third embodiment, and are connected to the bit lines BL, BLB, pre-spike lines PrL, word lines WL, and output lines OL in the same manner. The power supply lines and source lines are also connected in the same manner, but are omitted in FIG. 14. The weight storage units 64A-64D are connected to the common bit lines BL and BLB, but the pre-spike lines PrL and word lines WL are connected to those in different rows. The output lines OL from the weight storage units 64A-64D are each connected to the neuron circuits 17 in the same column.

[0091] The input circuit 20a has delay circuits 66a-66d corresponding to the weight memories 64A-64D of the synapse circuit 11, and are connected to the corresponding weight memories 64A-64D via word lines WL. The delay circuits 66a-66d receive a first pre-spike pulse, and output second to fifth pre-spike pulses (hereinafter, when no distinction is made between these, they will be referred to as delayed pre-spike pulses) that are obtained by delaying the input first pre-spike pulse by a preset delay time to the corresponding word lines WL. In this example, the second to fifth pre-spike pulses are common write pulses.

[0092] The delay circuits 66a to 66d are set with different delay times. In this example, the delay circuit 66a has a delay time of 1 / 4Tw, the delay circuit 66b has a delay time of 1 / 2Tw, the delay circuit 66c has a delay time of 3 / 4Tw, and the delay circuit 66d has a delay time of Tw, and the delay times are set in 1 / 4Tw steps. The delay times can be set appropriately, and may be set so that the delay times increase nonlinearly (at unequal intervals), for example.

[0093] In the learning mode, as shown in an example in FIG. 15, a second prespike pulse delayed by a delay time 1 / 4Tw, a third prespike pulse delayed by a delay time 1 / 2Tw, a fourth prespike pulse delayed by a delay time 3 / 4Tw, and a fifth prespike pulse delayed by a delay time Tw are generated based on the first prespike pulse.

[0094] The above delay times are merely examples and can be set as appropriate. For example, the delay time may be set to increase nonlinearly (unequal intervals). In addition, the value S may be an integer of 2 or more, and the delay time may be set to 1 / S·Tw, 2 / S·Tw, ..., (S-1) / S·Tw, Tw, and the value S may be set arbitrarily.

[0095] As described above, the second to fifth pre-spike pulses having different delay times from the first pre-spike pulse, i.e., time differences from one another, are output from the input circuit 20a to the corresponding word lines WL. As a result, the second pre-spike pulse is input to the load memory unit 64A, the third pre-spike pulse to the load memory unit 64B, the fourth pre-spike pulse to the load memory unit 64C, and the fifth pre-spike pulse to the load memory unit 64D, each at a different timing.

[0096] For example, when the first prespike pulse precedes the first postspike pulse and the pulse time difference ΔT is equal to or less than time Tw, the number of weight memories in synapse circuit 11 to which the second to fifth prespike pulses are input during the period when the bit line potential difference ΔVB is positive increases stepwise. Therefore, in this case, the smaller the pulse time difference ΔT, the more stepwise the number of weight memories in synapse circuit 11 to which the first connection weight is written increases.

[0097] Specifically, when the first prespike pulse precedes the first postspike pulse and the pulse time difference ΔT is less than time Tw and greater than 3 / 4Tw, the fifth prespike pulse is input to weight memory unit 64D during the period when the bit line potential difference ΔVB is positive, and the first coupling weight is written to this weight memory unit 64D. However, since the second to fourth prespike pulses are input to weight memory units 64A to 64C before the bit line potential difference ΔVB becomes positive, the coupling weights in weight memory units 64A to 64C are not rewritten.

[0098] 15, in the range where the first prespike pulse precedes the first postspike pulse and the pulse time difference ΔT is greater than 1 / 2Tw and less than 3 / 4Tw, the fourth and fifth prespike pulses are input to the weight memories 64C and 64D during the period when the bit line potential difference ΔVB is positive. Therefore, the first coupling weights are written to the weight memories 64C and 64D. In contrast, the second and third prespike pulses are input to the weight memories 64A-64B before the bit line potential difference ΔVB becomes positive, so the coupling weights in the weight memories 64A and 64B are not rewritten.

[0099] Similarly, in the range where the pulse time difference ΔT is greater than 1 / 4Tw and equal to or less than 1 / 2Tw, the first coupling weights are written to the weight memories 64B to 64D, respectively, and the coupling weights in the weight memory 64A are not rewritten. Furthermore, in the range where the pulse time difference ΔT is equal to or less than 1 / 4Tw, the first coupling weights are written to the weight memories 64A to 64D, respectively.

[0100] When the first pre-spike pulse precedes the first post-spike pulse and the pulse time difference ΔT exceeds the specified time Tw, the second to fifth pre-spike pulses are all input to the weight memories 64A to 64D before the bit line potential difference ΔVB becomes positive, and therefore the coupling weights in the weight memories 64A to 64D are not rewritten.

[0101] On the other hand, when the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT is equal to or less than time Tw, the larger the pulse time difference ΔT, the larger the number of weight memories in the synapse circuit 11 to which the second to fifth pre-spike pulses are input during the period when the bit line potential difference ΔVB is negative. In this case, the larger the pulse time difference ΔT, the smaller the number of weight memories in the synapse circuit 11 to which the second to fifth pre-spike pulses are input during the period when the bit line potential difference ΔVB is positive. Therefore, the larger the pulse time difference ΔT, the smaller the number of weight memories in the synapse circuit 11 to which the first coupling weight is written, and the larger the number of weight memories to which the second coupling weight is written, is. In FIG. 15, the case where the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT is larger than 3 / 4Tw, is shown by a two-dot chain line.

[0102] In addition, in the range where the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT exceeds the specified time Tw and reaches time 2Tw, the number of weight memories in the synapse circuit 11 to which the second connection weights are written decreases stepwise, and the number of weight memories in which the connection weights are not rewritten increases stepwise. In the range where the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT exceeds time 2Tw, the connection weights of the weight memories 64A to 64D are not rewritten.

[0103] In both the recognition mode and the learning mode, the main body 18 of the neuron circuit 17 refers to the sum of the voltage levels of the voltage signals Vpre output from the weight memories 64A to 64D of each synapse circuit 11. Therefore, when focusing on one synapse circuit 11, the main body 18 refers to the sum of the voltage levels of the voltage signals Vpre output from the weight memories 64A to 64D in that one synapse circuit 11. Therefore, the synapse circuit 11 essentially outputs a weighted pre-spike pulse determined by the number of weight memories storing the first connection weight and the number of weight memories storing the second connection weight to the neuron circuit 17. At this time, the weighted pre-spike pulse is weighted more heavily as the number of weight memories storing the first connection weight increases, and is weighted less heavily as the number of weight memories storing the second connection weight increases, so that multi-value connection weights can be stored in the synapse circuit 11.

[0104] As described above, according to this example, the number of weight memories in which the first and second connection weights in synapse circuit 11 are written can be changed in stages depending on the precedence / subsequence relationship between the first postspike pulse and the first prespike pulse and the pulse time difference ΔT. Moreover, the manner of change can be easily altered by adjusting the delay times of the second to fifth prespike pulses, which serve as a common write pulse.

[0105] In the above, the period in which the bit line potential difference ΔVB is positive (hereinafter referred to as the "first period") and the period in which the bit line potential difference ΔVB is negative (hereinafter referred to as the "second period") are the same length (time length), and each is the same as the specified time Tw, but the relationship between the length of the first period, the length of the second period, and the specified time Tw is not limited to this. For example, the length of the first period and the specified time may be the same, and these may be different from the length of the second period, or the length of the second period and the specified time may be the same, and these may be different from the length of the first period. Also, the length of the first period and the second period may be the same, and these may be different from the specified time Tw, or the length of the first period, the length of the second period, and the specified time Tw may be different from each other.

[0106] In the above example, the number of weight memories to which delayed prespike pulses with different delay times are input in one synapse circuit is one each, but some or all of them may be multiple. Also, the amount of change in the coupling weight based on the pulse time difference ΔT can be made different by changing the number of weight memories to which the delayed prespike pulse is input and the delay time for each delay time of the delayed prespike pulse. In this case, for example, the number of weight memories in one synapse circuit is increased as the delayed prespike pulse with a shorter delay time is input. It is also preferable to make the number of weight memories to which delayed prespike pulses with each delay time are input and the delay time programmable and to operate the neural network circuit device by appropriately setting them in advance.

[0107] If a delay circuit that delays the first prespike pulse by an arbitrarily set delay time to generate a delayed prespike pulse, as described above, is provided in each row of a plurality of synapse circuits arranged in a matrix, and the row (delay circuit) assigned to one input circuit can be set arbitrarily, then the number of weight memories and delay time of each synapse circuit can be adjusted arbitrarily, and a variety of synapse circuits can be driven based on STDP.

[0108] In each of the above embodiments, in one write operation of the coupling weight, a write current is passed once in a pulsed manner to the weight storage unit between a pair of bit lines, but in one write operation of the coupling weight, a write current may be passed multiple times in a pulsed manner. In an MTJ element that stores a coupling weight, there are rare cases where writing is not performed correctly even if a write current is passed, but by passing the write current multiple times in this way, it is possible to reliably write the coupling weight. In this case, the pulses (first pre-spike pulse, first post-spike pulse, pulsed change in the potential of the bit line) that are input to the synapse circuit and become the first write pulse, second write pulse, and common write pulse may be made to be multiple pulses.

[0109] The configuration of the load memory unit in each of the above examples is merely an example, and is not particularly limited to these. The load memory unit in each of the above examples is configured by cross-coupling a pair of inverters each including an MTJ element, but it can also be configured as a circuit using only one MTJ element, for example. In addition, the load memory unit is configured using a two-terminal MTJ element of the spin transfer torque (STT) type, but the magnetization reversal type of the MTJ element, the number of terminals, etc. are not limited to this. For example, a three-terminal MTJ element of the spin orbital torque (SOT) type can be used.

[0110] The load memory unit 70 shown in FIG. 16 is a configuration example using one MTJ element 71. The load memory unit 70 includes the MTJ element 71 and MOS transistors 72 and 73, which are N-type MOSFETs. The MTJ element 71 has a structure in which a magnetization fixed layer 71a and a magnetization free layer 71b are laminated with an insulating film 71c sandwiched therebetween, as in the MTJ element of the first embodiment. The load memory unit 70 stores the magnitude of the coupling load according to the resistance of the MTJ element 71 (the magnetization direction of the magnetization free layer 71b). In this example, the antiparallel state of the MTJ element 71 is the first coupling load, and the parallel state is the second coupling load.

[0111] The magnetization fixed layer 71a of the MTJ element 71 is connected to the power supply line PL via the MOS transistor 72, and the magnetization free layer 71b is connected to the source line SL. The gate of the MOS transistor 72 is connected to the pre-spike line PrL, and the connection node between the MTJ element 71 and the MOS transistor 72 is grounded via the MOS transistor 73. The gate of the MOS transistor 73 is connected to the second post-spike line POLb. One electrode of the capacitor 36 is connected to the connection node between the MTJ element 71 and the MOS transistor 72. As a result, a potential (voltage) according to the resistance value of the MTJ element 71 is output to the output line OL as a voltage signal Vpre via the capacitor 36.

[0112] In this example, the first pre-spike pulse is high active. The potential of the source line SL is controlled by the input circuit 20a. The potential of the source line SL is set to the ground level (0V) in the recognition mode. In the learning mode, the potential of the source line SL is usually set to the ground level, but is changed in synchronization with the output of the first pre-spike pulse. Specifically, the potential of the source line SL is made positive, i.e., higher than the ground level, during a period of time Tw from the time when the first pre-spike pulse falls, and the potential of the source line SL is made negative, i.e., lower than the ground level, during the subsequent period of time Tw. The magnitude (absolute value) of the potential of the source line SL relative to the ground level at this time is determined so that a write current required to change the magnetization state of the MTJ element 71 can be passed through the MTJ element 71.

[0113] A second post-spike pulse is supplied to the second post-spike line POLb from the neuron circuit 17. The second post-spike pulse is delayed by a time Tw from the first post-spike pulse and is generated by the neuron circuit 17 as having the same pulse width as the first post-spike pulse, for example. Note that in this example, the first post-spike pulse is not supplied to the synapse circuit 11.

[0114] In the learning mode, the input circuit 20a makes the potential of the source line SL positive for a time Tw immediately after outputting the first pre-spike pulse, and makes the potential of the source line SL negative for the following time Tw. On the other hand, when the neuron circuit 17 outputs the first post-spike pulse, it outputs a second post-spike pulse with a delay of a time Tw from the first post-spike pulse. The second post-spike pulse turns on the MOS transistor 73, and the MTJ element 71 is connected between the source line SL and the ground. Therefore, when the second post-spike pulse is output and the MOS transistor 73 turns on during a period in which the potential of the source line SL is positive or negative, a write current flows through the MTJ element 71 in a direction according to the potential of the source line SL.

[0115] For example, if the first pre-spike pulse precedes the first post-spike pulse and the pulse time difference ΔT between them is equal to or less than time Tw, the second post-spike pulse is input to the weight memory unit 70 when the potential of the source line SL is positive. Therefore, when the MOS transistor 73 is turned on, a write current flows from the source line SL to the MTJ element 71, and the MTJ element 71 enters an anti-parallel state. Therefore, the first coupling weight is written to the weight memory unit 70.

[0116] On the other hand, if the first post-spike pulse precedes the first pre-spike pulse and the pulse time difference ΔT between them is equal to or less than time Tw, the second post-spike pulse is input to the weight memory unit 70 when the potential of the source line is negative. Therefore, when the MOS transistor 73 is turned on, a write current flows from the MTJ element 71 to the source line SL, and the MTJ element 71 enters the parallel state. Therefore, the second coupling weight is written to the weight memory unit 70.

[0117] When either the first post-spike pulse or the first pre-spike pulse precedes the other by more than time Tw, the MOS transistor 73 is turned on when the potential of the source line SL is at the ground level, and therefore no write operation of the coupling weight is performed.

[0118] The load memory unit 80 shown in FIG. 17 is configured using a three-terminal MTJ element 81. The MTJ element 81 has a structure in which a laminate in which a magnetization fixed layer 81a and a magnetization free layer 81b are laminated with an insulating film 81c sandwiched therebetween is provided on a channel layer 81d. The laminate is laminated in the order of the magnetization free layer 81b, the insulating film 81c, and the magnetization fixed layer 81a from the channel layer 81d side. The magnetization fixed layer 81a and the magnetization free layer 81b are formed of a ferromagnetic material. The insulating film 81c is formed of a non-magnetic insulator. The channel layer 81d is a conductive layer containing an antiferromagnetic material, and is formed in a plate shape extending in one direction. The laminate is provided in the center of one surface of the channel layer 81d.

[0119] The magnetization direction of the magnetization fixed layer 81a is fixed in one direction perpendicular to the film surface (the vertical direction in FIG. 17), for example, and the magnetization free layer 81b has an easy axis of magnetization perpendicular to the film surface, and the magnetization direction can be changed to either a parallel state in the same direction as the magnetization fixed layer 81a or an antiparallel state in the opposite direction. This MTJ element 81 can change the magnetization direction of the magnetization free layer 81b by the action of a spin orbit torque generated by passing a write current in the extension direction of the channel layer 81d, and the magnetization direction of the magnetization free layer 81b can be made to correspond to the direction of the write current. The magnetization directions of the magnetization fixed layer 81a and the magnetization free layer 81b may be parallel to the film surface.

[0120] The MTJ element 81 is connected to each part with the upper surface of the magnetization fixed layer 81a (the surface opposite to the surface on which the insulating film 81c is formed) and one end and the other end in the extending direction of the channel layer 81d serving as terminals. In the MTJ element 81, the upper surface of the magnetization fixed layer 81a is connected to a power supply line PL via a MOS transistor 82, one end of the channel layer 81d is grounded via a MOS transistor 83, and the other end is connected to a source line SL.

[0121] MOS transistors 82, 83 are connected to a pre-spike line PrL and a second post-spike line POLb, similar to the MOS transistors 72, 73 in the example of Fig. 16. Moreover, control of the potential of source line SL and the generation timing of the second post-spike pulse are the same as in the example of Fig. 16.

[0122] The MTJ element 81 applies a read voltage to the stack, passes a read current through it, and can determine the resistance of the MTJ element 81 (stack) from the read voltage and read current. In this example, as in the above examples, a voltage signal Vpre corresponding to the magnetization state (resistance value) of the MTJ element 81 is output. Specifically, the potential of the top surface of the magnetization fixed layer 81a when the MOS transistor 82 is turned on is output to the output line OL as the voltage signal Vpre via the capacitor 36.

[0123] 17, as in the example of FIG. 16, during a period in which the potential of the source line SL is controlled to be positive or negative, a second post-spike pulse is input to the weight memory unit 80, changing the direction of the write current flowing through the channel layer 81d. As a result, when either the first post-spike pulse or the first pre-spike pulse precedes the other and the pulse time difference between these is equal to or less than the specified time Tw, the MTJ element 81 is magnetized in a state according to the order of the first post-spike pulse and the first pre-spike pulse. As a result, a coupling weight can be written to the synapse circuit 11 according to the order of the first post-spike pulse and the first pre-spike pulse.

[0124] 16 and 17, the change in the potential of the source line that changes in a pulse shape higher than the ground level is the first time window pulse, the change in the potential of the source line that changes in a pulse shape lower than the ground level is the second time window pulse, and the second post-spike pulse is the common write pulse.

[0125] The memory element that stores the coupling load in a non-volatile manner is not limited to the MTJ element. As such a memory element, one that stores data by utilizing the difference in electrical resistance can be preferably used. For example, a phase change element used in a phase change memory (PCRAM: Phase Change Random Access Memory) that changes the phase state of a phase change material by Joule heat generated when a current is passed through a phase change material layer to rewrite data, a resistive change element used in a ReRAM (Resistive RAM, Resistive Random Access Memory) that changes the resistance value of an oxide layer of a load storage section by applying a voltage pulse, etc. can be mentioned. In addition, a ferroelectric memory element having a ferroelectric capacitor used in a ferroelectric memory (Ferroelectric Random Access Memory) can also be used as a memory element that stores the coupling load in a non-volatile manner. In addition, other binary non-volatile memory elements, such as a NAND / NOR type flash memory element, can also be used.

[0126] In addition, in the above, an example of storing the connection weights in a non-volatile manner as the weight memory unit has been described, but the present invention can also be used in a volatile circuit configuration that stores the connection weights only while power is being supplied, such as SRAM or DRAM.

[0127] The load memory unit 90A shown in Fig. 18 has a circuit configuration similar to that of an SRAM, in which an inverter 21A consisting of a MOS transistor 91a and a MOS transistor 91b connected in series and an inverter 22A consisting of a MOS transistor 92a and a MOS transistor 92b connected in series are cross-coupled. Note that, except for the details described below, the load memory unit 90A is the same as the second or third embodiment.

[0128] The MOS transistors 91a and 92a serving as drive transistors are N-type MOSFETs, and the MOS transistors 91b and 92b serving as load transistors are P-type MOSFETs. The sources of the MOS transistors 91b and 92b are directly connected to a power supply line PL, and the sources of the MOS transistors 91a and 92a are connected to a source line SL. This allows power to be continuously supplied to the inverters 21A and 22A to hold a coupling load. The coupling load is held as a combination of on and off states of the MOS transistors 91a and 91b (or MOS transistors 91b and 92b).

[0129] A connection node SN where the drains of the MOS transistors 91a and 91b are connected to each other is connected to the bit line BL via the MOS transistor 23, and is also connected to the gates of the MOS transistors 92a and 92b of the inverter 22A. A connection node SNB where the drains of the MOS transistors 92a and 92b are connected to each other is connected to the bit line BLB via the MOS transistor 24, and is also connected to the gates of the MOS transistors 91a and 92a of the inverter 21A.

[0130] In this load memory unit 90A, a switch unit 93 is provided together with a capacitor 36 as an output circuit unit. The capacitor 36 and the switch unit 93 are connected in series, and one end of the capacitor 36 is connected to the connection node SNB via the switch unit 93. The switch unit 93 is turned on when the first pre-spike pulse is input, and is connected to the pre-spike line PrL. In response to the first pre-spike pulse, a voltage signal Vpre corresponding to the coupling weight stored in the load memory unit 90A is output from the other end of the capacitor 36. Note that the switch unit 93 is preferably a circuit having characteristics close to an ideal switch, in which the on-resistance when on is 0Ω and the off-resistance when off is infinite, such as a circuit configuration using a CMOS.

[0131] For example, when the MOS transistor 91a is off (the MOS transistor 91b is on) and the MOS transistor 92a is on (the MOS transistor 92b is off), the connection node SNB becomes the L level (0 V) and a voltage signal of 0 V is output. On the other hand, when the MOS transistor 91a is on (the MOS transistor 91b is off) and the MOS transistor 92a is off (the MOS transistor 92b is on), the connection node SNB becomes the H level and a relatively high voltage signal is output.

[0132] In the weight memory unit 90A, in the learning mode, a second post-spike pulse is generated as in the second or third embodiment, and the writing of the first or second coupling weight is controlled by switching the potentials of the bit lines BL and BLB. The potentials of the bit lines BL and BLB are changed between a state where the bit line BL is at H level and the bit line BLB is at L level, and a state where the bit line BL is at L level and the bit line BLB is at H level, instead of the positive or negative of the bit line potential difference ΔVB. For example, when writing the first coupling weight, the bit line BL is set to L level and the bit line BLB to H level, and when writing the second coupling weight, the bit line BL is set to H level and the bit line BLB to L level.

[0133] In the example of FIG. 18, load transistors are used, but instead of each load transistor, a resistive element 96 may be used as in a load memory section 90B shown in FIG.

[0134] In the above examples, a voltage signal is output as a weighted pre-spike pulse, but a current signal whose current is increased or decreased according to the coupling weight may be output as a weighted pre-spike pulse. In the example shown in Fig. 20, the output circuit section of weight memory section 64 is configured to output a current signal as a weighted pre-spike pulse.

[0135] The output circuit section is composed of a MOS transistor 98 made of a P-type MOSFET. Therefore, the MOS transistor 98 is provided instead of the capacitor 36 (see FIG. 9). The source of the MOS transistor 98 is connected to the connection node SNB, and the drain is connected to the output line OL. The gate of the MOS transistor 98 is connected to the pre-spike line PrL. In this way, in response to the first pre-spike pulse, the MOS transistors 25 and 98 are each turned on, so that a current signal Ipre corresponding to the coupling weight stored in the weight memory section 97 can be output. When a current signal is used, a circuit for integrating the current may be provided in the neuron circuit.

[0136] Similarly, the other weight memories can be configured to output a current signal as a weighted pre-spike pulse. In the example shown in FIG. 21, the output circuit unit of the weight memory unit 14 is configured to output a current signal Ipre. Similarly, in the example shown in FIG. 22, the output circuit unit of the weight memory unit 70 is configured to output a current signal Ipre, and in the example shown in FIG. 23, the output circuit unit of the weight memory unit 80 is configured to output a current signal Ipre. In the output circuit units of these weight memories 70 and 80, the first pre-spike pulse is high active, so that a MOS transistor 98A, which is an N-type MOSFET, is used as the output circuit unit. In the example shown in FIG. 24, the output circuit unit of the weight memory unit 90A is configured to output a current signal Ipre, and in the example shown in FIG. 25, the output circuit unit of the weight memory unit 90B is configured to output a current signal Ipre. The configuration of the output circuit unit can be changed as appropriate. [Explanation of symbols]

[0137] 10, 60 Neural network circuit device 11 Synaptic Circuits 14, 64, 64A~64D, 70, 80, 90A, 90B Load memory section 17 Neuronal Circuits 20a Input circuit 31, 33, 71, 81 MTJ elements 66a~66d Delay circuit

Claims

1. A method for driving a synapse circuit, comprising: a weight memory section for storing either a first connection weight or a second connection weight as a synaptic connection weight; the weight memory section is connected between a pre-neuron circuit and a post-neuron circuit; a pre-spike pulse input from the pre-neuron circuit is weighted by the synaptic connection weight to generate a weighted pre-spike pulse; and the synaptic connection weight is written based on a time difference between the pre-spike pulse and the post-spike pulse output from the post-neuron circuit, the method comprising the steps of: a first time window pulse that defines a first time window that allows writing of the synaptic connection weight to the weight memory unit when the pre-spike pulse precedes the post-spike pulse is input from one of the pre-neuron circuit and the post-neuron circuit to the synapse circuit, and a first write pulse that is a write timing of the synaptic connection weight to the weight memory unit and has a pulse width shorter than that of the first time window pulse is input from the other of the pre-neuron circuit and the post-neuron circuit to the synapse circuit; a second time window pulse that defines a second time window that allows writing of the synaptic connection weight to the weight memory unit when the post-spike pulse precedes the pre-spike pulse is input from one of the pre-neuron circuit and the post-neuron circuit to the synapse circuit, and a second write pulse that is a write timing of the synaptic connection weight to the weight memory unit and has a pulse width shorter than that of the second time window pulse is input from the other of the pre-neuron circuit and the post-neuron circuit to the synapse circuit; When the first time window pulse and the first write pulse are simultaneously input to the synapse circuit, and when the second time window pulse and the second write pulse are simultaneously input to the synapse circuit, the weight memory unit performs a write operation. A method for driving a synapse circuit comprising:

2. outputting the second time window pulse from the post-neuron circuit in synchronization with the post-spike pulse, and inputting the post-spike pulse as the first write pulse to the synapse circuit; The first time window pulse is output from the pre-neuron circuit in synchronization with the pre-spike pulse, and the pre-spike pulse is input to the synapse circuit as the second write pulse.

2. The method for driving a synapse circuit according to claim 1.

3. a bit line having a potential corresponding to the synaptic coupling weight written by the post-neuron circuit is connected to the weight storage unit; outputting one common time window pulse, which becomes the first time window pulse and the second time window pulse, from the pre-neuron circuit in synchronization with the pre-spike pulse; The post-neuron circuit As the first write pulse, the potential of the bit line is changed in a pulsed manner to a first potential corresponding to the first coupling weight in synchronization with the post-spike pulse, and after a time window length defined by the common time window pulse has elapsed since the change to the first potential, the potential of the bit line is changed in a pulsed manner to a second potential corresponding to the second coupling weight as the second write pulse.

2. The method for driving a synapse circuit according to claim 1.

4. a bit line having a potential corresponding to the synaptic coupling weight written by the post-neuron circuit is connected to the weight storage unit; the post-neuron circuit changes the potential of the bit line in a pulsed manner to a first potential corresponding to the first coupling weight in synchronization with the pre-spike pulse, thereby inputting the first time window pulse to the synapse circuit, and then changes the potential of the bit line in a pulsed manner to a second potential corresponding to the second coupling weight, thereby inputting the second time window pulse to the synapse circuit; A common write pulse which becomes the first write pulse and the second write pulse is output from the pre-neuron circuit by delaying the common write pulse from the pre-spike pulse.

2. The method for driving a synapse circuit according to claim 1.

5. the synapse circuit includes a plurality of the weight memories, The common write pulse delayed by different delay times from the pre-spike pulse is input to each of the weight memories, and the number of the weight memories in the synapse circuit to which the first connection weight and the second connection weight are written is changed based on the timing of the post-spike pulse and the pulse time difference.

5. The method for driving a synapse circuit according to claim 4.

6. 6. The method for driving a synapse circuit according to claim 5, further comprising the step of: presetting the number of said weight memories corresponding to each delay time of said common write pulse and each delay time in said synapse circuit.

7. 4. The method for driving a synapse circuit according to claim 1, wherein the first write pulse and the second write pulse are each input to the synapse circuit a plurality of times when writing the synapse connection weight to one of the weight memory units.

8. 6. The method for driving a synapse circuit according to claim 4, wherein the common write pulse is input to each of the synapse circuits a plurality of times when the synapse connection weight is written once to one of the weight storage sections.

9. The load memory unit has a pair of inverters, each of which is cross-coupled and includes an inverter MOS transistor and a magnetic tunnel junction element connected in series, operating the pair of inverters in response to the input of the pre-spike pulse, and outputting the weighted pre-spike pulse based on a potential at an output end of one of the pair of inverters; During a write operation, a write current based on the synapse connection weight is passed through each of the magnetic tunnel junction elements of the pair of inverters, thereby causing the magnetic tunnel junction elements to have different magnetization states.

2. The method for driving a synapse circuit according to claim 1.

10. the weight storage unit non-volatilely stores the synaptic connection weights based on the magnetization state of a magnetic tunnel junction element; 2. The method for driving a synapse circuit according to claim 1, further comprising the step of connecting a power supply line and the magnetic tunnel junction element in response to an input of the prespike pulse, thereby outputting the weighted prespike pulse according to a magnetization state.

11. A preneuron circuit that outputs a prespike pulse; A post-neuron circuit that outputs a post-spike pulse. a synapse circuit having a weight memory section for storing either the first connection weight or the second connection weight as a synapse connection weight, connected between the pre-neuron circuit and the post-neuron circuit, for outputting a weighted pre-spike pulse obtained by weighting the pre-spike pulse with the synapse connection weight to the post-neuron circuit, and for writing the synapse connection weight based on the lead-in and lead-out times and pulse time difference between the pre-spike pulse and the post-spike pulse; a first pulse generator for inputting a first time window pulse to said synapse circuit, said first time window pulse defining a first time window during which said synaptic connection weights are allowed to be written to said weight storage unit when said pre-spike pulse precedes said post-spike pulse; a second pulse generator for inputting a first write pulse, which is a write timing of the synapse connection weight of the weight memory unit and has a pulse width shorter than that of the first time window pulse, to the synapse circuit; a third pulse generator for inputting to said synapse circuit a second time window pulse defining a second time window during which said synaptic connection weights are allowed to be written into said weight storage unit when said postspike pulse precedes said prespike pulse; a fourth pulse generator for inputting a second write pulse, which is a write timing of the synapse connection weight of the weight memory unit and has a pulse width shorter than that of the second time window pulse, to the synapse circuit; Equipped with The first pulse generator is provided in one of the pre-neuron circuit and the post-neuron circuit, and the second pulse generator is provided in the other of the pre-neuron circuit and the post-neuron circuit, The third pulse generator is provided in one of the pre-neuron circuit and the post-neuron circuit, and the fourth pulse generator is provided in the other of the pre-neuron circuit and the post-neuron circuit, The synapse circuit performs an operation of writing the synapse connection weight to the weight storage unit when the first time window pulse and the first write pulse are input simultaneously and when the second time window pulse and the second write pulse are input simultaneously. A neural network circuit device comprising:

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