Radio Frequency Circuits for Phased Array Antennas

Abstract

To provide a wireless communication system that can be manufactured at low cost and operates with less power.SOLUTION: In a wireless communication system, an RF circuit board includes a board 202, an interconnect structure 204 arranged on the board 202, a plurality of antennas 206, and a plurality of RF chips 208 arranged in a row and coupled to the antennas 206, for providing a plurality of radio-frequency (RF) output signals to the plurality of antennas 206 according to an RF signal. The RF circuit board further includes a transmission line arranged to be a straight line in parallel to the row, and to connect to the RF chips 208, and a resistive load, coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive the RF signal. The RF chips 208 are evenly distributed and arranged between the first end and the second end and connect to the transmission line.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] (PRIORITY CLAIM AND CROSS REFERENCE) This application claims priority to U.S. Provisional Application No. 63 / 367,030, filed June 24, 2022, and U.S. Non-Provisional Application No. 18 / 065,934, filed December 14, 2022, the disclosures of which are incorporated by reference in their entireties herein.

[0002] The present invention relates to radio frequency circuits for phased array antennas. [Background technology]

[0003] In modern wireless communication technology, phased array antenna technology has attracted much attention because of its advantages such as high gain, high reliability, and beam steering capability compared with traditional antenna technology. Phased array antenna technology employs an array of antennas organized with proper management of antenna spacing, so the board area on which the array antenna is placed is much larger than that of traditional non-array antennas. The planarity of the board is one of the key challenges for developing large-scale antenna arrays at an acceptable cost. Meanwhile, high-frequency circuits with high circuit density and low power consumption are required to improve the signal processing performance of antenna arrays. Therefore, it is necessary to develop a new architecture for phased array antennas to solve the board problem and enable the formation of RF circuits and antennas with low cost and high performance. Summary of the Invention

[0004] An embodiment of the present disclosure proposes a wireless communication system including a plurality of antennas and a plurality of RF chips arranged in a row and coupled to the antennas for providing a plurality of radio frequency (RF) output signals to the antennas according to an RF signal. The wireless communication system also includes a transmission line arranged in a straight line parallel to the row and connected to the RF chips, and a resistive load coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive the RF signal.

[0005] According to an embodiment of the present disclosure, a wireless communication system includes a plurality of antennas, a plurality of RF chips organized in rows and coupled to the antennas for receiving a plurality of radio frequency (RF) signals from the antennas and outputting a plurality of RF output signals, transmission lines organized in a straight line parallel to the rows and connected to the RF chips for receiving the RF output signals, and a resistive load coupled to a first end of the transmission line, and a second end of the transmission line arranged to output a cumulative RF output signal of the RF output signals.

[0006] Through the proposed arrangement of phased array antennas and RF chips, transmitters and receivers can be manufactured more cheaply and can operate with less power, while improving device reliability. [Brief description of the drawings]

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact, dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] [Figure 1] 1 is a schematic diagram illustrating a wireless communication system in a next generation communication scenario, in accordance with some embodiments of the present disclosure. [Figure 2A] 2 is a schematic perspective view of a transmitter or receiver of a user device according to some embodiments. [Figure 2B] 2B is an expanded view of a portion of the transmitter or receiver shown in FIG. 2A according to some embodiments. [Figure 2C] 2C is a schematic cross-sectional view of the transmitter or receiver shown in FIG. 2B according to some embodiments. [Figure 3A] 2 is a schematic block diagram of a transmitter according to some embodiments. [Figure 3B] 3B is a schematic block diagram of a transmitter array of the transmitter shown in FIG. 3A according to some embodiments. [Figure 3C] FIG. 3C is a schematic block diagram of a transmitter block of the transmitter array shown in FIG. 3B according to some embodiments. [Figure 3D] 3D shows a schematic block diagram of the RF chip shown in FIG. 3C and an equivalent circuit of the input of the RF chip, according to some embodiments. [Figure 4A] 2 is a schematic block diagram of a receiver according to some embodiments. [Figure 4B] 4B is a schematic block diagram of a receiver array of the receiver shown in FIG. 4A according to some embodiments. [Figure 4C] FIG. 4C is a schematic block diagram of a receiver block of the receiver array shown in FIG. 4B according to some embodiments. [Figure 4D] 4D shows a schematic block diagram of the RF chip shown in FIG. 4C and an equivalent circuit of the input of the RF chip, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, spatially relative terms such as "below," "under," "lower," "upper," "top," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the present disclosure are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors necessarily resulting from the standard deviation found in each testing measurement. Also, as used herein, the terms "about", "substantial", or "substantially" generally mean within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the terms "about", "substantial", and "substantially" mean within an acceptable standard error of the mean as considered by one of ordinary skill in the art. Other than in the operating / operating examples, or unless otherwise indicated, all numerical ranges, amounts, values ​​and percentages, such as amounts of materials, durations, temperatures, operating conditions, ratios of amounts, etc., disclosed herein should be understood as being modified in all instances by the terms "about", "substantial", or "substantially". Thus, unless indicated to the contrary, the numerical parameters set forth in this disclosure and the appended claims are approximations that may be varied as desired. At the very least, each numerical parameter should be construed by applying ordinary rounding techniques in light of the number of reported significant digits. Ranges can be expressed herein as from one endpoint to another endpoint, i.e., between two endpoints. All ranges disclosed herein include the endpoints unless otherwise stated.

[0012] As used herein, the term “connected” may be interpreted as “electrically connected,” and the term “coupled” may be interpreted as “electrically coupled.” “Connected” and “coupled” may be used to indicate that two or more elements co-operate or interact with each other.

[0013] FIG. 1 is a schematic diagram illustrating a wireless communication system 10 in a next-generation communication scenario, according to some embodiments of the present disclosure. The wireless communication system 10 includes one or more user devices 12, 14, 16, 18, a terrestrial base station 22, and a non-terrestrial base station 24. In some embodiments, the user devices 12, 14 are carried or moved by humans and are referred to as handheld devices. In some embodiments, the user device 16 is a mobile device mounted on a vehicle moving on land, such as an automobile, a train, etc. In some embodiments, the user device 18 is a user device mounted on a vessel moving on seas, rivers, etc.

[0014] In some embodiments, the terrestrial base station 22 is an example of a base station deployed in a communication network, such as a cellular communication network. The terrestrial base station 22 is configured to provide a communication network for the user devices 12, 14, and 16, which can transmit or receive information between each other through the network established by the plurality of terrestrial base stations 22. The terrestrial base station 22 may also be referred to as a low altitude platform. In some embodiments, the non-terrestrial base station 24 is an example of a communication satellite deployed in a communication satellite network. The non-terrestrial base station 24 is configured to provide a communication network for the user devices 12, 14, 16, and 18, which can transmit or receive information between each other through the satellite network. The plurality of terrestrial base stations 22 and the plurality of non-terrestrial base stations 24 can be linked together to form a combined communication network, which can provide a global communication network that covers user devices around the world, whether they are located at low altitude locations, high altitude locations, or locations not covered by the network of the terrestrial base stations 22.

[0015] To achieve the goal of a global communication network exemplified by the wireless communication system 10, the user equipment 12, 14, 16 or 18 may need to be redesigned to include a transmitter or receiver with greater communication capabilities to communicate with the non-terrestrial base station 24 located at high altitude. Among various transmitter or receiver designs, phased array antenna technology can significantly increase the transmission or reception gain with higher reliability, and is a promising solution for realizing beamforming technology suitable for satellite communication.

[0016] 2A is a schematic perspective view of a transmitter 100 of the user equipment 12, 14, 16 or 18 shown in FIG. 1 according to some embodiments. In some embodiments, the transmitter 100 is an RF transmitter. In some embodiments, the transmitter 100 includes a control circuit board 110, an RF circuit board 120, and a connection circuit board 130 that electrically connects the RF circuit board 120 to the control circuit board 110. Furthermore, the RF circuit board 120 includes an antenna array formed with an array of antenna elements 140, such as antenna patches, formed on the substrate of the RF circuit board 120. In some embodiments, the transmitter 100 is applicable to a terrestrial base station 22 or a non-terrestrial base station 24.

[0017] In some embodiments, the control circuit board 110 is a printed circuit board (PCB) and includes a substrate on which a number of circuit chips and wiring are formed. In some embodiments, the control circuit board 110 includes one or more semiconductor dies, such as a semiconductor die 150 mounted on a surface of the control circuit board 110. The substrate of the control circuit board 110 may be formed of an epoxy resin with a metal (e.g., copper) foil. The control circuit board 110 is configured to generate control signals and data signals and provide these signals to the RF circuit board 120 via the connection circuit board 130. The data signals may be baseband signals or IF signals modulated by a modulated carrier at a predetermined frequency, e.g., an intermediate frequency (IF) of 455 kHz. In some embodiments, the control circuit board 110 is configured to convert a first voltage potential to a second voltage potential and transmit an appropriate power supply voltage to the RF circuit board 120. In some embodiments, the connection circuit board 130 includes a flexible or non-flexible substrate and includes a number of transmission lines configured to transmit the power supply voltage, the control signals, and the IF data signals to the RF circuit board 120.

[0018] In some embodiments, the user devices 12, 14, 16, and 18 also have a receiver (not shown separately) that works with the transmitter 100 to achieve bidirectional communication. The configuration of the transmitter 100 shown in FIG. 2A can also be applied to the receiver 101 (see FIG. 4A), which also has a control circuit board 111, an RF circuit board 121, and a connection circuit board 130 that are interconnected in a similar manner to the transmitter 100. The user devices 12, 14, 16, and 18 may include both the transmitter 100 and the receiver 101 to form a wireless communication system. The differences between the transmitter 100 and the receiver 101 will be described below.

[0019] FIG. 2B is a close-up view of a portion A1 of the RF circuit board 120 shown in FIG. 2A, according to some embodiments. Note that the vertical direction (positive Z-axis) of the RF circuit board 120 shown in FIG. 2B is reversed with respect to FIG. 2A. In some embodiments, the RF circuit board 120 includes a substrate 202 and an interconnect structure 204 arranged on the substrate 202. The interconnect structure 204 has a top surface, and the substrate 202 has a bottom surface. In some embodiments, an array of antenna elements 206 is formed on the bottom surface of the substrate 202, and a plurality of RF chips 208 are arranged on the top surface of the interconnect structure 204. The RF chips 208 may be interconnected via a plurality of conductive lines 210. In some embodiments, the conductive lines 210 may be encapsulated by an electrically insulating material or may be exposed through a surface of the interconnect structure 204. In some embodiments, the array of antennas of the transmitter 100 includes a patch antenna structure, and the antenna elements 206 are antenna patches of the respective antenna structures.

[0020] FIG. 2C is a schematic cross-sectional view of the RF circuit board 120 shown in FIG. 2B according to some embodiments. The schematic cross-sectional view shown in FIG. 2C is taken from the cross-sectional line AA in FIG. 2B. Referring to FIG. 2C, the substrate 202 is formed of a transparent material such as glass, fused silica, silicon oxide, quartz, etc. In some embodiments, the substrate 202 separates the antenna element 206 from the electronic circuitry of the interconnect structure 204 or the RF chip 208. In some embodiments, the RF signal is transmitted from the RF chip 208 formed on the upper side of the substrate 202 through the RF circuitry formed on the interconnect structure 204, radiated across the transparent substrate 202, and coupled to the antenna element 206 formed on the lower side of the substrate 202. In some embodiments, the thickness of the substrate 202 is determined based on the operating frequency of the antenna element 206. Because the material of the substrate 202 is transparent to the RF signal, the substrate 202 may not have a conductive member to connect the interconnect structure 204 to the antenna element 206.

[0021] In some embodiments, the interconnect structure 204 is formed of multiple metallization layers in a stack. The metallization layers include patterned conductive lines or conductive vias that are patterned or electrically interconnected to form interconnect paths and other portions of the antenna. For example, a first metallization layer formed on the substrate 202 includes a first conductive line or pad 222A. The first conductive line or pad 222A may be used as a ground plane, and the remaining space may be formed as an aperture for coupling RF signals to the antenna elements 206. A second metallization layer is formed on the first metallization layer and includes first conductive vias, including exemplary first conductive via 224A. Similarly, a third metallization layer is formed on the second metallization layer and includes a second conductive line or pad 222B, and a fourth metallization layer is formed on the third metallization layer and includes multiple second conductive vias, including exemplary second conductive via 224B. The second conductive line may be patterned to form a power line or a signal transmission line. A fifth metallization layer is formed on the fourth metallization layer and includes a third conductive line 222C. The third conductive line 222C may be patterned to form a transmission line for communicating RF or control signals between the RF chips 208. In some embodiments, the conductive lines 222A, 222B, 222C are interconnected through conductive vias 224A, 224B. In some embodiments, a plurality of conductive lines 210 are arranged on the sixth metallization layer and electrically connect the conductive line 222C to the RF chips 208.

[0022] In some embodiments, the conductive lines 222A, 222B, 222C, and 210 and the conductive vias 224A and 224B are formed of a conductive material such as copper, tungsten, aluminum, titanium, tantalum, alloys thereof, etc. The conductive lines 222A, 222B, 222C, and the conductive vias 224A, 224B are further electrically insulated by an insulating material 226A, 226B, or 226C, such as a polymer-based material, e.g., polyimide or epoxy resin.

[0023] Figure 3A is a schematic block diagram of the transmitter 100 shown in Figure 2A according to some embodiments. With reference to Figures 2A and 3A, in some embodiments, the control circuit board 110 includes a power conversion module 312, a memory module 314, a controller 316, a local oscillator module 318, and a data processing module 322. The control circuit board 110 is configured to provide a power supply voltage VD, an IF data signal IF_in, a reference frequency signal LO, and control signals (including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC) to the RF circuit board 120 through input / output ports on both sides of the connection circuit board 130 and signal lines of the connection circuit board 130.

[0024] In some embodiments, the power conversion module 312 is configured to receive input power from a power supply voltage source 302 external to the control circuit board 110. The power conversion module 312 may include a voltage converter configured to convert an initial power supply voltage (e.g., 110V) of the power supply voltage source 302 to a power supply voltage VD (e.g., 5V or 1.2V) for the components of the RF circuit board 120. The power conversion module 312 may further provide power to other components of the control circuit board 110, such as the memory module 314, the controller 316, the local oscillator module 318, and the data processing module 322. In some embodiments, the power conversion module 312 includes a voltage converter for providing the power supply voltage VD. In some embodiments, the power conversion module 312 further includes an electromagnetic interference filter for filtering interference.

[0025] In some embodiments, the memory module 314 is configured to store data and commands, e.g., transmission data, accessible by the controller 316 and the data processing module 322. The memory module 314 may include different types of memory, e.g., random access memory (RAM), read only memory (ROM), flash memory, cache memory, etc.

[0026] In some embodiments, the controller 316 is configured to generate an IF data signal IF_in by modulating the transmission data with an IF modulated carrier. The transmission data may be provided by the data processing module 322. The IF data signal IF_in will be upconverted by the RF circuit board 120 to become an RF signal RF_in.

[0027] In some embodiments, the controller 316 is further configured to generate control signals for calibration of the RF signal, such as calibration data Din, a data clock signal CLK, and a synchronous clock signal SYNC. In some embodiments, the calibration data Din is used to calibrate the amplitude or phase of the RF signal RF_in according to the transmission data or command. The calibration data may include amplitude calibration data or phase calibration data, or both. In some embodiments, the data clock signal CLK is used to provide a general-purpose clock to registers in the components of the RF circuit board 120. The frequency of the data clock signal CLK may represent the working frequency of the digital data processing in the RF circuit board 120. In some embodiments, the synchronous clock signal SYNC is used to provide a clock for some of the registers in different stages to output the calibration data at the same clock time. The synchronous clock signal SYNC may represent the update rate of the calibration data. In some embodiments, the control signals include a digital format, so they are also referred to as digital control signals.

[0028] The local oscillator module 318 is configured to generate a reference frequency signal FR for up-conversion or down-conversion between the IF signal IF_in and the RF signal RF_in. In some embodiments, the local oscillator module 318 includes a crystal oscillator configured to generate a reference frequency signal FR of a predetermined frequency.

[0029] In some embodiments, the data processing module 322 is configured to receive input data or commands from the control unit 304 external to the control circuit board 110. The data processing module 322 may also be configured to transmit output data provided by the controller 316. In some embodiments, the data processing module 322 includes a network interface circuit configured to receive or transmit data or commands under a transmission protocol. The data processing module 322 may be configured to extract transmission data or control signals from the input data.

[0030] In some embodiments, the RF circuit board 120 includes a pair of RF signal generating paths, a pair of power divider networks 342, and two rows of the transmitter array 300. Each RF signal generating path includes an IF signal receiver 332, a phase locked loop module 334, amplifiers 335 and 338, and a mixer 336.

[0031] In some embodiments, each of the power divider networks 342 is connected to the output of a corresponding mixer 336 and configured to deliver an RF signal RF_in to each RF chip 208 (see FIG. 3C ). In some embodiments, the power divider network 342 is a multi-stage power divider network formed from multiple power dividers 344 connected in a tree or binary structure. ... 1 and K 2 Including row K 1 Or K 2 Each power divider 344 of stages K is configured to distribute the power of the RF signal RF_in substantially equally to the two outputs of the power divider 344. 2Each output of the power divider 344 is connected to a corresponding transmitter array 300. In some embodiments, the left power divider network 342 and the right power divider network 342 are organized symmetrically about a centerline between the left power divider network 342 and the right power divider network 342. In some embodiments, the left column of the transmitter array 300 and the right column of the transmitter array 300 are organized symmetrically about a centerline between the left column of the transmitter array 300 and the right column of the transmitter array 300. In some embodiments, the power divider 344 can also be used as a power combiner in a receiver architecture, where the input and output terminals of the power divider 344 are inverted to the output and input terminals of the power combiner.

[0032] In some embodiments, control signals including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC are provided to each of the transmitter arrays 300 via a bus or multiple signal lines. In some embodiments, the illustrated embodiment shows only two stages of the power divider network 342. However, power divider networks 342 having more or less than two stages can also be applied to the transmitter 100 in other embodiments. In some embodiments, the illustrated embodiment shows only four transmitter arrays 300 in one column of the transmitter array 300. However, more or less than four transmitter arrays 300 in the array can also be applied to the transmitter 100 in other embodiments, with the number of transmitter arrays 300 being adjusted to the number of stages of the power divider network 342.

[0033] In some embodiments, the IF signal receiver 332 is configured to receive an IF data signal IF_in from the connecting circuit board 130. The phase locked loop module 334 may be configured to generate a local oscillator signal LO based on a reference frequency FR via a phase locked loop. In some embodiments, the local oscillator signal LO is amplified via an amplifier 335. In some embodiments, the amplifier 335 is an op-amp. The mixer 336 is configured to up-convert the IF signal IF_in to an RF signal RF_in at a predetermined operating frequency, for example, 18 GHz, 28 GHz, or other suitable frequency. In some embodiments, the RF signal RF_in is amplified via an amplifier 338. In some embodiments, the amplifier 338 is an op-amp. In some embodiments, more control signals, such as a phase locked loop control signal, are provided to the phase locked loop module 334 from the control circuit board 110.

[0034] 3B is a schematic block diagram of a transmitter array 300 of the transmitter 100 shown in FIG. 3A according to some embodiments. In some embodiments, the transmitter array 300 includes another power divider network 346 and multiple transmitter blocks 310. In some embodiments, the power divider network 346 forms a combined power divider network with the power divider network 342, in which the final stage K N Each of the power dividers 344 is connected to a corresponding transmitter block 310. In some embodiments, the power divider network 346 includes N-2 stages, with each power divider 344 of each stage configured to distribute the power of the RF signal RF_in at the input terminal substantially equally to two output terminals of the power divider 344. In some embodiments, a power supply voltage VD and control signals Din, CLK, SYNC are also provided to each of the transmitter blocks 310 via a bus or multiple signal lines.

[0035] FIG. 3C is a schematic block diagram of a transmitter block 310 of the transmitter array 300 shown in FIG. 3B according to some embodiments. In some embodiments, the transmitter block 310 is formed of a row of RF chips 208 and a row of antenna feeds 212 corresponding to the row of RF chips 208. In some embodiments, the RF chips 208 each include an individual RF circuit, also referred to as an RF circuit 208, as described above with reference to FIG. 2B. In some embodiments, the RF chips 208 are configured as transmitter (TX) RF chips. In some embodiments, a power supply voltage VD is provided and transmitted to each of the RF chips 208. In addition, control signals including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC are provided to each RF chip 208 via one or more signal lines. In some embodiments, an RF signal RF_in is also provided to each RF chip 208 via a transmission line 220. 2B and 3C, in some embodiments, the RF signal RF_in is transmitted through the transmission line 220, the RF chip 208 (output as the RF signal RF_out), the feed line 212 and the substrate 202 to the antenna patch 206 and is radiated outward by the antenna patch 206.

[0036] The RF chip 208 is configured to generate a calibrated RF signal as an RF output signal RF_out after calibration of the RF signal RF_in according to the calibration data Din. In some embodiments, the calibration update rate is controlled by a data clock signal CLK and a synchronization clock signal SYNC. In some embodiments, the RF chip 208 includes input ports for the respective RF signal RF_in, a power supply voltage VD, the calibration data Din, the data clock signal CLK and the synchronization clock signal SYNC. In some embodiments, the RF chip 208 includes output ports for the respective calibration data Dout and two branches of the RF output signal RF_out (i.e., RF component signals RF_out_I and RF_out_Q).

[0037] In some embodiments, the RF output signal RF_out is formed from an in-phase component RF_out_I and a quadrature component RF_out_Q corresponding to a horizontal (H) polarization component and a vertical (V) polarization component, respectively. The separate components RF_out_I and RF_out_Q represent the in-phase component RF_out_I and the quadrature component RF_out_Q and are orthogonal to each other. The separate quadrature components of the RF output signal may aid in the calibration of the RF signal RF_in or the RF output signal RF_out.

[0038] In some embodiments, the data clock signal CLK and the synchronization clock signal SYNC are respectively provided to the input ports of the data clock signal CLK and the synchronization clock signal SYNC of each of the RF chips 208. In some embodiments, the calibration data Din is transmitted from the input port of the calibration data Din to the first (leftmost) RF chip 208 via a signal line, and the first RF chip 208 relays the calibration data Din from the output port Dout of the first RF chip 208 to the second RF chip 20 adjacent to the first RF chip 20 via another signal line. Then, the calibration data Din is transmitted to the input port Din of the calibration data Din of the third RF chip 208. As a result, the calibration data Din is transmitted through the input ports and output ports of the cascaded RF chips 208 until the last (rightmost) RF chip 208. The data read timing may be controlled by the data clock signal CLK and the synchronization signal SYNC.

[0039] In some embodiments, the transmitter block 310 includes the transmission line 220 between a first end, i.e., an input port of the transmitter block 310, and a second end of the transmission line 220. In some embodiments, the second end of the transmission line 220 is grounded through a resistive load 372. In some embodiments, the transmission line 220 is a straight line or a line including multiple line segments extending in different directions. In some embodiments, the transmission line 220 is parallel to the row of RF chips 208. The resistive load 372 may include a resistor. In some embodiments, the resistance of the resistive load 372 is determined to match the impedance of the transmission line 220 to eliminate signal reflections. In some embodiments, the resistive load 372 includes a resistance of about 50 Ω.

[0040] In some embodiments, the RF signal RF_in is propagated from a first end to a second end of the transmission line 220. In some embodiments, in a phased array antenna configuration, adjacent antenna feeds 212 are spaced apart by a predetermined antenna spacing. The antenna spacing may be related to the wavelength of the RF signal RF_in. Furthermore, the RF output signals RF_out_I and RF_out_Q transmitted by the individual antenna feeds 212 need to be modulated with appropriate phase delays according to the phasing data of the calibration data Din to collectively construct a directional RF signal beam. Thus, each of the RF output component signals RF_out_I and RF_out_Q is phase modulated according to one or more design criteria, such as a position in the antenna array.

[0041] In some embodiments, the RF chips 208 may not be arbitrarily arranged on the interconnect structure 204. In some embodiments, the rows of RF chips 208 within the same transmitter block 310 are connected to the connection terminals of the transmission line 220 at different locations Di of the transmission line 220, where the index i represents the i-th RF chip 208 within the transmitter block 310, 1 < i ≦ L, and L can be any integer greater than 1. In some embodiments, the number L is in the range of 2 to 8. The locations Di are spaced apart by a predetermined distance. In some embodiments, the RF chips 208 are equally distributed between the first end and the second end of the transmission line 220. The signal feeding type of the RF chips 208 in the transmitter block 310 using a single transmission line 220 is called the "series power feeding" signal feeding method. The RF signal RF_in may have a phase difference between different locations D1, D2, …, D7, …, DL of the transmission line 220. The undesirable phase delay caused by the different locations D1 to DL may be simultaneously addressed and compensated by the phase adjustment data of the calibration data Din. As a result, without incurring additional costs, the problem of phase inaccuracy of the phased array antenna can be solved.

[0042] The in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are coupled to the antenna patch 206, combined, and radiated outward through the antenna patch 206. The combined RF signal RF_out based on the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q results in a circularly polarized RF signal RF_out. In some embodiments, the combined RF signal RF_out is a right-hand circularly polarized RF signal or a left-hand circularly polarized signal depending on the phase order of the in-phase RF signal RF_out_I relative to the quadrature RF signal RF_out_Q. In some embodiments, the validity of the calibration data Din plays an important role, since the ideal circular polarization of the RF signal output RF_out is achieved by equal amplitudes and precise phase differences of 90° between the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q. In some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are split and independently subjected to amplitude and phase calibration before being transmitted to the antenna patch 206. Furthermore, in some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are received from the antenna patch 206 and are independently subjected to amplitude and phase calibration at the RF chip 208 before they are combined and transmitted from the RF chip 208. Therefore, the calibration task can be easily accomplished without complex calibration circuitry.

[0043] In some embodiments, the RF chip 208 is designed to include an input terminal or port having a high impedance, for example, the input impedance Rin of the RF chip 208 seen by the transmission line 220 through the input terminal 208A or port of the RF chip 208 is relatively high, for example, greater than about 100 kΩ, greater than 500 kΩ, or greater than 1000 kΩ.

[0044] FIG. 3D shows in the left sub-diagram a schematic block diagram of the RF chip 208 shown in FIG. 3C according to some embodiments. In some embodiments, the input port 208A of the RF chip 208 is connected to a field effect transistor (FET) M1, e.g., a metal oxide semiconductor FET (MOSFET), in which the gate terminal M1G or gate electrode is connected to the transmission line 220 via the branch transmission line 221. In some embodiments, the MOSFET M1 is connected to the input port 208A of the RF chip 208 via a capacitor Cp1. In some embodiments, the capacitor Cp1 is connected to the diodes D11 and D12 of the RF chip 208 at the gate terminal M1G. Referring to the right sub-diagram of FIG. 3D, the circuit of the RF chip 208 connected to the input port 208A shown in the left sub-diagram can be represented by an equivalent circuit formed of a capacitor Cp connected in parallel with an input resistor Rp. In some embodiments, the input resistance Rp (or Rin) or input impedance of the RF chip 208 seen from the gate terminal M1G of the RF chip 208 is substantially equal to or greater than 10 times the impedance seen from the input terminal 208A connected to the transmission line 220, for example, about 500Ω or more. In some embodiments, the input resistance Rp, which is equal to the input resistance Rin shown in FIG. 3C, is at least 500Ω or more, 1000Ω or more, or 5000Ω or more. In some embodiments, in order to maintain the high impedance of the input port 208A of the RF chip 208, the MOSFET disposed at the input port 208A of the RF chip 208 is not connected in parallel with other circuits of the RF chip 208. In some embodiments, there is no intermediate circuit, matching network, or buffering circuit between the branch line 221 and the gate terminal M1G of the RF chip 208. In some embodiments, the above-mentioned series-fed signal feed type of the RF signal RF_in is achieved by a voltage-driven signal feed type. The RF output signal RF_out is generated based on a voltage signal delivered at the gate terminal M1G of the input MOSFET M1, rather than a current drive signal.

[0045] Based on the above, the proposed serial signal supply method provides advantages. If the leakage current can be properly managed, the current level flowing into the input port 208A of the RF chip 208 will be very low due to the high impedance of the MOSFET. Therefore, the power consumption of the RF chip 208 will be relatively low without compromising the device performance. Furthermore, since the calibration data of the control signal already includes the phase calibration data in the phased array antenna architecture to assist in the calibration of the RF signal RF_in, no additional phase calibration module for the transmitter block 310 is needed, and the adjustment of the delay phase also covers the phase adjustment or calibration.

[0046] Existing RF chips adopt the transmission of RF signals with a current drive signal supply type, and are accompanied by a tree-type power divider network. The power dividers at the final stage of the tree-type power divider network are respectively connected to the corresponding RF chips. The input ports are designed to follow the impedance matching rule, for example, including an impedance of about 50Ω. The drive current flows from the RF signal source to each RF chip through the tree-type divider network. Such an RF signal supply architecture consumes power when the RF signal is distributed to the RF chips at the end of the power divider network. Although the phase error between the RF chips of the current drive signal supply type can be smaller than that of the voltage drive signal supply type because the transmission lengths of all the RF chips to the RF signal source are substantially equal, still, a non-negligible phase error often occurs due to process-induced device variations. Therefore, a phase calibration module is usually required to ensure the performance of the phased array antenna. In contrast, the proposed voltage drive signal type consumes less power and requires fewer power dividers without compromising device performance. Thus, the proposed antenna array structure allows for improved transmitter power, cost and reliability.

[0047] In some embodiments, the serially powered signal feed of the present disclosure further improves wiring efficiency. With reference to Figures 3A, 3B and 3C, the transmitter array 300 (including the RF chips 208) is organized in a column direction in the center part of the RF circuit board 120, and the peripheral circuits, such as the power divider networks 342 and 346, the amplifiers 335, 338 and the mixer 336, are organized on two sides of the RF circuit board 120. The one-dimensional organization of the transmitter blocks 310 extends in a row direction, in which the antenna spacing and the number of RF chips determine the length / width ratio of the transmitter blocks 310. Taking the number of stages of the transmitter blocks 310 N=5 and the number of RF chips L=8 as an example, the transmitter array of the transmitter 100 forming the resulting transmitter array 300 is 32x32 RF chips 208 in size, and is square-shaped. Furthermore, when wiring the power supply and signal transmission lines of the transmitter block 310, such as the power supply voltage VD, the control signals Din, CLK, SYNC, and the RF signal RF_in, the proportion of wiring crossings is relatively low due to the row shape. As a result, a square phased array antenna can be implemented with high wiring efficiency. Furthermore, the phased array antenna of the present disclosure can be scaled up or down in a simple manner by simply adjusting the numbers N and L without the need to redesign the layout and wiring.

[0048] FIG. 4A is a schematic block diagram of a receiver 101 according to some embodiments. In some embodiments, the receiver 101 is an RF receiver. In some embodiments, the receiver 101 is seen as an intermediary device of the transmitter 100, and the receiver 101 also includes a control circuit board 111, an RF circuit board 121, and a connection circuit board 130 that connects the control circuit board 111 to the RF circuit board 121. The receiver 101 may have a different operating frequency from the transmitter 100 to facilitate dual transmission, for example, one of the transmitter 100 and the receiver 101 is configured to operate at a frequency of 18 GHz, and the other is configured to operate at a frequency of 28 GHz. The device design parameters of the transmitter 100 and the receiver 101 may be different due to the different operating frequencies. In some embodiments, the receiver 101 is applicable to the user equipment 12, 14, 16, 18, the terrestrial base station 22, or the non-terrestrial base station 24.

[0049] In some embodiments, the control circuit board 111 includes a power conversion module 312, a memory module 314, a controller 317, a local oscillator module 318, and a data processing module 323. In some embodiments, additional modules may be added to the control circuit board 111, or some of the above-mentioned modules may be omitted or replaced with different modules. The functions and configurations of the connection circuit board 130, the power conversion module 312, the memory module 314, and the local oscillator module 318 are similar to those described with reference to FIG. 3A, and therefore, for the sake of brevity, the details will not be repeated herein.

[0050] In some embodiments, the controller 317 is configured to control the demodulation of the received signal. In some embodiments, the received signal generated by the control circuit board 111 takes the form of an IF input signal as IF_out, which is downconverted to a baseband signal by the controller 317 or the data processing module 323. In some embodiments, the controller 317 is powered by an external power source or the power conversion module 312, and receives the IF signal IF_out according to the received data IF_out provided by the RF circuit board 121. In some embodiments, the controller 317 is configured to generate control signals for the phased array antenna, such as calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC.

[0051] 4A is configured to receive commands from a control unit 304 external to the control circuit board 110. The data processing module 323 or the controller 317 may be configured to receive transmit data extracted from the received IF signal IF_out provided by the RF circuit board 121 and transmit the transmit data to the control unit 304.

[0052] The RF circuit board 121 includes a pair of RF signal receiving paths, a pair of power combiner networks 352, and two rows of receiver arrays 301. Each of the RF signal receiving paths shown in FIG. 4A proceeds in a reverse manner to the RF signal generating paths shown in FIG. 3A. In some embodiments, the left column of receiver arrays 301 and the right column of receiver arrays 301 are organized symmetrically about a centerline between the left column and the right column of receiver arrays 301. In some embodiments, the left power combiner network 352 and the right power combiner network 352 are organized symmetrically about a centerline between the left power combiner network 352 and the right power combiner network 352. In some embodiments, each RF signal receiving path includes an IF signal receiver 362, a phase locked loop module 334, amplifiers 335 and 338, and a mixer 336. In some embodiments, the IF signal receiver 332 is configured to receive an IF signal IF_out from an output of the mixer 336. The phase-locked loop module 334 may be configured to generate a local oscillator signal LO based on the reference frequency FR through a phase-locked procedure. In some embodiments, the local oscillator signal LO is amplified through an amplifier 335. In some embodiments, the amplifier 335 is an operational amplifier. The mixer 336 is configured to down-convert the RF signal RF_out to an IF signal IF_out of a predetermined frequency band, for example, 445 kHz. In some embodiments, the RF signal RF_out is amplified through an amplifier, for example, an operational amplifier.

[0053] In some embodiments, a power combiner network 352 is connected to the input of the mixer 336 and configured to collect the RF signals RF_out from each RF chip 208 (see FIG. 4C) into a composite RF data signal RF_out. The power combiner network 352 shown in FIG. 4A is a multi-stage power combiner network similar to the power divider 342 shown in FIG. 3A, except that the input and output terminals are reversed. In some embodiments, control signals including the calibration data Din, the data clock signal CLK, and the synchronization clock signal SYNC are provided to each of the receiver array 301 via a bus or multiple signal lines.

[0054] 4B is a schematic block diagram of the receiver array 301 of the receiver 101 shown in FIG. 4A according to some embodiments. In some embodiments, the receiver array 301 includes another power combiner network 356 and multiple receiver blocks 311. In some embodiments, the power combiner network 356 shown in FIG. 4B is similar to the power divider network 346 shown in FIG. 3B, except that the input and output terminals are reversed. In some embodiments, a power supply voltage VD and control signals including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC are also provided to each of the receiver blocks 311 via a bus or multiple signal lines.

[0055] FIG. 4C is a schematic block diagram of a receiver block 311 of the receiver array 301 shown in FIG. 4B according to some embodiments. In some embodiments, the receiver block 311 is formed of a row of RF chips 209 and a row of antenna feed lines 213 corresponding to the row of RF chips 209. In some embodiments, the RF chips 209 each include an individual RF circuit, also referred to as RF circuit 209, as described above with reference to FIG. 2B. In some embodiments, the RF chips 209 are configured as receiver (RX) RF chips. In some embodiments, a power supply voltage VD is provided and transmitted to each of the RF chips 209. In addition, control signals including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC are provided to each RF chip 209. Referring to FIG. 2B and FIG. 4C, in some embodiments, an RF signal RF_in is received by the antenna patch 206 and transmitted to the signal port RF_in via the substrate 202, the feed line 213, the RF chip 209 (output as an RF signal RF_out), and the transmission line 220.

[0056] The RF chip 209 is configured to provide a calibration RF signal RF_out from an RF input signal RF_in on the antenna feed 213 according to the calibration data Din. In some embodiments, the calibration update rate is controlled by a data clock signal CLK and a synchronous clock signal SYNC. In some embodiments, the RF chip 209 includes input ports for the respective in-phase and quadrature RF signal components RF_in_I and RF_in_Q, a power supply voltage VD, the calibration data Din, the data clock signal CLK and the synchronous clock signal SYNC. In some embodiments, the RF chip 209 includes output ports Dout for the respective calibration data and the RF signal RF_out. The functions and configurations of the calibration data Din, the data clock signal CLK and the synchronous clock signal SYNC are similar to those described with reference to Figures 3A-3C, and the details will not be repeated here.

[0057] In some embodiments, the receiver block 311 includes a transmission line 220 between a first end, i.e., an output port of the receiver block 311, and a second end of the transmission line 220. In some embodiments, the second end of the transmission line 220 is grounded through a resistive load 372. In some embodiments, the transmission line 220 is a straight line or a line including multiple line segments extending in different directions. In some embodiments, the transmission line 220 is parallel to the row of the RF chips 209. The resistive load 372 may include a resistor. In some embodiments, the resistance of the resistive load 372 is determined to match the impedance of the transmission line 220 to eliminate signal reflections. In some embodiments, the resistive load 372 includes a resistance of about 50 Ω.

[0058] In some embodiments, the provided RF signal RF_out is propagated between a first end and a second end of the transmission line 220. The RF signals provided by the individual antenna feed lines 213 need to be demodulated with appropriate phase delays according to the phase adjustment data of the calibration data Din to collectively form the accumulated constituent RF signal RF_out. Thus, before the RF signal components RF_in_I and RF_in_Q are combined or before the individual RF signals RF_out are fed to the transmission line 220, they are phase demodulated according to one or more design criteria, such as their location in the antenna array. In some embodiments, each of the RF signals RF_out is a current signal I fed from the corresponding RF chip 209 to a corresponding connection terminal at a different location Di on the transmission line 220. out It is.

[0059] In some embodiments, the RF chip 209 may be configured to generate a current I out In order to maximize the transmission impedance, the transmission line 220 is designed to include an impedance-matched output terminal. For example, the output impedance of the RF chip 209 is approximately 50Ω.

[0060] 4A and 4B, the collected and combined RF signal RF_out is transmitted through the power combiner network 356 and 352 to reach the mixer 336 for down-conversion to the IF signal IF_out. The phase-locked loop module 334 may be configured to generate a local oscillator signal LO based on the reference frequency FR through a phase-locking procedure. In some embodiments, the IF signal receiver 362 is configured to receive the IF data signal IF_in from the output of the mixer 336. In some embodiments, the local oscillator signal LO is amplified through the amplifier 335. In some embodiments, the amplifier 335 is an operational amplifier. The IF signal IF_out is transmitted to the control circuit board 110 through the IF signal receiver 362 and the connection circuit board 130. In some embodiments, the IF signal IF_out is down-converted to a baseband signal by the controller 317 or the data processing module 323, and the transmission data modulated on the RF signal RF_out is demodulated and detected from the baseband signal.

[0061] FIG. 4D shows a schematic block diagram of the RF chip 209 shown in FIG. 4C and an equivalent circuit of the output of the RF chip 209, according to some embodiments. FIG. 4D shows in the left sub-diagram the schematic block diagram of the RF chip 209 shown in FIG. 4C, according to some embodiments. In some embodiments, the output terminal 209A or output port of the RF chip 209 is formed of a FET M2, with a drain terminal D2 connected to the transmission line 220 via a branch transmission line 221. In some embodiments, the output port 209A of the RF chip 209 is designed to include a relatively high input impedance, and the output current I of the received RF signal RF_out provided from one RF chip 209 to the transmission line 220 is out This prevents most of the signal from flowing back to other RF chips 209 in the same receiver block 311.

[0062] In some embodiments, the MOSFET M2 is connected to the output port 209A of the RF chip 209 through a capacitor Cp1. In some embodiments, the capacitor Cp1 is connected to the diodes D21 and D22 of the RF chip 209 at the drain terminal M2D. Referring to the right sub-diagram of FIG. 4D, the circuit of the RF chip 209 connected to the input port 209A shown in the left sub-diagram can be represented by an equivalent circuit formed of a capacitor Cp connected in parallel with an input resistance Rp. In some embodiments, the input impedance or resistance Rp of the RF chip 209 looking into the drain terminal M2D of the RF chip 209 is substantially equal to or greater than 10 times the input impedance looking into the transmission line 220 from the output terminal 209A connected to the transmission line 220. In some embodiments, the input resistance Rp of the RF chip 209 is at least equal to or greater than 500Ω, 1000Ω, or 5000Ω.

[0063] Based on the above, the proposed serial signal accumulation method provides advantages. If the leakage current can be properly managed, the current level flowing from one RF chip 209 to another RF chip 209 in the same receiver block 311 will be very low due to the high impedance of the MOSFET. Therefore, the power collection efficiency of the RF chip 209 will be relatively high without compromising the device performance. Furthermore, since the calibration data of the control signal already includes phase calibration data in the phased array antenna architecture to assist in the calibration of the RF signal RF_in (including the in-phase RF signal component RF_in_I and the quadrature RF signal component RF_in_Q), no additional phase calibration module for the receiver block 311 is needed, and the adjustment of the delay phase also covers the phase adjustment or calibration.

[0064] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. 1. A wireless communication system, comprising: A plurality of antennas; a plurality of radio frequency (RF) chips organized in rows and coupled to the antenna for providing a plurality of RF output signals to the antenna in accordance with an RF signal; a transmission line arranged in a straight line parallel to the rows and connected to the RF chip; a resistive load coupled to a first end of the transmission line; Equipped with a second end of the transmission line configured to receive the RF signal; Each of the RF chips comprises: a metal oxide semiconductor field effect transistor; A capacitor; Equipped with the metal oxide semiconductor field effect transistor having a gate terminal serving as an input terminal connected to the transmission line through the series connected capacitor; A wireless communication system, wherein a first impedance looking into the gate terminal of a corresponding RF chip is ten times greater than a second impedance looking into the transmission line from a corresponding input terminal connected to the transmission line.

2. The wireless communication system of claim 1 , wherein the RF chips are arranged evenly distributed between the first end and the second end and connect to the transmission line.

3. 2. The wireless communication system of claim 1, wherein each of the RF chips is arranged to receive the RF signal by coupling a voltage signal on a corresponding connection terminal of the transmission line.

4. Each of the RF chips includes a first diode and a second diode; The wireless communication system of claim 1 , wherein each of the first diode and the second diode includes a terminal connected to the gate terminal and the capacitor.

5. a plurality of branched transmission lines, each branched transmission line being coupled between a gate terminal of a corresponding RF chip and the transmission line; The wireless communication system of claim 1 further comprising:

6. The wireless communication system of claim 4, wherein the first diode and the second diode are arranged in a reverse bias configuration.

7. A substrate having a first surface and a second surface opposite the first surface. Further equipped with The wireless communication system of claim 1 , wherein the antenna is disposed on the first surface, and the plurality of RF chips and the transmission line are disposed on the second surface.

8. The wireless communication system of claim 7 , wherein the substrate is transparent.

9. The wireless communication system of claim 7 , wherein the substrate is formed of glass, fused silica, or quartz.

10. The wireless communication system of claim 7 , wherein the RF chip is configured to couple the RF signal to the antenna through the substrate, the substrate being free of conductive elements between the RF chip and the antenna.

11. The wireless communication system of claim 1 , further comprising a plurality of signal lines connected to the RF chip and configured to provide calibration data for the RF signal.

12. The wireless communication system of claim 11 , wherein the calibration data includes at least one of amplitude calibration data and phase calibration data.

13. The wireless communication system of claim 12 , wherein the phase calibration data provides a phase delay for each of the RF chips for a phased array antenna system of the antenna.

14. 1. A wireless communication system, comprising: A plurality of antennas; a plurality of radio frequency (RF) chips organized in rows and coupled to the antenna for receiving a plurality of RF signals from the antenna and outputting a plurality of RF output signals; transmission lines arranged in a straight line parallel to the rows and connected to the RF chip for receiving the RF output signal; a resistive load coupled to a first end of the transmission line; Equipped with a second end of the transmission line configured to output a cumulative RF output signal of the RF output signal; Each of the RF chips comprises: a metal oxide semiconductor field effect transistor; A capacitor; Equipped with the metal oxide semiconductor field effect transistor having a drain terminal serving as an output terminal connected to the transmission line via the series connected capacitor; A wireless communication system, wherein a first impedance looking into the drain terminal of a corresponding RF chip is ten times greater than a second impedance looking into the transmission line from a corresponding output terminal connected to the transmission line.

15. 15. The wireless communication system of claim 14, wherein the RF chips are organized so as to be evenly distributed between the first end and the second end for connection to the transmission line.

16. 15. The wireless communication system of claim 14, wherein each of the RF output signals is a current signal provided from a corresponding RF chip to a corresponding connection terminal on the transmission line.

17. The RF chips, each including a first diode and a second diode; 15. The wireless communication system of claim 14, wherein the first diode and the second diode each include a terminal connected to the drain terminal and the capacitor.

18. a plurality of branched transmission lines, each branched transmission line being coupled between a gate terminal of a corresponding RF chip and the transmission line; The wireless communication system of claim 14 further comprising:

19. The wireless communication system of claim 17, wherein the first diode and the second diode are arranged in a reverse bias configuration.

20. A substrate having a first surface and a second surface opposite the first surface. Further equipped with The wireless communication system of claim 14 , wherein the antenna is disposed on the first surface, and the plurality of RF chips and the transmission line are disposed on the second surface.

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