DC-DC Converter

Abstract

To provide a DCDC converter in which power consumption is small and switching operation can be performed at a high frequency.SOLUTION: A DCDC converter includes a comparator 10 that compares a reference voltage and a feedback voltage, an on-time control circuit 11 that controls an on time of a power FET 2, and a R-S flip-flop circuit 13 that outputs a signal for controlling the power FET 2. The on-time control circuit 11 includes a switch 23 that is controlled by a signal based on the on of the power FET 2, a capacitor 22 that is discharged when the switch 23 is turned on and is charged by a first current source 21, and a detection circuit that is formed of a MOS transistor 25 the gate voltage of which is controlled by voltages of a second current source 24 and the capacitor 22, and that outputs a signal for turning off the power FET 2 on the basis of the voltage of the capacitor 22.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a DC-DC converter. [Background technology]

[0002] Constant on-time control, which has excellent load responsiveness, is often used in power supply devices such as DC-DC converters. Constant on-time control is a control method that controls a switching transistor with an output signal based on the signal of an on-time control circuit (see, for example, Patent Document 1).

[0003] 4 is a circuit diagram showing a conventional on-time control circuit. The conventional on-time control circuit is composed of a capacitor 42, a comparator 45 that measures the time until the capacitor 42 is charged to a desired voltage by a current flowing from a current source 41, and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 8,476,887 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional on-time control circuit, it was difficult to switch the switching transistor at a high frequency due to the effect of the delay time from when the comparator 45 detects the voltage of the capacitor 42 to when it outputs a signal. In particular, in a DC-DC converter with low current consumption, it is required to set the operating current of the comparator 45 (the current of the current source 44) low, making it difficult to achieve a high frequency.

[0006] The present invention has been made in consideration of the above problems, and has an object to provide a DC-DC converter that consumes little current and is capable of switching at a high frequency. [Means for solving the problem]

[0007] The DC-DC converter of the present invention includes a comparator that compares a reference voltage with a feedback voltage, an on-time control circuit that controls the on-time of a power FET, and an RS flip-flop circuit that outputs a signal to control the power FET in response to a signal from the comparator and a signal from the on-time control circuit. The on-time control circuit includes a switch that is controlled by a signal based on the on-state of the power FET, and a resistor that is discharged when the switch is turned on. On the other hand, the switch is turned off. A capacitor is charged by a first current source, and a gate voltage is controlled by a second current source and the voltage of the capacitor. When the switch is turned off, the power FET is turned on or off, and a transition from off to on occurs after a predetermined time has elapsed since the switch was turned off. It is composed of MOS transistors controlled by R A detection circuit. The detection circuit outputs a signal including a level corresponding to the voltage level of the drain of the MOS transistor to a reset terminal of the RS flip-flop circuit. It is characterized by: Effect of the Invention

[0008] According to the DC-DC converter of the present invention, current consumption is small and switching operation at a high frequency is possible. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a DC-DC converter according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a circuit diagram showing an on-time control circuit according to an embodiment of the present invention. [Diagram 3] FIG. 4 is a circuit diagram showing another example of the on-time control circuit of the present embodiment. [Figure 4] FIG. 1 is a circuit diagram showing a conventional on-time control circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] FIG. 1 is a block diagram showing a DC-DC converter 100 according to the present embodiment. The DC-DC converter 100 of this embodiment includes a power FET 2, an inductor 3, a Schottky diode 4, a capacitor 5, a comparator 10, an on-time control circuit 11, a reference voltage circuit 12, an RS flip-flop circuit 13, an output control circuit 14, a driver circuit 15, and feedback resistors 17 and 18.

[0012] The feedback resistors 17 and 18 are connected between the output terminal OUT and the GND terminal. The comparator 10 has an inverting input terminal - connected to the output terminals of the feedback resistors 17 and 18, and a non-inverting input terminal + connected to the reference voltage circuit 12. The RS flip-flop circuit 13 has a set terminal S connected to the output terminal of the comparator 10, a reset terminal R connected to the output terminal of the on-time control circuit 11, an output terminal Q connected to the input terminal of the output control circuit 14, and an output terminal QB connected to the input terminal of the on-time control circuit 11. The driver circuit 15 has an input terminal connected to the output terminal of the output control circuit 14, and an output terminal connected to the gate of the power FET 2. The power FET 2 has a source connected to a power supply terminal, and a drain connected to one terminal of the inductor 3 and the cathode of the Schottky diode 4. The other terminal of the inductor 3 is connected to the output terminal OUT and one terminal of the capacitor 5. The other terminal of the Schottky diode 4 is connected to the GND terminal. The other terminal of the capacitor 5 is connected to the GND terminal.

[0013] FIG. 2 is a circuit diagram showing the on-time control circuit 11 of the present embodiment. The on-time control circuit 11 of the present embodiment includes current sources 21 and 24, a capacitor 22, NMOS transistors 23 and 25, and an inverting circuit .

[0014] The current source 21 has one end connected to a power supply terminal and the other end connected to one end of the capacitor 22. The NMOS transistor 23 has a drain connected to one end of the capacitor 22, a source connected to a GND terminal, and a gate connected to an output terminal QB of the RS flip-flop circuit 13. The other end of the capacitor 22 is connected to the GND terminal. The current source 24 has one end connected to a power supply terminal and the other end connected to an input terminal of the inverting circuit 26. The NMOS transistor 25 has a drain connected to the other end of the current source 24, a source connected to the GND terminal, and a gate connected to one end of the capacitor 22. The output terminal of the inverting circuit 26 is connected to the reset terminal R of the RS flip-flop circuit 13. The on-time control circuit 11 has a gate of the NMOS transistor 23 as an input terminal and an output terminal of the inverting circuit 26 as an output terminal. The current source 24 and the NMOS transistor 25 constitute a detection circuit that detects the voltage of the capacitor 22.

[0015] Hereinafter, the operations of the on-time control circuit 11 and the DC-DC converter 100 of the present embodiment will be described with reference to FIGS.

[0016] When a voltage Vin is input to the power supply terminal, the DC-DC converter 100 outputs an output voltage Vout from the output terminal. Feedback resistors 17 and 18 output a feedback voltage based on the output voltage Vout. When the feedback voltage falls below the reference voltage output by the reference voltage circuit 12, the comparator 10 outputs an H-level signal. Since an H-level signal is input to the set terminal S of the RS flip-flop circuit 13, the output terminal Q outputs an H-level signal and the output terminal QB outputs an L-level signal. When an H-level signal is input to the output control circuit 14, the output control circuit 14 outputs an L-level signal from the output terminal and turns on the power FET 2 via the driver circuit 15.

[0017] When an L-level signal is input to the on-time control circuit 11, the on-time control circuit 11 outputs an H-level signal after a predetermined time has elapsed. Since an H-level signal is input to the reset terminal R of the RS flip-flop circuit 13, the output terminal Q outputs an L-level signal and the output terminal QB outputs an H-level signal. When an L-level signal is input to the output control circuit 14, the output control circuit 14 outputs an H-level signal from its output terminal and turns off the power FET 2 via the driver circuit 15.

[0018] When an H-level signal is input to the input terminal of the on-time control circuit 11 in FIG. 2 from the output terminal QB of the RS flip-flop circuit 13, the NMOS transistor 23 is turned on and the NMOS transistor 25 is turned off, so that the on-time control circuit 11 outputs an L-level signal from the output terminal.

[0019] When an L-level signal is input to the input terminal of ON-time control circuit 11 from output terminal QB of RS flip-flop circuit 13, NMOS transistor 23 turns off and charging of capacitor 22 starts with the current from current source 21. When the voltage of capacitor 22 rises due to charging and the gate voltage of NMOS transistor 25 reaches a predetermined voltage, the voltage of the input terminal of inversion circuit 26 becomes L-level, so that ON-time control circuit 11 outputs an H-level signal from its output terminal.

[0020] Here, by configuring current source 24 with a depletion transistor, it is possible to make the gate voltage of NMOS transistor 25, which causes the voltage of the input terminal of inversion circuit 26 to change from H level to L level, constant with respect to voltage characteristics and temperature characteristics. In other words, on-time control circuit 11 can guarantee a constant on-time with respect to the power supply voltage and temperature.

[0021] As described above, the DC-DC converter 100 of this embodiment does not use a comparator in the on-time control circuit 11, so that the current consumption is small and switching operation at a high frequency is possible. In addition, it is possible to guarantee a constant on-time with respect to the power supply voltage and temperature. Furthermore, since a comparator is not used in the on-time control circuit 11, it is effective in reducing the circuit area.

[0022] FIG. 3 is a circuit diagram showing another example of the on-time control circuit 11 of the present embodiment. The on-time control circuit 11 of FIG. 3 includes current sources 31 and 34, a capacitor 32, and PMOS transistors 33 and 35.

[0023] The current source 31 has one end connected to the GND terminal and the other end connected to one end of the capacitor 32. The PMOS transistor 33 has a drain connected to one end of the capacitor 32, a source connected to a power supply terminal, and a gate connected to an output terminal Q of the RS flip-flop circuit 13. The other end of the capacitor 32 is connected to the power supply terminal. The current source 34 has one end connected to the GND terminal and the other end connected to a reset terminal R of the RS flip-flop circuit 13. The PMOS transistor 35 has a drain connected to the other end of the current source 34, a source connected to the power supply terminal, and a gate connected to one end of the capacitor 32. In the on-time control circuit 11, the gate of the PMOS transistor 33 is an input terminal, and the other end of the current source 34 is an output terminal. The current source 34 and the PMOS transistor 35 form a detection circuit that detects the voltage of the capacitor 32.

[0024] The operation of the on-time control circuit 11 in Fig. 3 is the same as that of the on-time control circuit 11 in Fig. 2 except that the signal levels are inverted, and therefore a detailed description thereof will be omitted. Therefore, even if the on-time control circuit 11 is configured as in Fig. 3, the same effect as that of the on-time control circuit 11 in Fig. 2 can be obtained.

[0025] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible within the scope of the present invention. For example, the NMOS transistor 23 and the PMOS transistor 33 are not limited to MOS transistors as long as they have a switch function. Also, for example, the ON-time control circuit 11 is configured to start operation by the output signal of the RS flip-flop circuit 13, but is not limited to this signal as long as it is a signal indicating that the power FET 2 is turned on. [Explanation of symbols]

[0026] 2 Power FETs 3. Inductor 4 Schottky Diodes 5. Capacitor 10. Comparator 11 ON time control circuit 12 Reference voltage circuit 13 RS Flip-Flop Circuit 14 Output control circuit 15 Driver circuit 17, 18 Feedback resistor 21, 24, 31, 34 current source 22, 32 Capacitor 23, 25 NMOS transistors 26 Inverting Circuit 33, 35 PMOS transistors 100 DC-DC Converters

Claims

1. a comparator for comparing a reference voltage with a feedback voltage; an on-time control circuit for controlling an on-time of the power FET; an RS flip-flop circuit that outputs a signal to control the power FET in response to a signal from the comparator and a signal from the on-time control circuit; The on-time control circuit comprises a switch controlled by a signal based on the power FET being turned on, a capacitor which is discharged when the switch is turned on and charged by a first current source when the switch is turned off, and a detection circuit composed of a MOS transistor whose gate voltage is controlled by a second current source and the voltage of the capacitor, and which is controlled so that when the switch is turned off, the switch transitions from off to on a predetermined time after the switch is turned off regardless of whether the power FET is on or off, and the detection circuit outputs a signal including a level corresponding to the voltage level of the drain of the MOS transistor to a reset terminal of the RS flip-flop circuit.

2. 2. The DC-DC converter according to claim 1, wherein the second current source is formed of a depletion-type MOS transistor.

3. 3. The DC-DC converter according to claim 1, wherein the switch is formed of a MOS transistor having the same conductivity type as the MOS transistor.

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