III-nitride stack

Abstract

To provide a technology for suppressing both a leakage current and current collapse in a HEMT using an epitaxial substrate in which a group III nitride layer is grown on a silicon carbide substrate.SOLUTION: A group III nitride laminate includes a substrate composed of semi-insulating silicon carbide of polytype 4H or polytype 6H, a first layer made of aluminum nitride and formed on the substrate, a second layer made of gallium nitride and formed directly on the first layer, and a third layer made of Group III nitride, which has a lower electron affinity than the gallium nitride that makes up the second layer, and is formed directly on the top of the second layer. The second layer is composed of a single gallium nitride layer that is not divided by carbon concentration in the thickness direction, the thickness of the second layer is less than 500 nm, the concentration of iron contained in the second layer is less than 1×1017 / cm3, and the concentration of carbon contained in the second layer is less than 1×1017 / cm3.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a Group III nitride stack. [Background technology]

[0002] Epitaxial substrates in which a group III nitride layer is grown on a silicon carbide substrate are being developed. Such epitaxial substrates are used as materials for fabricating semiconductor devices such as high electron mobility transistors (HEMTs) (see Patent Document 1).

[0003] In a HEMT using such an epitaxial substrate, it is desirable to suppress both leakage current and current collapse. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-4118 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a technique for suppressing both leakage current and current collapse in a HEMT that uses an epitaxial substrate in which a group III nitride layer is grown on a silicon carbide substrate. [Means for solving the problem]

[0006] According to one aspect of the present invention A substrate made of silicon carbide; a first layer formed on the substrate and made of aluminum nitride; a second layer formed on the first layer and composed of gallium nitride; a third layer formed on the second layer and made of a group III nitride having a smaller electron affinity than the gallium nitride constituting the second layer; having the second layer has a thickness of less than 500 nm; The concentration of iron in the second layer is 1×10 17 / cm 3 is less than The concentration of carbon contained in the second layer is 1×10 17 / cm 3 is less than III-nitride stack is provided. Effect of the Invention

[0007] A technique is provided for suppressing both leakage current and current collapse in a HEMT using an epitaxial substrate in which a group III nitride layer is grown on a silicon carbide substrate. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a III-nitride stack according to one embodiment of the present invention. [Diagram 2] 2(a) and 2(b) are graphs (results of simulation) showing the band structure of the epilayer in a III-nitride stack and the depth profile of the 2DEG, where FIG. 2(a) illustrates one embodiment and FIG. 2(b) illustrates a comparative example. [Diagram 3] FIG. 3(a) is a schematic diagram conceptually illustrating an MOVPE apparatus used in manufacturing an epitaxial substrate included in a Group III nitride stack according to one embodiment, and FIG. 3(b) is a schematic timing chart illustrating a growth process of an epitaxial layer included in a Group III nitride stack according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <One embodiment of the present invention> A III-nitride stack 100 (hereinafter also referred to as stack 100) according to one embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view illustrating the stack 100. The stack 100 includes a substrate 110 and a III-nitride layer 160 (hereinafter also referred to as epilayer 160) made of III nitride and formed on the substrate 110. The epilayer 160 includes (at least) a nucleation layer 120, a buffer / channel layer 130, and a barrier layer 140.

[0010] The laminate 100 may be, for example, an epitaxial substrate 170 (hereinafter, also referred to as epitaxial substrate 170) having a substrate 110 and an epitaxial layer 160. The laminate 100 may also be, for example, an embodiment of a semiconductor device formed using the epitaxial substrate 170 as a material, more specifically, an embodiment of a high electron mobility transistor (HEMT) 200 formed by providing electrodes 210 (a source electrode 211, a gate electrode 212, and a drain electrode 213) above the epitaxial layer 160 (a barrier layer 140). FIG. 1 illustrates the laminate 100 in the embodiment of the HEMT 200. The laminate 100 in the embodiment of the HEMT 200 may be in the form of a wafer, or may be in the form of a chip obtained by dividing the wafer.

[0011] The substrate 110 is made of silicon carbide (SiC) and serves as a base substrate for heteroepitaxial growth of the epitaxial layer 160. As the SiC constituting the substrate 110, for example, semi-insulating SiC of polytype 4H or polytype 6H is used. Here, "semi-insulating" refers to, for example, a material having a resistivity of 10 5 The surface of the substrate 110 that serves as a base for growing the epitaxial layer 160 is, for example, a (0001) surface (c-plane silicon surface).

[0012] The nucleation layer 120 is formed on the substrate 110. The nucleation layer 120 is made of aluminum nitride (AlN) and functions as a nucleation layer that generates nuclei for crystal growth of the buffer / channel layer 130. The thickness of the nucleation layer 120 is preferably, for example, 1 nm or more and 200 nm or less.

[0013] A buffer / channel layer 130 (hereinafter also referred to as the channel layer 130) is formed on the nucleation layer 120. The channel layer 130 is made of gallium nitride (GaN). A lower portion of the channel layer 130 functions as a buffer layer for improving the crystallinity of an upper portion of the channel layer 130. In addition, an upper portion of the channel layer 130 functions as a channel layer through which electrons travel when the HEMT 200 is in operation. The preferred thickness and the like of the channel layer 130 according to this embodiment will be described later.

[0014] The barrier layer 140 is formed on the channel layer 130. The barrier layer 140 is made of a group III nitride having a smaller electron affinity than GaN constituting the channel layer 130, for example, aluminum gallium nitride (AlGaN) containing aluminum (Al) and gallium (Ga) as group III elements. The barrier layer 140 functions as a barrier layer that generates a two-dimensional electron gas (2DEG) in the channel layer 130 and spatially confines the 2DEG within the channel layer 130. The thickness of the barrier layer 140 is preferably, for example, 1 nm or more and 50 nm or less.

[0015] A cap layer 150 may be formed on the barrier layer 140 as necessary. That is, the epitaxial layer 160 may have the cap layer 150 as necessary. The cap layer 150 is made of, for example, GaN, and is interposed between the barrier layer 140 and the gate electrode 212 in order to improve the device characteristics (such as the controllability of the threshold voltage) of the HEMT 200.

[0016] On the cap layer 150 (above the barrier layer 140), a source electrode 211, a gate electrode 212, and a drain electrode 213 are formed as electrodes 210 of the HEMT 200. The gate electrode 212 is composed of, for example, a Ni / Au layer in which a nickel (Ni) layer and a gold (Au) layer are laminated. In this specification, when a laminate is described as X / Y, it indicates that the layers are laminated in the order of X and Y.

[0017] Each of the source electrode 211 and the drain electrode 213 is formed, for example, of a Ti / Al layer in which a titanium (Ti) layer and an Al layer are laminated. Each of the source electrode 211 and the drain electrode 213 may also be formed, for example, of a Ni / Au layer laminated on a Ti / Al layer.

[0018] The channel layer 130 will be further described below. One feature of the laminate 100 of this embodiment is that the channel layer 130 is thin. Specifically, the thickness of the channel layer 130 is less than 500 nm, preferably less than 450 nm, more preferably less than 400 nm, and even more preferably less than 350 nm.

[0019] In the stack 100 according to the conventional technology (hereinafter referred to as the comparative embodiment), the channel layer (buffer / channel layer) 130 has a thickness of 500 nm or more. In the comparative embodiment, the channel layer 130 has a thickness of 500 nm or more, thereby reducing defects such as dislocations caused by lattice mismatch, thereby improving the quality of the channel crystal portion located directly below the barrier layer 140.

[0020] However, since the nitrogen vacancies present in the channel layer 130 made of GaN are donor-type point defects, if the channel layer 130 is thick as in the comparative embodiment, the leakage current in the HEMT 200 becomes large. In the comparative embodiment, in order to suppress the leakage current, impurities such as iron and carbon are added to the channel layer 130 to form a deep energy level, and it is possible to capture the free carriers supplied from the nitrogen vacancies and make the channel layer 130 highly resistive. However, in such an embodiment, the deep energy level formed by the impurities such as iron and carbon causes a transient response or reduction of the drain current, called a current collapse. Thus, in the stack 100 of the comparative embodiment, the thickness of the channel layer 130 is as thick as 500 nm or more, which causes a problem that the leakage current is large or the current collapse is large.

[0021] In contrast, in the stack 100 of this embodiment, the thickness of the channel layer (buffer / channel layer) 130 is thinned to less than 500 nm, so that the leakage current can be suppressed compared to the comparative embodiment. In addition, since the leakage current is suppressed, it is not necessary to add impurities such as iron and carbon to reduce the leakage current, so that the current collapse can be suppressed compared to the comparative embodiment. From the viewpoint of suppressing the current collapse, the concentrations of iron and carbon contained in the channel layer 130 according to this embodiment are each 1×10 17 / cm 3 Less than.

[0022] However, the crystallinity and surface flatness of the channel layer 130 are likely to be reduced due to the thinning of the channel layer 130. For this reason, in this embodiment, the epitaxial layer 160 is grown by a method described below, so that even if the thickness of the channel layer 130 is less than 500 nm, the deterioration of the crystallinity and the surface flatness of the channel layer 130 is suppressed (at least the deterioration of the crystallinity is suppressed, so that high electron mobility can be obtained). Note that if the channel layer 130 is made too thin, it becomes difficult to suppress the deterioration of the crystallinity and the surface flatness, so the thickness of the channel layer (buffer / channel layer) 130 is preferably 100 nm or more.

[0023] The degree of crystallinity of the channel layer 130 is evaluated, for example, by the magnitude of the electron mobility of the channel layer 130. The electron mobility of the channel layer 130 according to the present embodiment is preferably 1500 cm 2 / Vs or more, more preferably 1600 cm 2 In the HEMT 200 having the channel layer 130 according to the present embodiment, the leakage current is preferably 1×10 -5A / mm or less. The leakage current here refers to inter-element leakage current or off-leakage current. Inter-element leakage current can be measured by isolating each element on a wafer by ion implantation or ICP etching, etc., and then applying a voltage of, for example, about 50 V between the ohmic electrodes of adjacent elements. Off-leakage current can be measured by applying a sufficient negative voltage to the gate electrode of a formed transistor element to pinch off the element, i.e., turn it off, and then applying a voltage of, for example, about 50 V between the source and drain electrodes.

[0024] 2(a) and 2(b) are graphs (results of simulation) showing the band structure (near the interface between the channel layer 130 and the barrier layer 140) of the epitaxial layer 160 in the stack 100 and the depth profile of the 2DEG. FIG. 2(a) illustrates the present embodiment (channel layer 130 has a thickness of 400 nm), and FIG. 2(b) illustrates the comparative embodiment (channel layer 130 has a thickness of 1000 nm). The horizontal axis is in angstroms.

[0025] In the comparative example (FIG. 2(b)), the tail of the 2DEG distribution spreads downward (toward the substrate 110) compared to the embodiment (FIG. 2(a)). In other words, the electron concentration is high (for example, 1×10 16 / cm 3 The above range is wider downward in the comparative embodiment than in the embodiment. As a result, in the comparative embodiment, current flows more easily in the in-plane direction in the portion below the epitaxial substrate 170 than in the embodiment, resulting in a larger leakage current. In other words, in the embodiment, current flows less easily in the in-plane direction in the portion below the epitaxial substrate 170 than in the comparative embodiment, resulting in a suppression of leakage current.

[0026] Next, a method for manufacturing the stack 100 according to the embodiment will be described. Here, a method for manufacturing the stack 100 in the form of a HEMT 200 will be illustrated. First, a method for manufacturing the epitaxial substrate 170 will be described. A SiC substrate is prepared as the substrate 110. The layers constituting the epitaxial layer 160, that is, the nucleation layer 120, the channel layer 130, the barrier layer 140, and (if necessary) the cap layer 150, are grown above the substrate 110 by, for example, metal-organic vapor phase epitaxy (MOVPE) to form the epitaxial substrate 170.

[0027] Among the group III source gases, the Al source gas is, for example, trimethylaluminum (Al(CH 3 ) 3 Among the group III source gases, the Ga source gas is, for example, trimethylgallium (Ga(CH 3 ) 3 As the nitrogen (N) source gas, which is a Group V source gas, for example, ammonia (NH 3 ) is used as the carrier gas. For example, nitrogen gas (N 2 gas) and hydrogen gas (H 2 At least one of the above gases is used. As a cleaning gas used in the cleaning described below, for example, ammonia gas or chlorine gas is used. The growth temperature can be selected from the range of 900°C to 1400°C, and the V / III ratio, which is the flow rate ratio of the Group V source gas to the Group III source gas, can be selected from the range of 10 to 5000. The ratio of the supply amount of each source gas is adjusted according to the composition of each layer to be formed. The thickness of each layer to be formed can be controlled by the growth time, for example, by calculating the growth time corresponding to the designed thickness from the growth rate obtained in a preliminary experiment.

[0028] The present inventors have investigated a method for suppressing the deterioration of crystallinity and surface flatness while thinning the thickness of the channel layer (buffer / channel layer) 130 as described above (to less than 500 nm). As a result, they have found that one method is to suppress the incorporation of Al into the channel layer 130 due to the formation of the nucleation layer 120 made of AlN, thereby suppressing the deterioration of the crystallinity and surface flatness of the channel layer 130. This is probably because, in the growth of the channel layer 130 made of GaN, the incorporation of Al is suppressed, which facilitates the two-dimensional growth of GaN, thereby improving the crystallinity and surface flatness of GaN in a thin layer. As a result, even for a thin channel layer 130 less than 500 nm, it is preferable to suppress the incorporation of Al into the channel layer 130. 2 / Vs or higher, preferably 1600cm 2 It is believed that good crystallinity with an electron mobility of 100 / Vs or more can be obtained.

[0029] A method for suppressing the incorporation of Al into the channel layer 130 will be described below by way of example. Fig. 3(a) is a schematic diagram conceptually showing an MOVPE apparatus 300 used in the manufacture of the epitaxial substrate 170 according to this embodiment. A susceptor 320 for placing the substrate 110 thereon is installed in a reactor 310 of the MOVPE apparatus 300. A heater 330 for heating the substrate 110 to a predetermined temperature is installed below the placement surface of the susceptor 320. Gas pipes 341, 342, 343, and 344 for supplying various gases toward the substrate 110 are installed in the reactor 310.

[0030] The gas pipe 341 supplies an Al source (for example, TMA) among the group III sources. The gas pipe 342 supplies a group III source other than the Al source, here a Ga source (for example, TMG). The gas pipe 343 supplies a group V source (for example, NH 3 The gas pipe 344 supplies a cleaning gas for removing the Al raw material adhering to the furnace wall of the reaction furnace 310.

[0031] 3(b) is a schematic timing chart illustrating the growth process of the epitaxial layer 160 according to the present embodiment. In the process of forming the nucleation layer 120, an Al source gas and an N source gas are supplied toward the substrate 110 to grow AlN, thereby forming the nucleation layer 120. Due to the formation of the nucleation layer 120, the Al source material adheres to the furnace wall of the reaction furnace 310 and the like.

[0032] In the cleaning step following the formation of the nucleation layer 120, a cleaning gas is supplied into the reactor 310 to remove the Al raw material adhering to the furnace wall of the reactor 310. When chlorine gas is used for cleaning, the cleaning step is performed in a state where the substrate 110 on which the nucleation layer 120 is formed is temporarily taken out of the reactor 310. This is to prevent the nucleation layer 120 from being etched during the cleaning step. When ammonia gas is used for cleaning, the substrate 110 does not need to be taken out of the reactor 310. In the cleaning step, it is more preferable to remove the Al raw material adhering to the inner wall of the gas pipe 341 by flowing a cleaning gas (e.g., ammonia gas or, for example, chlorine gas) into the gas pipe 341 used for supplying the Al raw material in the formation step of the nucleation layer 120.

[0033] In the process of forming the channel layer 130 following the cleaning process, Ga raw material gas and N raw material gas are supplied toward the substrate 110 to grow GaN, thereby forming the channel layer 130. In this embodiment, prior to the process of forming the channel layer 130, a cleaning process is performed to remove the Al raw material adhering to the furnace wall of the reaction furnace 310, thereby suppressing Al contamination when forming the channel layer 130, and therefore, deterioration in the crystallinity and surface flatness of GaN caused by Al contamination can be suppressed.

[0034] Furthermore, in this embodiment, the gas pipe 341 for supplying the Al raw material gas and the gas pipe 342 for supplying the Ga raw material gas are separate. This makes it possible to prevent the Al raw material gas remaining in the gas pipe from being supplied together with the Ga raw material gas, which occurs in an embodiment in which the Al raw material gas and the Ga raw material gas are supplied from a common gas pipe, and therefore makes it possible to suppress deterioration in the crystallinity and surface flatness of GaN caused by the inclusion of Al in the channel layer 130.

[0035] In this embodiment, the channel layer 130 can be formed with a thickness of less than 500 nm and with reduced deterioration in crystallinity and surface flatness. The conditions in the cleaning step, such as the flow rate of the cleaning gas and the length of time for which the cleaning step is performed, can be determined by a preliminary experiment so that the channel layer 130 having the desired crystallinity and surface flatness is formed.

[0036] In the process of forming the channel layer 130, impurities such as iron and carbon are not added to increase the resistance of the channel layer 130. As for iron, by not supplying a raw material gas containing iron (for adding iron), the concentration of iron in the channel layer 130 is set to 1×10 17 / cm 3 Regarding carbon, the channel layer 130 is grown at a growth temperature and a V / III ratio that suppress the incorporation of carbon originating from a Ga source gas, which is an organic source gas such as TMG, into the channel layer 130, thereby making the carbon concentration in the channel layer 130 to be less than 1×10 17 / cm 3 Less than.

[0037] In the step of forming the barrier layer 140 following the step of forming the channel layer 130, Al source gas, Ga source gas, and N source gas are supplied toward the substrate 110 to grow AlGaN, thereby forming the barrier layer 140. When the epitaxial layer 160 has the cap layer 150, following the step of forming the barrier layer 140, Ga source gas and N source gas are further supplied toward the substrate 110 to grow GaN, thereby forming the cap layer 150. As described above, the epitaxial layer 160 is grown on the substrate 110 to manufacture the epitaxial substrate 170.

[0038] Next, a method for manufacturing the HEMT 200 will be described. After the epitaxial substrate 170 is manufactured, the electrodes 210 (the source electrode 211, the gate electrode 212, and the drain electrode 213) are formed on the epitaxial layer 160 to manufacture the HEMT 200. When manufacturing the HEMT 200, other members such as a protective film may be formed as necessary. The electrodes 210, the protective film, and the like may be formed by known methods. In this manner, the stack 100 according to this embodiment is manufactured.

[0039] As described above, according to this embodiment, by making the thickness of the channel layer 130 thin, less than 500 nm, it is possible to suppress the leakage current when the stack 100 is used as the HEMT 200. Furthermore, since the leakage current is suppressed, it is not necessary to add impurities such as iron and carbon to reduce the leakage current, and therefore it is also possible to suppress current collapse.

[0040] <Preferred embodiment of the present invention> Preferred aspects of the present invention will be described below.

[0041] (Appendix 1) A substrate made of silicon carbide; a first layer formed on the substrate and made of aluminum nitride; a second layer formed on the first layer and composed of gallium nitride; a third layer formed on the second layer and made of a group III nitride having a smaller electron affinity than the gallium nitride constituting the second layer; having the second layer has a thickness of less than 500 nm (preferably less than 450 nm, more preferably less than 400 nm, and even more preferably less than 350 nm); The concentration of iron in the second layer is 1×10 17 / cm 3 is less than The concentration of carbon contained in the second layer is 1×10 17 / cm 3 is less than III-nitride stacks.

[0042] (Appendix 2) 2. The III-nitride stack according to claim 1, wherein the second layer has a thickness of 100 nm or more.

[0043] (Appendix 3) The electron mobility of the second layer is preferably 1500 cm 2 / Vs or more, more preferably 1600 cm 2 3. The Group III nitride stack according to claim 1 or 2, wherein Vs is greater than or equal to 1.

[0044] (Appendix 4) an electrode disposed above the third layer; 4. The Group III nitride stack according to any one of claims 1 to 3, which is used as a high electron mobility transistor.

[0045] (Appendix 5) A leakage current (off leakage current) in the high electron mobility transistor is measured by applying a negative voltage to the gate electrode of the high electron mobility transistor to turn it off and then applying a voltage of 50 V between the source electrode and the drain electrode. The leakage current (off leakage current) in the high electron mobility transistor is 1×10 -5 A Group III nitride stack according to appendix 4, wherein the resistance of the stack is 0.05 A / mm or less. [Explanation of symbols]

[0046] 100... Group III nitride stack, 110... Substrate, 120... Nucleation layer, 130... Buffer / channel layer, 140... Barrier layer, 150... Cap layer, 160... Group III nitride layer, 170... Epitaxial substrate, 200... HEMT, 210... Electrode, 211... Source electrode, 212... Gate electrode, 213... Drain electrode, 300... MOVPE apparatus, 310... Reactor, 320... Susceptor, 330... Heater, 341-344... Gas tube

Claims

1. a substrate comprised of semi-insulating silicon carbide of polytype 4H or polytype 6H; a first layer formed on the substrate and made of aluminum nitride; a second layer formed directly on the first layer and made of gallium nitride; a third layer formed directly on the second layer and made of a Group III nitride having a smaller electron affinity than the gallium nitride constituting the second layer; having the second layer is composed of one gallium nitride layer that is not differentiated by carbon concentration in a thickness direction; the second layer has a thickness of less than 500 nm; The concentration of iron contained in the second layer is 1×10 １７ / cm ３ is less than The concentration of carbon contained in the second layer is 1×10 １７ / cm ３ is less than Group III nitride stacks.

2. The III-nitride stack of claim 1 , wherein the second layer has a thickness of less than 400 nm.

3. The III-nitride stack of claim 2 , wherein the second layer has a thickness of less than 350 nm.

4. 4. The Group III nitride stack according to claim 1, wherein the third layer has a thickness of 1 nm or more and 50 nm or less.

5. The electron mobility of the second layer is 1500 cm ２ The Group III nitride stack according to any one of claims 1 to 4, wherein the n-th order voltage Vs is 0.1 V or more.

6. an electrode disposed above the third layer; The Group III nitride stack according to any one of claims 1 to 5, which is used as a high electron mobility transistor.

7. A leakage current in the high electron mobility transistor is measured by applying a negative voltage to the gate electrode of the high electron mobility transistor to turn it off and then applying a voltage of 50 V between the source electrode and the drain electrode. The leakage current in the high electron mobility transistor is measured by applying a negative voltage to the gate electrode of the high electron mobility transistor to turn it off and then applying a voltage of 50 V between the source electrode and the drain electrode. －５ The III-nitride stack of claim 6 , wherein the dielectric constant is less than or equal to A / mm.

8. The III-nitride stack according to any one of claims 1 to 7, wherein the III-nitride stack is in the form of a wafer.

9. The III-nitride stack according to any one of claims 1 to 7, wherein the III-nitride stack is in the form of a chip.

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