DRIVE DEVICE AND METHOD FOR CONTROLLING DRIVE DEVICE

Abstract

A driving device and a control method are provided that reduce the circuit scale and suppress the malfunction of a transistor with a short dead time. [Solution] The driving device 100 includes a gate driver circuit G1 that outputs a control signal SG1 generated from a positive power supply voltage VCC1 of a positive power supply wiring HC1 and a negative power supply voltage VEE1 of a negative power supply wiring HE1 to a control terminal GATE1 of a transistor SW1 to control the operation of the transistor HC1, a gate driver circuit G2 that outputs a control signal SG2 generated from a positive power supply voltage VCC2 of a positive power supply wiring HC2 and a negative power supply voltage VEE2 of a negative power supply wiring HE2 to a control terminal GATE2 of the transistor SW2 to control the operation of the transistor SW2 so that the transistors are complementarily turned on / off, and a charge pump circuit P1 that generates a negative power supply voltage VEE1 of opposite polarity to the positive power supply voltage VCC1 based on the control signal SG1 and applies the negative power supply voltage VEE1 to the negative power supply wiring HE1.

Description

[Technical field]

[0001] The present invention relates to a drive device and a control method for the drive device. [Background technology]

[0002] Conventionally, there is a drive device that controls a high-side transistor and a low-side transistor so as to be turned on / off complementarily (see, for example, Japanese Patent Application Laid-Open No. 2016-67194).

[0003] In this conventional driving device, when the two transistors (n-channel FETs) described above are turned on / off, when the high-side transistor is turned on, the source potential of the high-side transistor and the drain potential of the low-side transistor increase, and dv / dt increases.

[0004] At this time, a current flows in through the parasitic capacitance between the drain and gate of the low-side transistor and the gate resistance, causing the gate potential of the low-side transistor to rise.

[0005] When the gate potential exceeds the threshold voltage Vth of the low-side transistor, the low-side transistor turns on, causing an arm short circuit between the high-side transistor and the low-side transistor.

[0006] For example, in a conventional driving device (Figure 4), a bootstrap power supply is used to configure the device with a single power supply, thereby reducing the circuit size of the auxiliary power supply for turning the transistor on and off.

[0007] However, this conventional drive device cannot generate a negative power supply, so it requires a large dead time (Figure 5).

[0008] Thus, the conventional driving device has a problem in that it is not possible to reduce the circuit scale while suppressing the malfunction of the transistor in a short dead time. DISCLOSURE OF THEINVENTION [Problem to be solved by the invention]

[0009] SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide a drive device capable of suppressing malfunction of transistors with a short dead time while reducing the circuit scale. [Means for solving the problem]

[0010] A drive device according to an embodiment of the present invention comprises: A power supply terminal to which a DC voltage is applied; A ground terminal connected to a ground; a first transistor having one end connected to the power supply terminal and the other end connected to an output terminal; a second transistor having one end connected to the output terminal and the other end connected to the ground terminal; a first DC power supply that outputs a first voltage; a first bootstrap circuit including a first bootstrap diode having an anode to which the first voltage is applied and a cathode connected to a first positive power supply wiring, and a first bootstrap capacitor having one end connected to the cathode of the first bootstrap diode and the other end connected to the output terminal; a first stabilization capacitor having one end connected to the output terminal and the other end connected to a first negative power supply wiring; a first gate driver circuit that outputs a first control signal generated from a first positive power supply voltage of the first positive power supply wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor to control an operation of the first transistor; a second gate driver circuit that outputs a second control signal generated from a second positive power supply voltage of a second positive power supply wiring and a second negative power supply voltage of a second negative power supply wiring to a control terminal of the second transistor to control an operation of the second transistor so that the first transistor and the second transistor are complementarily turned on / off; a first charge pump circuit that generates the first negative power supply voltage having a polarity opposite to that of the first positive power supply voltage with respect to a potential of the output terminal based on the first control signal and applies the first negative power supply voltage to the first negative power supply wiring. It is characterized by:

[0011] In the drive device, the first transistor is a first n-channel MOS transistor having one end connected to the power supply terminal and the other end connected to the output terminal; The second transistor is a second n-channel MOS transistor having one end connected to the output terminal and the other end connected to the ground terminal. It is characterized by:

[0012] In the drive device, a second stabilization capacitor having one end connected to the cathode of the first bootstrap diode and the other end connected to the first negative power supply wiring; It is characterized by:

[0013] In the drive device, a second DC power supply that outputs a second voltage; a second bootstrap circuit including a second bootstrap diode having an anode to which the second voltage is applied and a cathode connected to the second positive power supply wiring, and a second bootstrap capacitor having one end connected to the cathode of the second bootstrap diode and the other end connected to the ground terminal; a third stabilizing capacitor having one end connected to the ground terminal and the other end connected to the second negative power supply wiring; a fourth stabilization capacitor having one end connected to the cathode of the second bootstrap diode and the other end connected to the second negative power supply wiring; a second charge pump circuit that generates the second negative power supply voltage having a polarity opposite to that of the second positive power supply voltage with respect to a potential of the ground terminal based on the second control signal and applies the second negative power supply voltage to the second negative power supply wiring. It is characterized by:

[0014] In the drive device, The first charge pump circuit comprises: A power supply line connected to the first positive power supply line, the first negative power supply line, the control terminal of the first transistor, and the output terminal It is characterized by:

[0015] In the drive device, The second charge pump circuit comprises: a second positive power supply wiring, a second negative power supply wiring, the control terminal of the second transistor, and the ground terminal; It is characterized by:

[0016] In the drive device, The capacitance value of the first bootstrap capacitor is set to be equal to the capacitance value of the first stabilization capacitor. It is characterized by:

[0017] In the drive device, The capacitance value of the second bootstrap capacitor is set to be equal to the capacitance value of the third stabilization capacitor. It is characterized by:

[0018] In the drive device, The capacitance value of the first stabilization capacitor is set to be larger than the capacitance value of the second stabilization capacitor. It is characterized by:

[0019] In the drive device, The capacitance value of the third stabilization capacitor is set to be larger than the capacitance value of the fourth stabilization capacitor. It is characterized by:

[0020] In the drive device, The first gate driver circuit includes: PWM-controlling an operation of the first transistor by the first control signal; The second gate driver circuit includes: The operation of the second transistor is PWM-controlled by the second control signal so that the first transistor and the second transistor are complementarily turned on / off. It is characterized by:

[0021] In the drive device, In the relationship between the PWM control of the first transistor by the first control signal and the PWM control of the second transistor by the second control signal, a dead time during which both transistors are turned off is set. It is characterized by:

[0022] In the drive device, The first charge pump circuit comprises: a first pump resistor having one end connected to the control terminal of the first transistor; a first pump bipolar transistor having a collector connected to the first positive power supply wiring and a base connected to the other end of the first pump resistor; a second pump bipolar transistor having a collector connected to the emitter of the first pump bipolar transistor, a base connected to the other end of the first pump resistor, and an emitter connected to the output terminal; a second pump resistor having one end connected to the emitter of the first pump bipolar transistor; a first pump capacitor, one end of which is connected to the other end of the second pump resistor; a first pump diode having an anode connected to the other end of the first pump capacitor and a cathode connected to the output terminal; a second pump diode having a cathode connected to the other end of the first pump capacitor; a second pump capacitor having one end connected to the anode of the second pump diode and the other end connected to the output terminal; a third pump resistor, one end of which is connected to the anode of the second pump diode and the other end of which is connected to the first negative power supply wiring; a first pump Zener diode having an anode connected to the first negative power supply wiring and a cathode connected to the output terminal; a third pump capacitor having one end connected to the first negative power supply wiring and the other end connected to the output terminal; It is characterized by:

[0023] In the drive device, The second charge pump circuit comprises: a fourth pump resistor having one end connected to the control terminal of the second transistor; a third pump bipolar transistor having a collector connected to the second positive power supply wiring and a base connected to the other end of the fourth pump resistor; a fourth pump bipolar transistor having a collector connected to the emitter of the third pump bipolar transistor, a base connected to the other end of the fourth pump resistor, and an emitter connected to the ground terminal; a fifth pump resistor having one end connected to the emitter of the third pump bipolar transistor; a fourth pump capacitor, one end of which is connected to the other end of the fifth pump resistor; a third pump diode having an anode connected to the other end of the fourth pump capacitor and a cathode connected to the ground terminal; a fourth pump diode having a cathode connected to the other end of the fourth pump capacitor; a fifth pump capacitor having one end connected to the anode of the fourth pump diode and the other end connected to the ground terminal; a sixth pump resistor having one end connected to the anode of the fourth pump diode and the other end connected to the second negative power supply wiring; a second pump Zener diode having an anode connected to the other end of the sixth pump resistor and a cathode connected to the ground terminal; a sixth pump capacitor having one end connected to the second negative power supply wiring and the other end connected to the ground terminal; It is characterized by:

[0024] A method for controlling a drive device according to an embodiment of the present invention includes the steps of: a power supply terminal to which a DC voltage is applied, a ground terminal which is grounded, a first transistor having one end connected to the power supply terminal and the other end connected to an output terminal, a second transistor having one end connected to the output terminal and the other end connected to the ground terminal, a first DC power supply which outputs a first voltage, a first bootstrap diode having an anode to which the first voltage is applied and a cathode connected to a first positive power supply wiring, and a first bootstrap capacitor having one end connected to the cathode of the first bootstrap diode and the other end connected to the output terminal, a first stabilization capacitor having one end connected to the output terminal and the other end connected to a first negative power supply wiring, 1. A method for controlling a drive device comprising: a first gate driver circuit that outputs a first control signal generated from a first negative power supply voltage of a negative power supply wiring to a control terminal of the first transistor to control an operation of the first transistor; a second gate driver circuit that outputs a second control signal generated from a second positive power supply voltage of a second positive power supply wiring and a second negative power supply voltage of a second negative power supply wiring to a control terminal of the second transistor to control an operation of the second transistor so that the first transistor and the second transistor are complementarily turned on / off; and a first charge pump circuit that generates the first negative power supply voltage of an opposite polarity to the first positive power supply voltage with reference to a potential of the output terminal based on the first control signal, and applies the first negative power supply voltage to the first negative power supply wiring, outputting the first control signal generated from a first positive power supply voltage of the first positive power supply wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor, thereby controlling an operation of the first transistor; outputting the second control signal generated from the second positive power supply voltage of the second positive power supply wiring and the second negative power supply voltage of the second negative power supply wiring to a control terminal of the second transistor, thereby controlling an operation of the second transistor so that the first transistor and the second transistor are complementarily turned on / off; The first charge pump circuit generates the first negative power supply voltage having a polarity opposite to that of the first positive power supply voltage with respect to the potential of the output terminal based on the first control signal, and applies the first negative power supply voltage to the first negative power supply wiring. It is characterized by: Effect of the Invention

[0025] A drive device according to one aspect of the present invention includes a power supply terminal to which a DC voltage is applied, a ground terminal which is grounded, a first transistor having one end connected to the power supply terminal and the other end connected to an output terminal, a second transistor having one end connected to the output terminal and the other end connected to the ground terminal, a first DC power supply which outputs a first voltage, a first bootstrap circuit having a first bootstrap diode having an anode to which the first voltage is applied and a cathode connected to a first positive power supply wiring, and a first bootstrap capacitor having one end connected to the cathode of the first bootstrap diode and the other end connected to the output terminal, a first stabilization capacitor having one end connected to the output terminal and the other end connected to a first negative power supply wiring, and a first positive power supply the first gate driver circuit outputs a first control signal generated from a first positive power supply voltage of the wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor to control operation of the first transistor; a second gate driver circuit outputs a second control signal generated from a second positive power supply voltage of the second positive power supply wiring and a second negative power supply voltage of the second negative power supply wiring to a control terminal of the second transistor SW2 to control operation of the second transistor such that the first transistor and the second transistor are complementarily turned on / off; and a first charge pump circuit generates a first negative power supply voltage of an opposite polarity to the first positive power supply voltage based on the first control signal and applies the first negative power supply voltage to the first negative power supply wiring.

[0026] In this way, in the driving device of the present invention, the power supply circuit for generating a negative voltage is omitted to reduce the circuit size, while the first charge pump circuit is operated by the control signal of the first transistor output by the first driver circuit to generate a negative power supply voltage from the positive power supply voltage, and the negative power supply voltage is used to ensure a margin between the threshold voltage of the first transistor and the control signal when it is off, thereby shortening the dead time.

[0027] That is, according to the driving device of the present invention, it is possible to reduce the circuit scale and suppress the malfunction of the transistor with a short dead time. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a drive device 100 according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of operational waveforms of the driving device 100 shown in FIG. [Diagram 3] FIG. 3 is a diagram illustrating an example of a configuration of a drive device 200 according to the second embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a conventional driving device. [Diagram 5] FIG. 5 is a diagram showing an example of an operation waveform of the conventional driving device shown in FIG. BEST MODE FOR CARRYING OUT THEINVENTION

[0029] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Example 1

[0030] Fig. 1 is a diagram showing an example of a configuration of a driving device 100 according to the first embodiment. Fig. 2 is a diagram showing an example of an operation waveform of the driving device 100 shown in Fig. 1.

[0031] As shown in FIG. 1, the driving device 100 controls a first transistor SW1 and a second transistor SW2 to be turned on / off complementarily, and outputs a predetermined voltage from an output terminal TOUT.

[0032] Here, as shown in FIG. 1, for example, the driving device 100 includes a power supply terminal TS, a ground terminal TGND, a first transistor SW1, a second transistor SW2, a first body diode D1, a second body diode D2, a first DC power supply X1, a second DC power supply X2, a first bootstrap circuit BS1, a first stabilization capacitor AC1, a second stabilization capacitor AC2, a second bootstrap circuit BS2, a third stabilization capacitor AC3, a fourth stabilization capacitor AC4, a first gate driver circuit G1, a second gate driver circuit G2, a first charge pump circuit P1, and a second charge pump circuit P2.

[0033] The power supply terminal TS is connected to the positive electrode of a DC power supply BAT so that a DC voltage is applied thereto.

[0034] Moreover, the ground terminal TGND is connected to the negative electrode of the DC power supply BAT and is grounded.

[0035] Moreover, the first transistor (high-side transistor) SW1 has one end (drain) connected to the power supply terminal TS and the other end (source) connected to the output terminal TOUT.

[0036] The first body diode D1 has a cathode connected to one end (drain) of the first transistor SW1 and an anode connected to the other end (source) of the first transistor SW1.

[0037] Here, the first transistor SW1 is, for example, a first n-channel MOS transistor having one end (drain) connected to the power supply terminal TS and the other end (source) connected to the output terminal TOUT, as shown in FIG.

[0038] The first transistor SW1 may be an NPN bipolar transistor.

[0039] Moreover, the second transistor (low-side transistor) SW2 has one end (drain) connected to the output terminal TOUT and the other end (source) connected to the ground terminal TGND.

[0040] The second body diode D2 has a cathode connected to one end (drain) of the second transistor SW2 and an anode connected to the other end (source) of the second transistor SW2.

[0041] Here, the second transistor SW2 is, for example, as shown in FIG. 1, a second n-channel MOS transistor having one end (drain) connected to the output terminal TOUT and the other end (source) connected to the ground terminal TGND.

[0042] The second transistor SW2 may be an NPN bipolar transistor.

[0043] The first DC power source X1 outputs a first voltage V1.

[0044] As shown in FIG. 1, the first DC power supply X1 is, for example, a first battery having a negative electrode grounded and a positive electrode connected to the anode of a first bootstrap diode BD1.

[0045] Moreover, the first bootstrap circuit BS1 includes, for example, a first bootstrap diode BD1 and a first bootstrap capacitor BC1 as shown in FIG.

[0046] As shown in FIG. 1, the first bootstrap diode BD1 has an anode connected to the positive electrode of the first DC power supply X1, a first voltage V1 is applied to the anode, and a cathode connected to the first positive power supply wiring HC1.

[0047] Also, as shown in FIG. 1, for example, one end of the first bootstrap capacitor BC1 is connected to the cathode of the first bootstrap diode BD1, and the other end is connected to the output terminal TOUT (first source terminal SOURSE1).

[0048] The capacitance value of the first bootstrap capacitor BC1 is set to be equal to the capacitance value of the first stabilization capacitor AC1, for example.

[0049] The first stabilization capacitor AC1 has one end connected to the output terminal TOUT (first source terminal SOURSE1) and the other end connected to the first negative power supply wiring HE1.

[0050] Moreover, the second stabilization capacitor AC2 has one end connected to the cathode of the first bootstrap diode BD1 and the other end connected to the first negative power supply wiring HE1.

[0051] The capacitance value of the first stabilization capacitor AC1 is set to be larger than the capacitance value of the second stabilization capacitor AC2.

[0052] In addition, the first gate driver circuit (high side gate driver circuit) G1 outputs a first control signal SG1 generated from the first positive power supply voltage VCC1 of the first positive power supply wiring HC1 and the first negative power supply voltage VEE1 of the first negative power supply wiring HE1 to the control terminal (first gate terminal GATE1) of the first transistor SW1 to control the operation of the first transistor SW1.

[0053] In particular, the first gate driver circuit G1 performs PWM control of the operation of the first transistor SW1 using a first control signal SG1.

[0054] In addition, the second gate driver circuit (low-side gate driver circuit) G2 outputs a second control signal SG2 generated from the second positive power supply voltage VCC2 of the second positive power supply wiring HC2 and the second negative power supply voltage VEE2 of the second negative power supply wiring HE2 to the control terminal (second gate terminal GATE2) of the second transistor SW2, thereby controlling the operation of the second transistor SW2 so that the first transistor SW1 and the second transistor SW2 are turned on / off complementarily.

[0055] In particular, the second gate driver circuit G2 is configured to PWM-control the operation of the second transistor SW2 so that the first transistor SW1 and the second transistor SW2 are turned on / off complementarily by a second control signal SG2.

[0056] In relation to the PWM control of the first transistor SW1 by the first control signal SG1 and the PWM control of the second transistor SW1 by the second control signal SG2, a dead time is set during which both transistors SW1 and SW2 are turned off (to prevent a through current from flowing) (Figure 2).

[0057] In addition, the first charge pump circuit P1 generates a first negative power supply voltage VEE1 of opposite polarity to the first positive power supply voltage VCC1 based on the potential of the output terminal TOUT (the potential of the first source terminal SOURSE1) based on a first control signal SG1 that controls the first transistor SW1, and applies it to the first negative power supply wiring HE1.

[0058] In this manner, the first charge pump circuit P1 operates as a negative power supply generating circuit.

[0059] This first charge pump circuit P1 is connected to, for example, a first positive power supply wiring HC1, a first negative power supply wiring HE1, a control terminal (first gate terminal GATE1) of the first transistor SW, and an output terminal TOUT (first source terminal SOURSE1), as shown in FIG.

[0060] More specifically, as shown in FIG. 1, the first charge pump circuit P1 includes, for example, a first pump resistor RP1, a first pump bipolar transistor MP1, a second pump bipolar transistor MP2, a second pump resistor RP2, a first pump capacitor CP1, a first pump diode DP1, a second pump diode DP2, a second pump capacitor CP2, a third pump resistor RP3, a first pump Zener diode VP1, and a third pump capacitor CP3.

[0061] The first pump resistor RP1 has one end electrically connected to the control terminal (first gate terminal GATE1) of the first transistor SW1.

[0062] The first pump bipolar transistor MP1 has a collector connected to the first positive power supply wiring HC1 and a base connected to the other end of the first pump resistor RP1.

[0063] In addition, the second pump bipolar transistor MP2 has a collector connected to the emitter of the first pump bipolar transistor MP1, a base connected to the other end of the first pump resistor RP1, and an emitter connected to the output terminal TOUT (first source terminal SOURSE1).

[0064] Moreover, one end of the second pump resistor RP2 is connected to the emitter of the first pump bipolar transistor MP1.

[0065] Moreover, one end of the first pump capacitor CP1 is connected to the other end of the second pump resistor RP2.

[0066] The first pump diode DP1 has an anode connected to the other end of the first pump capacitor CP1 and a cathode connected to the output terminal TOUT (first source terminal SOURSE1).

[0067] The second pump diode DP2 has a cathode connected to the other end of the first pump capacitor CP1.

[0068] Moreover, one end of the second pump capacitor CP2 is connected to the anode of the second pump diode DP2, and the other end is connected to the output terminal TOUT (first source terminal SOURSE1).

[0069] Moreover, one end of the third pump resistor RP3 is connected to the anode of the second pump diode DP2 (one end of the second pump capacitor CP2), and the other end is connected to the first negative power supply wiring HE1.

[0070] The first pump Zener diode VP1 has an anode connected to the other end of the third pump resistor RP3 (first negative power supply wiring HE1) and a cathode connected to the output terminal TOUT (first source terminal SOURSE1).

[0071] Moreover, the third pump capacitor CP3 has one end connected to the first negative power supply wiring HE1 and the other end connected to the output terminal TOUT (first source terminal SOURSE1).

[0072] The first charge pump circuit P1 having such a configuration generates a first negative power supply voltage VEE1 of opposite polarity to the first positive power supply voltage VCC1 based on the potential of the output terminal TOUT (the potential of the first source terminal SOURSE1) based on the first control signal SG1 that controls the first transistor SW1, and applies it to the first negative power supply wiring HE1.

[0073] Moreover, the second DC power source X2 outputs a second voltage V2.

[0074] The second DC power supply X2 is, for example, a second battery having a negative electrode grounded and a positive electrode connected to the anode of a second bootstrap diode BD2 as shown in FIG.

[0075] In addition, the above-mentioned first DC power supply X1 and second DC power supply X2 are shown as separate configurations in the example of FIG. 1, but may be a common power supply.

[0076] Furthermore, the second bootstrap circuit BS2 includes, for example, a second bootstrap diode BD2 and a second bootstrap capacitor BC2 as shown in FIG.

[0077] The second bootstrap diode BD2 has an anode connected to the positive electrode of the first DC power supply X1, a second voltage V2 is applied to the anode, and a cathode connected to the second positive power supply wiring HC2.

[0078] Moreover, one end of the second bootstrap capacitor BC2 is connected to the cathode of the second bootstrap diode BD2, and the other end is connected to the ground terminal TGND (second source terminal SOURSE2).

[0079] Moreover, the third stabilization capacitor AC3 has one end connected to the ground terminal TGND (second source terminal SOURSE2) and the other end connected to the second negative power supply wiring HE2.

[0080] The capacitance value of the second bootstrap capacitor BC2 is set, for example, to be equal to the capacitance value of the third stabilization capacitor AC3.

[0081] Moreover, the fourth stabilization capacitor AC4 has one end connected to the cathode of the second bootstrap diode BD2 and the other end connected to the second negative power supply wiring HE2.

[0082] The capacitance value of the third stabilization capacitor AC4 is set to be larger than the capacitance value of the fourth stabilization capacitor AC4.

[0083] In addition, the second charge pump circuit P2 generates a second negative power supply voltage VEE2 of opposite polarity to the second positive power supply voltage VCC2 based on the potential of the ground terminal TGND (the potential of the second source terminal SOURSE2) based on a second control signal SG2 that controls the second transistor SW2, and applies it to the second negative power supply wiring HE2.

[0084] In this manner, the second charge pump circuit P2 operates as a negative power supply generating circuit.

[0085] In addition, instead of the second charge pump circuit P2 shown in FIG. 1, a three-terminal regulator may be used as the negative voltage generating circuit, which generates a second negative power supply voltage VEE2 of the opposite polarity to the second positive power supply voltage VCC2 and applies it to the second negative power supply wiring HC2.

[0086] This second charge pump circuit P2 is connected to, for example, a second positive power supply wiring HC2, a second negative power supply wiring HE2, a control terminal (second gate terminal GATE2) of the second transistor SW2, and a ground terminal TGND (second source terminal SOURSE2), as shown in FIG.

[0087] More specifically, the second charge pump circuit P2 includes, for example, a fourth pump resistor RP4, a third pump bipolar transistor MP3, a fourth pump bipolar transistor MP4, a fifth pump resistor RP5, a fourth pump capacitor CP4, a third pump diode DP3, a fourth pump diode DP4, a fifth pump capacitor CP5, a sixth pump resistor RP6, a second pump Zener diode VP2, and a sixth pump capacitor CP6, as shown in FIG. 1.

[0088] One end of the fourth pump resistor RP4 is electrically connected to the control terminal (second gate terminal GATE2) of the second transistor SW2.

[0089] The third pump bipolar transistor MP3 has a collector connected to the second positive power supply wiring HC2 and a base connected to the other end of the fourth pump resistor RP4.

[0090] In addition, the fourth pump bipolar transistor MP4 has a collector connected to the emitter of the third pump bipolar transistor MP3, a base connected to the other end of the fourth pump resistor RP4, and an emitter connected to the ground terminal TGND (second source terminal SOURSE2).

[0091] Moreover, one end of the fifth pump resistor RP5 is connected to the emitter of the third pump bipolar transistor MP3.

[0092] Moreover, one end of the fourth pump capacitor CP4 is connected to the other end of the fifth pump resistor RP5.

[0093] Moreover, the third pump diode DP3 has an anode connected to the other end of the fourth pump capacitor CP4 and a cathode connected to the ground terminal TGND (the second source terminal SOURSE2).

[0094] Moreover, the cathode of the fourth pump diode DP4 is connected to the other end of the fourth pump capacitor CP4.

[0095] Moreover, one end of the fifth pump capacitor CP5 is connected to the anode of the fourth pump diode CP4, and the other end is connected to the ground terminal TGND (the second source terminal SOURSE2).

[0096] Moreover, one end of the sixth pump resistor RP6 is connected to the anode of the fourth pump diode DP4 (one end of the fifth pump capacitor CP5), and the other end is connected to the second negative power supply wiring HE2.

[0097] The second pump Zener diode VP2 has an anode connected to the other end of the sixth pump resistor RP6 (second negative power supply wiring HE2) and a cathode connected to the ground terminal TGND (second source terminal SOURSE2).

[0098] Moreover, the sixth pump capacitor CP6 has one end connected to the second negative power supply wiring HE2 and the other end connected to the ground terminal TGND (second source terminal SOURSE2).

[0099] The second charge pump circuit P2 having such a configuration generates a second negative power supply voltage VEE2 of opposite polarity to the second positive power supply voltage VCC2 based on the potential of the ground terminal TGND (the potential of the second source terminal SOURSE2) as a reference based on the second control signal SG2 that controls the second transistor SW2, and applies it to the second negative power supply wiring HE2.

[0100] Here, an example of a method for controlling the driving device 100 having the above configuration will be described.

[0101] As described above, the first gate driver circuit G1 outputs a first control signal SG1 generated from the first positive power supply voltage VCC1 of the first positive power supply wiring HC1 and the first negative power supply voltage VEE1 of the first negative power supply wiring HE1 to the control terminal (first gate terminal GATE1) of the first transistor SW1 to control the operation of the first transistor SW1.

[0102] Furthermore, the second gate driver circuit G2 outputs a second control signal SG2 generated from the second positive power supply voltage VCC2 of the second positive power supply wiring HC2 and the second negative power supply voltage VEE2 of the second negative power supply wiring HE2 to the control terminal (second gate terminal GATE2) of the second transistor SW2 to control the operation of the second transistor SW2 so that the first transistor SW1 and the second transistor SW2 are turned on / off complementarily.

[0103] As a result, the first transistor SW1 and the second transistor SW2 are controlled to be turned on / off complementarily, and a predetermined voltage is output from the output terminal TOUT.

[0104] On the other hand, as already described, the first charge pump circuit P1 generates a first negative power supply voltage VEE1 of opposite polarity to the first positive power supply voltage VCC1 based on the potential of the output terminal TOUT (the potential of the first source terminal SOURSE1) based on the first control signal SG1 that controls the first transistor SW1, and applies it to the first negative power supply wiring HE1.

[0105] Furthermore, the second charge pump circuit P2 generates a second negative power supply voltage VEE2 of opposite polarity to the second positive power supply voltage VCC2 based on the potential of the ground terminal TGND (the potential of the second source terminal SOURSE2) based on a second control signal SG2 that controls the second transistor SW2, and applies it to the second negative power supply wiring HE2.

[0106] In this manner, in the driving device 100 according to the first embodiment, the power supply circuit for generating a negative voltage is omitted to reduce the circuit size, while the first charge pump circuit is operated by the control signal of the first transistor output by the first driver circuit to generate a negative power supply voltage from the positive power supply voltage, and the negative power supply voltage is used to ensure a margin between the threshold voltage Vth of the first transistor and the control signal (gate voltage) when it is off, thereby shortening the dead time (FIG. 2).

[0107] That is, according to the driving device 100 of the first embodiment, it is possible to reduce the circuit scale and suppress the malfunction of the transistors with a short dead time.

[0108] In the driving device 100 according to the first embodiment, any or all of the second stabilization capacitor AC2, the second bootstrap diode BD2 of the second bootstrap circuit BS2, and the fourth stabilization capacitor AC4 may be omitted, as necessary. Example 2

[0109] As described above, in the driving device 100 according to the first embodiment, any or all of the second stabilization capacitor AC2, the second bootstrap diode BD2 of the second bootstrap circuit BS2, and the fourth stabilization capacitor AC4 may be omitted, as necessary.

[0110] Therefore, in the second embodiment, another configuration example of the drive device in which the above configuration is omitted will be described.

[0111] Here, Fig. 3 is a diagram showing an example of the configuration of a drive device 200 according to the second embodiment. In Fig. 3, the same reference numerals as those in Fig. 1 indicate the same configuration as in the first embodiment.

[0112] As shown in FIG. 3, for example, the driving device 200 according to the second embodiment has a configuration in which the second stabilization capacitor AC2, the fourth stabilization capacitor AC4, and the second bootstrap diode BD2 of the second bootstrap circuit BS2 are omitted, as compared with the driving device 100 according to the first embodiment.

[0113] Other configurations of the drive device according to the second embodiment are similar to those of the drive device according to the first embodiment shown in FIG.

[0114] That is, in the driving device 200 according to the present embodiment 2, similarly to the embodiment 1, the power supply circuit for generating a negative voltage is omitted to reduce the circuit size, while the first charge pump circuit is operated by the control signal of the first transistor output by the first driver circuit to generate a negative power supply voltage from the positive power supply voltage, and the negative power supply voltage is used to ensure a margin between the threshold voltage Vth of the first transistor and the control signal (gate voltage) when it is off, thereby shortening the dead time (FIG. 2).

[0115] That is, according to the driving device 200 of the second embodiment, it is possible to reduce the circuit scale and suppress the malfunction of the transistors with a short dead time.

[0116] As described above, the drive device according to one aspect of the present invention includes a power supply terminal TS to which a DC voltage is applied, a ground terminal TGND which is grounded, a first transistor SW1 having one end connected to the power supply terminal TS and the other end connected to the output terminal TOUT, a second transistor SW2 having one end connected to the output terminal TOUT and the other end connected to the ground terminal TGND, a first DC power supply X1 which outputs a first voltage V1, a first bootstrap diode BD1 having an anode to which the first voltage V1 is applied and a cathode connected to a first positive power supply wiring HC1, and a first bootstrap capacitor BC1 having one end connected to the cathode of the first bootstrap diode BD1 and the other end connected to the output terminal TOUT(SOURSE1), and a first stabilization capacitor AC1 having one end connected to the output terminal TOUT(SOURSE1) and the other end connected to a first negative power supply wiring (VEE1). a first gate driver circuit G1 that outputs a first control signal SG1 generated from a first positive power supply voltage VCC1 of the first positive power supply wiring and a first negative power supply voltage VEE1 of the first negative power supply wiring to a control terminal (gate) of the first transistor SW1 to control the operation of the first transistor; a second gate driver circuit G2 that outputs a second control signal generated from a second positive power supply voltage VCC2 of the second positive power supply wiring HC2 and a second negative power supply voltage VEE2 of the second negative power supply wiring to a control terminal (gate) of the second transistor SW2 to control the operation of the second transistor so that the first transistor and the second transistor are turned on / off complementarily; and a first charge pump circuit P1 that generates a first negative power supply voltage VEE1 of an opposite polarity to the first positive power supply voltage VCC1 based on the first control signal SG1 and applies the first negative power supply voltage VEE1 to the first negative power supply wiring.

[0117] In this way, in the driving device of the present invention, the power supply circuit for generating a negative voltage is omitted to reduce the circuit size, while the first charge pump circuit is operated by the control signal of the first transistor output by the first driver circuit to generate a negative power supply voltage from the positive power supply voltage, and the negative power supply voltage is used to ensure a margin between the threshold voltage Vth of the first transistor and the control signal (gate voltage) when it is off, thereby shortening the dead time (Figure 2).

[0118] That is, according to the driving device of the present invention, it is possible to reduce the circuit scale and suppress the malfunction of the transistor with a short dead time.

[0119] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0120] 100 Drive unit TS power terminal TGND Ground terminal SW1 First transistor SW2 Second transistor D1 First body diode D2 Second body diode X1 First DC power supply X2 Second DC power supply BS1 First bootstrap circuit BS2 Second bootstrap circuit AC1 First stabilizing capacitor AC2 Second stabilizing capacitor AC3 Third Stabilizing Capacitor AC4 4th stabilizing capacitor G1 First gate driver circuit G2 Second gate driver circuit P1 First charge pump circuit P2 Second charge pump circuit RP1 Resistor for the first pump RP2 Resistor for the second pump RP3 Third pump resistor RP4 4th pump resistor RP5 5th pump resistor RP6 6th pump resistor MP1 First pump bipolar transistor MP2 Second pump bipolar transistor MP3 Third pump bipolar transistor MP4 4th pump bipolar transistor CP1 First pump capacitor CP2 Second pump capacitor CP3 Third pump capacitor CP4 4th pump capacitor CP5 Fifth pump capacitor CP6 6th pump capacitor DP1 First pump diode DP2 Second pump diode DP3 Third pump diode DP4 4th pump diode VP1 First pump Zener diode VP2 Second pump Zener diode

Claims

1. A power supply terminal to which a DC voltage is applied; A ground terminal connected to a ground; a first transistor having one end connected to the power supply terminal and the other end connected to an output terminal; a second transistor having one end connected to the output terminal and the other end connected to the ground terminal; a first DC power supply that outputs a first voltage; a first bootstrap circuit including a first bootstrap diode having an anode to which the first voltage is applied and a cathode connected to a first positive power supply wiring, and a first bootstrap capacitor having one end connected to the cathode of the first bootstrap diode and the other end connected to the output terminal; a first stabilization capacitor having one end connected to the output terminal and the other end connected to a first negative power supply line; a first gate driver circuit that outputs a first control signal generated from a first positive power supply voltage of the first positive power supply wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor to control an operation of the first transistor; a second gate driver circuit that outputs a second control signal generated from a second positive power supply voltage of a second positive power supply wiring and a second negative power supply voltage of a second negative power supply wiring to a control terminal of the second transistor, thereby controlling an operation of the second transistor so that the first transistor and the second transistor are turned on / off complementarily; a first charge pump circuit that generates the first negative power supply voltage having a polarity opposite to that of the first positive power supply voltage with reference to a potential of the output terminal based on the first control signal and applies the first negative power supply voltage to the first negative power supply wiring; a second DC power supply that outputs a second voltage; a second bootstrap circuit including a second bootstrap diode having an anode to which the second voltage is applied and a cathode connected to the second positive power supply wiring, and a second bootstrap capacitor having one end connected to the cathode of the second bootstrap diode and the other end connected to the ground terminal; a third stabilizing capacitor having one end connected to the ground terminal and the other end connected to the second negative power supply wiring; a fourth stabilization capacitor having one end connected to the cathode of the second bootstrap diode and the other end connected to the second negative power supply wiring; a second charge pump circuit that generates the second negative power supply voltage having a polarity opposite to that of the second positive power supply voltage with respect to a potential of the ground terminal based on the second control signal and applies the second negative power supply voltage to the second negative power supply wiring; The first gate driver circuit includes: PWM-controlling an operation of the first transistor by the first control signal; The second gate driver circuit includes: The operation of the second transistor is PWM-controlled by the second control signal so that the first transistor and the second transistor are complementarily turned on / off. A drive device characterized by:

2. The first charge pump circuit includes: A power supply line connected to the first positive power supply line, the first negative power supply line, the control terminal of the first transistor, and the output terminal 2. The drive device according to claim 1 .

3. The second charge pump circuit includes: a second positive power supply wiring, a second negative power supply wiring, the control terminal of the second transistor, and the ground terminal; 2. The drive device according to claim 1 .

4. In the relationship between the PWM control of the first transistor by the first control signal and the PWM control of the second transistor by the second control signal, a dead time during which both transistors are turned off is set.

2. The drive device according to claim 1 .

5. The first charge pump circuit includes: a first pump resistor having one end connected to the control terminal of the first transistor; a first pump bipolar transistor having a collector connected to the first positive power supply wiring and a base connected to the other end of the first pump resistor; a second pump bipolar transistor having a collector connected to the emitter of the first pump bipolar transistor, a base connected to the other end of the first pump resistor, and an emitter connected to the output terminal; a second pump resistor having one end connected to the emitter of the first pump bipolar transistor; a first pump capacitor, one end of which is connected to the other end of the second pump resistor; a first pump diode having an anode connected to the other end of the first pump capacitor and a cathode connected to the output terminal; a second pump diode having a cathode connected to the other end of the first pump capacitor; a second pump capacitor having one end connected to the anode of the second pump diode and the other end connected to the output terminal; a third pump resistor, one end of which is connected to the anode of the second pump diode and the other end of which is connected to the first negative power supply wiring; a first pump Zener diode having an anode connected to the first negative power supply wiring and a cathode connected to the output terminal; a third pump capacitor having one end connected to the first negative power supply wiring and the other end connected to the output terminal; 3. The drive device according to claim 2.

6. The second charge pump circuit includes: a fourth pump resistor having one end connected to the control terminal of the second transistor; a third pump bipolar transistor having a collector connected to the second positive power supply wiring and a base connected to the other end of the fourth pump resistor; a fourth pump bipolar transistor having a collector connected to the emitter of the third pump bipolar transistor, a base connected to the other end of the fourth pump resistor, and an emitter connected to the ground terminal; a fifth pump resistor having one end connected to the emitter of the third pump bipolar transistor; a fourth pump capacitor, one end of which is connected to the other end of the fifth pump resistor; a third pump diode having an anode connected to the other end of the fourth pump capacitor and a cathode connected to the ground terminal; a fourth pump diode having a cathode connected to the other end of the fourth pump capacitor; a fifth pump capacitor, one end of which is connected to the anode of the fourth pump diode and the other end of which is connected to the ground terminal; a sixth pump resistor having one end connected to the anode of the fourth pump diode and the other end connected to the second negative power supply wiring; a second pump Zener diode having an anode connected to the other end of the sixth pump resistor and a cathode connected to the ground terminal; a sixth pump capacitor having one end connected to the second negative power supply wiring and the other end connected to the ground terminal; 4. The drive device according to claim 3.

7. a power supply terminal to which a DC voltage is applied, a ground terminal which is grounded, a first transistor having one end connected to the power supply terminal and the other end connected to an output terminal, a second transistor having one end connected to the output terminal and the other end connected to the ground terminal, a first DC power supply which outputs a first voltage, a first bootstrap diode having an anode to which the first voltage is applied and a cathode connected to a first positive power supply wiring, and a first bootstrap diode having one end connected to the cathode of the first bootstrap diode and the other end connected to the output terminal. a first bootstrap circuit having a bootstrap capacitor, a first stabilization capacitor having one end connected to the output terminal and the other end connected to a first negative power supply wiring, a first gate driver circuit which outputs a first control signal generated from a first positive power supply voltage of the first positive power supply wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor to control an operation of the first transistor, and a second gate driver circuit that outputs a control signal to a control terminal of the second transistor to control an operation of the second transistor so that the first transistor and the second transistor are complementarily turned on / off; a first charge pump circuit that generates the first negative power supply voltage having an opposite polarity to the first positive power supply voltage with reference to the potential of the output terminal based on the first control signal and applies the first negative power supply voltage to the first negative power supply wiring; a second DC power supply that outputs a second voltage; a second bootstrap circuit having a second bootstrap diode connected to the cathode of the second bootstrap diode and a second bootstrap capacitor having one end connected to the ground terminal and the other end connected to the ground terminal; a third stabilization capacitor having one end connected to the ground terminal and the other end connected to a second negative power supply wiring; and a fourth stabilization capacitor having one end connected to the cathode of the second bootstrap diode and the other end connected to the second negative power supply wiring,a second charge pump circuit that generates the second negative power supply voltage having a polarity opposite to that of the second positive power supply voltage with respect to a potential of the ground terminal as a reference and applies the second negative power supply voltage to the second negative power supply wiring, outputting the first control signal generated from a first positive power supply voltage of the first positive power supply wiring and a first negative power supply voltage of the first negative power supply wiring to a control terminal of the first transistor to control an operation of the first transistor; outputting the second control signal generated from the second positive power supply voltage of the second positive power supply wiring and the second negative power supply voltage of the second negative power supply wiring to a control terminal of the second transistor, thereby controlling an operation of the second transistor so that the first transistor and the second transistor are turned on / off complementarily; the first charge pump circuit generates the first negative power supply voltage having a polarity opposite to that of the first positive power supply voltage with reference to a potential of the output terminal based on the first control signal, and applies the first negative power supply voltage to the first negative power supply wiring; The first gate driver circuit PWM-controls an operation of the first transistor using the first control signal; The second gate driver circuit PWM-controls the operation of the second transistor so that the first transistor and the second transistor are complementarily turned on / off by the second control signal. A method for controlling a drive device comprising:

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