Treatment to improve material structure

Abstract

To provide a system and a method that can be used to form a thin (e.g., less than 1 nm EOT) high-k dielectric material layer with a chemical structure that can be controlled to ensure desired structural and electrical properties.SOLUTION: A method of forming a semiconductor structure includes pre-cleaning the surface of a substrate, forming an interfacial layer on the pre-cleaned surface of the substrate, depositing a high-k dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer, and performing a post-nitridation annealing process to passivate the chemical bonds within the plasma-nitrided high-k dielectric layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments described herein relate generally to the manufacture of semiconductor devices, and more particularly to systems and methods for forming high quality, high k dielectric material layers in semiconductor structures. [Background technology]

[0002]

[0002] As the size of metal oxide semiconductor field effect transistors (MOSFETs) has been reduced to achieve high device performance and low power consumption, the traditional silicon dioxide (SiO 2 The thickness of the SiO2 gate dielectric has been reduced to its physical limit. As a result, replacing the silicon dioxide gate dielectric with a high-k dielectric material is inevitable to achieve further scaling. Among the various high-k dielectric materials, hafnium oxide (HfO 2 ) has been applied since the 45-nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on silicon substrates. However, for further scaling of the equivalent oxide thickness (EOT) to the 32-nm MOSFET technology node and beyond, simply reducing the thickness of the high-k dielectric material layer is problematic because of the increased leakage current through the high-k dielectric material layer.

[0003]

[0003] Therefore, there is a need for systems and methods that can be used to form thin (e.g., less than 1 nm EOT), high-k dielectric material layers having chemical structures that can be controlled to ensure desired structural and electrical properties. Summary of the Invention

[0004]

[0004] An embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including pre-cleaning a surface of a substrate, forming an interfacial layer on the pre-cleaned surface of the substrate, depositing a high-k dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer, and performing a post-nitridation annealing process to passivate chemical bonds in the plasma nitrided high-k dielectric layer.

[0005]

[0005] An embodiment of the present disclosure also provides a method of forming a semiconductor structure, the method including pre-cleaning a surface of a substrate, depositing a high-k dielectric layer on the substrate, and performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer.

[0006]

[0006] An embodiment of the present disclosure further provides a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, and a system controller. The system controller is configured to pre-clean a surface of a substrate in the first processing chamber, form an interface layer on the pre-cleaned surface of the substrate in the second processing chamber, deposit a high-k dielectric layer on the interface layer in the third processing chamber, expose the deposited high-k dielectric layer to a nitrogen plasma in the fourth processing chamber, and anneal the plasma-nitrided high-k dielectric layer in the fifth processing chamber. The substrate is transferred between the first, second, third, fourth, and fifth processing chambers without breaking a vacuum environment in the processing system.

[0007]

[0007] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic top view of an exemplary multi-chamber processing system according to an embodiment. [Diagram 2] FIG. 1 is a process flow diagram of a method for forming a semiconductor structure according to one embodiment. [Diagram 3] 3A and 3B are schematic diagrams of a semiconductor structure according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0011] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0010]

[0012] As gate structures scale to smaller dimensions, new material structures are sought to provide improvements. The use of high-k dielectric materials provides a gate structure with a higher dielectric constant than traditional gate structures that use materials such as silicon oxide. However, similar to silicon oxide, as the thickness of the gate structure decreases, leakage current increases. For example, as the equivalent oxide thickness decreases, gate leakage increases. Thus, the inverse relationship between gate leakage and equivalent oxide thickness can form a limit on the performance of the transistor and the devices fabricated.

[0011]

[0013] High-k dielectric materials can provide greater channel mobility than silicon oxide at similar thicknesses. As the industry continues to push for thinner equivalent oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also called "kappa value") of known high-k materials are reaching limits due to morphological characteristics. Conventional techniques have struggled to overcome the natural properties of high-k materials that can set an upper limit on kappa values, and have subsequently modified devices to incorporate new films.

[0012]

[0014] The embodiments described herein provide systems and methods for improving the properties of high-k dielectric materials. By fabricating high-k dielectric materials that exhibit specific morphologies or grain structures, higher dielectric constants and subsequent improved device performance can be possible. To control grain formation in exemplary devices, treatments can be performed to provide an activated substrate surface that can induce specific grain growth, as well as to stabilize the film after formation, which can result in a higher dielectric constant.

[0013]

[0015] FIG. 1 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 may be processed in and transferred between various chambers without exposing the wafers to an ambient environment outside the processing system 100 (e.g., an atmospheric environment such as may be present in a fab). For example, wafers may be processed in and transferred between various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment between various processes performed on the wafers in the processing system 100. Thus, the processing system 100 may provide an integrated solution for several processing of wafers.

[0014]

[0016] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems available from Applied Materials, Inc., Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from aspects described herein.

[0015]

[0017] 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate transfer of wafers. The docking station 140 is configured to receive one or more front opening integrated pods (FOUPs) 144. In some examples, each factory interface robot 142 generally comprises a blade 148 disposed at one end of the respective factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0016]

[0018] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings with slit valves for passing a wafer through by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas passing between the respective chambers. Generally, any port is open to pass a wafer through; otherwise, the port is closed.

[0017]

[0019] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 to the load lock chamber 104 or 106 through the port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. Additionally, the gas and pressure control system maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chambers 104 or 106 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0018]

[0020] The transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 to the transfer chamber 108 via the port 154 or 156 after it has been pumped down. The transfer robot 112 can then transfer the wafer to and / or between any of the processing chambers 120, 122 via the respective ports 162, 164 for processing, any of the holding chambers 116, 118 via the respective ports 158, 160 for holding awaiting further transfer. Similarly, the transfer robot 114 can access the wafer in the holding chamber 116 or 118 via the port 166 or 168 and transfer the wafer to and / or between any of the processing chambers 124, 126, 128, 130 via the respective ports 170, 172, 174, 176 for processing, any of the holding chambers 116, 118 via the respective ports 166, 168 for holding awaiting further transfer. Transfer and holding of the wafer within and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0019]

[0021] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some examples, the processing chamber 122 may perform a cleaning process, the processing chamber 120 may perform an etching process, and the processing chambers 124, 126, 128, 130 may perform respective epitaxial growth processes. The processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., Santa Clara, Calif. The processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials, Inc., Santa Clara, Calif.

[0020]

[0022] A system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or its components. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. During operation, the system controller 190 allows for data collection and feedback from each chamber to regulate the performance of the processing system 100.

[0021]

[0023] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 194, i.e., a non-transitory computer-readable medium, is accessible by the CPU 192 and may be one or more of memory such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or other forms of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be performed under the control of the CPU 192 by the CPU 192 executing computer instruction codes stored in the memory 194 (or in the memory of a particular processing chamber), for example as software routines. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chamber to perform processes according to various methods.

[0022]

[0024] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0023]

[0025] FIG. 2 is a process flow diagram of a method 200 of forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. FIGs. 3A and 3B are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIGs. 3A and 3B show only a partial schematic view of the semiconductor structure 300, and that the semiconductor structure 300 may include any number of transistor sections and additional materials having the aspects as shown in the figures. It should also be noted that while the method steps shown in FIG. 2 are described sequentially, other process sequences including one or more method steps omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the present disclosure provided herein.

[0024]

[0026] The method 200 begins with a pre-cleaning process at block 210 to pre-clean the surface of the substrate 302. The pre-cleaning process includes the use of NH 4 OH (ammonium hydroxide), H 2 O 2 (hydrogen peroxide), and H 2 By a wet etching process using an etching solution such as a Standard Clean 1 (SC1) etching solution containing O (water), or by a dry etching process, e.g., where the surface of the substrate 302 is N 2 , N.F. 3 , and N.H. 3This can include etching the surface of the substrate 302 by a SiConi™ remote plasma assisted dry etching process, which exposes the surface to plasma by-products. The pre-clean process can be performed in a pre-clean chamber, such as processing chamber 122 or 120 shown in FIG.

[0025]

[0027] In block 220, as shown in FIG. 3A, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302. The interface formation process uses nitrous oxide (N 2 The interface layer 304 formed in block 220 may include a suitable thermal oxidation process such as an enhanced in situ steam generation (eISSG) process utilizing O (O) gas. 2 ) layer and has a thickness of between about 3 Å and about 10 Å, e.g., about 5 Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interfacial layer 304 is a H 2 and O 2 The in situ steam generation (ISSG) process utilizes gas, or NH 3 and O 2 The interface layer 304 may be formed by a rapid thermal oxidation (RTO) process utilizing a gas. The interface layer 304 may act as a nucleation layer for a high-k dielectric material layer deposited thereon and improve the quality of the interface (e.g., interface state density, storage capacitance, frequency dispersion, leakage current, etc.) between the substrate 302 and the high-k dielectric material layer. The interface formation process may be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0026]

[0028] In some embodiments, the interface formation process of block 220 is omitted, and the interface layer 304 is not formed before depositing the high-k dielectric material layer on the substrate 302. In that case, the interface layer 304 is formed by the thermal oxidation process of block 250 or block 290 described below, which thermally oxidizes the substrate 302 through the high-k dielectric material layer deposited on the substrate 302. The interface layer 304 formed by the thermal oxidation process of block 250 or block 290 may be thick enough to ensure reliable device characteristics (e.g., interface state density, storage capacitance, frequency dispersion, leakage current, etc.) and reduce atomic diffusion from the high-k dielectric material layer to the substrate 302, and has a thickness between about 0.3 nm and about 1 nm, for example about 0.5 nm.

[0027]

[0029] In block 230, a deposition process is performed to deposit a high-k dielectric layer 306 on the exposed surface of the semiconductor structure 300 (i.e., the interfacial layer 304 as shown in FIG. 3B if the interfacial layer 304 is formed in block 220, and the substrate 302 if the interfacial layer 304 is not formed in block 220). The high-k dielectric layer 306 is made of hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), ytterbium oxide (Y 2 O 3 ), or aluminum oxide (Al 2 O 3302。 The deposition process may include an atomic layer deposition (ALD) process in which a metal-containing precursor and an oxygen-containing precursor are alternately delivered to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before delivering the oxygen-containing precursor. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), yttrium (Y), an alkaline earth metal such as strontium (Sr), or other metals such as aluminum (Al). For the oxidizer, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen and oxygen-containing precursors, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated into a metal to produce a layer of oxide of the metal on the substrate 302. In one example, hafnium dioxide (HfO 2 To form the CrN layer, the metal-containing precursor is hafnium tetrachloride (HfCl 4 ) and the oxidizing agent is water (H 2 O). The ALD process can be performed at a temperature between about 200° C. and about 400° C., for example, about 270° C. The high-k dielectric layer 306 deposited by the ALD process can be amorphous and can have a thickness between about 10 Å and about 30 Å. The deposition process can be performed in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1.

[0028]

[0030] In block 240, an optional post-deposition anneal process is performed to harden and densify the as-deposited high-k dielectric layer 306. Crystallization of the as-deposited amorphous high-k dielectric layer 306 may occur. The post-deposition anneal process may be performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif., using nitrogen (N 21. The RTP chamber may include a thermal annealing process in an inert atmosphere, such as a SiO 2 (SiO 3 ) and Argon (Ar) atmosphere. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The post-deposition annealing process may thermally harden and densify the interfacial layer 304 and the high-k dielectric layer 306.

[0029]

[0031] The post-deposition anneal process can be carried out for about 1 second to about 60 seconds, at a temperature between about 500° C. and about 800° C., and at a pressure between about 0.01 Torr and 10 Torr.

[0030]

[0032] In block 250, instead of the post-deposition anneal process of block 240, an optional re-oxidation process is performed to thermally oxidize the substrate 302. The re-oxidation process is performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif. 2 ), nitrous oxide (N 2 O), and H 2 1. The RTP chamber may include a thermal annealing process at ambient temperature. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The re-oxidation process of block 250 may thermally oxidize the underlying layers through the high-k dielectric layer 306, thus thickening the interfacial layer 304 to a thickness of between about 3 Å and about 10 Å if the interfacial layer 304 is formed in block 220, or forming the interfacial layer 304 in the substrate 302 near the interface with the high-k dielectric layer 306 if the interfacial layer 304 is not formed in block 220.

[0031]

[0033] The reoxidation process can be carried out for about 1 second to about 30 seconds, at a temperature between about 400° C. and about 900° C., and at a pressure between about 0.01 Torr and 100 Torr.

[0032]

[0034] At block 260, a plasma nitridation process is performed to insert nitrogen atoms into the vacancies and defects of the high-k dielectric layer 306. The plasma nitridation process can be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, Calif. The DPN chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The plasma nitridation process exposes the high-k dielectric layer 306 to a nitrogen plasma, which allows nitrogen radicals or nitrogen atoms to be incorporated into the high-k dielectric layer 306 throughout its thickness. During the plasma nitridation process, the nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in the plasma process include nitrogen (N 2 ), ammonia (NH 3 ), or mixtures thereof. In one example, the nitrogen gas contains about 3% to about 8% nitrogen (N 2 ) and ammonia (NH 3 ) The plasma nitridation process does not change the thickness of the high-k dielectric layer 306 as a result of nitrogen incorporation into pores and defects in the as-deposited high-k dielectric layer 306.

[0033]

[0035] The nitridation process can be carried out at a temperature between about 0° C. and about 500° C. for a time period between about 10 seconds and about 300 seconds.

[0034]

[0036] At block 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into vacancies and defects in the plasma nitrided high-k dielectric layer 306. The thermal nitridation process is performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif., using ammonia (NH 3The RTP chamber may include a thermal annealing process in a .) ambient atmosphere. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG.

[0035]

[0037] The thermal nitridation process can be carried out for about 10 seconds to about 300 seconds, at a temperature between about 700° C. and about 900° C., and at a pressure between about 10 Torr and 740 Torr.

[0036]

[0038] At block 280, a post-nitridation anneal process is performed to passivate remaining chemical bonds in the plasma nitrided high-k dielectric layer 306. The post-nitridation anneal process is performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif., using nitrogen (N 2 ) and argon (Ar) ambient. The RTP chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-nitridation anneal process can passivate metastable nitrogen bonds formed in the plasma nitridation process of block 240, and crystallization of the amorphous high-k dielectric layer 306 can occur.

[0037]

[0039] The spike thermal anneal process can be carried out for about 1 second to about 30 seconds, at a temperature between about 700° C. and about 850° C., and at a pressure between about 10 Torr and 740 Torr.

[0038]

[0040] In block 290, instead of the post-nitridation anneal process of block 280, a post-nitridation anneal and reoxidation process is performed to passivate the remaining chemical bonds in the high-k dielectric layer 306 as in block 280, while simultaneously thermally oxidizing the substrate 302 as in block 250. The post-nitridation anneal and reoxidation process in block 290 is the same as the reoxidation process in block 250. Therefore, details of the post-nitridation anneal and reoxidation process in block 290 are omitted here.

[0039]

[0041] In the embodiments described herein, systems and methods for forming high-quality thin high-k dielectric material layers are provided. The properties of such high-k dielectric material layers can be well controlled. For example, the nitridation process in blocks 260 and 270 can be controlled to provide between about 3 atomic % and about 20 atomic % nitrogen incorporation into the high-k dielectric layer 306 to achieve a higher κ value than more nitrogen incorporation and better structural stabilization than less nitrogen incorporation. The annealing process in blocks 240, 270, 280, and 290 can also be controlled to provide grains having a size greater than about 20 Å in the high-k dielectric layer 306 to reduce leakage current through the high-k dielectric layer 306.

[0040]

[0042] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims. The present application further includes the aspects described below. (Aspect 1) 1. A method of forming a semiconductor structure, comprising: Pre-cleaning a surface of the substrate; depositing a high-k dielectric layer on the substrate; performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer; performing a re-oxidation process to passivate remaining chemical bonds in the plasma nitrided high-k dielectric layer and to thermally oxidize the substrate; 23. A method comprising forming a semiconductor structure comprising: (Aspect 2) 2. The method of embodiment 1, wherein forming the semiconductor structure is performed in a processing system without breaking vacuum. (Aspect 3) Nitrous oxide (N 2 forming an interfacial layer on the pre-cleaned surface of the substrate, the interfacial layer comprising thermally oxidizing the substrate utilizing silicon oxide (SiO) gas, 2 2. The method of embodiment 1, comprising: (Aspect 4) The high dielectric constant dielectric layer is made of hafnium oxide (HfO 2 2. The method of embodiment 1, comprising: (Aspect 5) The plasma nitridation process nitriding the deposited high-k dielectric layer with nitrogen (N 2 ) and ammonia (NH 3 2. The method of embodiment 1, comprising exposing the material to a nitrogen plasma using a mixture of N 2 ) gases. (Aspect 6) The re-oxidation process is a process for reoxidizing the high-k dielectric layer by treating the layer with oxygen (O2 ), nitrous oxide (N 2 O), and H 2 2. The method of embodiment 1, comprising annealing in an atmosphere. (Aspect 7) A first processing chamber; A second processing chamber; a third processing chamber; and System Controller, 1. A processing system comprising: pre-cleaning a surface of a substrate in the first processing chamber; depositing a high-k dielectric layer on the substrate in the second processing chamber; performing a plasma nitridation process in the third processing chamber to expose the deposited high-k dielectric layer to a nitrogen plasma; The device is configured to: A processing system, wherein the substrate is transferred between the first processing chamber, the second processing chamber, and the third processing chamber without breaking a vacuum environment within the processing system. (Aspect 8) further comprising a fourth processing chamber; 8. The processing system of embodiment 7, wherein the system controller is further configured to form an interface layer on the pre-cleaned surface of the substrate in the fourth processing chamber. (Aspect 9) further comprising a fifth processing chamber; 9. The processing system of claim 8, wherein the system controller is further configured to perform a post-nitridation annealing process in the fifth processing chamber to anneal the plasma nitrided high-k dielectric layer. (Aspect 10) further comprising a sixth processing chamber; 10. The processing system of embodiment 9, wherein the system controller is further configured to perform a post-deposition annealing process prior to the plasma nitridation process to harden and densify the deposited high-k dielectric layer. (Aspect 11) further comprising a sixth processing chamber; 10. The processing system of claim 9, wherein the system controller is further configured to perform a plasma nitridation process prior to the post-nitridation annealing process to further insert nitrogen atoms into the plasma nitrided high-k dielectric layer. (Aspect 12) further comprising a fifth processing chamber; The processing system of aspect 8, wherein the system controller is further configured to perform a re-oxidation process in the fifth processing chamber to passivate remaining chemical bonds in the plasma nitrided high-k dielectric layer and to thermally oxidize the substrate. [Explanation of symbols]

[0041] 100 Processing Systems 102 Factory Interface 104 Load Lock Chamber 106 Load Lock Chamber 108 Transfer chamber 110 Transfer chamber 112 Transport Robot 114 Transport Robot 116 Chamber 118 Chamber 120 Processing chamber 122 Processing chamber 124 Processing chamber 126 Processing Chamber 128 Processing Chamber 130 Processing chamber 140 Stations 142 Factory Interface Robot 144 Forward Opening Integrated Pod (FOUP) 148 Blade 150 Port 152 each port 154 Port 156 Port 158 Port 160 Port 162 port 164 port 166 Port 168 Port 170 Port 172 Port 174 Port 176 Port 190 System Controller 192 Central Processing Unit (CPU) 194 Memory 196 Support Circuit 200 ways 210 Block 220 Block 230 Block 240 blocks 250 blocks 260 blocks 270 blocks 280 blocks 290 blocks 300 Semiconductor Structure 302 Substrate 304 Interface layer 306 Gate dielectric layer 400 ways 410 Block 420 Block 430 Block 440 Block 450 Block 460 blocks 480 blocks 500 Metal Gate Structure 502 Dielectric Cap Layer 504 Sacrificial Silicon Cap Layer 506 Metal layer

Claims

1. 1. A method of forming a semiconductor structure, comprising: Pre-cleaning a surface of a substrate; forming an interface layer on the pre-cleaned surface of the substrate; depositing a high-k dielectric layer over the interfacial layer; performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer; performing a post-nitridation anneal process to passivate chemical bonds within the plasma nitrided high-k dielectric layer; forming a semiconductor structure comprising:

20. The method of claim 19, further comprising: performing a thermal nitridation process prior to said post-nitridation anneal process to further insert nitrogen atoms into said plasma nitrided high-k dielectric layer.

2. The method of claim 1 , wherein forming the semiconductor structure is performed in a processing system without breaking vacuum.

3. The interface layer is made of silicon oxide (SiO ２ ), The formation of the interface layer comprises nitrous oxide (N ２ 10. The method of claim 1, further comprising thermally oxidizing the substrate using a fluorine-containing gas.

4. The high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ 2. The method of claim 1 , comprising:

5. The plasma nitridation process nitriding the deposited high-k dielectric layer with nitrogen (N ２ ) and ammonia (NH ３ 2. The method of claim 1, comprising exposing the material to a nitrogen plasma using a mixture of nitrogen and argon gases.

6. The post-nitridation anneal process anneals the deposited high-k dielectric layer at a temperature between 700° C. and 850° C. with nitrogen (N ２ 2. The method of claim 1, comprising spike annealing in an atmosphere of 0.1% NaCl and 0.1% Argon (Ar).

7. 10. The method of claim 1, further comprising performing a post-deposition anneal process prior to said plasma nitridation process to harden and densify the deposited high-k dielectric layer.

8. The post-deposition anneal process anneals the deposited high-k dielectric layer at a temperature between 500° C. and 800° C. with nitrogen (N ２ 8. The method of claim 7, comprising annealing in an atmosphere of 0.1 MgO and 0.2 MgO.

9. The thermal nitridation process is performed by nitriding the plasma-nitrided high-k dielectric layer with ammonia (NH ３ 2. The method of claim 1 , comprising annealing in a .

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