Stacked capacitor and method of manufacturing same

Abstract

To provide a lamination type capacitor capable of reducing thickness deviations between an internal electrode and a dielectric layer in the whole capacitor body and end bending of the internal electrode, and a method for manufacturing the same.SOLUTION: A lamination type capacitor includes: a capacitor body in which two or more lamination units 110 and 210 which include a plurality of dielectric layers 111 and 211 and a plurality of first and second internal electrodes 121, 221, 122 and 222 that are alternately arranged so as to sandwich the dielectric layer are arranged in one row in a lamination direction of the dielectric layer; and first and second external electrodes 131 and 132 which are arranged in the capacitor body so as to be electrically connected to the first and second internal electrode. In the capacitor body, the mutually adjacent lamination units are arranged so that faces having similar densities face each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a multilayer capacitor and a method for manufacturing the same. [Background technology]

[0002] A multi-layer ceramic capacitor (MLCC) is a passive element that controls electrical signals in a circuit.

[0003] The main role of a multilayer capacitor is to accumulate electric charge in the electrodes and act as a filter that blocks direct current (DC) signals and passes alternating current (AC) signals.

[0004] In other words, the stacked capacitor plays a role in stabilizing the operation of ICs by bypassing and removing AC noise from the power line.

[0005] Recently, as technologies such as 5G, electrical products, and servers continue to develop, the demand for stacked capacitors in these fields is also increasing significantly.

[0006] As an example, in the case of 5G mobile phones, the amount of stacked capacitors used is expected to increase by about 2 to 3 times compared to currently used 4G mobile phones.

[0007] One of the characteristics of such a multilayer capacitor is the breakdown voltage (BDV).

[0008] BDV refers to the voltage at which dielectric breakdown of the ceramic occurs when the voltage applied to a multilayer capacitor is increased. It is known that such dielectric breakdown occurs when the temperature of a locally thin portion of the dielectric increases rapidly due to leakage current.

[0009] In particular, if the thickness or shape of the ends of the internal electrodes stacked in the capacitor body is not constant and deformed into an irregular shape due to the step between the dielectric layer and the internal electrodes, the capacitor may be vulnerable to dielectric breakdown.

[0010] On the other hand, such deformation becomes larger as the number of layers in the multilayer capacitor increases, that is, the sum of the interlayer steps between the dielectric layers and the internal electrodes increases.

[0011] Recently, in the case of products for servers, highly stacked internal electrodes of 800 to 1500 layers are used to achieve high capacitance, so such deformation can become a serious problem. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Korean Patent Publication No. 2015-0053424 [Patent Document 2] JP 2009-71106 A Summary of the Invention [Problem to be solved by the invention]

[0013] An object of the present invention is to provide a multilayer capacitor and a manufacturing method thereof that can reduce the deviation in thickness between the internal electrodes and the dielectric layers and the bending of the ends of the internal electrodes throughout the entire capacitor body. [Means for solving the problem]

[0014] One aspect of the present invention provides a multilayer capacitor including: a capacitor body in which two or more multilayer units, each including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately arranged with the dielectric layers in between, are arranged in a row along a stacking direction of the dielectric layers; and first and second external electrodes arranged on the capacitor body to be electrically connected to the first and second internal electrodes, respectively, wherein adjacent multilayer units in the capacitor body are arranged such that surfaces corresponding to high density portions face each other or surfaces corresponding to low density portions face each other.

[0015] In an embodiment of the present invention, the capacitor body may further include a buffer layer disposed between adjacent stack units.

[0016] In one embodiment of the present invention, the capacitor body may include a first lamination unit having a low density portion located at an upper portion, and a second lamination unit disposed below the first lamination unit and having a high density portion located at an upper portion.

[0017] In one embodiment of the present invention, the capacitor body may include a first stack unit having a low-density portion located at an upper portion, and a second stack unit disposed below the first stack unit and having a high-density portion located at an upper portion, and the first stack unit and the second stack unit may be stacked alternately once.

[0018] Another aspect of the present invention provides a multilayer capacitor including: a capacitor body in which two or more multilayer units, each including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately arranged with the dielectric layers therebetween, are arranged in a row along a stacking direction of the dielectric layers; and first and second external electrodes arranged on the capacitor body to be electrically connected to the first and second internal electrodes, respectively, wherein each of the multilayer units is formed such that the widths of the first and second internal electrodes gradually narrow from a middle portion of the multilayer unit toward the top and bottom.

[0019] In one embodiment of the present invention, when the maximum width of the first or second internal electrode is defined as W1 and the minimum width of the first or second internal electrode is defined as W2, the laminate unit can satisfy W2 / W1≧0.96.

[0020] In yet another aspect of the present invention, there is provided a method for manufacturing a multilayer capacitor, the method including: providing a multilayer bar including a plurality of ceramic sheets and a plurality of first and second internal electrodes alternately disposed with the ceramic sheets in between; arranging the two or more multilayer bars in a row such that faces corresponding to high density portions of the two or more multilayer bars face each other or faces corresponding to low density portions of the two or more multilayer bars face each other to provide a multilayer body; pressing the multilayer body; cutting and firing the multilayer body so that first and second internal electrodes of the pressed multilayer body are exposed to provide a capacitor body; and forming first and second external electrodes on the capacitor body to be electrically connected to the exposed portions of the first and second internal electrodes, respectively.

[0021] In the step of providing the stack according to an embodiment of the present invention, the stack may be formed by disposing a buffer layer between adjacent stack bars.

[0022] In one embodiment of the present invention, in the step of providing the laminate, the laminate may be formed by placing a second laminate bar having a high density portion located at an upper portion, and stacking a first laminate bar having a low density portion located at an upper portion on top of the second laminate bar.

[0023] In one embodiment of the present invention, the laminate may include a plurality of first and second laminate bars, and may be formed by stacking the first laminate bars and the second laminate bars one by one in an alternating arrangement.

[0024] In one embodiment of the present invention, in the step of providing the laminate, the alignment of the laminate bars may be performed by forming holes in each laminate bar using a laser drill and then using an alignment lamination machine.

[0025] Another aspect of the present invention provides a method for manufacturing a multilayer capacitor, the method including: providing a multilayer bar including a plurality of ceramic sheets and a plurality of first and second internal electrodes alternately arranged with the ceramic sheets sandwiched therebetween; arranging the two or more multilayer bars in a row such that surfaces on which the ceramic sheets are first laminated in two or more multilayer bars face each other or surfaces on which the ceramic sheets are last laminated face each other to provide a multilayer body; pressing the multilayer body; cutting and firing the multilayer body so that first and second internal electrodes of the pressed multilayer body are exposed to provide a capacitor body; and forming first and second external electrodes on the capacitor body to be electrically connected to exposed portions of the first and second internal electrodes, respectively.

[0026] In one embodiment of the present invention, in the step of providing the laminate, the laminate may be formed by first placing a second laminate bar having a surface on which a ceramic sheet is laminated at an upper position, and then finally laminating a first laminate bar having a surface on which a ceramic sheet is laminated at an upper position on the second laminate bar. Effect of the Invention

[0027] According to an embodiment of the present invention, two or more ceramic multilayer units are manufactured, and the ceramic multilayer units are arranged in a row such that the first laminated surfaces of the two or more ceramic multilayer units face each other or the last laminated surfaces of the two or more ceramic multilayer units face each other, and then compressed to form a capacitor body. This has the effect of reducing the deviation in thickness of the internal electrodes and the dielectric layers throughout the capacitor body and reducing bending of the ends of the internal electrodes. [Brief description of the drawings]

[0028] [Figure 1] 1 is a perspective view illustrating a multilayer capacitor according to a first embodiment of the present invention; [Diagram 2] 2 is a plan view showing an internal electrode included in the first laminate unit of FIG. 1. FIG. [Diagram 3] 2 is a plan view showing an internal electrode included in the second laminate unit of FIG. 1. FIG. [Figure 4] 2 is a cross-sectional view taken along line II' in FIG. [Diagram 5] 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 6] 2 is a cross-sectional view taken along line II-II' of FIG. 1, showing the multilayer capacitor according to the second embodiment of the present invention. [Figure 7] 2 is a cross-sectional view showing a cross section taken along line II-II' of FIG. 1 in a multilayer capacitor according to a third embodiment of the present invention. [Figure 8] 2 is a cross-sectional view showing a cross section corresponding to line II' of FIG. 1 in a multilayer capacitor according to a third embodiment of the present invention. [Figure 9] 2 is a cross-sectional view showing a cross section corresponding to line II-II' of FIG. 1 in a multilayer capacitor according to a fourth embodiment of the present invention. [Figure 10] 1. FIG. 11 is a cross-sectional view of a multilayer capacitor according to a fifth embodiment of the present invention taken along line II' of FIG. [Figure 11] 2 is a cross-sectional view showing a cross section taken along line II-II' of FIG. 1 in a multilayer capacitor according to a fifth embodiment of the present invention. [Figure 12] 2 is a cross-sectional view showing a cross section taken along line II-II' of FIG. 1 in a multilayer capacitor according to a sixth embodiment of the present invention. [Figure 13] 4 is a graph showing a comparison between the range of widths of internal electrodes in a conventional multilayer capacitor and the range of widths of internal electrodes in the multilayer capacitor according to the first embodiment of the present invention. [Figure 14]11 is a graph showing a comparison between the range of the ratio of the maximum width to the minimum width of the internal electrodes in a conventional multilayer capacitor and the range of the ratio of the maximum width to the minimum width of the internal electrodes in one multilayer unit in a multilayer capacitor according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and the same reference numerals are used to refer to components having the same functions within the same concept.

[0030] Furthermore, throughout this specification, when a certain element is referred to as "comprising," it does not mean that it excludes other elements, but rather that it may further include other elements, unless specifically stated to the contrary.

[0031] Hereinafter, in order to clearly describe the embodiments of the present invention, the directions of the capacitor body 101 will be defined, with X, Y, and Z shown in the drawings indicating the length direction, width direction, and thickness direction of the capacitor body 101, respectively.

[0032] In addition, in this embodiment, the Z direction can be used as the same concept as the lamination direction in which the dielectric layers are laminated.

[0033] In addition, in this embodiment, for ease of explanation, the two surfaces of the capacitor body 101 facing each other in the Z direction are defined as the first and second surfaces 1, 2 and the first and second surfaces 1, 2, respectively, the two surfaces facing each other in the X direction are defined as the third and fourth surfaces 3, 4 and the two surfaces connected to the first and second surfaces 1, 2 and the third and fourth surfaces 3, 4 and facing each other in the Y direction are defined as the fifth and sixth surfaces 5, 6.

[0034] In this embodiment, the mounting surface of the multilayer capacitor 100 can be the first surface 1 of the capacitor body 101 .

[0035] In the laminate unit described below, both surfaces facing each other in the X direction of the laminate unit can be defined as third and fourth surfaces 3, 4, and both surfaces facing each other in the Y direction can be defined as fifth and sixth surfaces 5, 6.

[0036] FIG. 1 is a schematic perspective view of a multilayer capacitor according to a first embodiment of the present invention, FIG. 2 is a plan view showing internal electrodes included in a first multilayer unit of FIG. 1, FIG. 3 is a plan view showing internal electrodes included in a second multilayer unit of FIG. 1, FIG. 4 is a cross-sectional view along line I-I' of FIG. 1, and FIG. 5 is a cross-sectional view along line II-II' of FIG. 1.

[0037] 1 to 5, a multilayer capacitor 100 according to the present embodiment includes a capacitor body 101 and first and second external electrodes 131 and 132. The multilayer capacitor 100 includes a capacitor body 101 and first and second external electrodes 131 and 132.

[0038] The capacitor body 101 is formed by arranging two or more laminate units 110, 210 in a row along the Z direction, which is the laminate direction of the dielectric layers 111, 211, and each laminate unit includes a plurality of dielectric layers 111, 211, a plurality of first internal electrodes 121, 221 arranged alternately between the dielectric layers 111, 211, and a plurality of second internal electrodes 122, 222.

[0039] In the following, in this embodiment, the laminate unit is described as consisting of an upper first laminate unit and a lower second laminate unit, but the present invention is not limited to this, and if necessary, three or more laminate units can be stacked in a row along the Z direction to form the capacitor body.

[0040] In this embodiment, the second laminate unit is the first laminate unit flipped 180° in the Z direction. The structure of the laminate unit described below will be described based on the first laminate unit, and any description of the second laminate unit that overlaps with the first laminate unit will be omitted, but this is deemed to include a description of the second laminate unit.

[0041] In the drawings, in the description of the second laminated unit, reference numeral 211 denotes a dielectric layer, reference numerals 221 and 222 denote first and second internal electrodes, respectively, and reference numerals 212 and 213 denote covers.

[0042] The first laminate unit 110 is formed by stacking a plurality of dielectric layers 111 in the Z direction and then firing the same, and the boundaries between adjacent dielectric layers 111 of the first laminate unit 110 can be so integrated that they are difficult to confirm without using a scanning electron microscope (SEM).

[0043] In this case, the first laminate unit 110 may be substantially hexahedral, but the present invention is not limited thereto. In addition, the shape and dimensions of the first laminate unit 110 and the number of laminated dielectric layers 111 are not limited to those shown in the drawings of this embodiment.

[0044] The dielectric layer 111 may include a ceramic material with a high dielectric constant, such as a barium titanate (BaTiO3)-based or strontium titanate (SrTiO3)-based ceramic powder, but the present invention is not limited thereto as long as sufficient capacitance can be obtained.

[0045] In addition to the ceramic powder, the dielectric layer 111 may further contain a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like.

[0046] The ceramic additive may be, for example, a transition metal oxide or transition metal carbide, a rare earth element, magnesium (Mg), or aluminum (Al).

[0047] The first laminated unit 110 may include an active region that contributes to forming the capacitance of the capacitor, and covers 112, 113 that are formed on the top and bottom of the active region in the Z direction, respectively, as top and bottom margins.

[0048] The covers 112, 113 may have the same material and composition as the dielectric layer 111, except that they do not include the internal electrodes.

[0049] The covers 112, 113 may be formed by stacking a single dielectric layer or two or more dielectric layers in the Z direction on the upper and lower surfaces of the active region, respectively, and may essentially serve to prevent damage to the first and second internal electrodes 121, 122 due to physical or chemical stress.

[0050] At this time, it is preferable that the thickness of the covers 112, 113, 212, 213 is above a certain level so as to prevent the capacitor body 101 from being damaged by external impacts, etc. when the capacitor body 101 is constructed by the first and second stacked units 110, 210.

[0051] In particular, since one side of the laminate unit is the surface that comes into contact with other laminate units, in order to maintain a constant distance between adjacent internal electrodes, it is preferable to form the thickness of the cover on the side that comes into contact with the other laminate unit to be thinner than the thickness of the cover on the opposite side.

[0052] For example, in this embodiment, in the case of the first laminate unit 110, it is preferable that the upper cover 112 is formed by stacking two or more dielectric layers, and in the case of the second laminate unit 210, the lower cover 212 is formed by stacking two or more dielectric layers.

[0053] The first and second internal electrodes 121, 122 are electrodes to which different polarities are applied, and are arranged alternately along the Z direction across the dielectric layer 111, and one end can be exposed through the third and fourth surfaces 3, 4 of the first laminate unit 110, respectively.

[0054] At this time, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0055] In this manner, the ends of the first and second internal electrodes 121, 122 alternately exposed through the third and fourth surfaces 3, 4 of the first laminate unit 110 can be electrically connected to the first and second external electrodes 131, 132, respectively, arranged on the third and fourth surfaces 3, 4 of the capacitor body 101 described later.

[0056] With the above-mentioned configuration, when a predetermined voltage is applied to the first and second external electrodes 131, 132, charges are accumulated between the first and second internal electrodes 121, 122.

[0057] At this time, the capacitance of the multilayer capacitor 100 is proportional to the overlapping area of ​​the first and second internal electrodes 121 and 122 that overlap each other along the Z direction in the active region of the capacitor body 101.

[0058] In addition, the material for forming the first and second internal electrodes 121, 122 is not particularly limited, and may be formed using a conductive paste made of one or more of precious metal materials such as platinum (Pt), palladium (Pd), and palladium-silver (Pd-Ag) alloy, nickel (Ni), and copper (Cu).

[0059] In this case, the conductive paste may be printed by a screen printing method, a gravure printing method, or the like, but the present invention is not limited thereto.

[0060] In the capacitor body 101 of the present embodiment, the first and second stacked units 110 and 210 may be arranged such that their surfaces corresponding to the high density portions face each other.

[0061] At this time, although not shown, the first and second stacked units 110 and 210 may be arranged such that the surfaces corresponding to the low density portions face each other, if necessary.

[0062] Meanwhile, in the capacitor body, the first and second stacked units 110 and 210 may be disposed such that the surfaces corresponding to the first stacked portions face each other.

[0063] At this time, if necessary, the first and second stacked units 110 and 210 may be arranged such that the surfaces corresponding to the last stacked portions face each other.

[0064] The first and second external electrodes 131, 132 are provided with voltages of different polarities, are disposed on the third and fourth surfaces 3, 4 of the capacitor body 101, and can be electrically connected to the exposed portions of the first and second internal electrodes 121, 122 in the first and second stacked units 110, 210, respectively.

[0065] In this case, the first and second external electrodes 131, 132 may include a conductive layer formed on the third and fourth faces 3, 4 of the capacitor body 101 and a plating layer formed on the conductive layer, if necessary.

[0066] The plating layer may include a nickel (Ni) plating layer formed on the conductive layer, and a tin (Sn) plating layer formed on the nickel (Ni) plating layer.

[0067] The first external electrode 131 may include a first connection portion 131a and a first band portion 131b.

[0068] The first connection portion 131a is formed on the third surface 3 of the capacitor body 101 and is connected to the exposed portions of the first internal electrodes 121, 221, and the first band portion 131b is extended from the first connection portion 131a to a portion of the first surface 1 of the capacitor body 101.

[0069] At this time, the first band portion 131b may be further extended to a part of the fifth and sixth surfaces 5 and 6 of the capacitor body 101 and a part of the second surface 2 in order to improve the fixing strength.

[0070] The second external electrode 132 may include a second connection portion 132a and a second band portion 132b.

[0071] The second connection portion 132a is formed on the fourth surface 4 of the capacitor body 101 and is connected to the exposed portions of the second internal electrodes 122, 222, and the second band portion 132b is extended from the second connection portion 132a to a portion of the first surface 1 of the capacitor body 101.

[0072] At this time, the second band portion 132b may be further extended to a part of the fifth and sixth surfaces 5 and 6 of the capacitor body 101 and a part of the second surface 2 in order to improve the fixing strength.

[0073] In this embodiment, in the case of the first stacked unit 110, the upper portion can be a low density portion and the lower portion can be a high density portion.

[0074] In this case, in the case of the first stacked unit 110, when manufacturing the stacked unit, the upper part can be the last part to be stacked, and the lower part can be the first part to be stacked.

[0075] In addition, in this embodiment, the second stacked unit 210 can be disposed below the first stacked unit 110.

[0076] The second stacked unit 210 can have a high density portion at the top and a low density portion at the bottom.

[0077] In this case, in the case of the second stacked unit 210, when manufacturing the stacked unit, the upper part can be the first part to be stacked, and the lower part can be the last part to be stacked.

[0078] Meanwhile, referring to FIG. 6, the first and second stacked units 110′ and 210′ ​​may be formed such that the width of the first or second internal electrode gradually narrows from the middle of the stacked unit toward the top and bottom in the Z direction.

[0079] That is, when viewed from the third surface of the first stacked unit 110', the first internal electrode 121' can be formed such that the width in the Y direction of the first internal electrode 121' located in the middle in the Z direction is the longest, and the width in the Y direction of the first internal electrode 121' gradually becomes shorter as it moves up and down along the Z direction.

[0080] Although not shown, when viewed from the fourth surface of the first laminate unit 110', the second internal electrode may also have a shape and structure similar to those of the first internal electrode 121'.

[0081] Furthermore, when viewed from the third surface of the second stacked unit 210', the first internal electrode 221' can be formed such that the width in the Y direction of the first internal electrode 221' located in the middle in the Z direction is the longest, and the width in the Y direction of the first internal electrode 221' gradually becomes shorter as it moves up and down along the Z direction.

[0082] Although not shown, when viewed from the fourth surface of the second laminate unit 210', the second internal electrode may also have a shape and structure similar to that of the first internal electrode 221'.

[0083] Therefore, when viewed from the third and fourth faces of the capacitor body 101', the exposed shape of the internal electrodes in the Z direction can be generally formed in a snowman shape along the Z direction.

[0084] In addition, the first and second multilayer units 110' and 210' may satisfy W2 / W1≧0.96, where W1 is the maximum width of the first or second internal electrode, and W2 is the minimum width of the first or second internal electrode. The closer this ratio is to 1, the more uniform the width of the internal electrodes. Therefore, according to this embodiment, the thickness of the internal electrodes is also generally uniform, improving the breakdown voltage characteristics of the multilayer capacitor.

[0085] 14, the comparative example is a multilayer capacitor including a capacitor body in which internal electrodes are stacked from the bottom to the top, rather than stacking multilayer units one above the other. The example is a multilayer capacitor according to a second embodiment of the present invention, including a capacitor body 101' formed by stacking first and second multilayer units 110', 210' one above the other. In FIG. 6, W1 indicates the width of the longest internal electrode, and W2 indicates the width of the shortest internal electrode.

[0086] In the comparative example, the upper limit of W2 / W1 was 0.953, the lower limit was 0.947, and the average was 0.950, all of which were lower than 0.960, whereas in the example, the upper limit was 0.976, the lower limit was 0.965, and the average was 0.970, all of which were higher than 0.960.

[0087] That is, according to the embodiment of the present invention, the deviation in width of the internal electrodes when viewed from the entire capacitor body is reduced, but the deviation in width of the internal electrodes when viewed from each stacking unit is also significantly reduced compared to the comparative example. As described above, according to the present embodiment, the deviation in width and thickness of the internal electrodes is reduced to improve the breakdown voltage characteristics, thereby providing a highly reliable multilayer capacitor that is resistant to dielectric breakdown.

[0088] Meanwhile, according to another embodiment of the present invention, a buffer layer 300 may be disposed between the first stack unit 110 and the second stack unit 210 as shown in FIGS.

[0089] Since the buffer layer 300 is composed only of a dielectric layer, it can reduce the influence of the step between the dielectric layer and the internal electrodes, and can further suppress irregular deformation of the internal electrodes.

[0090] Referring to FIG. 9, a buffer layer 300 is disposed between a first stack unit 110' and a second stack unit 210', and the first and second stack units 110', 210' may be formed such that the width of the first or second internal electrode gradually narrows from the middle of the stack unit toward the top and bottom along the Z direction.

[0091] That is, when viewed from the third surface of the first stacked unit 110', the first internal electrode 121' can be formed such that the width in the Y direction of the first internal electrode 121' located in the middle in the Z direction is the longest, and the width in the Y direction of the first internal electrode 121' gradually becomes shorter as it moves up and down along the Z direction.

[0092] Although not shown, when viewed from the fourth surface of the first laminate unit 110', the second internal electrode may also have a shape and structure similar to those of the first internal electrode 121'.

[0093] In addition, when viewed from the third surface of the second stacked unit 210', the first internal electrode 221' can be formed such that the width in the Y direction of the first internal electrode 221' located in the middle in the Z direction is the longest, and the width in the Y direction of the first internal electrode 221' gradually becomes shorter as it moves up and down along the Z direction.

[0094] Although not shown, when viewed from the fourth surface of the second laminate unit 210', the second internal electrode may also have a shape and structure similar to that of the first internal electrode 221'.

[0095] Therefore, when viewed from each of the third and fourth faces of the capacitor body, the exposed shape of the internal electrodes in the Z direction can be formed into a snowman-like shape overall along the Z direction.

[0096] FIG. 10 is a cross-sectional view showing a cross section corresponding to line II' in FIG. 1 in a multilayer capacitor according to another embodiment of the present invention, and FIG. 11 is a cross-sectional view showing a cross section corresponding to line II-II' in FIG. 1 in a multilayer capacitor according to another embodiment of the present invention.

[0097] 10 and 11, a multilayer capacitor 100' of the present embodiment may include a capacitor body 101'' that includes a plurality of first multilayer units 110' and a plurality of second multilayer units 210'.

[0098] Here, the first stacked unit 110' may have a structure in which the low density portion is located at the top.

[0099] In this case, the first stacked unit 110' may have a structure in which the last stacked portion is located at the top.

[0100] Also, the second stacked unit 210' may have a structure in which the high density portion is located at the top.

[0101] In this case, the second stacked unit 210' may have a structure in which the first stacked portion is located at the top.

[0102] The capacitor body 101'' of the present embodiment may be formed by alternately stacking the first stack unit 110' and the second stack unit 210' once each in the Z direction, with the second stack unit 210' located at the bottom.

[0103] In this case, in order to manufacture the multilayer capacitor so that its overall size is similar to that of the multilayer capacitor of the embodiment shown in FIG. 4 described above, the number of dielectric layers and internal electrodes included in each multilayer unit may be appropriately adjusted.

[0104] Meanwhile, as shown in FIG. 12, when the capacitor body 101'' includes a plurality of first and second stacked units 110', 210', the first stacked unit 110' may be formed such that the width of the first or second internal electrode gradually narrows from the middle portion of the stacked unit toward the top and bottom along the Z direction.

[0105] Also, the second stacked unit 210' may be formed such that the width of the first or second internal electrode gradually narrows from the center of the stacked unit toward the top and bottom in the Z direction.

[0106] Hereinafter, a method for manufacturing a multilayer capacitor according to an embodiment of the present invention will be described.

[0107] First, a plurality of ceramic sheets are prepared.

[0108] The ceramic sheets are intended to form the dielectric layers of the laminated unit.

[0109] The ceramic sheet can be produced by mixing ceramic powder, a polymer and a solvent to produce a slurry, and then forming the slurry into a sheet having a thickness of several μm using a technique such as a doctor blade.

[0110] Then, a conductive paste is printed on the ceramic sheets to a predetermined thickness to form internal electrodes, and then multiple ceramic sheets are stacked to provide a laminated bar including multiple dielectric layers and multiple first and second internal electrodes arranged alternately with the dielectric layers in between.

[0111] Next, the two laminate bars are arranged in a line so that the faces corresponding to the high density portions of the two laminate bars face each other, or so that the faces corresponding to the low density portions of the two laminate bars face each other, to provide a laminate.

[0112] At this time, the lamination pressure applied to the ceramic sheets is cumulative, so that the surface that is laminated first has the highest density, and the surface that is laminated last has the lowest density.

[0113] Thus, when preparing the laminate, the two laminate bars can be arranged in a row so that the faces on which the ceramic sheets are first laminated face each other, or they can be arranged in a row so that the faces on which the ceramic sheets are last laminated face each other.

[0114] In this embodiment, a second laminate bar having a high density portion located at the top can be placed, and then a first laminate bar having a low density portion located at the top can be stacked on top of the second laminate bar to form a laminate.

[0115] That is, a second laminate bar is first placed with the surface on which the ceramic sheet is laminated facing up, and then the first laminate bar is finally laminated on top of the second laminate bar with the surface on which the ceramic sheet is laminated facing up to form a laminate.

[0116] At this time, in order to align the stacked bars arranged above and below, holes may be formed in each stacked bar using a laser drill, and an alignment stacking machine may be used.

[0117] Meanwhile, the laminate may be formed by further disposing a buffer layer between adjacent laminate bars, if necessary.

[0118] To this end, one or more ceramic sheets may be laminated on the upper surface of the lower second laminate bar to form a buffer layer, and then the first laminate bar may be laminated on the buffer layer.

[0119] In another embodiment, in the step of providing the laminate, the laminate may include a plurality of first and second laminate bars, and may be formed by stacking the first laminate bars and the second laminate bars in a Z direction so that the first laminate bars and the second laminate bars are alternately arranged once each.

[0120] Next, the laminate is pressure-bonded.

[0121] The laminate may be formed such that the width of the first or second internal electrode gradually narrows from the middle of the first or second laminate bar toward the top or bottom.

[0122] Next, the laminate is cut into regions corresponding to one capacitor so that the first and second internal electrodes of the pressed laminate are alternately exposed through both end faces, and then fired at high temperature to provide a capacitor body.

[0123] Next, a conductive paste is applied to the capacitor body so as to be electrically connected to the exposed portions of the first and second internal electrodes, respectively, to form first and second external electrodes.

[0124] A typical multilayer capacitor is manufactured by forming an active region on a lower cover, laminating an upper cover on the active region, and then compressing the upper cover.

[0125] Recently, as dielectric layers have become thinner and the number of layers has increased, the difference in thickness between the active region in the capacitor body where the internal electrodes are formed and the marginal portion where no internal electrodes are formed has become larger.

[0126] Such a difference in thickness occurs more significantly in the width direction of the multilayer capacitor than in the length direction.

[0127] As a result, some of the layers collapse during the lamination and compression processes when manufacturing a multilayer capacitor, which can lead to delamination or cracks at the margins and allow moisture, plating solution, and foreign matter to penetrate into the capacitor body, reducing the reliability of the capacitor body.

[0128] Furthermore, in the case of a conventional multilayer capacitor, the capacitor body after compression has a potbelly shape in which the middle part of the active region protrudes compared to the upper and lower parts of the active region.

[0129] This occurs due to the above-mentioned interlayer step between the dielectric layer and the internal electrode and the density difference at the upper and lower margins.

[0130] That is, when the laminate is compressed, the upper and lower portions of the active region are restricted from lateral expansion, but the middle portion of the active region is allowed to lateral expand more.

[0131] Therefore, in the capacitor body, the thickness of the internal electrode increases toward the lower side of the active region, and the thickness of the internal electrode increases toward the margin portion.

[0132] At this time, the thickness of the dielectric layer exhibits a tendency opposite to that of the internal electrodes, so that the active area of ​​the capacitor body generally has a pot-bellied shape.

[0133] If the active area of ​​the capacitor body is generally pot-bellied, the multilayer capacitor becomes vulnerable to dielectric breakdown and short circuit defects.

[0134] In other words, in a conventional multilayer capacitor, when the laminate is compressed, the density of the dielectric layer located at the lower part becomes high. In this case, the internal electrodes adjacent to the lower part with higher density do not stretch significantly, and the internal electrodes adjacent to the upper part with lower density do not stretch significantly because the compression auxiliary material and the upper cover are pressed downward.

[0135] However, in the case of the intermediate portion of the capacitor body, the margin density is relatively low, so that the internal electrodes can freely expand, and therefore the internal electrodes of the capacitor body are deformed into a potbelly shape as a whole.

[0136] Also, a thinner dielectric layer results in a higher voltage per unit thickness of the dielectric layer.

[0137] Therefore, even when a low voltage is applied to the multilayer capacitor, the possibility of dielectric breakdown occurring in the dielectric layer increases.

[0138] In particular, when viewed from the cross section in the width and thickness directions of the multilayer capacitor, both ends of the internal electrodes in the width direction are elongated during the compression process to form a wedge shape, and the electric field strength is further increased due to a notch effect.

[0139] Therefore, high electric field strengths are applied to the ends of the internal electrodes adjacent in the stacking direction, which may cause dielectric breakdown in the dielectric layers more easily.

[0140] However, in the multilayer capacitor of the present embodiment, the capacitor body is formed of two multilayer units, and the two multilayer units are arranged in a row so that the surfaces corresponding to high density face each other symmetrically, and then compressed to be manufactured.

[0141] As a result, the internal electrodes do not stretch significantly in the middle portion of the active region in the capacitor body due to the high margin density, and although the margin density is low in the upper and lower portions of the active region, the internal electrodes are restricted in stretching by the cover, so that the internal electrodes included in the capacitor body can be deformed uniformly overall.

[0142] By making the deformation of the internal electrodes symmetrical and uniform in the vertical direction in this manner, the deviation in thickness between the dielectric layer and the internal electrodes within the capacitor body can be reduced, and the phenomenon of bending of the ends of the internal electrodes can also be reduced.

[0143] Therefore, by reducing the effect of the difference in thickness between the active region and the marginal portion in the width direction of the multilayer capacitor, it is possible to realize a miniaturized multilayer capacitor with a high capacity, and it is possible to prevent delamination and cracks that mainly occur in the marginal portion due to collapse of a part of the layer during the stacking and pressurizing process.

[0144] Furthermore, the reliability of the multilayer capacitor can be improved, and dielectric breakdown under high voltage can be prevented.

[0145] Meanwhile, in the present invention, the number of laminate units constituting the capacitor body is not limited to two, but may be three or more, and preferably, the number of laminate units may be a multiple of two.

[0146] For example, as shown in Figures 10 and 11, when the total number of multilayer units is doubled to four compared to the above embodiment, the internal electrodes can be deformed more uniformly overall, which can further reduce the deviation in thickness between the dielectric layers and the internal electrodes in the capacitor body and further reduce the bending phenomenon of the ends of the internal electrodes.

[0147] As a result, problems such as dielectric breakdown, short circuit failure, and capacitance reduction of the multilayer capacitor 100' can be more effectively alleviated, and the reliability of the multilayer capacitor can be further improved.

[0148] Fig. 13 is a graph showing a comparison between the range of widths of internal electrodes in a conventional multilayer capacitor and the range of widths of internal electrodes in the multilayer capacitor according to the embodiment of the present invention shown in Figs. 1 to 5. Here, the multilayer capacitor has a length and a width of 2.0 mm and 1.2 mm, respectively, and the number of laminated layers of the internal electrodes is 900 in total.

[0149] In Figure 13, #1 shows the width of the internal electrode in a conventional multilayer capacitor whose capacitor body is made of a single laminate, #2 shows the width of the internal electrode included in the second laminate unit in the multilayer capacitor shown in Figures 1 to 5, and #3 shows the width of the internal electrode included in the first laminate unit in the multilayer capacitor shown in Figures 1 to 5.

[0150] Referring to FIG. 13, it can be seen that the maximum and minimum values ​​of the average width of the internal electrodes in #2 and #3 are both smaller than the maximum and minimum values ​​of the average width of the internal electrodes in #1.

[0151] In addition, in the case of #1, the average electrode width at the top and bottom of the capacitor body is smallest and the width at the midpoint is largest, whereas in the case of one embodiment of the present invention including #2 and #3, the widths at the top, middle, and bottom of the capacitor body are almost similar, and the widths from the top to the middle and from the middle to the bottom are also almost similar.

[0152] That is, according to the present embodiment, the deviation in thickness of the internal electrodes in the active region of the capacitor body can be reduced, and it can be confirmed that the potbelly shape of the internal electrodes of the capacitor body in the conventional multilayer capacitor is numerically improved.

[0153] Although the embodiments of the present invention have been described in detail above, the scope of the invention is not limited thereto, and it will be obvious to those having ordinary knowledge in the art that various modifications and variations are possible without departing from the technical matters of the invention described in the claims. [Explanation of symbols]

[0154] 100, 100' stacked capacitor 101, 101', 101'', 101''' Capacitor body 110, 110' First stacked unit 111, 211 Dielectric layer 112, 113, 212, 213 Cover 121, 121', 221, 221' 1st internal electrode 122, 222 2nd internal electrode 131, 132 First and second external electrodes 210, 210' Second stacked unit 300 Buffer Layer

Claims

1. a capacitor body including two or more laminate units arranged in a line along a lamination direction of the dielectric layers, the two or more laminate units including a plurality of dielectric layers and a plurality of first and second internal electrodes arranged alternately with the dielectric layers interposed therebetween, the two or more laminate units having first and second surfaces facing each other in a direction in which the dielectric layers are laminated, and formed such that density gradually decreases from the first surface toward the second surface; first and second external electrodes disposed on the capacitor body to be electrically connected to the first and second internal electrodes, respectively; The number of dielectric layers in each of the two or more laminate units is the same, The multilayer capacitor, wherein adjacent multilayer units in the capacitor body are arranged such that surfaces corresponding to the first surfaces face each other or surfaces corresponding to the second surfaces face each other.

2. The multilayer capacitor of claim 1 , wherein the capacitor body further comprises a buffer layer disposed between adjacent stack units.

3. 3. The multilayer capacitor according to claim 1, wherein the capacitor body includes a first stacked unit having the second surface located at an upper portion thereof, and a second stacked unit disposed below the first stacked unit and having the first surface located at an upper portion thereof.

4. the capacitor body includes a first stacked unit having the second surface located at an upper portion thereof, and a second stacked unit disposed below the first stacked unit and having the first surface located at an upper portion thereof, 3. The multilayer capacitor according to claim 1, wherein the first multilayer unit and the second multilayer unit are alternately stacked once each.

5. The multilayer capacitor of claim 1 , wherein each of the multilayer units is formed such that the widths of the first and second internal electrodes are gradually narrowed from a central portion of the multilayer unit toward the top and bottom.

6. 6. The multilayer capacitor according to claim 5, wherein when a maximum width of the first or second internal electrode is defined as W1 and a minimum width of the first or second internal electrode is defined as W2, the multilayer unit satisfies W2 / W1≧0.

96.

7. providing a laminated bar including a plurality of ceramic sheets and a plurality of first and second internal electrodes alternately disposed with the ceramic sheets interposed therebetween, the laminated bar having first and second surfaces facing each other in a direction in which the plurality of ceramic sheets are laminated, the first surface being an outer surface formed by laminating a first ceramic sheet, the second surface being an outer surface formed by laminating a last ceramic sheet, and the density of the laminated bar gradually decreasing from the first surface to the second surface; providing a stack by arranging two or more laminate bars in a row such that the first surfaces of the two or more laminate bars face each other or the second surfaces of the two or more laminate bars face each other; compressing the laminate; cutting the laminate so that the first and second internal electrodes of the laminate are exposed, and then firing the laminate to provide a capacitor body; forming first and second external electrodes on the capacitor body to be electrically connected to exposed portions of the first and second internal electrodes, respectively; The method for manufacturing a stacked capacitor, wherein each of the two or more stacked bars has the same number of dielectric layers.

8. In the step of providing the laminate, The method for manufacturing a multilayer capacitor according to claim 7, wherein the stack is formed by disposing a buffer layer between adjacent stack bars.

9. In the step of providing the laminate, 9. The method for manufacturing a multilayer capacitor according to claim 7 or 8, wherein the laminate is formed by placing a second laminate bar having the first surface located at an upper portion, and stacking a first laminate bar having the second surface located at an upper portion on the second laminate bar.

10. 10. The method of claim 9, wherein the laminate includes a plurality of first and second laminate bars, and the first and second laminate bars are alternately stacked one after another.

11. In the step of providing the laminate, The method for manufacturing a multilayer capacitor according to any one of claims 7 to 10, wherein the alignment of the laminated bars is performed by forming holes in each laminated bar using a laser drill and then using an alignment lamination machine.

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