Switching circuit, switching power supply, gate driver circuit for switching power supply, control circuit for switching power supply

Abstract

A switching controller 130 generates control pulses Sp1, Sp2 serving as instructions to turn a first transistor M1 and a second transistor M2 on or off. One end of a capacitor Cs is connected with a switching node Nsw, and a constant voltage is applied to the other end via a rectifier element Ds. A dead time controller 120 controls the delay time between adjacent edges of a first control pulse Sp1 and a second control pulse Sp2 in accordance with the sense voltage Vs between the two ends of the capacitor Cs.

Description

[Technical field]

[0001] Books Disclosure relates to switching circuits. [Background technology]

[0002] Switching circuits such as half-bridge circuits and full-bridge circuits are used in the field of power electronics, including DC / DC converters, AC / DC converters, and inverters.

[0003] In controlling a switching circuit, dead time is inserted to prevent shoot-through current. The longer the dead time is, the lower the risk of shoot-through current, but during the dead time, current flows through the body diode or freewheel diode (flywheel diode) of the transistor, reducing efficiency.

[0004] Therefore, it is preferable to make the dead time as short as possible without causing a through current to flow. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] "Predictive Gate Drive Frequency Asked Questions", [online], February, 2003, [Searched 20200327], Internet<URL:https: / / www.ti.com / lit / an / slua285 / slua285.pdf> Summary of the Invention [Problem to be solved by the invention]

[0006] In some cases, the switching transistor (power transistor) is composed of discrete elements separate from the control circuit that generates the pulse signal that controls the switching transistor. In other cases, the gate driver that drives the switching transistor is a separate IC (Integrated Circuit) from the control circuit. Furthermore, a transformer may be inserted between the control circuit and the switching transistor. In such cases, the dead time must be determined taking into account the gate capacitance of the switching transistor, the delay time of the gate driver, and the delay time of the transformer. Previously, switching circuit designers had to determine the dead time empirically or by trial and error, taking into account the characteristics of the surrounding circuits.

[0007] In particular, in recent years, there has been a trend to replace the Si-FET and IGBT (Insulated Gate Bipolar Transistor) used as switching transistors with GaN-HEMTs, which are capable of faster switching. In this case, the switching cycle becomes shorter, making it even more difficult to adjust the length of the dead time.

[0008] Books Disclosure has been made in such a situation, and one of the exemplary purposes of an embodiment thereof is to provide a switching circuit capable of optimizing the dead time. [Means for solving the problem]

[0009] An embodiment of the present disclosure relates to a switching circuit. The switching circuit includes a first transistor and a second transistor, and a high-level voltage is generated during a period when the first transistor is on and the second transistor is off. No. 1the switching node generates a low-level voltage during a period when the transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second end of the capacitor; a switching controller that generates a first control pulse and a second control pulse that instruct the first transistor and the second transistor to be on and off; a first gate driver that drives the first transistor in response to the first control pulse; a second gate driver that drives the second transistor in response to the second control pulse; and a dead time controller that controls the delay time between adjacent edges of the first control pulse and the second control pulse in response to a sense voltage across the capacitor.

[0010] Another embodiment of the present disclosure also relates to a switching circuit. The switching circuit includes a first transistor and a second transistor, and a high-level voltage is generated during a period when the first transistor is on and the second transistor is off, No. 1 the switching node generates a low-level voltage during a period when the transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second end of the capacitor; a switching controller that generates a first control pulse and a second control pulse that instruct the first transistor and the second transistor to be on or off; a first gate driver that drives the first transistor in response to the first control pulse; a second gate driver that drives the second transistor in response to the second control pulse; and a dead time controller that controls a delay time of at least one of the first gate driver and the second gate driver in response to a sense voltage across the capacitor.

[0011] Another aspect of the present disclosure is a control circuit for a switching power supply. The switching power supply includes a first transistor and a second transistor, and a high-level voltage is generated during a period when the first transistor is on and the second transistor is off, No. 1The control circuit includes a switching node which generates a low-level voltage during a period when the transistor is off and the second transistor is on and generates a negative voltage during a period when both the first transistor and the second transistor are off, a capacitor having a first end connected to the switching node, a rectifying element which applies a constant voltage to a second end of the capacitor, a first gate driver which drives the first transistor in response to a first control pulse, and a second gate driver which drives the second transistor in response to a second control pulse. The control circuit includes a switching controller which generates a first control pulse and a second control pulse which instruct the first transistor and the second transistor to be on or off, and a dead time controller which controls a delay time between adjacent edges of the first control pulse and the second control pulse in response to a sense voltage across the capacitor.

[0012] Yet another embodiment of the present disclosure relates to a gate driver circuit for a switching power supply. The switching power supply includes a first transistor and a second transistor, and generates a high-level voltage during a period when the first transistor is on and the second transistor is off, No. 1 The switching power supply includes a switching node that generates a low-level voltage during a period when the transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off, a capacitor having a first end connected to the switching node, a rectifying element that applies a constant voltage to a second end of the capacitor, and a switching controller that generates a control signal that indicates a duty cycle of the first transistor and the second transistor so that the electrical state of the switching power supply approaches a predetermined target state. The gate driver circuit includes a pulse generating unit that generates a first control pulse and a second control pulse having a duty cycle according to the control signal, a first gate driver that drives the first transistor according to the first control pulse, a second gate driver that drives the second transistor according to the second control pulse, and a dead time controller that controls a delay time between adjacent edges of the first control pulse and the second control pulse according to a sense voltage across the capacitor.

[0013] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0014] According to an aspect of the present disclosure, the length of the dead time during which both transistors are off can be optimized. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram of a switching circuit according to the first embodiment. [Diagram 2] FIG. 2 is an operational waveform diagram of the switching circuit of FIG. [Diagram 3] FIG. 3 is a diagram illustrating the charging of the sense capacitor Cs. [Figure 4] FIG. 4 is a diagram showing the relationship between the length of the dead time τD and the sense voltage Vs. [Diagram 5] 5(a) to (c) are diagrams illustrating the advantages of the switching circuit. [Figure 6] FIG. 6 is a flowchart of an optimization process of the control delay Td by the dead time controller of FIG. [Figure 7] FIG. 7 is a circuit diagram of the switching power supply according to the first embodiment. [Figure 8] FIG. 8 is an operation waveform diagram of the switching power supply of FIG. [Figure 9] FIG. 9 is a circuit diagram of a switching power supply according to a second embodiment. [Figure 10] FIG. 10 is a block diagram of a switching power supply according to a third embodiment. [Figure 11] FIG. 11 is an operation waveform diagram of the switching power supply of FIG. [Figure 12] FIG. 12 is a block diagram of a switching power supply according to a fourth embodiment. [Figure 13] FIG. 13 is an operation waveform diagram of the switching power supply of FIG. [Figure 14] FIG. 14 is a circuit diagram of a switching circuit according to the second embodiment. [Figure 15] FIG. 15 is a circuit diagram of a switching circuit according to the third embodiment. [Figure 16] 16(a) to 16(f) are diagrams showing variations of switching power supplies. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] (Overview of the embodiment) A switching circuit according to an embodiment of the present invention includes a first transistor and a second transistor, and a high-level voltage is generated during a period when the first transistor is on and the second transistor is off. No. 1 The switching circuit includes a switching node which generates a low-level voltage during a period when the transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off, a capacitor having a first end connected to the switching node, a rectifying element which applies a constant voltage to a second end of the capacitor, a switching controller which generates a first control pulse and a second control pulse which instruct the first transistor and the second transistor to be on or off, a dead time controller which controls a delay time between adjacent edges of the first control pulse and the second control pulse in accordance with a sense voltage across the capacitor, a first gate driver which drives the first transistor in accordance with the first control pulse, and a second gate driver which drives the second transistor in accordance with the second control pulse.

[0017] In this configuration, the length of the dead time (also called the high impedance period) during which both the first and second transistors are off is positively correlated with the voltage across the capacitor. Therefore, the actual length of the dead time can be detected by monitoring the sense voltage across the capacitor. Then, by optimizing the delay time between the edges of the control pulse according to the detected sense voltage (i.e., the length of the dead time), the length of the dead time during which the first and second transistors are actually off can be optimized.

[0018] A switching circuit according to another embodiment includes a first transistor and a second transistor, and a high-level voltage is generated during a period when the first transistor is on and the second transistor is off; No. 1 a switching node which generates a low-level voltage during a period when the transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off, a capacitor having a first end connected to the switching node, a rectifying element which applies a constant voltage to a second end of the capacitor, a switching controller which generates a first control pulse and a second control pulse which instruct the first transistor and the second transistor to be on and off, a first gate driver which drives the first transistor in response to the first control pulse, a second gate driver which drives the second transistor in response to the second control pulse, and and a dead time controller that controls one of the delay times.

[0019] In this configuration, by optimizing the delay time of the gate driver, it is possible to optimize the length of the dead time during which the first transistor and the second transistor are actually turned off.

[0020] The dead time controller may include a comparator that compares the voltage across the capacitor with a predetermined target voltage, and may increase or decrease the delay time between edges depending on the output of the comparator, which may be a digital or analog comparator.

[0021] The dead time controller may feedback control the delay time between edges so that the voltage across the capacitor approaches a predetermined target voltage. The dead time controller may be configured with a digital circuit including a PI controller or a PID controller, or may be configured with an analog circuit including an error amplifier.

[0022] The dead time controller may independently control the delay time when the first transistor turns on and the delay time when the second transistor turns on.

[0023] The switching circuit may further include a discharge circuit connected to the capacitor and discharging the charge of the capacitor while the first transistor is on.

[0024] The switching power supply may further include a transformer including a primary winding and a secondary winding, the first transistor may be connected to the primary winding, the second transistor may be connected to the secondary winding, and the switching node may be a connection node between the secondary winding and the second transistor.

[0025] The first transistor and the second transistor may be connected in series, and the switching node may be a connection node between the first transistor and the second transistor.

[0026] (Details of the embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are not intended to limit the invention, but are merely examples, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0027] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0028] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0029] (Embodiment 1) 1 is a circuit diagram of a switching circuit 100 according to embodiment 1. The switching circuit 100 includes a main circuit 110, a sense capacitor Cs, a rectifier element Ds, a dead time controller 120, a switching controller 130, and gate drivers 140_1 and 140_2.

[0030] The main circuit 110 includes a first transistor M1 and a second transistor M2. A load 2 is connected to the main circuit 110, and power is supplied to the load 2 according to the on / off states of the first transistor M1 and the second transistor M2. Typically, the main circuit 110 may be a part of a switching power supply such as a DC / DC converter, an inverter, or a converter. As will be described later, there are various variations in the circuit configuration of the main circuit 110, and the configuration is not particularly limited. The first transistor M1 and the second transistor M2 may be directly connected or may be connected via a transformer.

[0031] The switching controller 130 controls at least one of the voltage, current, or power supplied to the load 2, or the state of the load, and generates control pulses Sp1 and Sp2 that regulate the on / off states of the first transistor M1 and the second transistor M2 so that the controlled object approaches a target value. The gate driver 140_1 drives the first transistor M1 in response to the first control pulse Sp1. The gate driver 140_2 drives the second transistor M2 in response to the second control pulse Sp2.

[0032] In the switching controller 130, an intentional control delay Td is set between the edges of the first control pulse Sp1 and the second control pulse Sp2. This control delay (sometimes called dead time) Td is a period during which both the first transistor M1 and the second transistor M2 are off (dead time τ D ) is inserted. However, the control delay Td is the design dead time, but the actual dead time τ D The length of the control delay Td does not necessarily match the control delay Td because the delay times until the two control pulses Sp1 and Sp2 reach the corresponding gates are not necessarily equal, and if the gate capacitances of the first transistor M1 and the second transistor M2 are different, the turn-on delay (turn-off delay) also differs.

[0033] During the period when the first transistor M1 is on and the second transistor M2 is off, the main circuit 110 outputs a high-level voltage V H During the period when the second transistor M2 is on and the first transistor M1 is off, the low-level voltage V L occurs, and the first transistor M1 and the second transistor M2 are both turned off during a dead time (also called a high impedance period) τ D During this time, negative voltage -V NEG The switching node Nsw where

[0034] One end of the sense capacitor Cs is connected to the switching node Nsw. The other end of the sense capacitor Cs is connected to a positive constant voltage V REG is applied. The rectifying element Ds is typically a diode, but a transistor may be used instead. A constant voltage V REG may be a power supply voltage or a reference voltage.

[0035] The dead time controller 120 determines the dead time τ D Detect and optimize settings.

[0036] The discharge circuit 122 is connected to the sense capacitor Cs. When the discharge circuit 122 is enabled, the discharge circuit 122 discharges the charge of the sense capacitor Cs. For example, the discharge circuit 122 may include a switch connected in parallel to the sense capacitor Cs.

[0037] The switching controller 130 may control the enable (active) / disable (inactive) of the discharge circuit 122 in synchronization with the on / off of the control pulses Sp1 and Sp2. For example, the discharge circuit 122 controls the enable (active) / disable (inactive) of the discharge circuit 122 in synchronization with the on / off of the control pulses Sp1 and Sp2. H During this period, the discharge circuit 122 may be enabled, and during the remaining period, the discharge circuit 122 may be disabled.

[0038] The above is the configuration of the switching circuit 100. Next, the operation will be described.

[0039] 2 is an operational waveform diagram of the switching circuit 100 in FIG. 1. During the period when the first transistor M1 is on, the switching voltage Vsw is a high-level voltage V H During the period when the second transistor M2 is on, the switching voltage Vsw is a low-level voltage V L (0V) and the dead time τ D During this time, the switching voltage Vsw is a negative voltage -V NEG Negative voltage -V NEG The size of V NEG depends on the type of the second transistor M2. For example, when the second transistor M2 is a Si-MOSFET, the forward voltage Vf of its body diode is equal to the magnitude of the negative voltage V NEG When the second transistor M2 is a GaN-HEMT, the drain-source voltage V DS is the magnitude of the negative voltage V NEG This amounts to several volts.

[0040] A switching voltage Vsw is applied to one end of the sense capacitor Cs, and a switching voltage VREG -V F ) is applied. V F is the forward voltage of the rectifier diode Ds. Therefore, (V REG -V F )>Vsw, the voltage across the sense capacitor Cs is REG -V F )-Vsw is applied.

[0041] 3 is a diagram illustrating the charging of the sense capacitor Cs. While the switching voltage Vsw is low (0 V), a low-level voltage V L (0V) and V REG -V F is applied, and the voltage across it, Vs, is therefore V REG -V F The subsequent dead time τ D In this case, the voltage Vsw at one end of the sense capacitor Cs is a negative voltage -V NEG Then, the sense capacitor Cs is further charged, and the voltage Vc between both ends of the capacitor increases further. The increase ΔV at this time is the same as the dead time τ D The longer the dead time τ D In other words, the sense voltage Vs is smaller than the dead time τ D The longer it is, the higher it will be, and the shorter it is, the lower it will be.

[0042] Figure 4 shows the dead time τ D Sense voltage Vs is a relationship between the length of dead time τ D The sense voltage Vs and the actual dead time τ D are in one-to-one correspondence.

[0043] Therefore, the dead time controller 120 sets the sense voltage Vs to a target value Vs (REF) is determined, and the sense voltage Vs is set to the target value Vs (REF) When the voltage Vs is higher, the control delay Td is shortened and the sense voltage Vs is equal to the target value Vs (REF) When the dead time τD The length of the target value Vs (REF) Length τ according to D(REF) can be optimized to

[0044] 5(a) to (c) are diagrams illustrating the advantages of the switching circuit 100. FIG. 5(a) to (c) show the control pulses Sp1 and Sp2 and the actual on and off states of the first transistor M1 and the second transistor M2. After the control pulse Sp2 transitions from high (on level) to low (off level), the off delay time τ 2 After the control pulse Sp1 transitions from low (off level) to high (on level), the second transistor M2 is turned off. 1 After a period of time, the first transistor M1 turns on.

[0045] Delay time τ 1 , τ 2 is affected by the gate driver capability, the element sizes of the first transistor M1 and the second transistor M2, and the parasitic impedance of the wiring. 1 , τ 2 shows different behavior.

[0046] In this embodiment, the sense voltage Vs is the target voltage Vs (REF) In other words, the dead time τ D The length of is the target value τ D(REF) The control delay Td, which is the delay time of the level transition of the control pulses Sp1 and Sp2, is adjusted so as to approach τ 1 = τ 2 In this case, the dead time τ D The length of the control delay Td is substantially equal to the control delay Td.

[0047] Figure 5(b) shows τ 1 >τ 2 In this case, the dead time τ DFeedback is applied so that the length of approaches the target value, and the control delay Td becomes longer.

[0048] Figure 5(c) shows τ 1 <τ 2 In this case, the dead time τ D Feedback is applied so that the length of approaches the target value, and the control delay Td becomes shorter.

[0049] As described above, according to this embodiment, the control delay Td is optimized, so that the influence of variations and fluctuations in the ON delay time and the OFF delay time can be cancelled.

[0050] 6 is a flowchart of the optimization process of the control delay Td by the dead time controller 120 of FIG. D The dead time τ immediately after the second transistor M2 is turned off (immediately before the first transistor M1 is turned on) D1 and a dead time τ immediately after the first transistor M1 is turned off (immediately before the second transistor M2 is turned on). D2 , which are affected by independent variation factors. Therefore, the dead time controller 120 determines two dead times τ D1 , τ D2 It is advisable to independently optimize two dead times (control delays) Td1 and Td2 corresponding to the above. The control delay Td1 is the delay time between the negative edge of the control pulse Sp2 and the positive edge of the control pulse Sp2, and the control delay Td2 is the delay time between the negative edge of the control pulse Sp1 and the positive edge of the control pulse Sp2.

[0051] First, initial values ​​Td1_init and Td2_init are set to the two dead times Td1 and Td2 (S100).

[0052] Next, the sense voltage V S The initial value of V SMeasure _init (S102). Subsequently, a perturbation is applied to the dead time Td1 (S104). The dead time Td1 should be as short as possible within the range where the through-current does not flow for higher efficiency. Therefore, the perturbation is applied in the direction of decreasing the dead time Td1. Δtd1 is a predetermined perturbation width. Td1 = Td1 - Δtd1

[0053] The sense voltage V after the perturbation is applied S is measured (S106), and the variation width ΔV S of the sense voltage V due to the perturbation S = |V S - V S _init| is calculated (S108). In this state, the perturbation is removed (S110). Td1 = Td1 + Δtd1

[0054] As shown in FIG. 4, in the region where the dead time τ D (i.e., the dead times Td1, Td2) is small, the sensitivity of the sense voltage V S with respect to the dead times Td1, Td2 decreases. In this region, the risk of through-current flowing increases. To avoid this risk, the variation width ΔV S is compared with a minute threshold value A (S112). When ΔV S < A (Y in S112), since there is a possibility of through-current flowing, the dead time Td1 is increased (S116).

[0055] ΔV S > A (N in S112), it can be said that the risk of through-current flowing is low. In this case, V S is compared with its target level V S(REF) . Then, if V S > V S(REF) (Y in S114), the dead time Td1 is decreased (S116), and if V S < V S(REF) (N in S114), the dead time Td1 is increased (S118).

[0056] In steps S202 to S218, the same processing as steps S102 to S118 is performed on Td2. Note that the method for optimizing the dead times Td1 and Td2 is not limited to the above.

[0057] The optimization of the dead times Td1, Td2 may be performed constantly or intermittently during the operation of the switching circuit 100. Alternatively, the optimization may be performed before the shipment of a final product including the switching circuit 100, and the dead times Td1, Td2 obtained there may be stored in a non-volatile memory, and the dead times Td1, Td2 loaded from the non-volatile memory may be used during operation.

[0058] The present invention encompasses various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or that are derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present invention, but to aid in understanding and clarify the essence and operation of the invention.

[0059] Example 1 7 is a circuit diagram of a switching power supply 300A according to Example 1. The switching power supply 300A is a forward converter, in which the architecture of the switching circuit 100 described above is implemented.

[0060] The switching power supply 300A includes a transformer TRN1, four transistors MA to MD, gate drivers 340A to 340D, isolators 342A and 342B, a dead time controller 320, and a switching controller 330. In the switching power supply 300A, the primary side and the secondary side are insulated by the transformer TRN1 and the isolators 342A and 342B. The dead time controller 320 and the switching controller 330 may be integrated into a single control circuit 310A. The discharge circuit 122 may also be integrated into this control circuit 310A.

[0061] The switching controller 330 controls the output voltage V OUT The switching controller 330 generates control pulses SpA to SpD so that the output voltage V OUT A duty cycle command value may be generated to adjust the duty cycle, frequency, etc. so that the duty cycle, frequency, etc., approaches a target value, and an internal pulse dpwm may be generated according to this duty cycle command value. Then, the control pulses SpA to SpD may be generated by providing an appropriate control delay to the positive edge and negative edge of this internal pulse dpwm. Alternatively, the control pulses SpA to SpD may be directly converted from the duty cycle command value.

[0062] The gate drivers 340A and 340B receive control pulses SpA and Sp2 via isolators 342A and 342B and drive the primary side transistors MA and MB. The gate drivers 340C and 340D receive control pulses SpC and SpD and drive the secondary side transistors MC and MD.

[0063] In this embodiment, a pair of a primary-side transistor MB and a secondary-side transistor MD corresponds to the first transistor M1 and the second transistor M2 described above, and a connection node between the secondary winding Ws of the transformer TRN2 and the transistor M2 serves as the switching node Nsw described above. One end of the sense capacitor Cs is connected to this switching node Nsw.

[0064] The dead-time controller 320 optimizes the control delay Td between the control pulses SpA and SpD based on the sense voltage Vs across the sense capacitor Cs.

[0065] The above is the configuration of the switching power supply 300A. FIG. 8 is an operation waveform diagram of the switching power supply 300A of FIG. 7. A to D show the actual on and off states of the transistors MA to MD. The high level of the switching voltage Vsw is VIN / N, where N is the turns ratio of the transformer TRN1, and the low level is the ground voltage. Dead time τ D According to the switching power supply 300A, the switching voltage Vsw is a negative voltage during the dead time τ D can be optimized.

[0066] 9 is a circuit diagram of a switching power supply 300B according to Example 2. The switching power supply 300B is a non-insulated DC / DC converter (step-down converter). The step-down converter includes a high-side transistor MB (switching transistor), a low-side transistor (synchronous rectification transistor) MA, an inductor L1, a capacitor C1, a sense capacitor Cs, a rectifier element Ds, a dead-time controller 320, a switching controller 330, and gate drivers 340A and 340B.

[0067] The dead time controller 320 and the switching controller 330 may be integrated into a single control circuit 210B. Furthermore, the gate drivers 340A and 340B and the discharge circuit 122 may also be integrated into this control circuit 210B.

[0068] The switching controller 330 controls the output voltage V OUT The control pulses SpA and SpB are generated so that the output voltage V (or another electrical state) approaches a target value. The configuration and control method of the switching controller 330 are not particularly limited, and any known technology may be used. For example, the switching controller 330 may be configured to OUT A duty cycle command value may be generated to adjust the duty cycle, frequency, etc. so that the duty cycle, frequency, etc., approaches a target value, and an internal pulse dpwm may be generated according to this duty cycle command value. Then, the control pulses SpA and SpB may be generated by providing an appropriate control delay to the positive edge and negative edge of this internal pulse dpwm. Alternatively, the control pulses SpA and SpB may be directly converted from the duty cycle command value.

[0069] The gate drivers 340A and 340B drive the transistors MA and MB in response to control pulses SpA and Sp2.

[0070] In this embodiment, the high-side transistor MB and the low-side transistor MA correspond to the first transistor M1 and the second transistor M2 described above, and the connection node between the two transistors is the switching node Nsw. One end of the sense capacitor Cs is connected to the switching node Nsw.

[0071] The dead-time controller 320 optimizes the control delay Td between the control pulses SpA and SpB based on the sense voltage Vs across the sense capacitor Cs.

[0072] Example 3 10 is a block diagram of a switching power supply 400 according to Example 3. The switching power supply 400 is a half-bridge converter, and includes a transformer TRN1, transistors MA to MD, capacitors C1 to C3, a control circuit 410, gate drivers 422A to 422D, sense capacitors Cs1 and Cs2, and rectifier elements Ds1 and Ds2.

[0073] The control circuit 410 includes a switching controller 412 and a dead time controller 414. The switching controller 412 controls the output voltage V OUT The control pulses SpA to SpD are generated so that the control signal S pA (or another electrical state) approaches a target value.

[0074] The control pulses SpA and SpB are input to the gate drivers 422A and 422B. In an isolation application, an isolator is added between the gate drivers 422A and 422B and the control circuit 410.

[0075] In a half-bridge converter, the pair of transistors MA and MC switches in a complementary manner, and the pair of transistors MB and MD switches in a complementary manner. Therefore, there is a first control delay Td between the control pulses SpA and SpC. AC is introduced, and a second control delay Td is introduced between the control pulses SpB and SpD. BD will be introduced.

[0076] The drain of the transistor MC is the first switching node Nsw1, to which the capacitor Cs1 and the diode Ds1 are connected. The dead time controller 414 controls the first control delay Td AC The drain of the transistor MD is the second switching node Nsw2, to which the capacitor Cs2 and the diode Ds2 are connected. The dead time controller 414 adjusts the second control delay Td BD Adjust.

[0077] For example, the switching controller 412 includes a pulse width modulator 416 and a pulse generator 418. The pulse width modulator 416 controls the output voltage V OUT The duty cycle Don is feedback-controlled so that a feedback signal corresponding to the duty cycle Don (or another electrical state) approaches the target value. A signal corresponding to the duty cycle Don is supplied from the pulse width modulator 416 to the pulse generator 418. The pulse generator 418 calculates the duty cycle Don generated by the pulse width modulator 416 and the control delay Td AC ,Td BD The control pulses SpA to SpD are generated based on the above. The configuration and control method of the switching controller 412 are not particularly limited, and any known technology may be used.

[0078] Fig. 11 is an operational waveform diagram of the switching power supply of Fig. 10. The duty cycle Don is feedback-controlled by the pulse width modulator 416. pwm_p1 and pwm_p2 denote pulse signals having the duty cycle Don. τ12 represents the delay time from the occurrence of an edge of the control pulse SpB (or SpA) to the occurrence of a change in the switching voltage Vsw2 (or Vsw1) based on that edge. This delay time may include the delay of the driver 422B (422A), the turn-on time of the transistor MB, the delay of the transformer TRN, etc.

[0079] Focusing on the transistor pair MB and MD, the dead time τ BD1 is the control delay Td BD1 and delay time τ 12 The total time is: τ BD1 =Td BD1 +τ 12 Also, the dead time τ BD2 is the control delay Td BD2 from delay time τ 12 The time is the time subtracted from the time. τ BD2 =Td BD2 -τ 12

[0080] The dead time controller 414 is BD1 Based on the sense voltage Vs2 according to the length of BD1 The dead time controller 414 also optimizes τ BD2 Based on the sense voltage Vs2 according to the length of BD2 Optimize.

[0081] When we look at the transistor pair MA and MC, the dead time τ AC1 is the control delay Td AC1 and delay time τ 12 The total time is: τ AC1 =Td AC1 +τ 12 Also, the dead time τ AC2 is the control delay Td AC2 from delay time τ 12 The time is the time subtracted from the time. τ AC2 =Td AC2 -τ 12

[0082] The dead time controller 414 is AC1 Based on the sense voltage Vs1 according to the length of AC1 The dead time controller 414 also optimizes τ AC2 Based on the sense voltage Vs1 according to the length of AC2 Optimize.

[0083] Example 4 Fig. 12 is a block diagram of a switching power supply 400A according to a fourth embodiment. This switching power supply 400A is a half-bridge converter, similar to the switching power supply 400 in Fig. 10, but the location of the switching node is different. In Fig. 12, the connection node between the tap of the secondary winding of the transformer TRN and the inductor L1 serves as the switching node. The switching power supply 400A includes a capacitor Cs and a rectifier element Ds connected to the switching node Nsw.

[0084] The dead time controller 414 of the control circuit 410A controls the control delay Td based on the sense voltage Vs across the capacitor Cs. AC ,Td BD Control.

[0085] 13 is an operation waveform diagram of the switching power supply 400A of FIG. 12. The switching voltage Vsw is a voltage obtained by combining the two switching voltages Vsw1 and Vsw2 of FIG. 11. BD1 The control delay Td is based on the sense voltage Vs according to the length of BD1 Optimize τ BD2 The control delay Td is based on the sense voltage Vs according to the length of BD2 Similarly, the dead time controller 414 optimizes τ AC1 The control delay Td is based on the sense voltage Vs according to the length of AC1 Optimize τ AC2The control delay Td is based on the sense voltage Vs according to the length of AC2 Optimize.

[0086] According to the fourth embodiment, the number of parts and the number of pins of the control circuit 410A can be reduced.

[0087] (Embodiment 2) 14 is a circuit diagram of a switching circuit 200 according to the second embodiment. In the first embodiment, the delay time between the edges of the two control pulses Sp1 and Sp2 is optimized, whereas in the second embodiment, the delay time Td of the gate driver is controlled to reduce the dead time τ D Optimize.

[0088] The switching circuit 200 includes a main circuit 110, a dead time controller 120, a controller 130, a gate driver 140_1, and a gate driver 140_2. At least one of the gate driver 140_1 and the gate driver 140_2 is configured so that the delay time Td is variable.

[0089] For example, the gate driver 140_1 may be capable of individually controlling the delay time for the positive edge of the control pulse Sp1 and the delay time for the negative edge of the control pulse Sp1. Similarly, the gate driver 140_2 may be capable of individually controlling the delay time for the positive edge of the control pulse Sp2 and the delay time for the negative edge of the control pulse Sp2.

[0090] The above is the configuration of the switching circuit 200. With this switching circuit 200, the delay time of the gate driver is controlled to reduce the dead time τ D can be optimized.

[0091] (Embodiment 3) 15 is a circuit diagram of a switching circuit 200 including a gate driver circuit 500 according to embodiment 3. The gate driver circuit 500 includes a dead time controller 510, a pulse generating section 520, a first gate driver 530_1, and a second gate driver 530_2.

[0092] The switching controller 130 includes a pulse width modulator, generates a control signal indicating a duty cycle Don of the first transistor M1 and the second transistor M2, and supplies the control signal to the gate driver circuit 500. The control signal may be a pulse signal, a digital value, or an analog signal.

[0093] The pulse generating unit 520 generates a first control pulse Sp1 and a second control pulse Sp2 having a duty cycle according to a control signal from the switching controller 130.

[0094] The dead time controller 510 controls the delay time between adjacent edges of the first control pulse Sp1 and the second control pulse Sp2 in response to the sense voltage Vs across the capacitor Cs.

[0095] The first gate driver 530_1 drives the first transistor M1 in response to a first control pulse Sp1, and the second gate driver 530_2 drives the second transistor M2 in response to a second control pulse Sp2.

[0096] The present invention has been described above based on an embodiment. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each treatment process, and that such modifications are also within the scope of the present invention. Such modifications will be described below.

[0097] The topology of the switching power supply is not limited to that described in the embodiment. Figures 16(a) to 16(f) are diagrams showing variations of the switching power supply.

[0098] 16(a) shows a step-down converter, which was described in Example 2. The architecture of the second or third embodiment may be applied to this step-down converter. In this case, the connection node between transistors A and B may be used as a switching node to change the delay time of the gate drivers of transistors A and B.

[0099] FIG. 16(b) shows a forward converter, which was described in the first embodiment. In the first embodiment, the control of the dead time between the transistors A and D was described. Instead of this, or in addition to this, the dead time between the transistors A and C (control delay T AC ) may be controlled. The architecture of the second or third embodiment may be applied to this forward converter.

[0100] 16(c) shows a half-bridge converter, which has been described in Examples 3 and 4. The architecture of the second or third embodiment may be applied to this half-bridge converter.

[0101] Figure 16(d) shows a full-bridge converter. This full-bridge converter has the same secondary side configuration as the half-bridge converter. The primary side is controlled so that the transistor pair A1 and A2 are turned on simultaneously, and the transistor pair B1 and B2 are turned on simultaneously.

[0102] Therefore, the dead time can be optimized in the same manner as in the half-bridge converter of the third embodiment or the fourth embodiment. Specifically, the operation of the transistor A should be read as the transistor pair A1, A2, and the operation of the transistor B should be read as the transistor pair B1, B2. Either the architecture of the first embodiment or the architecture of the second embodiment may be used for the optimization.

[0103] Figure 15(e) shows a current doubler synchronous rectifier. In this configuration, a pair of transistors A and C operate in a complementary manner, with a control delay Td between them. ACThe drain of transistor C can be optimized as the switching terminal. The pair of transistors B and D operates complementary to each other, and the control delay between them, Td BD can be optimized by using the drain of transistor D as the switching terminal.

[0104] FIG. 15(f) shows a secondary-side full-bridge synchronous rectifier. In the primary-side full-bridge circuit, transistor pairs A and C are turned on and off simultaneously, and transistor pairs B and D are turned on and off simultaneously. In the secondary-side full-bridge circuit, transistor pairs E and G are turned on and off simultaneously, and transistor pairs F and H are turned on and off simultaneously. In this configuration, the drain of transistor E is used as a switching node Nsw1, and the control delay (dead time) Td between transistor pair A, C and transistor pair E, G is determined based on a sense voltage Vs1 corresponding to the switching voltage Vsw1. AE In addition, the drain of the transistor H is set as a switching node Nsw2, and the control delay Td between the transistor pair B, D and the transistor pair F, H is optimized based on the sense voltage Vs2 corresponding to the switching voltage Vsw2. BF (dead time) can be optimized.

[0105] Alternatively, in FIG. 15(f), the connection node between the secondary full-bridge circuit and the secondary inductor is set as the switching node Nsw, and the control delay Td AE ,Td BF may be optimized.

[0106] Switching circuits are used in a variety of applications, such as power supplies and motor drive circuits, and the present invention is also applicable to applications other than power supplies.

[0107] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments without departing from the spirit of the present invention defined in the claims. [Industrial Applicability]

[0108] The present invention relates to a switching circuit. [Explanation of symbols]

[0109] 100 Switching Circuits M1 First transistor M2 Second transistor Cs capacitor Ds Rectifier 110 Main circuit 120 Dead Time Controller 122 Discharge circuit 130 Switching Controller 140,142 Gate Driver 200 Switching Circuits 300 Switching Power Supply 310 Control circuit 320 Dead Time Controller 330 Switching Controller 340 Gate Driver

Claims

1. a first transistor and a second transistor; a switching node which generates a high-level voltage during a period when the first transistor is on and the second transistor is off, generates a low-level voltage during a period when the first transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second terminal of the capacitor; a switching controller that generates a first control pulse and a second control pulse that instruct the first transistor and the second transistor to be turned on and off; a first gate driver that drives the first transistor in response to the first control pulse; a second gate driver that drives the second transistor in response to the second control pulse; a dead time controller for controlling a delay time between edges of the first control pulse and the second control pulse in response to a sense voltage across the capacitor; A switching circuit comprising:

2. a first transistor and a second transistor; a switching node which generates a high-level voltage during a period when the first transistor is on and the second transistor is off, generates a low-level voltage during a period when the first transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second terminal of the capacitor; a switching controller that generates a first control pulse and a second control pulse that instruct the first transistor and the second transistor to be turned on and off; a first gate driver that drives the first transistor in response to the first control pulse; a second gate driver that drives the second transistor in response to the second control pulse; a dead time controller that controls a delay time of at least one of the first gate driver and the second gate driver in response to a sense voltage across the capacitor; A switching circuit comprising:

3. 3. The switching circuit according to claim 1, wherein the dead time controller includes a comparator that compares the voltage across the capacitor with a predetermined target voltage, and increases or decreases the delay time according to an output of the comparator.

4. 3. The switching circuit according to claim 1, wherein the dead time controller feedback controls the delay time so that the voltage across the capacitor approaches a predetermined target voltage.

5. 5. The switching circuit according to claim 1, wherein the dead time controller independently controls the delay time when the first transistor turns on and the delay time when the second transistor turns on.

6. 6. The switching circuit according to claim 1, further comprising a discharge circuit connected to the capacitor and discharging an electric charge of the capacitor while the first transistor is on.

7. a transformer including a primary winding and a secondary winding; the first transistor is connected to the primary winding; the second transistor is connected to the secondary winding; The switching circuit according to claim 1 , wherein the switching node is a connection node between the secondary winding and the second transistor.

8. 7. The switching circuit according to claim 1, wherein the first transistor and the second transistor are connected in series, and the switching node is a connection node between the first transistor and the second transistor.

9. A switching power supply comprising the switching circuit according to any one of claims 1 to 8.

10. A control circuit for a switching power supply, The switching power supply comprises: a first transistor and a second transistor; a switching node which generates a high-level voltage during a period when the first transistor is on and the second transistor is off, generates a low-level voltage during a period when the first transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second terminal of the capacitor; a first gate driver that drives the first transistor in response to a first control pulse; a second gate driver that drives the second transistor in response to a second control pulse; Equipped with The control circuit includes: a switching controller that generates a first control pulse and a second control pulse that instruct the first transistor and the second transistor to be turned on and off; a dead time controller for controlling a delay time between adjacent edges of the first control pulse and the second control pulse in response to a sense voltage across the capacitor; A control circuit comprising:

11. 11. The control circuit of claim 10, wherein the dead time controller includes a comparator that compares the voltage across the capacitor with a predetermined target voltage, and increases or decreases the delay time depending on an output of the comparator.

12. 12. The control circuit according to claim 10, wherein the dead time controller feedback controls the delay time so that the voltage across the capacitor approaches a predetermined target voltage.

13. 13. The control circuit according to claim 10, wherein the dead time controller independently controls the delay time when the first transistor turns on and the delay time when the second transistor turns on.

14. 14. The control circuit according to claim 10, further comprising a discharge circuit connected to the capacitor and discharging an electric charge of the capacitor while the first transistor is on.

15. The switching power supply further comprises a transformer including a primary winding and a secondary winding; the first transistor is connected to the primary winding; the second transistor is connected to the secondary winding; 15. The control circuit according to claim 10, wherein the switching node is a connection node between the secondary winding and the second transistor.

16. 15. The control circuit according to claim 10, wherein the first transistor and the second transistor are connected in series, and the switching node is a connection node between the first transistor and the second transistor.

17. A switching power supply comprising a control circuit according to any one of claims 10 to 16.

18. A gate driver circuit for a switching power supply, comprising: The switching power supply is a first transistor and a second transistor; a switching node which generates a high-level voltage during a period when the first transistor is on and the second transistor is off, generates a low-level voltage during a period when the first transistor is off and the second transistor is on, and generates a negative voltage during a period when both the first transistor and the second transistor are off; a capacitor having a first end connected to the switching node; a rectifying element that applies a constant voltage to a second terminal of the capacitor; a switching controller that generates control signals indicative of duty cycles of the first transistor and the second transistor such that an electrical state of the switching power supply approaches a predetermined target state; Equipped with The gate driver circuit includes: a pulse generating unit that generates a first control pulse and a second control pulse having a duty cycle according to the control signal; a first gate driver that drives the first transistor in response to the first control pulse; a second gate driver that drives the second transistor in response to the second control pulse; a dead time controller for controlling a delay time between adjacent edges of the first control pulse and the second control pulse in response to a sense voltage across the capacitor; A gate driver circuit comprising:

19. 20. The gate driver circuit of claim 18, wherein the dead-time controller increases or decreases the delay time based on a comparison of a voltage across the capacitor to a predetermined target voltage.

20. 20. The gate driver circuit of claim 18, wherein the dead-time controller feedback controls the delay time so that the voltage across the capacitor approaches a predetermined target voltage.

21. 21. The gate driver circuit according to claim 18, wherein the dead time controller independently controls the delay time when the first transistor turns on and the delay time when the second transistor turns on.

22. 22. The gate driver circuit according to claim 18, further comprising a discharge circuit connected to the capacitor and discharging an electric charge of the capacitor while the first transistor is on.

23. The switching power supply further comprises a transformer including a primary winding and a secondary winding; the first transistor is connected to the primary winding; the second transistor is connected to the secondary winding; 23. The gate driver circuit according to claim 18, wherein the switching node is a connection node between the secondary winding and the second transistor.

24. 23. The gate driver circuit according to claim 18, wherein the first transistor and the second transistor are connected in series, and the switching node is a connection node between the first transistor and the second transistor.

25. A switching power supply comprising a switching circuit according to any one of claims 18 to 24.

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