Logic analyzer for integrated circuits

Abstract

To provide a method for monitoring signals in an IC, and a logic analyzer.SOLUTION: A method for monitoring signals in an integrated circuit comprises: monitoring a signal to be probed of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit 405; detecting state change in the signals to be probed using the logic analyzer circuit 415; and generating, within a logic analyzer circuit 430, a file specifying time-stamped state change of the signal to be probed.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to integrated circuits (ICs), and more particularly to logic analyzers for monitoring signals within an IC. [Background technology]

[0002] A logic analyzer is an electronic system that can monitor one or more signals of another electronic system. In some cases, a logic analyzer can be utilized as a core that can be incorporated into a circuit design that is implemented within an integrated circuit (IC). In such cases, the logic analyzer and the target circuit and / or signals monitored by the logic analyzer may be implemented within the same IC.

[0003] Typically, a logic analyzer samples the values ​​of the signals it monitors. Typically, the sampling rate matches the clock rate to capture the value of the signals at each clock cycle over time. The logic analyzer attempts to store the resulting data, e.g., the sampled values, in the memory of the IC itself, or output the data to another system. Depending on the sampling rate, the number of signals monitored, and the time frame over which the signals are monitored, logic analyzers generate a large amount of data. If this data is stored in the IC, a significant amount of memory is required. If this data is output from the IC, a significant amount of bandwidth is required. These constraints limit the time frame over which signals can be monitored, or limit the number of signals that can be monitored. Summary of the Invention

[0004] One or more embodiments relate to a method for monitoring signals in an integrated circuit (IC). In one aspect, the method includes monitoring probed signals of the IC using a logic analyzer circuit implemented in the IC, detecting state changes of the probed signals using the logic analyzer circuit, and generating, in the logic analyzer circuit, a file specifying time-stamped state changes of the probed signals.

[0005] In some embodiments, the file may be specified in ASCII format.

[0006] In some embodiments, the file may be a value change dump file.

[0007] In some embodiments, the method may further include outputting the generated file to an external system in substantially real-time.

[0008] In some embodiments, the method may further include initiating a predetermined action associated with the trigger condition in response to determining that a state change in the probed signal corresponds to the trigger condition.

[0009] In some embodiments, the method may further include providing the file to a processor within the integrated circuit. The processor may be configured to execute the program code.

[0010] In some embodiments, the method may further include providing the file to an external system, which may be configured to generate a visualization of the file.

[0011] In some embodiments, generating the file may include encoding a header section, encoding a variable definition section, encoding an initial value section, and encoding a value change section.

[0012] In some embodiments, the logic analyzer circuitry may be implemented in hardware using programmable circuitry of an integrated circuit.

[0013] One or more embodiments relate to an IC. In one aspect, the IC includes a monitored circuit configured to generate a signal and a logic analyzer circuit configured to monitor the signal to detect state changes of the signal and generate a file specifying time-stamped state changes of the signal.

[0014] In some embodiments, the file may be an ASCII format file.

[0015] In some embodiments, the file may be a value change dump file.

[0016] In some embodiments, the logic analyzer circuit may include a trace circuit configured to receive the signal and determine whether a current state of the signal differs from a previous state of the signal, and a file generation circuit coupled to the trace circuit. The file generation circuit may be configured to generate a file specifying time-stamped state changes of the signal.

[0017] In some embodiments, the trace circuitry may be configured to initiate a predetermined action associated with the trigger condition in response to determining that a change in state of the signal corresponds to a trigger condition.

[0018] In some embodiments, the logic analyzer circuitry may include an interface coupled to the file generation circuitry.

[0019] In some embodiments, the integrated circuit may further include a processor coupled to the interface. The processor may be configured to execute the program code and receive the file.

[0020] In some embodiments, the processor may be configured to generate a waveform view of the monitored signal from the file.

[0021] In some embodiments, the integrated circuit may further include an input / output circuit coupled to the interface, the input / output circuit may be configured to output the file to an external system.

[0022] In some embodiments, the external system may generate a waveform view of the signal from the file.

[0023] In some embodiments, the logic analyzer circuitry may be implemented in hardware using programmable circuitry of an integrated circuit.

[0024] This summary section is provided merely to introduce certain concepts, and is not intended to identify key or essential features of the claimed subject matter. Other features of the inventive subject matter will be apparent from the accompanying drawings and the detailed description that follows.

[0025] Configurations of the present invention are illustrated by way of example in the accompanying drawings. The drawings should not, however, be construed as limiting the configuration of the present invention to only the particular embodiments shown. Various aspects and advantages will become apparent upon consideration of the following detailed description and upon reference to the drawings. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 illustrates an exemplary integrated circuit (IC) including a logic analyzer circuit. [Diagram 2] FIG. 1 illustrates an exemplary implementation of a logic analyzer circuit. [Diagram 3] FIG. 2 illustrates another exemplary IC that includes a logic analyzer circuit. [Figure 4] FIG. 2 illustrates an exemplary method for generating trace data. [Diagram 5] FIG. 1 illustrates an exemplary architecture of an IC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The disclosure ends with claims that define novel features, but it is believed that the various features described in the disclosure will be better understood in light of the description in conjunction with the drawings. The processes, machines, manufactures, and any variations thereof described herein are provided for illustrative purposes. The specific structural and functional details described in the disclosure should not be construed as limiting, but merely as a basis for the claims, and as a representative basis for teaching those skilled in the art to employ the described features in various ways in substantially any appropriately detailed structure. Moreover, the terms and phrases used in the disclosure are not intended to be limiting, but rather to provide an understandable description of the described features.

[0028] The present disclosure relates to integrated circuits (ICs), and more particularly to logic analyzers for monitoring signals within an IC. The inventive arrangements described within this disclosure facilitate monitoring and analysis of internal signals of an IC. In one or more embodiments, a logic analyzer is implemented within an IC and can monitor one or more selected signals, referred to as "probed signals." Additionally, the logic analyzer can analyze the probed signals of the IC itself.

[0029] In one or more embodiments, the logic analyzer can detect state changes of the signals being probed. The logic analyzer can determine a timestamp for each detected state change of the signals being probed. The logic analyzer can further generate a file specifying the time-stamped state changes of the signals being probed. The file is generated by logic analyzer hardware within the IC. The logic analyzer can further output the file to another circuit and / or system within the IC and / or to another circuit and / or system external to the IC.

[0030] A conventional logic analyzer attempts to continuously capture the values ​​of the probed signals. The values ​​are sampled, for example, at the clock rate of the system being monitored. The sampled values ​​are saved and retained as trace data for at least the time frame during which the logic analysis is performed. Thus, a logic analyzer generates and saves a large amount of trace data, e.g., the value of each probed signal at each clock cycle over the time frame during which the probed signals are monitored. Capturing this amount of data requires significant memory resources in the IC to store the data. This means that logic analyzers become larger and more complex, and fewer memory resources (and routing resources) are available for the implementation of the electronic system being monitored.

[0031] Also, capturing large amounts of trace data requires significant bandwidth to offload the trace data from the IC in a timely manner. Often, conventional logic analyzers in ICs use a Joint Test Action Group (JTAG) interface to offload trace data from the IC. However, JTAG interfaces tend to be slow. For example, the JTAG interface offloads trace data from the IC at a rate that is much slower than the rate at which the trace data is generated. This means that the IC may lack memory resources to implement a logic analyzer to store the trace data. The increased complexity of the logic analyzer can, in some cases, lower the maximum achievable operating frequency of a circuit design during synthesis, placement, and / or routing for implementation within the IC. In such cases, a circuit design that includes a conventional logic analyzer operates at a slower frequency than if the conventional logic analyzer was not included.

[0032] The exemplary embodiments described herein address these limitations and others by utilizing a file format that represents trace data as state change data. The file format is generated by or within the logic analyzer hardware itself. By generating the file on the logic analyzer hardware, the logic analyzer hardware in effect applies a compressed format to the generated trace data. For example, each sampled value of a probed signal does not need to be stored for more than a few clock cycles in order to detect state changes relative to the previous clock cycle. Furthermore, the resulting file is specified in a format that does not require proprietary decoding techniques to access the trace data contained therein.

[0033] Further aspects of the inventive arrangement are described in more detail below with reference to the drawings. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding, similar or like features.

[0034] FIG. 1 illustrates an exemplary IC 100 that includes a logic analyzer circuit. In the example of FIG. 1, IC 100 may be implemented as any of a variety of different types of ICs. Examples include, but are not limited to, digital ICs, application specific integrated circuits (ASICs), programmable ICs, partially programmable ICs, or other suitable ICs. Examples of programmable and / or partially programmable ICs include, but are not limited to, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and / or other ICs that include one or more programmable circuit blocks, programmable circuit tiles, or other programmable circuits.

[0035] As shown, IC 100 includes a circuit to be monitored 105. Circuit to be monitored 105 is coupled to logic analyzer circuit 110. More specifically, one or more wires 115 or interconnects couple circuit to be monitored 105 and logic analyzer circuit 110. Each of wires 115 carries a signal to be monitored. For purposes of explanation, the signals carried by wires 115 are referred to herein as "signals to be probed."

[0036] The monitored circuit 105 may be implemented as any circuit that contains or generates a signal to be monitored (e.g., a signal to be probed). In one or more embodiments, the monitored circuit 105 is a circuit specified by a user. For example, the monitored circuit 105 may include a circuit that is implemented as part of a user circuit design. In the case of a programmable IC, the monitored circuit 105 may be implemented in whole or in part using the programmable circuitry of the IC.

[0037] In one or more embodiments, logic analyzer circuit 110 is implemented as a hardwired circuit within IC 100. In one or more other embodiments, logic analyzer circuit 110 is implemented within programmable circuitry of the IC. For example, logic analyzer 110 may be provided as a core, a parameterizable portion of a circuit or core, or a predefined unit of a circuit that may be incorporated into a user circuit design that includes monitored circuit 105. In the latter case, when implemented in programmable circuitry, logic analyzer circuit 110 may have a user-selectable number of probe ports. Each probe port may have a user-selectable probe width.

[0038] In any case, logic analyzer circuitry 110 is not implemented as a processor executing program code, but rather is circuitry dedicated to performing the operations described herein, whether implemented as hardwired or hard circuitry, programmable circuitry, or a combination of hard and programmable circuitry.

[0039] The logic analyzer circuit 110 can receive the probed signals carried by the wires 115. The logic analyzer circuit 110 can further analyze the probed signals. In one or more embodiments, the logic analyzer circuit 110 can detect a state change of each of the probed signals received from the monitored circuit 105. For each detected state change, the logic analyzer circuit 110 can determine a timestamp at which the detected state change occurred. In one or more embodiments, the logic analyzer circuit 110 at least temporarily stores only the time-stamped state changes of the probed signals, rather than continuously storing sampled signal values ​​regardless of the detected state change.

[0040] In one or more embodiments, logic analyzer circuit 110 can detect a trigger condition. A trigger condition is the occurrence of a particular or predetermined state on one or more of the signals being probed. Logic analyzer circuit 110 can monitor the state of the signals being probed and can initiate an action associated with the trigger condition in response to detecting the predetermined state of the signals being probed or the predetermined state of the multiple signals being probed that corresponds to the trigger condition. In one example, logic analyzer circuit 110 can refrain from generating file 120 until the particular trigger condition is detected. In response to detecting the trigger condition, logic analyzer circuit 110 can generate or initiate generation of file 120 to output trace data. Multiple probe ports of logic analyzer circuit 110 may be coupled to a single trigger condition, such as monitoring a signal thereon.

[0041] In one or more embodiments, logic analyzer circuit 110 may output trace data of the probed signals as file 120. File 120 may specify state change data of the probed signals and timestamps of the state change data. For example, file 120 may specify each state change and timestamp of such state change for each of the probed signals.

[0042] In the example of Figure 1, file 120 is generated in hardware. Logic analyzer circuit 110 generates file 120. In one or more embodiments, file 120 is encoded using American Standard Code for Information Interchange (ASCII). As an illustrative and non-limiting example, file 120 is implemented as a Value Change Dump (VCD) file. In one or more embodiments, file 120 complies with IEEE Standard 1364-1995. In one or more embodiments, file 120 complies with IEEE Standard 1364-2001.

[0043] Listing 1 shows an example of a file 120. Listing 1 is formatted in ASCII as a VCD file.

[0044] Listing 1 $date Sept 10 2008 12:00:05 $end #Version Example simulator V0.1 $end $timescale 1ns $end $scope module top $end $var wire 32 ! data $end $var wire 1 @ en $end $var wire 1 # rx $end $var wire 1 $ tx $end $var wire 1% err $end $var wire 1 ^ ready $end $upscope $end $enddefinitions $end #0 b10000001! 0@ 1# 0$ 1% 0^ #1 1@ #2 0@ #3 1@ #5 1@ #11 b0 0# #16 b101010101010110101010101010101 ! 1# #20 0% #twenty three ...

[0045] By generating the trace data as files in ASCII format and as VCD files, various systems can easily display and render the trace data without further processing. For example, the VCD files can be provided directly to a VCD waveform viewer. VCD waveform viewers are readily available and can be implemented, for example, within a standard browser, without the need to perform special or proprietary decoding of the trace data.

[0046] In certain embodiments, logic analyzer circuit 110 may continue to output file 120 as a data stream for the period that logic analyzer circuit 110 is monitoring the probed signal. Logic analyzer circuit 110 may output file 120 in real-time or substantially real-time, within which the analysis is performed. Thus, in one or more embodiments, logic analyzer circuit 110 is not limited or constrained by the amount of on-chip memory of IC 100.

[0047] In accordance with the inventive configurations described herein, logic analyzer circuit 110 is able to monitor a large number of signals without storing trace data for each monitored signal for each clock cycle. As an illustrative example, a user may specify that logic analyzer 110 is implemented in a programmable circuit of an IC and is to monitor 1,000 signals of monitored circuit 105. Rather than storing the values ​​of each of the 1,000 probed signals as trace data for each clock cycle, the logic analyzer only stores the state changes of each event as trace data along with a timestamp of the state change. Given known initial states of the probed signals, the resulting trace data in file 120 indicates the value of each probed signal at any given time that the probed signals are monitored. By recording state changes, the logic analyzer is able to use fewer memory resources (e.g., use less block random access memory) than would a conventional logic analyzer.

[0048] Figure 2 shows an exemplary implementation of logic analyzer circuit 110 of Figure 1. In the example of Figure 2, logic analyzer circuit 110 includes trace circuit 205, file generation circuit 220, and interface 225. Trace circuit 205 may include trace capture circuit 210 and trace analysis circuit 215.

[0049] The trace capture circuit 210 is coupled to wires 115 (not shown). The trace capture circuit 210 may receive each of the probed signals. In one or more embodiments, the trace capture circuit 210 may buffer the values ​​of the probed signals. In one or more embodiments, the trace capture circuit may capture or store a current value of each probed signal (e.g., for the current clock cycle) and a previous value of each probed signal (e.g., from the immediately preceding clock cycle to before the current clock cycle).

[0050] The trace analysis circuit 215 may perform an analysis of the probed signals. In one or more embodiments, the trace analysis circuit 215 may determine whether each probed signal has changed state. For example, for each probed signal, the trace analysis circuit 215 may determine whether the value of the probed signal has transitioned from 0 to 1 or from 1 to 0. The trace analysis circuit 215 may receive a current value and a previous value of each probed signal from the trace capture circuit 210 and perform a comparison to determine whether the current value of each probed signal differs from the previous value of the probed signal.

[0051] 2, the trace analysis circuit 215 may output trace data specifying which probed signals have changed state and a timestamp for each such change in state of the probed signals. As shown, the file generation circuit 220 is coupled to the output of the trace analysis circuit 215. Thus, the file generation circuit 220 receives the trace data.

[0052] The file generation circuit 220 can generate a file that specifies the trace data. In one or more embodiments, the file generation circuit 220 can generate an ASCII-encoded file. The ASCII-encoded file is a VCD file or another suitable file type. Thus, rather than saving the value of each probed signal as trace data over time (e.g., the entire time that the logic analyzer 110 is active and monitoring the probed signals), the logic analyzer 110 can detect and save state changes of the probed signals as part of generating the file 120.

[0053] As described, in certain embodiments, logic analyzer circuit 110 is implemented in programmable circuitry of IC 100. As part of the implementation of a circuit design, for example, a user may specify which signals of the circuit design to monitor. An electronic design automation (EDA) system may include an instance of logic analyzer circuit 110 within the user's circuit design, configure logic analyzer circuit 110 to monitor signals to be probed (specified by the user), and route the signals to be probed to logic analyzer circuit 110 as part of the implementation flow (e.g., synthesis, placement, and routing).

[0054] Thus, the EDA system can generate logic analyzer circuitry 110, and more specifically file generation circuitry 220, to create and / or write various sections of file 120. Since logic analyzer circuitry 110 knows, for example, the signals to be monitored, file generation circuitry 220 can be pre-configured to generate specific portions of file 120, such as a header section and a variable definition section. File generation circuitry 220 includes the circuitry necessary to encode other data, such as initial values ​​and value changes (with timestamps) when such information is detected.

[0055] The file generation circuit 220 outputs the file 120 to the interface 225. In one or more embodiments, the file generation circuit 220 writes the file 120 to a memory. In certain embodiments, the memory is implemented or included within the file generation circuit 220. The memory may be implemented as a first-in, first-out (FIFO) memory or other type of memory circuit (e.g., a buffer memory or a RAM). The interface 225 can read the file 120 from the memory and provide the file 120 to another circuit and / or system. In one or more embodiments, the interface 225 can stream the file 120 to the circuit and / or system. For example, the interface 225 can output the file 120 as it is generated in real time or substantially real time without waiting for the file 120 to be completely generated (e.g., due to the end of a monitoring window).

[0056] In one example, interface 225 is implemented as an AMBA eXtensible Interface (AXI) bus. The AMBA AXI bus is an embedded microcontroller bus interface used to establish on-chip connections between circuit blocks or systems. For example, interface 225 may be implemented as an AXI stream interface, an AXI memory-mapped interface, or another native interface of an IC. Other implementations of an interconnect or interface may include, but are not limited to, a bus, a crossbar, and a network-on-chip (NoC).

[0057] In one or more embodiments, the interface 225 is coupled to input / output (I / O) circuitry. The I / O circuitry may be implemented as various peripheral circuits and / or ports, such as gigabit transceivers, universal serial bus (USB) ports, Ethernet ports, or other communication ports implemented within the IC that allow the IC to provide the files 120 to an external system. The I / O circuitry may be a high-speed communication interface, thereby removing the JTAG dependency from the logic analyzer 110. In one or more other embodiments, the interface 225 is coupled to a processor implemented within the IC. The processor may be capable of executing program code. The processor may be hardwired within the IC or may be implemented using programmable circuitry included in the IC.

[0058] The exemplary implementation of Figure 2 facilitates low latency from the capture of trace data to the display of the trace data by an external system. In particular embodiments, the exemplary architecture described in connection with Figure 2 supports live, e.g., real-time or substantially real-time, debugging of IC 100 from nearly any external data processing system, regardless of the location and proximity of IC 100. For example, file 120 may be rendered and displayed in real time by an external system as file 120 is generated, output from the IC, and received by the external system.

[0059] In one or more embodiments, logic analyzer circuit 110 may be pipelined to facilitate capture of clock signal data without loss of data. In an exemplary implementation, logic analyzer circuit 110 may include sufficient memory resources (e.g., block RAM) to ensure 512 / 1024 sample retention in the event that software capture (e.g., by a remote system) is not possible or there is a software failure.

[0060] 3 illustrates another exemplary IC 300 that includes logic analyzer circuit 110. In one or more embodiments, logic analyzer circuit 110 is coupled to processor 305. Processor 305 is coupled to memory 310 and I / O circuit 315. In the example of FIG. 3, I / O circuit 315 may also be coupled to memory 310. Memory 310 may be any of a variety of different types of RAM. For example, I / O circuit 315 may be coupled to memory 310 via one or more direct memory access (DMA) circuits. Thus, processor 305 may initiate output of a trace data file to external system 320 via I / O circuit 315.

[0061] In one or more embodiments, the processor 305 is implemented using programmable circuitry of the IC 300. In one or more embodiments, the processor 305 is implemented as a hardwired processor of the IC 300. The memory 310 may be implemented on-chip using programmable circuit memory resources or as hardwired memory resources. In one or more other embodiments, the memory 310 is implemented off-chip.

[0062] The external system 320 may be a data processing system, such as a computer system. For example, the external system 320 may be a server. In one or more embodiments, the IC 300 is included within a larger, more complex system and / or a remote environment, such as a computer system in a data center and / or server farm.

[0063] In embodiments where the external system 320 is a data processing system, the external system 320 may execute a browser. The browser may then render a file received from the logic analyzer 110 (e.g., an IC). For example, the browser or other application executed by the external system 320 may generate a visualization of the file showing a waveform. For example, the external system 320 may receive the file in substantially real time and continue to generate the waveform specified by the file in substantially real time, such that a user may view the waveform of the trace data generated by the file generation circuit 220 in substantially real time.

[0064] In an illustrative example, the processor 305 may receive a request to launch the logic analyzer circuit 110 from the external system 320. In response to the request, the processor 305 may launch the logic analyzer circuit 110 and send a file to a particular address or destination, such as the external system 320.

[0065] In one or more other embodiments, the processor 305 may execute a browser or other software capable of reading and / or processing the file 120. For example, the processor 305 may generate (or render) a waveform view of the file 120. In that case, for example, the I / O circuitry 315 may be a video output port that may be provided to or coupled to a monitor that displays the waveform of the file 120.

[0066] In certain embodiments, logic analyzer circuitry 110 is directly coupled to I / O device 315 without utilizing and / or including processor 305. In that case, logic analyzer circuitry 110 can output files generated therein directly to external system 320 via I / O circuitry 315 without using or relying on processor 305 and / or memory 310.

[0067] 4 illustrates an exemplary method 400 for generating trace data. Method 400 may be performed by a logic analyzer circuit as described in connection with FIGS. 1-3 herein. Method 400 may begin with the logic analyzer circuit implemented within an integrated circuit. Additionally, probed signals of a circuit to be monitored, such as a user circuit design, are routed and / or provided to the logic analyzer circuit for monitoring.

[0068] At block 405, the logic analyzer circuitry begins monitoring the signals being probed. At block 410, the logic analyzer circuitry determines whether a state change is detected in one or more or all of the signals being probed. If the logic analyzer detects a state change in one or more or all of the signals being probed, method 400 continues at block 415. If the logic analyzer does not detect a state change, method 400 returns to block 405 to continue monitoring the signals being probed.

[0069] At block 415, the logic analyzer determines whether a trigger condition is detected. In one or more embodiments, the trigger condition is the presence of a particular value or state in one or more of the signals being probed. If a trigger condition is detected, method 400 proceeds to block 420. If a trigger condition is not detected, method 400 continues to block 430.

[0070] At block 420, if a trigger condition is detected, the logic analyzer selects an action associated with the particular trigger condition detected. For example, the logic analyzer may be capable of initiating multiple different actions. These different actions may be associated with different trigger conditions. Thus, the logic analyzer may select an action from multiple actions based on the particular trigger condition detected at block 415.

[0071] After block 420, the method 400 continues at block 425. At block 425, the logic analyzer initiates or performs the action selected in block 420.

[0072] Continuing at block 430, the logic analyzer generates a file specifying the time-stamped state changes of the probed signal. For example, the logic analyzer may generate an ASCII encoded file. As mentioned above, in one or more embodiments, the file may be a VCD file.

[0073] In one or more embodiments, the logic analyzer generates and / or encodes a header section of the file. The logic analyzer may further generate and / or encode a variable definition section of the file. The logic analyzer may further generate and / or encode an initial value section of the file. The initial value section of the file specifies a starting value or state of each of the signals being probed. The logic analyzer may further generate a value change section. It should be appreciated that the logic analyzer circuitry continues to generate value change sections as long as the logic analyzer continues to monitor the signals being probed and detect state changes.

[0074] As an illustrative example, the logic analyzer circuit may generate a beginning portion of a file. As further state changes in the probed signal are detected, the logic analyzer circuit continues to generate value change sections. Because the file is continually generated by the logic analyzer circuit, the logic analyzer circuit may output the file. Thus, at block 435, the logic analyzer circuit outputs the file. As previously discussed, because outputting the file includes cases where the logic analyzer circuit generates a portion of the file and continues to generate further portions of the file, the file may be streamed out from the logic analyzer circuit to another circuit and / or system, or from the IC to another circuit and / or system external to the IC.

[0075] As described, in one or more embodiments, the file may be output to an external system. The external system may generate a waveform view of the trace data. The external system may receive and display the waveform view in substantially real-time. For example, the external system may generate the waveform view within about one second of acquiring the probed signal.

[0076] FIG. 5 illustrates an exemplary architecture 500 of an IC. In one aspect, the architecture 500 may be implemented in a programmable IC. For example, the architecture 500 may be used to implement an FPGA. The architecture 500 may be representative of a system-on-chip (SOC) type IC. A SOC is an IC that includes a processor that executes program code and one or more other circuits. The other circuits may be implemented as hardwired circuits, programmable circuits, and / or combinations thereof. The circuits may operate in cooperation with each other and / or with the processor. In one or more embodiments, the monitored circuit 105, the logic analyzer circuit 110, the processor 305, the memory 310, and / or the I / O circuit 315 may be implemented in an IC having an architecture the same or similar to that of FIG. 5.

[0077] As shown, architecture 500 includes several different types of programmable circuits, e.g., logic, blocks. For example, architecture 500 may include a number of different programmable tiles, including multi-gigabit transceivers (MGTs) 501, configurable logic blocks (CLBs) 502, random access memory blocks (BRAMs) 503, input / output blocks (IOBs) 504, configuration and clock logic (CONFIG / CLOCKS) 505, digital signal processing blocks (DSPs) 506, specialized I / O blocks 507 (e.g., configuration and clock ports), and other programmable logic 508, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc.

[0078] In some ICs, each programmable tile includes a programmable INT 511 with standardized connections between corresponding interconnect elements (INT) 511 in each adjacent tile. Thus, the INTs 511 together implement the programmable interconnect structure of the illustrated IC. Each INT 511 also includes connections with programmable logic elements in the same tile, as shown in the example included at the top of FIG.

[0079] For example, CLB 502 may include a configurable logic element (CLE) 512 that can be programmed to implement a single INT 511 in addition to user logic. BRAM 503 may include a BRAM logic element (BRL) 513 in addition to one or more INTs 511. Typically, the number of INTs 511 included in a tile depends on the height of the tile. As shown, a BRAM tile is as tall as five CLBs, although other numbers (e.g., four) may be used. DSP tile 506 may include a DSP logic element (DSPL) 514 in addition to an appropriate number of INTs 511. IOB 504 may include, for example, two instances of I / O logic element (IOL) 515 in addition to one instance of INT 511. The actual I / O pads connected to IOL 515 may not be limited to the area of ​​IOL 515.

[0080] 5, a columnar region near the center of the die formed, for example, by regions 505, 507, and 508 may be used for configuration, clocks, and other control logic. A horizontal region 509 extending from the columns may be used to distribute clocks and configuration signals across the width of the programmable IC.

[0081] Some ICs utilizing the architecture shown in Figure 5 include additional logic blocks that break down the normal column structure that makes up the bulk of the IC. The additional logic blocks may be programmable blocks and / or dedicated circuits. For example, the processor block shown as PROC 510 spans several columns of CLBs and BRAMs.

[0082] In one aspect, PROC 510 may be implemented as a dedicated circuit, e.g., a hardwired processor, fabricated as part of a die that implements the programmable circuitry of an IC. PROC 510 may represent any of a variety of different processor types and / or systems ranging in complexity from an individual processor, e.g., a single core capable of executing program code, to an entire processor system having one or more cores, modules, co-processors, interfaces, etc.

[0083] In alternative embodiments, PROC 510 may be omitted from architecture 500 and replaced with one or more of the other types of programmable blocks described. Moreover, such blocks may be utilized to form a "soft processor," in that, as in the case of PROC 510, various blocks of programmable circuitry may be used to form a processor capable of executing program code.

[0084] The phrase "programmable circuitry" refers to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or tiles described herein, as well as interconnect circuitry that selectively couples the various circuit blocks, tiles, and / or elements according to configuration data loaded into the IC. For example, the circuit blocks shown in FIG. 5 that are external to PROC 510, such as CLB 502 and BRAM 503, are considered programmable circuitry of the IC.

[0085] Generally, the functionality of a programmable circuit is not established until configuration data is loaded into the IC. A set of configuration bits can be used to program the programmable circuit of an IC, such as an FPGA. The configuration bits are typically referred to as a "configuration bitstream." Generally, a programmable circuit will not operate or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements a particular circuit design within the programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connectivity between the various programmable circuit blocks.

[0086] "Hardwired" or "hardened" i.e., non-programmable, circuits are fabricated as part of an IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented by the loading of a configuration bitstream after the fabrication of the IC. Hardwired circuits are generally thought of as having dedicated circuit blocks and interconnections that function without first loading a configuration bitstream into the IC, e.g., PROC510.

[0087] In some cases, a hardwired circuit may have one or more operating modes that can be set or selected according to register settings or values ​​stored in one or more memory elements within the IC. The operating mode may be set, for example, by loading a configuration bitstream into the IC. Despite this feature, a hardwired circuit is not considered a programmable circuit because the hardwired circuit is operational and has a particular function when manufactured as part of an IC.

[0088] In the case of an SOC, the configuration bitstream may specify the circuitry to be implemented in the programmable circuitry and the program code to be executed by PROC 510 or a soft processor. In some cases, architecture 500 includes a dedicated configuration processor that loads the configuration bitstream into appropriate configuration memory and / or processor memory. The dedicated configuration processor does not execute user-specified program code. In other cases, architecture 500 may use PROC 510 to receive the configuration bitstream, load the configuration bitstream into appropriate configuration memory, and / or extract the program code for execution.

[0089] FIG. 5 is intended to illustrate an exemplary architecture that may be used to implement a programmable circuit, e.g., an IC including a programmable fabric. For example, the number of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the implementation of interconnect / logic included in the upper portion of FIG. 5 are purely exemplary. For example, in an actual IC, adjacent columns of multiple CLBs will typically be included wherever a CLB appears to facilitate efficient implementation of a user circuit design. However, the number of adjacent CLB columns may vary depending on the overall size of the IC. Additionally, the size and / or location of blocks such as PROC 510 within an IC are for illustrative purposes only and are not intended as limitations.

[0090] Exemplary embodiments described herein allow a logic analyzer to monitor a large number of signals using fewer IC resources than traditional logic analyzer designs. In one or more embodiments, data can be continuously output from an IC in a VCD file format without limitations on on-chip memory availability. Furthermore, an external system, such as a host system running a browser, can display or render the VCD file without first converting the IC's proprietary data format into a usable format, such as a format used by an EDA tool.

[0091] In one or more embodiments, the time lag between capturing the probed signal and viewing the VCD file occurs in real time (e.g., within about one second of capturing the probed signal). In certain embodiments, a clock signal may be monitored. Thus, the designer can monitor the IC's internal signals in real time. Additionally, the designer can monitor the probed signal for a longer period of time than if the probed signal were stored within the IC, because the logic analyzer is not constrained by the amount of internal memory available in the IC.

[0092] For purposes of explanation, specific nomenclature is set forth in order to provide a thorough understanding of the various inventive concepts disclosed herein. However, the terminology used herein is for the purpose of describing particular aspects of the inventive configurations only and is not intended to be limiting.

[0093] As defined herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. As defined herein, the terms "at least one," "one or more," and "and / or" are open-ended expressions that are both conjunctive and disjunctive in operation unless otherwise indicated. For example, "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" mean A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0094] As defined herein, "one embodiment," "embodiment," "one or more embodiments," or similar phrases mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment described within this disclosure. Thus, appearances of "in one embodiment," "in an embodiment," "in one or more embodiments," and similar phrases throughout this disclosure all refer to the same embodiment, although not necessarily the same.

[0095] The term "real-time" as defined herein means a level of processing responsiveness that a user or system perceives as immediate enough for a particular process or decision to occur, or that allows the processor to keep up with some external process.

[0096] As defined herein, the term "responsive" means to readily respond or react to an action or event. Thus, when a second action is performed "in response" to a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. The term "responsive" indicates a causal relationship.

[0097] The term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but deviations or variations including, for example, tolerances, measurement errors, limitations in measurement accuracy, and other factors known to those skilled in the art may occur in an amount that does not interfere with the effect that the characteristic is intended to provide.

[0098] In this specification, terms such as first, second, etc. may be used to describe various elements, but these elements should not be limited by these terms, as these terms are only used to distinguish one element from another, unless otherwise noted or clearly indicated otherwise by context.

[0099] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various aspects of the inventive configuration. In some alternative implementations, the operations described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may be executed substantially simultaneously, or sometimes the blocks may be executed in reverse order, depending on the functionality involved. In other examples, the blocks are generally executed in ascending numerical order, while in still other examples, one or more blocks may be executed in various orders, with the results stored and utilized in a subsequent block or in another block that does not immediately follow. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or operations or execute a combination of special-purpose hardware and computer instructions.

[0100] The corresponding structure, materials, acts, and equivalents of all means or step-plus-function elements found in the following claims are intended to include the structure, materials, or acts for performing the function in combination with other claimed elements as specifically claimed.

[0101] One or more embodiments relate to a method for monitoring signals in an IC. In one aspect, the method includes monitoring probed signals of the IC using a logic analyzer circuit implemented in the IC, detecting state changes of the probed signals using the logic analyzer circuit, and generating, in the logic analyzer circuit, a file specifying time-stamped state changes of the probed signals.

[0102] In one embodiment, the file is specified in ASCII format.

[0103] In another aspect, the file is a value change dump file.

[0104] In another aspect, the method may also include outputting the generated file to an external system in substantially real-time.

[0105] In another aspect, the method may also include, in some embodiments, in response to determining that a state change in the probed signal corresponds to the trigger condition, initiating a predetermined action associated with the trigger condition.

[0106] In another aspect, the method may also include providing the file to a processor within the integrated circuit, the processor being configured to execute the program code.

[0107] In another aspect, the method may also include providing the file to an external system, the external system configured to generate a visualization of the file.

[0108] In another aspect, generating the file includes encoding a header section, encoding a variable definition section, encoding an initial value section, and encoding a value change section.

[0109] In another aspect, the logic analyzer circuit is implemented in hardware using programmable circuitry of an integrated circuit.

[0110] One or more embodiments relate to an IC. In one aspect, the IC includes a monitored circuit configured to generate a signal and a logic analyzer circuit configured to monitor the signal to detect state changes of the signal and generate a file specifying time-stamped state changes of the signal.

[0111] In one embodiment, the file is an ASCII format file.

[0112] In another aspect, the file is a value change dump file.

[0113] In another aspect, the logic analyzer circuit includes a trace circuit configured to receive the signal and determine whether a current state of the signal differs from a previous state of the signal. The logic analyzer circuit can also include a file generation circuit coupled to the trace circuit, the file generation circuit configured to generate a file specifying time-stamped state changes of the signal.

[0114] In another aspect, the tracing circuitry is configured to initiate a predetermined action associated with the trigger condition in response to determining that a change in state of the signal corresponds to the trigger condition.

[0115] In another aspect, the logic analyzer circuit includes an interface coupled to the file generation circuit.

[0116] In another aspect, an IC includes a processor coupled to the interface, the processor configured to execute program code and receive the file.

[0117] In another aspect, the processor is configured to generate a waveform view of the monitored signal from the file.

[0118] In another aspect, the IC includes an I / O circuit coupled to the interface, the I / O circuit configured to output the file to an external system.

[0119] In another aspect, the external system generates a waveform view of the signal from the file.

[0120] In another embodiment, the logic analyzer circuit is implemented in hardware using programmable circuitry of an IC.

[0121] One or more embodiments relate to implementing an IC that includes a logic analyzer circuit. In one aspect, a method can include providing a logic analyzer circuit. The logic analyzer circuit is configured to monitor a signal to detect state changes of the signal and generate a file specifying time-stamped state changes of the signal. For example, the file can be an ASCII format file. In a particular example, the file can be a value change dump file.

[0122] In another aspect, the method includes providing a logic analyzer circuit to include a trace circuit configured to receive a signal and determine whether a current state of the signal differs from a previous state of the signal. Providing the logic analyzer circuit can include providing a file generation circuit coupled to the trace circuit, the file generation circuit configured to generate a file specifying time-stamped state changes of the signal.

[0123] In another aspect, the tracing circuitry is configured to initiate a predetermined action associated with the trigger condition in response to determining that a change in state of the signal corresponds to the trigger condition.

[0124] In another aspect, providing the logic analyzer circuitry includes providing an interface coupled to the file generation circuitry.

[0125] The description of the inventive configurations provided herein is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed forms and examples. The terms used herein are selected to explain the principles of the inventive configurations, practical applications or technical improvements to the technology found in the market, and / or to enable those skilled in the art to understand the inventive configurations disclosed herein. Modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the inventive configurations described. Accordingly, reference should be made to the following claims, rather than the foregoing disclosure, as indicating the scope of such features and embodiments.

Claims

1. 1. A method for monitoring a signal in an integrated circuit, comprising: monitoring a probed signal of a monitored circuit implemented within said integrated circuit using a logic analyzer circuit also implemented within said integrated circuit; detecting a change in state of the signal being probed using a trace circuit within the logic analyzer circuit, the trace circuit being configured to receive the signal being probed and determine whether a current state of the signal being probed differs from a previous state of the signal being probed; storing only state change data of the probed signals and timestamps of the state change data by a file generation circuit in the logic analyzer circuit coupled to the trace circuit in the integrated circuit, rather than storing values ​​of the probed signals as trace data; generating, by the file generation circuitry, a file specifying state change data of the probe target signal and a timestamp of the state change data as an ASCII encoded file or a value change dump encoded file; The method includes:

2. Outputting the generated file to an external system in substantially real time. The method of claim 1 further comprising: In response to determining that a state change of the probed signal corresponds to a trigger condition, initiating a predetermined action associated with the trigger condition. The method of claim 1 further comprising:

4. Providing the file to a processor within the integrated circuit, the processor being configured to execute program code; or Providing the file to an external system, the external system being configured to generate a visualization of the file. The method of claim 1 further comprising:

5. Generating the file comprises: said file generation circuitry encoding a header section of said file; said file generation circuitry encoding a variable definition section of said file; said file generation circuitry encoding an initial value section of said file; said file generation circuitry encoding a value change section of said file; The method of claim 1 , comprising:

6. The method of claim 1, wherein the logic analyzer circuit is implemented in hardware using programmable circuitry of the integrated circuit.

7. The method of claim 1, wherein the monitored circuit is a user-specified circuit that is at least partially implemented in programmable circuitry of the integrated circuit.

8. a monitored circuit configured to generate a signal; a logic analyzer circuit configured to monitor the signal to detect state changes of the signal, the logic analyzer circuit configured to generate a file specifying time-stamped state changes of the signal; The logic analyzer circuit includes: a trace circuit configured to receive the monitored signal and determine whether a current state of the signal differs from a previous state of the signal; a file generation circuit coupled to the trace circuit, the file generation circuit configured to not store values ​​of the signals as trace data, but to store only state change data of the signals and timestamps of the state changes, and to generate a file specifying the state change data of the signals and the timestamps of the state change data as an ASCII encoded file or a value change dump encoded file; 4. An integrated circuit comprising:

9. The integrated circuit of claim 8, wherein the trace circuit is configured to initiate a predetermined action associated with the trigger condition in response to determining that a state change of the signal corresponds to the trigger condition.

10. The logic analyzer circuit includes: an interface coupled to the file generation circuit 9. The integrated circuit of claim 8, comprising:

11. The integrated circuit of claim 8, further comprising a processor coupled to the logic analyzer circuit, the processor configured to post-process the generated file.

12. The integrated circuit of claim 11, wherein the processor executes program code that performs operations including receiving a request from an external system to start the logic analyzer circuit, starting the logic analyzer circuit in response to the request, and sending the file to a specific address corresponding to the external system.

13. The integrated circuit of claim 11 , wherein the processor executes program code to render a waveform view of the file and output the waveform view of the file on a video output port.

14. 9. The integrated circuit of claim 8, further comprising an input / output circuit coupled to the logic analyzer circuit, the input / output circuit configured to output the file to an external system, the external system generating a waveform view of the signal from the file.

15. The integrated circuit of claim 8 , wherein the logic analyzer circuit is implemented in hardware using programmable circuitry of the integrated circuit.

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