System and method for charging a buffer capacitor - Patents.com

Abstract

To provide a system and a method for charging a buffer capacitor.SOLUTION: A method by a charging system comprises the steps of: monitoring a first voltage across a buffer capacitor; actuating a first current path between a power supply node and the buffer capacitor when the monitored first voltage falls below a first threshold voltage; actuating a second current path between the power supply node and the buffer capacitor when the monitored first voltage falls below a second threshold voltage; and transferring power to a driver circuit coupled to both ends of the buffer capacitor from the buffer capacitor.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention generally relates to a system and method for charging a buffer capacitor. [Background technology]

[0002] AC motors, such as three-phase motors, are becoming increasingly popular in applications such as automotive, industrial, and HVAC (heat, ventilation, and air conditioning) sectors. By replacing the mechanical commutator used in traditional motors with electronic devices, improved reliability, increased durability, and smaller form factors are achieved. Additional advantages of AC motors include improved speed-torque characteristics, faster dynamic response, and higher speed ranges, to name a few. Generally, AC motors (e.g., three-phase motors) have a controller that generates pulse-width modulated (PWM) signals that are used to generate drive signals for power switches coupled to different phases of the motor. These PWM signals can determine the average voltage and average current supplied to the motor's coils, thus controlling the motor's speed and torque.

[0003] The voltage level of the drive signal used to operate the power switch is often higher than the voltage level supplied to the motor control system. For example, a high-side power switch supplying current to a motor from a 12V car battery may require a drive voltage that exceeds the 12V supplied by the car battery. Therefore, in many systems, an additional boost circuit is used to generate the higher voltage level used to operate the power switch. This boost circuit may include, for example, a switch mode power converter, a charge pump, and / or a boost capacitor. However, the use of such a switch mode boost circuit may cause electrical interference that affects the operation of the motor system, particularly or the system in which the motor resides. Summary of the Invention [Means for solving the problem]

[0004] According to one embodiment, the method comprises the following steps: monitoring a first voltage across a buffer capacitor; activating a first current path between the power supply node and the buffer capacitor when the monitored first voltage falls below a first threshold voltage, the first current path providing a first current proportional to a difference between the first threshold voltage and the monitored first voltage, up to a first maximum current; activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage falls below a second threshold voltage, the second current path providing a second current proportional to a difference between the second threshold voltage and the monitored first voltage up to a second maximum current, wherein the first threshold voltage is greater than the second threshold voltage and the first maximum current is less than the second maximum current; transferring power from a buffer capacitor to a driver circuit coupled across the buffer capacitor.

[0005] According to another embodiment, the system includes: a driver circuit having a driver circuit supply node configured to be coupled to a first terminal of a buffer capacitor, a reference node configured to be coupled to a second terminal of the buffer capacitor, and a drive output configured to be coupled to a control node of a switching transistor; a first current path circuit coupled between the power supply node and the driver circuit supply node; a second current path circuit coupled between the power supply node and the driver circuit supply node; and a buffer capacitor monitoring circuit configured to measure a first voltage between the driver circuit supply node and a reference node, activate a first current path circuit and cause the first current path circuit to output a first current proportional to a difference between the first threshold voltage and the first voltage up to a first maximum current when the measured first voltage falls below a first threshold voltage, and activate a second current path circuit and cause the second current path circuit to output a second current proportional to a difference between the second threshold voltage and the first voltage up to a second maximum current when the measured first voltage falls below a second threshold voltage, where the first threshold voltage is greater than the second threshold voltage and the first maximum current is less than the second maximum current.

[0006] According to a further embodiment, the motor system includes: a half-bridge circuit having a high-side transistor and a low-side transistor; a high side driver having an output coupled to a control node of the high side transistor; a low side driver having an output coupled to the control node of the low side transistor; a buffer capacitor having a first terminal coupled to the boosted supply node and to a supply node of the high side driver, and a second terminal coupled to a reference node of the high side driver and to an output node of the half bridge circuit; a first transistor coupled between the power supply node and the boosted supply node and configured to source a first current; a second transistor coupled between the power supply node and the boosted supply node and configured to supply a second current at least ten times greater than the first current; a buffer capacitor monitoring circuit, the buffer capacitor monitoring circuit comprising: measuring a first voltage between the boosted supply node and a reference node; activating the first transistor when the measured first voltage is below a first threshold; measuring a second voltage between the boosted supply node and the reference node; configured to activate the second transistor when the measured first voltage falls below a second threshold, the first threshold being greater than the second threshold; and An analog-to-digital converter is coupled to the half-bridge circuit and configured to digitize a current flowing through the half-bridge circuit.

[0007] The following provides a detailed description of the construction and use of the presently preferred embodiments. It should be understood, however, that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention. [Brief description of the drawings]

[0008] [Figure 1] Schematic diagram of a charging system according to an embodiment. [Diagram 2] Graphs A, B, C, and D show the operation of a charging circuit according to one embodiment. [Diagram 3] 1A and 1B are schematic diagrams of a charging circuit according to one embodiment. [Figure 4] Schematic diagram of a motor control system according to one embodiment. [Diagram 5] Block diagram of the method of one embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the different drawings, corresponding numbers and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly show relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly show a particular embodiment, a figure number may be followed by a letter indicating a variation of the same structure, material, or method step.

[0010] The following provides a detailed description of the construction and use of the presently preferred embodiments. It should be understood, however, that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described herein are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0011] In connection with preferred embodiments in certain contexts, the present invention describes a system and method for charging a buffer capacitor in the context of a motor control circuit, however, the present invention is also applicable to other types of circuits that control the switching state of one or more transistors, including, but not limited to, switched mode power supply systems, power systems, industrial control systems, audio systems, and processing systems.

[0012] According to one embodiment, a charging circuit is used to charge a buffer capacitor of a switch driver with at least two different levels of current, a higher current level and a lower current level. When the buffer capacitor is more discharged, a higher current level is used to charge the buffer capacitor, and when the buffer capacitor is less discharged, a lower current level is used to charge the buffer capacitor. For example, when the voltage across the capacitor is lower than a threshold voltage, the capacitor can be charged with a higher current level, whereas when the voltage across the capacitor is greater than the threshold voltage (but less than the fully charged voltage), the capacitor can be charged with a lower current level. By using a lower current level to charge the buffer capacitor when the buffer capacitor is less discharged, the occurrence of large transient currents can be advantageously reduced or avoided. This reduction or avoidance of such transient currents can also advantageously reduce the occurrence of interference that induces measurement errors.

[0013] FIG. 1 illustrates a switching system 2 according to an embodiment of the present invention. As illustrated, the charging system 2 includes an integrated circuit 10 coupled to a half-bridge driver 15 having a high-side switching transistor 18 and a low-side switching transistor 19. The half-bridge driver 15 is shown coupled to a load 20. The load 20 may represent any type of load, including, but not limited to, a motor, an inductor or transformer in a switched mode power supply, or other type of load. The integrated circuit 10 includes a voltage booster 30, a charging circuit 12, a current measurement circuit 40, a controller 46, a drive circuit 32 configured to drive the high-side switching transistor 18, and a drive circuit 34 configured to drive the low-side switching transistor 19. In some embodiments, the various circuits of the integrated circuit 10 may be located on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or on the same monolithic semiconductor integrated circuit as the other disclosed system components.

[0014] As shown, the driver 32 is a floating gate driver coupled in parallel with a buffer capacitor 36 that serves as a local power supply for the driver 32, whereby one terminal of the buffer capacitor 36 is coupled to a driver circuit supply node of the driver 32 at a boosted supply node BH, and the other terminal of the buffer capacitor 36 is coupled to a reference node of the driver 32 at an output node SH. In operation, the charging circuit 12 charges the buffer capacitor 36 to a predetermined voltage to ensure that the driver 32 has a high enough supply voltage for the turn-on of the high-side transistor 18. The charging circuit 12 includes a low current path circuit 26 (also referred to as a "first current path circuit"), an amplifier 22 that controls the low current path circuit 26, a high current path circuit 28 (also referred to as a "second current path circuit"), and an amplifier 24 that controls the high current path circuit 28. The amplifiers 22 and 24 may collectively be referred to as a buffer capacitor monitoring circuit. Diode D1 may be coupled between boosted supply node BH and the outputs of low and high current pass circuits 26, 28 to prevent discharge of the buffer capacitor through charging circuit 12. In alternative embodiments, additional current pass circuits (with additional corresponding control amplifiers) may be coupled in parallel with low and high current pass circuits 26, 28 to provide a finer relationship between the voltage across buffer capacitor 36 and the amount of current provided by charging circuit 12.

[0015] In operation, amplifier 22 regulates the voltage across buffer capacitor 36 (also referred to as the “first voltage”) relative to a first threshold voltage V T1 , and the current of the low current path circuit 26 is compared with the first voltage and the first threshold voltage V T1 Similarly, amplifier 24 controls the voltage across buffer capacitor 36 according to the difference between a second threshold voltage V T2 , and the current of the high current path circuit 28 is compared with the first voltage and the second threshold voltage V T2In various embodiments, the current provided by the high current path circuit 28 is greater than the current provided by the low current path circuit 26 and is controlled according to the difference between the first threshold voltage V T1 is the second threshold voltage V T2 For example, in one embodiment, the current provided by the high current pass circuit 28 is between about 100 mA and about 350 mA, the current provided by the low current pass circuit 26 is between about 10 mA and about 35 mA, and the first threshold voltage V T1 is about 10V, and the second threshold voltage V T2 is approximately 9V. However, other threshold voltages may be used depending on the particular embodiment and its specifications. In some embodiments, the current provided by the high current path circuit 28 is approximately 10 times greater than the current provided by the low current path circuit 26. However, in other embodiments, the current provided by the high current path circuit 28 is greater than the current provided by the low current path circuit 26, but less than 10 times.

[0016] In various embodiments, the capacitance of the buffer capacitor 36 is set so that the current provided by the low-current pass circuit 26 is sufficient to prevent the voltage VCAP across the buffer 36 from exceeding the first threshold voltage V under nominal operating conditions. T1 The low current path circuit 26 is set to be sufficient to ensure that the current is greater than 1 LSB. By using the relatively low current of the low current path circuit 26 to maintain charge on the buffer capacitor 36, the occurrence of power disturbances seen across the power input side of the driver circuit 32 is significantly reduced compared to systems that utilize uncontrolled buffer capacitor charging and / or where the buffer capacitor is subject to high inrush currents. In such systems, such high inrush currents can cause transient currents in the half-bridge driver. These transient currents can lead to current measurement errors and affect the performance of the driver circuit. In some embodiments of the present invention, the use of the low current path circuit 26 under nominal operating conditions can keep the magnitude of such disturbance currents below one least significant bit (LSB), as measured by the analog-to-digital converter 42 and the current measurement circuit 40 described below.

[0017] However, in non-nominal or emergency operating conditions, the higher current provided by the high current pass circuit 28 may be used to quickly recharge the buffer capacitor 36. For example, in a situation where the charging system 2 is exposed to strong electromagnetic interference (EMI), electrostatic discharge (ESD), or other transient conditions, the voltage VCAP across the buffer capacitor 36 may drop below the second threshold voltage V T2 , in which case the high current pass circuit 28 is activated to quickly recharge the buffer capacitor 36. Maintaining the voltage VCAP across the buffer capacitor 36 at a sufficiently high voltage prevents the high-side transistor 18 from operating in a dangerous operating region where it could damage or destroy itself. In such a non-nominal or emergency situation, the inrush current caused by the fast charging of the buffer capacitor 36 can exceed the half-bridge driver current I HB In some cases, electromagnetic interference can cause larger disturbances in the system than the smaller disturbances seen during nominal operating conditions. In such a situation, one or more current measurements made at the time of the electromagnetic interference event may be discarded and an error notification may be sent to an external system controller (not shown) to aid in order to recover from the non-nominal or emergency system condition.

[0018] In any case, use of this embodiment of charging circuit 12 may assist charging system 2 in maintaining compliance with various electromagnetic compatibility standards, such as International Organization for Standardization (ISO) standard 7637 directed to electromagnetic compatibility for land vehicles having 12 volt and 24 volt electrical systems. This standard, as well as other standards directed to various types of systems, defines various electromagnetic waveforms and pulses that compliant systems are required to withstand.

[0019] In various embodiments, the boost circuit 30 is configured to step up or increase the voltage of the input voltage VBAT to a higher voltage at the power supply node HSS. For example, in one embodiment, the input voltage VBAT is configured to have a voltage of about 12V while the power supply node HSS is configured to have a voltage of about 24V, although other voltages may be used for the input voltage VBAT and the power supply node HSS depending on the particular embodiment and its specifications. In some embodiments, such as those directed to automotive applications, the input voltage VBAT may be a battery voltage or a voltage derived from a battery voltage. In alternative embodiments, the input voltage VBAT may be coupled to other power sources. The boost circuit 30 may be implemented using a charge pump, a switched mode power supply circuit, or other boost circuits known in the art. In embodiments utilizing a switched mode power supply circuit for the boost circuit 30, various switched mode power supply architectures known in the art may be used, such as a boost converter.

[0020] In some embodiments, the current I flowing through the half bridge 15 HB may be determined by measuring the voltage across shunt resistor 38 with current measurement circuit 40. In some embodiments, current measurement circuit 40 may include an analog-to-digital converter 42 and an amplifier 44. The analog-to-digital converter 42 may be implemented using a variety of analog-to-digital converter architectures, such as a sigma-delta analog-to-digital converter, a successive approximation analog-to-digital converter, a flash analog-to-digital converter, or any other suitable analog-to-digital converter architecture known in the art. However, in some embodiments, amplifier 44 may be omitted. In operation, amplifier 44 amplifies the voltage across resistor 38, and analog-to-digital converter 42 converts the analog output of amplifier 44 to the digital domain.

[0021] The output of the analog-to-digital converter 42 may be used by the controller 46 as a feedback signal to control the switching signals DH and DL. For example, the current I HB Measurement of current I may be used to determine when to activate and / or deactivate high-side transistor 18 and / or low-side transistor 19 according to switch control methods known in the art. HB Measurement of the half-bridge current I as measured by analog-to-digital converter 42 may be used to implement overvoltage and overcurrent protection schemes according to methods known in the art. As mentioned above, in various embodiments, the half-bridge current I as measured by analog-to-digital converter 42 may be used to implement overvoltage and overcurrent protection schemes according to methods known in the art. HB The amount of disturbance current to the analog-to-digital converter 42 may be kept below 1 LSB. By maintaining this disturbance level below 1 LSB, high measurement accuracy may be maintained during operation within the charging system 2. In such an embodiment, the buffer capacitor 36 may be periodically recharged in a manner that is asynchronous to the sampling of the analog-to-digital converter 42, independent of the drive signal, without compromising measurement accuracy. In an alternative embodiment of the present invention, the charging system 2 may be configured such that the amount of disturbance caused by the recharging of the buffer capacitor 36 during nominal operation may cause a disturbance of more than 1 LSB as measured by the analog-to-digital converter 42, while still providing performance that meets system requirements.

[0022] In alternative embodiments of the present invention, the current measurement circuit 40 may be omitted depending on the particular embodiment and its specifications. HB For embodiments in which the current I is not measured, resistor 38 shown in half bridge circuit 15 may also be omitted. HBmay be measured in ways other than measuring the voltage across resistor 38. For example, in some embodiments, one or both of high side transistor 18 or low side transistor 19 may include a replica current measurement transistor that provides a scaled version of the current flowing through one or both of high side transistor 18 or low side transistor 19.

[0023] The driver circuit 32 includes a drive input DH and a drive output GH coupled to the gate (also referred to as a "control node") of the high-side switching transistor 18. Similarly, the driver circuit 34 includes a drive input 34DL and a drive output GL coupled to the gate of the low-side switching transistor 19. In operation, the driver circuit 32 generates a first drive output signal at the drive output GH based on a first drive input signal at the drive input DH. The first drive output signal can be configured to change the state of the high-side switching transistor 18 (e.g., turn on / off the high-side switching transistor 18). Similarly, the driver circuit 34 includes a drive input DL and a drive output GL coupled to the gate of the low-side switching transistor 19. In operation, the driver circuit 34 generates a second drive output signal at the drive output GL based on a second drive input signal at the drive input DL. The second drive output signal can be configured to change the state of the low-side switching transistor 19 (e.g., turn on / off the low-side switching transistor 19).

[0024] In one example, when the drive signal DH is asserted (either active high or active low), the drive circuit 32 increases the voltage of the drive signal GH so that the high-side switching transistor 18 is turned on. When the high-side switching transistor 18 is turned on, current is provided to the load 20 and the output node SH through the source of the high-side switching transistor 18. When DH is deasserted, the drive circuit 32 decreases the voltage of the drive signal GH so that the high-side switching transistor 18 is turned off. Similarly, when the drive signal DL is asserted (either active high or active low), the drive circuit 34 increases the voltage of the drive signal GL so that the low-side switching transistor 19 is turned on. When the low-side switching transistor 19 is turned on, current is drawn from the load 20 and the output node SH through the drain of the low-side switching transistor 19. When the drive signal DL is deasserted, the drive circuit 34 decreases the voltage of the drive signal GL so that the low-side switching transistor 19 is turned off. In embodiments utilizing p-type channel or PNP devices, the various drive signals reduce the voltage to turn on the switching transistors and increase the voltage to turn off the switching transistors.

[0025] In some embodiments, the drive signals DH and DL are asserted alternately such that only one of the high side switching transistor 18 and the low side switching transistor 19 is activated at a particular time. Generation of the drive signals DH and DL may be performed using the controller 46 as shown, or may be generated external to the integrated circuit 10. Such drive signal generation circuits may include, but are not limited to, pulse width modulation circuits, pulse frequency modulation circuits, non-overlapping signal generation circuits, and other circuits known in the art configured to generate drive signals. The driver circuits 32 and 34 may be implemented using switching transistor drivers known in the art, and the drive signals GH and GL may be adapted to the particular transistor technology used to implement the high side switching transistor 18 and the low side switching transistor 19.

[0026] In various embodiments, the high-side switching transistor 18 and the low-side switching transistor 19 may be realized with transistors, such as, for example, IGBT transistors, MOS transistors (NMOS and / or PMOS), bipolar transistors, or other types of transistors. In some embodiments, the high-side switching transistor 18 and the low-side switching transistor 19 may be power IGBTs, power MOSFETs, or power bipolar transistors to support high current and high power applications. In some embodiments, the high-side switching transistor 18 and the low-side switching transistor 19 may operate as switching transistors used in a switched mode power supply or used to drive a motor. In some embodiments, the charging system 2 may be adapted to support driving a single switching transistor. For example, the drive circuit 34 and the low-side switching transistor 19 may be omitted.

[0027] Driver circuits 32 and 34 may be implemented using drive circuit architectures known in the art and may include auxiliary and support circuitry such as buffers, level shifters, isolators, and circuitry as described in more detail in connection with the embodiments herein. As shown, driver circuit 32 is a floating driver powered by a buffer capacitor 36 using a floating high side drive circuit known in the art. As mentioned above, buffer capacitor 36 is configured to provide a booster capacitor 36 with a floating high side drive circuit such that the voltage across booster capacitor 36 is at least a threshold voltage V, which may be approximately 10V in some embodiments, although other voltages may be used. T1 Thus, during nominal operation, the voltage at the boosted supply node BH is typically at least 10V higher than the voltage at the output node SH. Thus, when the high side switching transistor 18 is deactivated, the low side switching transistor 19 is activated, and the voltage at the output node SH is approximately ground, the voltage at the boosted supply node BH will be at least 10V. When the high side switching transistor 18 is activated, the low side switching transistor 19 is deactivated, and the voltage at the output node SH is approximately the voltage of the input voltage VBAT, the voltage at the boosted supply node BH will be at least 24V (e.g., 12V battery voltage plus the first threshold voltage V of 12V). T1 ). The use of a floating driver ensures that there is sufficient gate drive voltage to keep high side switching transistor 18 turned on when drive signal DH is asserted. It should be understood that the specific voltages referred to herein are merely examples of voltages for a particular embodiment, and that specific operating voltages may vary depending on the details of a particular embodiment and its specifications.

[0028] FIG. 2A illustrates the currents I generated by the low current path circuit 26 and the high current path circuit 28, respectively, with respect to the voltage VCAP across the buffer capacitor 36. C1 and I C2 3 shows a graph illustrating the relationship between the first current I generated by the low current path circuit 26. C1, and trace 64 represents a second current I generated by high current path circuit 28. C2 As shown with respect to trace 62, the voltage VCAP across the buffer capacitor 36 decreases relative to the first threshold voltage V T1 When the voltage VCAP exceeds the first threshold voltage V, the current generated by the low current path circuit 26 becomes approximately zero. T1 When the voltage VCAP falls below 1 V, the low current path circuit 26 generates a current inversely proportional to the voltage VCAP according to a first slope SLOPE1. C1 is the first maximum current I C1_MAX When the voltage VCAP reaches the voltage V T3 When the first maximum current I C1_MAX Similarly, when the voltage VCAP is equal to the second threshold voltage V T2 If the voltage VCAP falls below VCAP, the high current path circuit 28 flows a current I C2 (represented by trace 64). C2 is the second maximum current I C2_MAX When the voltage VCAP reaches the voltage V T4 ), the high current path circuit 28 provides a second maximum current I C2_MAX In various embodiments, the first maximum current I C1_MAX is the second maximum current I C2_MAX In one embodiment, the first maximum current I C1_MAX is about 20mA, and the second maximum current I C2_MAX is about 200mA, and the first threshold V T1 is about 10V, and the second threshold V T2 The first current I is about 9V, but other maximum currents and thresholds may be used depending on the embodiment and its specifications. C1 The slope of SLOPE1 and the second current I C2The slope SLOPE2 of the first current I may be the same or different depending on the particular embodiment and its specifications. In some embodiments, such as those using a comparator and / or those in which the first current path circuit 26 and the second current path circuit 28 are not gradually turned on and off, the slope SLOPE2 of the first current I C1 The slope of SLOPE1 and the second current I C2 The slope SLOPE2 of the first threshold voltage V T1 and / or a second threshold voltage V T2 can be applied to.

[0029] FIG. 2B illustrates the output current I of the charging circuit 12 with respect to the voltage V across the buffer capacitor 36. CHG 6 shows a graph illustrating the relationship between the output current I CHG are the currents I generated by the low current path circuit 26 and the high current path circuit 28, respectively, shown in FIG. C1 and I C2 As shown, the voltage VCAP across the buffer capacitor 36 is the sum of the first threshold voltage V T1 When the voltage VCAP exceeds the first threshold voltage V, the current generated by the low current path circuit 26 becomes approximately zero. T1 When the voltage VCAP falls below the voltage V, the charging circuit 12 generates a current inversely proportional to the voltage VCAP according to a first slope SLOPE1, and the voltage VCAP falls below the voltage V T3 When the current I CHG plateaus at a current I1, which is the first maximum current I shown in FIG. 1A. C1_MAX The voltage VCAP corresponds to the second threshold voltage V T2 If the voltage VCAP falls below the voltage V, the charging circuit 12 generates a current inversely proportional to the voltage VCAP according to a second slope SLOPE2. T4 When the current I CHG plateaus at a current I2, which is the second maximum current I2 shown in Figure 1A. C2_MAX Corresponds to.

[0030] In some embodiments, the current I CHG The actual value of varies depending on the temperature, operating conditions, and the first threshold voltage V T1 and a second threshold voltage V T2 In some embodiments, this variation may be maintained within the boundaries of a tolerance mask represented by lines 68 and 70 in FIG. 2B. For example, if voltage VCAP is lower than voltage VT4, then current I CHG may be between about 100 mA and about 350 mA. T4 and the first threshold voltage V T1 For voltages VCAP between 0 and 1, the allowable current within the boundaries of the tolerance mask is reduced accordingly. CHG It should be understood that the relationships and tolerance mask boundaries shown in Figure 2B are merely one example of many possible implementations. In alternative embodiments of the invention, the current values, threshold voltages, and tolerance mask values ​​may vary depending on the particular embodiment and its specifications.

[0031] As shown in FIG. 2C, in some embodiment implementations of the charging circuit 12, the first current I C1 The relationship between the voltage V and the voltage V across the buffer capacitor 36 is T3 may not be completely flat for values ​​of VCAP below C2 The relationship between the voltage V and the voltage V across the buffer capacitor 36 is T4 The VCAP voltage may not be completely flat for values ​​of VCAP below V. T3 When the first current I C1 (represented by trace 72) has a slope SLOPE3 and the voltage VCAP rises to the voltage V T4 When the second current I C2 2A, except that the first current I (represented by trace 74) has a slope SLOPE4. In various embodiments, the first current I C1 and the second current I C2The continued rise in is due to finite impedance in the particular implementation of the charging circuit 12. The first current I shown in FIG. C1 , the second current I C2 It should be understood that the relationship between the first current I and the voltage V of the buffer capacitor 36 is merely one of many example relationships. C1 and the second current I C2 may have a relationship different from the linear relationship represented by the straight lines of traces 72 and 74. In such an embodiment, the first current I C1 , the second current I C2 , and the voltage VCAP of the buffer capacitor 36 may have a higher order (eg, more “curved”) relationship, and in some cases may even be non-monotonic.

[0032] FIG. 2D illustrates the first current I C1 and the second current I C2 The output current I of the charging circuit 12 with respect to the voltage VCAP across the buffer capacitor 36 according to the current characteristic of CHG 2B shows a graph illustrating the relationship between the output current I CHG remains within the tolerance mask represented by lines 68 and 70.

[0033] FIG. 3A shows a schematic diagram of the charging circuit 12 that can be used to realize the charging circuit 12 shown in FIG. 1. In one embodiment, the low current path circuit 26 is realized using a PMOS transistor MOUT1 having a load path coupled between the power supply node HSS and the driver circuit supply node, and the high current path circuit 28 is realized using a PMOS transistor MOUT2 coupled between the power supply node HSS and the driver circuit supply node. The PMOS transistor MOUT1 has an aspect ratio m, and the PMOS transistor MOUT2 has an aspect ratio n, where n is greater than m (e.g., the PMOS transistor MOUT2 is larger than the PMOS transistor MOUT1 to supply a higher current). The diode D1 prevents the buffer capacitor 36 from discharging through the PMOS transistor MOUT1 or the PMOS transistor MOUT2. The function of the amplifier 22 shown in FIG. 1 is realized using a first reference current generator 102, a first voltage-to-current converter 104, and a first limiting amplifier 106. 1 is realized using a second reference current generator 108, a second voltage-to-current converter 110, and a second limiting amplifier 112. Resistors RZ1 and RZ2 represent finite resistances at the outputs of the first voltage-to-current converter 104 and the second voltage-to-current converter 110, respectively.

[0034] In operation, the first voltage-to-current converter 104 converts the voltage VCAP across the buffer capacitor 36 (coupled between the boosted supply node BH and the output node SH) into a first measured current I VI1 This current is converted into the current I generated by the first reference current generator 102. REF1 and this summed current is applied to resistor RZ1 to generate an input voltage VIN1 for the first limiting amplifier 106. This input voltage VIN1 is coupled to a voltage V DR1 Similarly, a second voltage-to-current converter 110 converts the voltage VCAP across the buffer capacitor 36 into a second measured current I VI2This current is converted into the current I generated by the second reference current generator 108. REF2 and this summed current is applied to resistor RZ2 to generate an input voltage VIN2 for the second limiting amplifier 112. This input voltage VIN2 is coupled to a voltage V DR2 In various embodiments, the first threshold voltage V T1 is the reference current I REF1 and can be set via the selection of the transconductance of the first voltage / current converter 104. The output current I C1 The magnitude of the PMOS transistor output current I can be set by selecting the size of the PMOS transistor MOUT1 as well as the output voltage limit of the first limiting amplifier 106. Similarly, the magnitude of the PMOS transistor output current I C2 The magnitude of can be set by selecting the size of PMOS transistor MOUT2 as well as the output voltage limit of second limiting amplifier 112. In some embodiments, the effective sizes of PMOS transistors MOUT1 and MOUT2, the gains and limits of first limiting amplifier 106 and second limiting amplifier 112, the transconductances of first voltage-to-current converter 104 and second voltage-to-current converter 110, and the reference current I generated by first reference current generator 102 and second reference current generator 108 can be set by selecting the size of PMOS transistor MOUT2 as well as the output voltage limit of second limiting amplifier 112. In some embodiments, the effective sizes of PMOS transistors MOUT1 and MOUT2, the gains and limits of first limiting amplifier 106 and second limiting amplifier 112, the transconductances of first voltage-to-current converter 104 and second voltage-to-current converter 110, and the reference current I REF1 and I REF2 may be programmable.

[0035] FIG. 3B shows a schematic diagram of a transistor level circuit that can be used to realize the charging circuit 12 shown in FIG. 1 and FIG. 3A. As shown, the first voltage / current converter 104 is realized using an NMOS transistor M1 and a resistor R1 coupled to the source of the NMOS transistor M1. The first reference current generator 102 is realized using a current source, and the first limiting amplifier is realized using a PMOS transistor M3, a current source 122, and a Zener diode D5. An optional diode D3 can be coupled between the first reference current generator 102 and the first voltage / current converter 104. Similarly, the second voltage / current converter 110 is realized using an NMOS transistor M2 and a resistor R2 coupled to the source of the NMOS transistor M2. The second reference current generator 108 is realized using a current source, and the second limiting amplifier 112 is realized using a PMOS transistor M4, a current source 124, and a Zener diode D4. An optional diode D2 may be coupled between the second reference current generator 108 and the second voltage-to-current converter 110.

[0036] The first voltage-to-current converter 104 is configured such that the transistor M1 has a high aspect ratio and the voltage VCAP across the buffer capacitor 36 is equal to the threshold voltage V of the NMOS transistor M1. TM1 and the second voltage-to-current converter 110 has a transconductance of approximately 1 / R2 when the transistor M2 has a high aspect ratio and the voltage VCAP across the buffer capacitor 36 exceeds the threshold voltage VTM2 of the NMOS transistor M2. REF1 (V REF +V OFF ) / R, and the second current I REF2 is V REF / R. However, V REF represents the reference voltage, and V OFF represents the offset voltage, and R represents the resistance of the reference resistor.

[0037] In some embodiments, (V REF +V OFF ) / R and V REF A reference current proportional to R / R is generated by applying a voltage (or a scaled voltage) generated by a bandgap voltage reference circuit to one or more reference resistors (not shown) having a value proportional to R, which generate the reference current using bias generation circuits and methods known in the art. These reference currents are mirrored to the first reference current generator 102 and the second reference current generator 108, for example, using current mirror circuits (not shown) known in the art. In various embodiments, the reference resistors used in the bias generators use the same material (e.g., polysilicon, diffusion, etc.) as the resistors R1 and R2 of the first and second voltage-to-current converters 104 and 110, such that the ratios of R / R1 and R / R2 are substantially constant over semiconductor process and temperature. In one embodiment, the first and second threshold voltages V T1 and V T2 can be expressed as follows: V T1 =(V REF +V OFF )×(R2 / R)+V TM1 and V T2 =V REF ×(R2 / R)+V TM1

[0038] In operation, the PMOS transistor M3 loaded by the current source 122 of the first limiting amplifier 106 is coupled to a voltage V DR1 A Zener diode D5 amplifies the input voltage VIN1 to generate the output voltage V of the first limiting amplifier in order to effectively limit the amount of current output by the PMOS transistor MOUT1. DR1 Similarly, the PMOS transistor M4 loaded by the current source 124 of the second limiting amplifier 112 limits / clamps the voltage V DR2A Zener diode D4 amplifies the input voltage VIN2 to generate the output voltage V of the second limiting amplifier in order to effectively limit the amount of current output by the PMOS transistor MOUT2. DR2 to its own Zener voltage.

[0039] It should be understood that the example embodiment of the charging circuit 12 shown and described above in connection with Figures 3A and 3B is only a specific example of many possible embodiments of the charging circuit. In alternative embodiments, other transistor types, such as NMOS transistors, NPN or PNP BJT transistors, JFETs, and other transistor types known in the art, can be used in place of the PMOS transistors for MOUT1 and MOUT2. The first and second voltage-to-current converters 104 and 110 can be implemented using other voltage-to-current converter circuits and systems, and the first and second limiting amplifiers 106 and 112 can be implemented using other limiting amplifier circuits and systems known in the art. Additionally, the clamping function of the Zener diodes D4 and D5 described above can be implemented using other clamping circuits and systems known in the art. For example, in some embodiments, a transistor-based clamping circuit may be used.

[0040] FIG. 4 illustrates a motor system 200 including an integrated circuit 202 coupled to a three-phase motor 216 via three half-bridge driver circuits 15. In some embodiments, the three-phase motor 216 may be used in an automotive system. In one example, the three-phase motor is a motor used for power steering. The integrated circuit 202 is similar in structure and operation to the integrated circuit 10 illustrated in FIG. 1, except that three parallel half-bridge driver channels are implemented instead of a single channel. For example, the control logic 204 is configured to provide three channels of input drive signals represented by signals DHx and DLx. Three level shifters 206, three high-side drivers 32, and three low-side drivers 34 are provided to assist in driving and actuating each of the three half-bridge drivers 15 via drive outputs GHx and GLx. Thus, in some embodiments, the charging circuits 12 of the three embodiments are configured to charge three buffer capacitors 36 to power three corresponding driver circuits 32 according to the embodiments described herein. In various embodiments, the three current measurement circuits 40 are configured to measure the current of each half-bridge driver by measuring the voltage across the shunt resistor 38 of the half-bridge driver 15 at node SLx.

[0041] In various embodiments, the control logic 204 is configured to generate three-phase input drive signals DHx and DLx configured to drive the three-phase motor 216 according to three-phase motor drive methods known in the art. In some embodiments, each phase of these input drive signals DHx and DLx is configured to provide a three-phase pulse width modulated signal that provides motor drive signals that are phase shifted from each other by approximately 120 degrees. In some embodiments, each pulse width modulated signal includes multiple pulse cycles whose pulse widths and / or pulse densities increase and decrease over a single motor drive cycle. The peak pulse width of each channel is shifted by 120 degrees relative to the other channels. In other embodiments, each pulse width modulated signal includes a single pulse cycle for a single motor drive cycle. In such embodiments, each single pulse cycle of each channel is shifted by 120 degrees relative to the other channels.

[0042] The digital interface 212 is shown coupled to a digital bus DBUS having n signal pins and can be used to control, configure and monitor the operation of the integrated circuit 202. In various embodiments, this digital interface 212 may be a serial bus interface circuit, a parallel bus interface circuit and / or may conform to any bus standard including, but not limited to, SPI, CAN, I2C, LVDS, USB. Thus, the number n of signal pins of the digital bus DBUS may be any number suitable for the implemented bus protocol. In some embodiments, various operating parameters of the integrated circuit 202 may be received from the digital bus DBUS via the digital interface 212 and transferred to registers in the control logic 204 to control the generation of the drive signals DH and DL.

[0043] Figure 5 shows a block diagram of a method 300 of one embodiment. In step 302, a first voltage, such as the voltage VCAP across the buffer capacitor 36 shown in Figures 1, 3A, 3B, and 4, is monitored across the buffer capacitor. In some embodiments, the first voltage is monitored using an amplifier, such as the amplifiers 22 and 24 or the voltage-to-current converters 104 and 110 shown in Figures 3A and 3B. In other embodiments, the first voltage can be monitored using a comparator circuit.

[0044] In step 304, a first current path is activated between the power supply node and the buffer capacitor when the monitored first voltage falls below a first threshold voltage. In some embodiments, the first current path can be implemented using the low current path circuit 26 shown in FIG. 1 and / or the PMOS transistor MOUT1 shown in FIG. 3A and 3B. In various embodiments, the first current path provides a first current proportional to the difference between the first threshold voltage and the monitored first voltage, up to a first maximum current.

[0045] In step 306, a second current path is activated between the power supply node and the buffer capacitor when the monitored first voltage falls below a second threshold voltage. In some embodiments, the second current path can be implemented using the high current path circuit 28 shown in FIG. 1 and / or the PMOS transistor MOUT2 shown in FIGS. 3A and 3B. In various embodiments, the second current path provides a second current proportional to the difference between the second threshold voltage and the monitored first voltage up to a second maximum current, where the first threshold voltage is greater than the second threshold voltage and the first maximum current is less than the second maximum current. In step 308, power is transferred from the buffer capacitor to a driver circuit coupled across the buffer capacitor. In various embodiments, the driver circuit can be implemented using a driver 32, which can be, for example, a high-side driver.

[0046] Embodiments of the present invention are summarized herein, and other embodiments may be understood from the entirety of this specification and the claims appended hereto.

[0047] Example 1. The method includes the following steps: monitoring a first voltage across a buffer capacitor; activating a first current path between a power supply node and the buffer capacitor when the monitored first voltage falls below a first threshold voltage, the first current path providing a first current proportional to a difference between the first threshold voltage and the monitored first voltage up to a first maximum current; activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage falls below a second threshold voltage, the second current path providing a second current proportional to a difference between the second threshold voltage and the monitored first voltage up to a second maximum current, wherein the first threshold voltage is greater than the second threshold voltage and the first maximum current is less than the second maximum current; and transferring power from the buffer capacitor to a driver circuit coupled across the buffer capacitor.

[0048] Example 2. The method of example 1 further includes driving the control nodes of the switching transistors of the half-bridge circuit with a driver circuit.

[0049] Example 3. The method of example 2 further includes driving the motor with a half-bridge circuit.

[0050] Example 4. The method of example 2 or 3 further includes measuring a current in the half-bridge circuit.

[0051] Example 5. The method of example 4, wherein the step of measuring a current in the half-bridge circuit includes using an analog-to-digital converter, and the first current corresponds to a magnitude less than a least significant bit of the analog-to-digital converter.

[0052] Example 6. The method of any one of Examples 1 to 5, wherein monitoring the first voltage includes converting the first voltage to a first measured current, comparing the first measured current to a first reference current, converting the first voltage to a second measured current, and comparing the second measured current to the second reference current.

[0053] Example 7. The method of Example 6, wherein activating the first current path includes turning on a first transistor coupled between the power supply node and the buffer capacitor when the first measured current is less than the second measured current, and activating the second current path includes turning on a second transistor coupled between the power supply node and the buffer capacitor when the second measured current is less than the second measured current, wherein the second transistor is greater than the first transistor.

[0054] Example 8. The method of any one of Examples 1 to 7, wherein the second current is at least 10 times greater than the first current.

[0055] Example 9. The system includes: The present invention relates to a driver circuit having a driver circuit supply node configured to be coupled to a first terminal of a buffer capacitor, a reference node configured to be coupled to a second terminal of the buffer capacitor, and a drive output configured to be coupled to a control node of a switching transistor, a first current path circuit coupled between a power supply node and the driver circuit supply node, a second current path circuit coupled between the power supply node and the driver circuit supply node, and a buffer capacitor monitoring circuit, the buffer capacitor monitoring circuit detecting a first voltage between the driver circuit supply node and the reference node. and when the measured first voltage falls below a first threshold voltage, actuating a first current path circuit and causing the first current path circuit to output a first current proportional to a difference between the first threshold voltage and the first voltage up to a first maximum current, and when the measured first voltage falls below a second threshold voltage, actuating a second current path circuit and causing the second current path circuit to output a second current proportional to a difference between the second threshold voltage and the first voltage up to a second maximum current, where the first threshold voltage is greater than the second threshold voltage and the first maximum current is less than the second maximum current.

[0056] Example 10 The system of example 9, wherein the switching transistor is a high side transistor of a half bridge circuit, and the reference node is further configured to be coupled to an output node of the high side transistor.

[0057] Example 11 The system of Example 9 or 10 further includes a buffer capacitor and a half-bridge circuit.

[0058] Example 12. The system of any one of Examples 9 to 11 further includes a motor coupled to an output side of the half-bridge circuit.

[0059] Example 13. The system of any one of Examples 9 to 12 further includes a current measurement circuit having an analog-to-digital converter, where the current measurement circuit is configured to be coupled to the half-bridge circuit, the current measurement circuit is configured to measure a current of the half-bridge circuit using the analog-to-digital converter, and the first current corresponds to a magnitude smaller than a least significant bit of the analog-to-digital converter.

[0060] Example 14. The method of any one of Examples 9 to 13, wherein the buffer capacitor monitoring circuit includes a first voltage-to-current converter coupled between the driver circuit supply node and the reference node, a first reference current generator coupled to the first voltage-to-current converter and to the first current path circuit, a second voltage-to-current converter coupled between the driver circuit supply node and the reference node, and a second reference current generator coupled to the second voltage-to-current converter and to the second current path circuit.

[0061] Example 15. The system of example 14, wherein the first current path circuit includes a first transistor having a load path coupled between the power supply node and the driver circuit supply node and a control node coupled to the first voltage to current converter; The second current path circuit includes a second transistor having a load path coupled between the power supply node and the driver circuit supply node and a control node coupled to the second voltage-to-current converter, where the second transistor is larger than the first transistor.

[0062] Example 16 The method of any one of Examples 9 to 15, wherein the second current is at least 10 times greater than the first current.

[0063] Example 17. The method of any one of examples 9 to 16, wherein the driver circuit, the first current path circuit, the second current path circuit, and the buffer capacitor monitoring circuit are disposed on a single semiconductor substrate.

[0064] Example 18. The motor system includes: a half-bridge circuit having a high-side transistor and a low-side transistor; a high side driver having an output coupled to a control node of the high side transistor; a low side driver having an output coupled to the control node of the low side transistor; a buffer capacitor having a first terminal coupled to the boosted supply node and to a supply node of the high side driver, and a second terminal coupled to a reference node of the high side driver and to an output node of the half bridge circuit; a first transistor coupled between the power supply node and the boosted supply node and configured to source a first current; a second transistor coupled between the power supply node and the boosted supply node and configured to supply a second current at least ten times greater than the first current; a buffer capacitor monitoring circuit, the buffer capacitor monitoring circuit comprising: measuring a first voltage between the boosted supply node and a reference node; activating the first transistor when the measured first voltage is below a first threshold; measuring a second voltage between the boosted supply node and the reference node; configured to activate the second transistor when the measured first voltage falls below a second threshold, the first threshold being greater than the second threshold; and An analog-to-digital converter is coupled to the half-bridge circuit and configured to digitize a current flowing through the half-bridge circuit.

[0065] Example 19. The motor system of Example 18 further includes a motor coupled to the output node of the half-bridge circuit.

[0066] Example 20. The motor system of example 18 or 19, wherein the high side transistor and the low side transistor each comprise a MOSFET.

[0067] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method, comprising: monitoring a first voltage across a buffer capacitor; activating a first current path between a power supply node and the buffer capacitor when the monitored first voltage falls below a first threshold voltage, the first current path providing a first current proportional to a difference between the first threshold voltage and the monitored first voltage, up to a first maximum current; activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage falls below a second threshold voltage, the second current path providing a second current proportional to a difference between the second threshold voltage and the monitored first voltage up to a second maximum current, the first threshold voltage being greater than the second threshold voltage and the first maximum current being less than the second maximum current; transferring power from the buffer capacitor to a driver circuit coupled across the buffer capacitor; The method includes:

2. The method further includes driving control nodes of switching transistors of the half-bridge circuit with a driver circuit. The method of claim 1.

3. The method further includes driving a motor with the half-bridge circuit. The method of claim 2.

4. The method further comprises measuring a current in the half-bridge circuit. The method of claim 2.

5. the step of measuring a current in the half-bridge circuit includes using an analog-to-digital converter, the first current corresponding to a magnitude less than a least significant bit of the analog-to-digital converter. The method of claim 4.

6. The step of monitoring the first voltage includes: converting the first voltage into a first measured current; comparing the first measured current to a first reference current; converting the first voltage into a second measured current; comparing the second measured current to a second reference current; Including, The method of claim 1.

7. activating the first current path includes turning on a first transistor coupled between the power supply node and the buffer capacitor when the first measured current is less than the first reference current; activating the second current path includes turning on a second transistor coupled between the power supply node and the buffer capacitor when the second measured current is less than the second reference current, the second transistor being larger than the first transistor; The method of claim 6.

8. the second current is at least 10 times greater than the first current; The method of claim 1.

9. 1. A system comprising: a driver circuit having a driver circuit supply node configured to be coupled to a first terminal of a buffer capacitor, a reference node configured to be coupled to a second terminal of the buffer capacitor, and a drive output configured to be coupled to a control node of a switching transistor; a first current path circuit coupled between a power supply node and the driver circuit supply node; a second current path circuit coupled between the power supply node and the driver circuit supply node; a buffer capacitor monitoring circuit; Including, The buffer capacitor monitoring circuit includes: measuring a first voltage between the driver circuit supply node and the reference node; activate the first current path circuit when the measured first voltage falls below a first threshold voltage, causing the first current path circuit to output a first current proportional to a difference between the first threshold voltage and the first voltage up to a first maximum current; and configured to activate the second current path circuit when the measured first voltage falls below a second threshold voltage, causing the second current path circuit to output a second current proportional to a difference between the second threshold voltage and the first voltage up to a second maximum current, the first threshold voltage being greater than the second threshold voltage and the first maximum current being less than the second maximum current. system.

10. the switching transistor being a high-side transistor of a half-bridge circuit, and the reference node being further configured to be coupled to an output node of the high-side transistor.

10. The system of claim 9.

11. The system further includes a buffer capacitor and a half bridge circuit. The system of claim 10.

12. The system further includes a motor coupled to an output of the half bridge circuit. The system of claim 11.

13. The system further includes a current measurement circuit having an analog-to-digital converter; the current measurement circuit is configured to be coupled to the half-bridge circuit; the current measurement circuit is configured to measure a current in the half-bridge circuit using the analog-to-digital converter; the first current corresponds to a magnitude less than a least significant bit of the analog-to-digital converter. The system of claim 10.

14. The buffer capacitor monitoring circuit includes: a first voltage to current converter coupled between the driver circuit supply node and the reference node; a first reference current generator coupled to the first voltage-to-current converter and the first current path circuit; a second voltage-to-current converter coupled between the driver circuit supply node and the reference node; a second reference current generator coupled to the second voltage-to-current converter and the second current path circuit; Including, 10. The system of claim 9.

15. the first current path circuit includes a first transistor having a load path coupled between the power supply node and the driver circuit supply node and a control node coupled to the first voltage to current converter; the second current path circuit includes a second transistor having a load path coupled between the power supply node and the driver circuit supply node and a control node coupled to the second voltage-to-current converter, the second transistor being larger than the first transistor; 15. The system of claim 14.

16. the second current is at least 10 times greater than the first current; 10. The system of claim 9.

17. the driver circuit, the first current path circuit, the second current path circuit, and the buffer capacitor monitoring circuit are disposed on a single semiconductor substrate.

10. The system of claim 9.

18. 1. A motor system, comprising: a half-bridge circuit having a high-side transistor and a low-side transistor; a high side driver having an output coupled to a control node of the high side transistor; a low side driver having an output coupled to a control node of the low side transistor; a buffer capacitor having a first terminal coupled to a boosted supply node and a supply node of the high side driver, and a second terminal coupled to a reference node of the high side driver and an output node of the half bridge circuit; a first transistor coupled between a power supply node and the boosted supply node and configured to source a first current; a second transistor coupled between the power supply node and the boosted supply node and configured to supply a second current; a buffer capacitor monitoring circuit; an analog-to-digital converter coupled to the half-bridge circuit and configured to digitize a current flowing through the half-bridge circuit; Including, The buffer capacitor monitoring circuit includes: measuring a first voltage between the boosted supply node and the reference node; activating the first transistor when the measured first voltage falls below a first threshold; measuring a first voltage between the boosted supply node and the reference node; configured to activate the second transistor when the measured first voltage falls below a second threshold, the first threshold being greater than the second threshold; Motor system.

19. The motor system further includes a motor coupled to the output node of the half bridge circuit.

20. The motor system of claim 18.

20. The high-side transistor and the low-side transistor each include a MOSFET.

20. The motor system of claim 18.

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