Three-dimensional memory device and system

Abstract

In a particular embodiment, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Description

[Technical field]

[0001] The present disclosure relates to memory devices and methods for manufacturing the same.

[0002] Planar memory cells are scaled to smaller sizes by improving processing techniques, circuit designs, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planarization processes and manufacturing techniques become more difficult and expensive. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures include a memory array and peripheral circuitry to facilitate operation of the memory array. Summary of the Invention

[0004] In one embodiment, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

[0005] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit for the array of memory cells. The second peripheral circuit includes a second transistor. The system also includes a memory controller coupled to the memory device and configured to control the array of memory cells via the first peripheral circuit and the second peripheral circuit. [Brief description of the drawings]

[0006] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. [Figure 1A] 1 shows a schematic diagram of a cross section of a 3D memory device according to some embodiments of the present disclosure. [Figure 1B] 1 illustrates a schematic diagram of a cross section of another 3D memory device according to some embodiments of the present disclosure. [Diagram 2] 1 illustrates a schematic circuit diagram of a memory device including peripheral circuits in accordance with some aspects of the present disclosure. [Diagram 3] 1 illustrates a block diagram of a memory device including memory cell array peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 4A] FIG. 2 illustrates a block diagram of peripheral circuits supplied with various voltages in accordance with some aspects of the present disclosure. [Figure 4B] FIG. 1 shows a schematic diagram of peripheral circuits provided with various voltages arranged in separate semiconductor structures, in accordance with some aspects of the present disclosure. [Figure 5A] FIG. 1 is a perspective view of a planar transistor according to some aspects of the present disclosure. [Figure 5B] FIG. 2 is a side view of a planar transistor according to some aspects of the present disclosure. [Figure 6A] FIG. 1 is a perspective view of a 3D transistor according to some embodiments of the present disclosure. [Figure 6B] FIG. 2 is a side view of a 3D transistor according to some embodiments of the present disclosure. [Figure 7] 1 illustrates a circuit diagram of a word line driver and a page buffer in accordance with some aspects of the present disclosure. [Figure 8] 1 illustrates a side view of a NAND memory string in a 3D memory device according to some embodiments of the present disclosure. [Figure 9A] FIG. 1 illustrates a schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various embodiments of the present disclosure. [Figure 9B] FIG. 1 illustrates a schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various embodiments of the present disclosure. [Figure 10] 9C shows a schematic diagram of a cross section of the 3D memory device of FIGS. 9A and 9B according to various embodiments of the present disclosure. FIG. [Figure 11A] 11A-11C show side views of various examples of the 3D memory device of FIG. 10 according to various aspects of the disclosure. [Figure 11B] 11A-11C show side views of various examples of the 3D memory device of FIG. 10 according to various aspects of the disclosure. [Figure 12A] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12B] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12C] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12D] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12E] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12F]11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 12G] 11 illustrates a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 13A] 11 illustrates another manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 13B] 11 illustrates another manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 14] 11 shows a flowchart of a method for forming the 3D memory device of FIG. 10 according to some embodiments of the present disclosure. [Figure 15A] 9C shows a schematic diagram of a cross section of the 3D memory device of FIGS. 9A and 9B according to various embodiments of the present disclosure. FIG. [Figure 15B] 9C shows a schematic diagram of a cross section of the 3D memory device of FIGS. 9A and 9B according to various embodiments of the present disclosure. FIG. [Figure 16A] 15B show side views of various examples of the 3D memory device of FIG. 15A according to various aspects of the disclosure. [Figure 16B] 15C show side views of various examples of the 3D memory device of FIG. 15B according to various aspects of the disclosure. [Figure 17A] 15A and 15B according to some embodiments of the present disclosure. [Figure 17B] 15A and 15B according to some embodiments of the present disclosure. [Figure 17C] 15A and 15B according to some embodiments of the present disclosure. [Figure 17D] 15A and 15B according to some embodiments of the present disclosure. [Figure 17E]15A and 15B according to some embodiments of the present disclosure. [Figure 17F] 15A and 15B according to some embodiments of the present disclosure. [Figure 17G] 15A and 15B according to some embodiments of the present disclosure. [Figure 17H] 15A and 15B according to some embodiments of the present disclosure. [Figure 18A] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 18B] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 18C] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 18D] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 18E] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 18F] 15C illustrates another manufacturing process for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 19] 15C shows a flowchart of a method for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 20] 15C shows a flowchart of a method for forming the 3D memory device of FIGS. 15A and 15B according to some embodiments of the present disclosure. [Figure 21A]FIG. 1 illustrates a schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various embodiments of the present disclosure. [Figure 21B] FIG. 1 illustrates a schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various embodiments of the present disclosure. [Figure 22A] 21A and 21B show schematic diagrams of cross sections of the 3D memory device of FIG. 21A and 21B according to some embodiments of the present disclosure. [Figure 22B] 21A and 21B show schematic diagrams of cross sections of the 3D memory device of FIG. 21A and 21B according to some embodiments of the present disclosure. [Figure 23A] 22C show side views of various examples of the 3D memory device of FIGS. 22A and 22B according to various embodiments of the present disclosure. [Figure 23B] 22C show side views of various examples of the 3D memory device of FIGS. 22A and 22B according to various embodiments of the present disclosure. [Figure 24A] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 24B] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 24C] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 24D] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 24E] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 24F] 22C illustrates a manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25A] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25B]22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25C] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25D] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25E] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25F] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 25G] 22C illustrates another manufacturing process for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 26] 22C shows a flowchart of a method for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 27] 22C shows a flowchart of another method for forming the 3D memory device of FIGS. 22A and 22B according to some embodiments of the present disclosure. [Figure 28A] 21A and 21B show schematic diagrams of cross sections of the 3D memory device of FIG. 21A and 21B according to some embodiments of the present disclosure. [Figure 28B] 21A and 21B show schematic diagrams of cross sections of the 3D memory device of FIG. 21A and 21B according to some embodiments of the present disclosure. [Figure 29A] 28B show side views of various examples of the 3D memory device of FIG. 28A according to various aspects of the disclosure. [Figure 29B] 28C show side views of various examples of the 3D memory device of FIG. 28B according to various aspects of the disclosure. [Figure 30A] 28A and 28B according to some embodiments of the present disclosure. [Figure 30B] 28A and 28B according to some embodiments of the present disclosure. [Figure 30C] 28A and 28B according to some embodiments of the present disclosure. [Figure 30D] 28A and 28B according to some embodiments of the present disclosure. [Figure 30E] 28A and 28B according to some embodiments of the present disclosure. [Figure 30F] 28A and 28B according to some embodiments of the present disclosure. [Figure 30G] 28A and 28B according to some embodiments of the present disclosure. [Figure 31A] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 31B] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 31C] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 31D] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 31E] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Fig. 31F] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 31G]28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Fig. 31H] 28C illustrates another manufacturing process for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Diagram 32] 28A and 28B according to some embodiments of the present disclosure. [Diagram 33] 28C shows a flowchart of another method for forming the 3D memory device of FIGS. 28A and 28B according to some embodiments of the present disclosure. [Figure 34A] 1 illustrates a manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 34B] 1 illustrates a manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 34C] 1 illustrates a manufacturing process for a transfer bond according to some aspects of the present disclosure. [Fig. 34D] 1 illustrates a manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 35A] 1 illustrates another manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 35B] 1 illustrates another manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 35C] 1 illustrates another manufacturing process for a transfer bond according to some aspects of the present disclosure. [Figure 35D] 1 illustrates another manufacturing process for a transfer bond according to some aspects of the present disclosure. [Diagram 36] FIG. 1 illustrates a block diagram of an example system having a memory device in accordance with some aspects of the disclosure. [Figure 37A] 1 illustrates a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 37B] 1 illustrates a diagram of an exemplary solid-state drive (SSD) having a memory device according to some embodiments of the present disclosure.

[0007] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be applied to a variety of other applications. The functional and structural features described in the present disclosure can be combined, coordinated, and modified with each other, and in ways not specifically shown in the drawings, such that these combinations, coordination, and modifications are within the scope of the present disclosure.

[0009] Generally, terms may be understood at least in part from their use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Furthermore, the term "based on" may not necessarily be intended to convey an exclusive set of factors, but rather may similarly be understood to permit the presence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0010] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with intermediate features or layers between, and "above" or "over" not only means "above" or "over" something, but also can include the meaning "above" or "over" of something without intermediate features or layers between (i.e., directly on top of something).

[0011] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0012] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a uniform or non-uniform region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along tapered surfaces. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed), and one or more dielectric layers.

[0013] With the development of 3D memory devices, such as 3D NAND flash memory devices, more stacks (e.g., more word lines and resulting more memory cells) require more peripheral circuits (and components such as transistors that form the peripheral circuits) to operate the 3D memory device. For example, the number and / or size of page buffers needs to increase to match the increased number of memory cells. In another example, the number of string drivers of a word line driver is proportional to the number of word lines in a 3D NAND flash memory. Thus, the continued increase in word lines also increases the area occupied by the word line drivers, as well as the complexity of the metal routing, sometimes even the number of metal layers. Furthermore, in some 3D memory devices where the peripheral circuits are fabricated below the memory cell array, sometimes known as the "periphery under the cell" (PUC) architecture or "complementary metal oxide semiconductor (CMOS) under the array" (CuA) architecture, the continued increase in the area of ​​the peripheral circuits becomes a bottleneck for reducing the total chip size, since the memory cell array can be expanded vertically by increasing the number of levels instead of increasing the size of the plane.

[0014] For this reason, it is desirable to reduce the planar area occupied by the peripheral circuits of 3D memory devices with an increased number of peripheral circuits and their transistors. However, reducing the size of the transistors of the peripheral circuits according to the trend of the advanced CMOS technology nodes used for logic devices will cause a significant increase in cost and leakage current, which is undesirable for memory devices. Furthermore, unlike logic devices, which can reduce their operating voltage as the CMOS technology nodes advance, 3D NAND flash memory devices cannot reduce the voltage supplied to the memory peripheral circuits because they require relatively high voltages (e.g., more than 5V) for certain memory operations such as programming and erasing. As a result, it becomes unfeasible to reduce the size of the memory peripheral circuits according to the trend of advancing CMOS technology nodes, as in the case of normal logic devices.

[0015] To address one or more of the above problems, the present disclosure introduces various solutions in which peripheral circuits of a memory device are arranged vertically in different planes (levels, hierarchies), i.e., stacked on each other, to reduce the planar chip size of the peripheral circuits and the overall chip size of the memory device. In some implementations, memory cell arrays (e.g., NAND memory strings), memory peripheral circuits supplied with relatively high voltages (e.g., greater than 3.3V), and memory peripheral circuits supplied with relatively low voltages (e.g., less than 2V) are arranged vertically in different planes, i.e., stacked on each other, to further reduce the size of the chip. The 3D memory device architecture and manufacturing process disclosed in the present disclosure can be easily scaled up vertically to stack more peripheral circuits in different planes to further reduce the size of the chip. Furthermore, the 3D memory device architecture and manufacturing process disclosed herein can be compatible with PUC / CuA architectures and processes. In some implementations, a memory cell array (e.g., a NAND memory string) can be formed on a deposited polysilicon (aka polycrystalline silicon) layer (e.g., in contact with a plate of a polysilicon source) as opposed to a single crystal silicon substrate, which is suitable for a specific design of the channel structure of a "floating gate" type NAND memory string, or a "charge trap" type NAND memory string suitable for, e.g., gate-induced drain leakage (GIDL) erase operation.

[0016] The peripheral circuits can be separated vertically into different planes based on different performance requirements, such as the dimensions of the transistors (e.g., gate dielectric thickness), the dimensions of the substrate on which the transistors are formed (e.g., substrate thickness), and the voltages applied to the transistors that affect the thermal budget (e.g., interconnect material). Thus, peripheral circuits with different dimensional requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budgets can be fabricated in different processes to reduce design and process constraints against each other, thereby improving device performance and manufacturing complexity.

[0017] According to some aspects of the present disclosure, memory cell arrays and various peripheral circuits with different performance and dimensional requirements can be fabricated in parallel on different substrates and then stacked on top of each other using various bonding techniques such as hybrid bonding, transfer bonding, etc. As a result, the manufacturing cycle of memory devices can be further shortened. Furthermore, since the thermal budgets of different devices become independent of each other, interconnect materials with desirable electrical performance but low thermal budgets such as copper can be used to interconnect memory cells and transistors of peripheral circuits, thereby further improving device performance. Bonding techniques can also introduce additional benefits. In some implementations, face-to-face hybrid bonding can achieve millions of parallel short interconnects between bonded semiconductor structures to increase the throughput and input / output (I / O) speed of memory devices. In some implementations, transfer bonding can reuse a single wafer to transfer its thin semiconductor layer onto different memory devices to form transistors thereon, reducing the cost of memory devices.

[0018] The 3D memory device architecture and manufacturing process disclosed in this disclosure also have flexibility to allow different device pad-out schemes to meet different needs and different designs of memory cell arrays. In some implementations, the pad-out interconnect layer is formed from the side of the semiconductor structure with the peripheral circuitry, shortening the interconnect distance between the pad-out interconnect layer and the transistors of the peripheral circuitry to reduce parasitic capacitance from the interconnect and improve electrical performance. In some implementations, the pad-out interconnect layer is formed in a thinned substrate to enable interlayer vias (LLVs, e.g., sub-micron level) for pad-out interconnect with high I / O throughput and low manufacturing complexity.

[0019] FIG. 1A shows a schematic diagram of a cross section of a 3D memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. In some implementations, the components of the 3D memory device 100 (e.g., a memory cell array and peripheral circuits) are formed separately in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process"). In some implementations, a semiconductor layer (e.g., single crystal silicon) is deposited on another semiconductor structure using transfer bonding, and then some of the components of the 3D memory device 100 (e.g., some peripheral circuits) are formed on the deposited semiconductor layer (a process referred to herein as a "serial process").

[0020] Note that x- and y-axes have been added in FIG. 1A to further illustrate the spatial relationships of the components of the semiconductor device. The substrate of a semiconductor device, e.g., 3D memory device 100, includes two lateral faces (e.g., top and bottom faces) that extend laterally in the x-direction (horizontal or width direction). As used herein, whether one component (e.g., layer or device) is "on," "above," or "below" another component (e.g., layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the y-direction (vertical or thickness direction) when the substrate is located at the lowest plane of the semiconductor device in the y-direction. The same concepts apply throughout this disclosure to describe spatial relationships.

[0021] The 3D memory device 100 may include a first semiconductor structure 102 including an array of memory cells (also referred to herein as a "memory cell array"). In some implementations, the memory cell array includes an array of NAND flash memory cells. For ease of explanation, a NAND flash memory cell array may be used as an example to explain the memory cell array in this disclosure. However, it is understood that the memory cell array is not limited to a NAND flash memory cell array, but may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few.

[0022] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers, which are then organized into blocks, with each NAND memory cell coupled to a separate line called a bit line (BL). All cells having the same vertical position of the NAND memory cell can be coupled through their control gates by a word line (WL). In some implementations, a memory plane includes a certain number of blocks coupled through the same bit line. The first semiconductor structure 102 can include one or more memory planes, and the peripheral circuits required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104 and the first semiconductor structure 102.

[0023] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some embodiments, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series (similar to a NAND gate) and two select transistors. According to some embodiments, each 2D NAND memory string is disposed in the same plane (i.e., a flat two-dimensional (2D) surface, which is different from the term "memory plane" herein) of a substrate. In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically (in 3D) above the substrate through a stack structure, e.g., a memory stack. Depending on the 3D NAND technology (e.g., the number of layers / tiers of the memory stack), the 3D NAND memory string typically includes a certain number of NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor.

[0024] Consistent with the scope of the present disclosure, the first semiconductor structure 102 may also include a polysilicon layer 106 on which a memory cell array is formed. In some implementations, the memory cell array includes an array of NAND memory strings, and the polysilicon layer 106 is in contact with the sources of the NAND memory strings. That is, the polysilicon layer 106 may function as a common source plate for multiple NAND memory strings. As described in more detail below, the polysilicon layer 106 may be formed on the first semiconductor structure 102 using one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, that are compatible with PUC / CuA processes. It is understood that in some examples, the polysilicon layer 106 may be a semiconductor layer, generally not limited to polysilicon.

[0025] As shown in FIG. 1A, the first semiconductor structure 102 may further include a portion of the peripheral circuitry of the memory cell array, and the memory cell array and the peripheral circuitry of the first semiconductor structure 102 may be vertically separated by a polysilicon layer 106. That is, the polysilicon layer 106 may be vertically disposed between the memory cell array and the peripheral circuitry in the first semiconductor structure 102. In some implementations, the peripheral circuitry is disposed below the polysilicon layer 106 and the memory cell array formed thereon. Depending on the thickness of the polysilicon layer 106, wiring (e.g., submicron level interlayer vias (ILVs) or micron or tens of micron level through-substrate vias (TSVs)) may be formed through the polysilicon layer 106 to form direct short-distance (e.g., submicron to tens of micron level) electrical connections between the memory cell array and the peripheral circuitry in the first semiconductor structure 102.

[0026] As shown in FIG. 1A, the 3D memory device 100 may also include a second semiconductor structure 104 that includes some of the peripheral circuits of the memory cell array in the first semiconductor structure 102. That is, the peripheral circuits of the memory cell array may be separated into at least two semiconductor structures (e.g., 102 and 104 in FIG. 1A). The peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuits used to facilitate operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an I / O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the functional circuits described above, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuit. The peripheral circuits in the first and second semiconductor structures 102 and 104 may use, for example, CMOS technology that may be implemented using logic processes of any suitable technology node.

[0027] 1A, according to some embodiments, the first and second semiconductor structures 102 and 104 are stacked on top of each other in different planes, which allows the memory cell array of the first semiconductor structure 102, the peripheral circuits of the first semiconductor structure 102, and the peripheral circuits of the second semiconductor structure 104 to be stacked on top of each other in different planes, thereby reducing the planar size of the 3D memory device 100 compared to a memory device in which all peripheral circuits are arranged on the same plane.

[0028] 1A, the 3D memory device 100 further includes a bonding interface 103 vertically between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 103 can be an interface between the two semiconductor structures formed by any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few, as described in more detail below.

[0029] It is understood that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited and may vary in different examples. Figure 1B shows a schematic cross-sectional view of another exemplary 3D memory device 101 according to some implementations. Unlike the 3D memory device 100 of Figure 1A in which the memory cell array of the first semiconductor structure is vertical between the peripheral circuit of the first semiconductor structure 102 and the peripheral circuit of the second semiconductor structure 104, in the 3D memory device 101 of Figure 1B, the peripheral circuit of the first semiconductor structure 102 is vertical between the memory cell array of the first semiconductor structure 102 and the peripheral circuit of the second semiconductor structure. That is, the second semiconductor structure 102 can be bonded to the first semiconductor structure 102 on either side, such as the side on which the memory cell array is formed in the 3D memory device 100 of Figure 1A or the side on which the peripheral circuit is formed in the 3D memory device 101 of Figure 1B. As a result, in contrast to the 3D memory device 100 in which the bonding interface 103 is formed vertically between the second semiconductor structure 104 and the memory cell array of the first semiconductor structure 102, the bonding interface 105 is formed vertically between the second semiconductor structure 104 and the peripheral circuitry of the first semiconductor structure 102. Like the bonding interface 103, the bonding interface 105 can be an interface between two semiconductor structures formed by any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few, as described in more detail below.

[0030] As described in more detail below, in some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (and in some embodiments in parallel) in a parallel process such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process for fabricating the other. Additionally, multiple interconnects (e.g., bond contacts and / or ILVs / TSVs) can be formed across the bond interface 103 or 105 to provide direct, short-distance (e.g., micron or sub-micron) electrical connections between the semiconductor structures 102 and 104, as opposed to long-distance (e.g., millimeter or centimeter) chip-to-chip data buses on a circuit board such as a printed circuit board (PCB), thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array and different peripheral circuits in different semiconductor structures 102 and 104 can be performed through interconnects (e.g., bond contacts and / or ILV / TSV) across the bond interface 103 or 105 and the polysilicon layer 106. The vertical integration of the first semiconductor structure 102 and the second semiconductor structure 104, along with the vertical separation of the memory cell array and the peripheral circuits in different planes in the first semiconductor structure 102, can reduce the chip size and increase the memory cell density.

[0031] FIG. 2 shows a schematic circuit diagram of a memory device 200 including peripheral circuits according to some aspects of the disclosure. The memory device 200 can include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory devices 100 and 101 can be examples of memory devices 200 in which at least two portions of the memory cell array 201 and the peripheral circuit 202 can be included in different stacked semiconductor structures 102 and 104. The memory cell array 201 can be a NAND flash memory cell array in which memory cells 206 are provided in the form of an array of NAND memory strings 208, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 can hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the area of ​​the memory cell 206. Each memory cell 206 can be either a floating gate type memory cell including floating gate transistors or a charge trap type memory cell including charge trap transistors.

[0032] In some implementations, each memory cell 206 is a single level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0033] 2, each NAND memory string 208 may include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and the DSG transistor 212 may be configured to activate a selected NAND memory string 208 (column of the array) during read and program operations. In some implementations, the SSG transistors 210 of the NAND memory strings 208 of the same block 204 are coupled to the same source line (SL) 214, e.g., a common SL, e.g., to ground. According to some implementations, the DSG transistors 212 of each NAND memory string 208 are coupled to a respective bit line 216 from which data may be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 212) or a deselect voltage (e.g., 0V) to the respective DSG transistor 212 via one or more DSG lines 213, and / or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 210) or a deselect voltage (e.g., 0V) to the respective SSG transistor 210 via one or more SSG lines 215.

[0034] As shown in FIG. 2, NAND memory strings 208 can be organized into multiple blocks 204, each of which can have a common source line 214. In some implementations, each block 204 is the basic data unit for erase operations, i.e., all memory cells 206 in the same block 204 are erased at the same time. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218 that select which row of memory cells 206 is affected by read and program operations. In some implementations, each word line 218 is coupled to a page 220 of memory cells 206, which is the basic data unit for program and read operations. The size of one page 220 of bits can correspond to the number of NAND memory strings 208 coupled by the word lines 218 of one block 204. Each word line 218 can include multiple control gates (gate electrodes) to each memory cell 206 of the respective page 220 and gate lines coupling the control gates.

[0035] FIG. 8 illustrates a side view of a NAND memory string 208 in a 3D memory device according to some embodiments of the present disclosure. As illustrated in FIG. 8, the NAND memory string 208 can extend vertically through a memory stack 804 on a polysilicon layer 805. The polysilicon layer 805 can be an example of the polysilicon layer 106 of FIGS. 1A and 1B. The memory stack 804 can include interleaved gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 of the memory stack 804 can determine the number of memory cells 206 in the memory cell array 201. The gate conductive layers 806 can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 806 comprises a doped polysilicon layer. Each gate conductive layer 806 may comprise a control gate surrounding a memory cell, the gate of a DSG transistor 212, or the gate of a SSG transistor 210, and may extend laterally as a DSG line 213 at the top of a memory stack 804, an SSG line 215 at the bottom of a memory stack 804, or a word line 218 between the DSG line 213 and the SSG line 215.

[0036] As shown in FIG. 8, the NAND memory string 208 includes a channel structure 812 that extends vertically through the memory stack 804. In some implementations, the channel structure 812 includes a channel hole filled with a semiconductor material (e.g., as the semiconductor channel 820) and a dielectric material (e.g., as the memory film 818). In some implementations, the semiconductor channel 820 includes silicon, such as polysilicon. In some implementations, the memory film 818 is a composite dielectric layer including a tunnel layer 826, a storage layer 824 (also known as a "charge trap / storage layer"), and a blocking layer 822. The channel structure 812 can have a cylindrical shape (e.g., that of a pillar). According to some implementations, the semiconductor channel 820, the tunnel layer 826, the storage layer 824, and the blocking layer 822 are radially arranged from the center of the pillar to the outer surface in that order. The tunnel layer 826 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 can include silicon oxide, silicon oxynitride, silicon, or any combination thereof. The blocking layer 822 can include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 818 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure 812 can further include a channel plug 816 at the drain end of the NAND memory string 208. The channel plug 816 can include polysilicon and can contact the semiconductor channel 820.

[0037] In some implementations, the polysilicon layer 805 contacts the semiconductor channel 820 of the channel structure 812 on the source end of the NAND memory string 208. A portion of the memory film 818 of the channel structure 812 on the source end may be removed to expose the semiconductor channel 820 in contact with the polysilicon layer 805. In some implementations, a portion of the semiconductor channel 820 on the source end of the NAND memory string 208 is doped to form a doped region 832 in contact with the polysilicon layer 805. It is understood that in some examples, the polysilicon layer 805 may be doped with the same dopant as the doped region 832, or the dopant may diffuse into a portion of the semiconductor channel 820 to form the doped region 832. In some implementations, the polysilicon layer 805 includes N-type doped polysilicon to enable a GILD erase operation.

[0038] 8, the slit structure 828 does not include any conductors (e.g., source contacts) therein and therefore, according to some implementations, does not function as part of the source line 214. Instead, a source contact (not shown) can be formed on the opposite side of the polysilicon layer 805 to the channel structure 812, such that the source contact and a portion of the polysilicon layer 805 can function as part of the source line 214 coupled to the source of the NAND memory string 208, for example, to apply an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0039] Referring back to FIG. 2, the peripheral circuits 202 can be coupled to the memory cell array 201 via bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213. As discussed above, the peripheral circuits 202 can include any suitable circuitry to facilitate operation of the memory cell array 201 by applying and sensing voltage and / or current signals via the bit lines 216 to and from each target memory cell 206 via the word lines 218, source lines 214, SSG lines 215, and DSG lines 213. The peripheral circuits 202 can include various types of peripheral circuits formed using CMOS technology. For example, FIG. 3 illustrates some exemplary peripheral circuits 202 including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It is understood that in some examples, additional peripheral circuits 202 can also be included.

[0040] The page buffer 304 can be configured to buffer data read from or programmed into the memory cell array 201 according to control signals of the control logic 312. In one example, the page buffer 304 may store one page of program data (write data) to be programmed into one page 220 of the memory cell array 201. In another example, the page buffer 304 also performs program verify operations to ensure that data is properly programmed into the memory cells 206 coupled to the selected word line 218.

[0041] The row decoder / word line driver 308 can be configured to be controlled by the control logic 312 and the select block 204 of the memory cell array 201 and the word line 218 of the select block 204. The row decoder / word line driver 308 can be further configured to drive the memory cell array 201. For example, the row decoder / word line driver 308 can drive the memory cell 206 coupled to the selected word line 218 using a word line voltage generated from a voltage generator 310.

[0042] The column decoder / bit line driver 306 can be configured to select one or more 3D NAND memory strings 208 by applying bit line voltages generated from a voltage generator 310 as controlled by the control logic 312. For example, the column decoder / bit line driver 306 can apply column signals to select a set of N bits of data from the page buffer 304 to be output in a read operation.

[0043] The control logic 312 may be coupled to each peripheral circuit 202 and may be configured to control the operation of the peripheral circuit 202. The registers 314 may be coupled to the control logic 312 and may include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0044] The interface 316 can be coupled to the control logic 312 and can be configured to interface the memory cell array 201 with a memory controller (not shown). In some implementations, the interface 316 functions as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to the control logic 312 and relay status information received from the control logic 312 to the memory controller and / or host. The interface 316 can also be coupled to the page buffer 304 and the column decoder / bit line driver 306 via a data bus 318 and functions as an I / O interface and data buffer to buffer and relay program data received from the memory controller and / or host to the page buffer 304 and relay data read from the page buffer 304 to the memory controller and / or host. In some implementations, the interface 316 and the data bus 318 are part of the I / O circuitry of the peripheral circuit 202.

[0045] The voltage generator 310 is controlled by the control logic 312 and can be configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) and bit line voltages that are supplied to the memory cell array 201. In some implementations, the voltage generator 310 is part of a voltage source that supplies voltages at various levels to different peripheral circuits 202, as described in more detail below. Consistent with the scope of the present disclosure, in some implementations, the voltages supplied by the voltage generator 310 to, for example, the row decoder / word line driver 308, the column decoder / bit line driver 306, and the page buffer 304 are above a certain level sufficient to perform memory operations. For example, the voltage supplied to the page buffer circuitry in the page buffer 304 and / or the logic circuitry in the control logic 312 may be between 2V and 3.3V, such as 3.3V, and the voltage supplied to the drive circuitry in the row decoder / word line driver 308 and / or the column decoder / bit line driver 306 may be between 5V and 30V.

[0046] Unlike logic devices (e.g., microprocessors), memory devices such as 3D NAND flash memories require a wide range of voltages to be supplied to different memory peripheral circuits. For example, FIG. 4A shows a block diagram of peripheral circuits supplied with various voltages according to some aspects of the present disclosure. In some implementations, a memory device (e.g., memory device 200) includes a low low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each of which is configured to supply a voltage of a respective level (Vdd1, Vdd2, or Vdd3). For example, Vdd3>Vdd2>Vdd1. Each voltage source 401, 403, or 405 can receive a voltage input of an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 may also include a voltage converter and / or a voltage regulator to convert an input external voltage to a respective level (Vdd1, Vdd2, or Vdd3) and to maintain and output a voltage at the respective level (Vdd1, Vdd2, or Vdd3) via a corresponding power rail. In some implementations, the voltage generator 310 of the memory device 200 is part of the voltage sources 401, 403, and 405.

[0047] In some implementations, the LLV source 401 is configured to provide a voltage less than 2V, such as between 0.9V and 2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some embodiments, the LV source 403 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded at the lower end by any of these values, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, HV source 405 is configured to supply a voltage greater than 3.3V, such as 5V to 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). It is understood that the voltage ranges set forth above with respect to HV source 405, LV source 403, and LLV source 401 are for illustrative purposes and are non-limiting, and any other suitable voltage ranges may be supplied by HV source 405, LV source 403, and LLV source 401.

[0048] Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), the memory peripheral circuits (e.g., peripheral circuits 202) can be categorized into LLV circuits 402, LV circuits 404, and HV circuits 406, which can be coupled to LLV sources 401, LV sources 403, and HV sources 405, respectively. In some implementations, the HV circuits 406 include one or more driver circuits coupled to the memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and configured to drive the memory cell array by applying appropriate levels of voltages to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing a memory operation (e.g., read, program, or erase). In one example, the HV circuits 406 can include word line driver circuits (e.g., in row decoder / word line driver 308) coupled to the word lines and applying a program voltage (Vprog) or a pass voltage (Vpass), e.g., in the range of 5V to 30V, to the word lines during a program operation. In another example, the HV circuitry 406 may include a bit line driver circuit (e.g., in the column decoder / bit line driver 306) coupled to the bit lines and configured to apply an erase voltage (Veras) to the bit lines during an erase operation, e.g., in a range of 5V to 30V. In some implementations, the LV circuitry 404 includes a page buffer circuit (e.g., in the latches of the page buffer 304) configured to buffer data read from or programmed into the memory cell array. For example, the page buffer may be supplied with a voltage of, e.g., 3.3V by the LV source 403. The LV circuitry 404 may also include logic circuitry (e.g., in the control logic 312). In some implementations, the LLV circuitry 402 includes I / O circuitry (e.g., in the interface 316 and / or the data bus 318) configured to interface the memory cell array with a memory controller. For example, the I / O circuitry may be supplied with a voltage of, e.g., 1.2V by the LLV source 401.

[0049] As mentioned above, to reduce the total area occupied by the memory peripheral circuits, the peripheral circuits 202 can be formed separately on different planes based on different performance requirements such as applied voltage. For example, FIG. 4B shows a schematic diagram of peripheral circuits supplied with various voltages arranged in separate semiconductor structures according to some embodiments of the present disclosure. In some implementations, the LLV circuit 402 and the HV circuit 406 are separated in the semiconductor structures 408 and 410, respectively, due to, for example, significant differences in their voltages and resulting differences in device dimensions such as different substrate thicknesses and different gate dielectric thicknesses. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) on which the HV circuit 406 is formed in the semiconductor structure 410 may be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) on which the LLV circuit 402 is formed in the semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistors forming the HV circuit 406 may be greater than the thickness of the gate dielectric of the transistors forming the LLV circuit 402. For example, the thickness difference may be at least 5 times. It will be appreciated that the stacked LLV circuit 402 and the HV circuit 406 in different planes may be formed in two semiconductor structures 408 or 410 separated by a bonded interface (eg, in FIGS. 1A and 1B).

[0050] The LV circuitry 404 can be formed in either the semiconductor structure 408 or 410, or in another semiconductor, i.e., in the same plane as the LLV circuitry 402 or the HV circuitry 406, or in a different plane than the LLV circuitry 402 and the HV circuitry 406. As shown in FIG. 4B, in some implementations, some of the LV circuitry 404 is formed in the semiconductor structure 408, i.e., in the same plane as the LLV circuitry 402, while some of the LV circuitry 404 is formed in the semiconductor structure 410, i.e., in the same plane as the HV circuitry 406. That is, the LV circuitry 404 can also be separated into different planes. The gate dielectric thickness of the transistors forming the LV circuitry 404 in the semiconductor structure 408 can be the same as the gate dielectric thickness of the transistors forming the LV circuitry 404 in the semiconductor structure 410, for example, when the same voltage is applied to the LV circuitry 404 in the different semiconductor structures 408 and 410. In some embodiments, the same voltage is applied to both the LV circuit 404 in the semiconductor structure 408 and the LV circuit 404 in the semiconductor structure 410, such that the voltage applied to the HV circuit 406 in the semiconductor structure 410 is higher than the voltage applied to the LV circuit 404 in the semiconductor structure 408 or 410, which in turn is higher than the voltage applied to the LLV circuit 402 in the semiconductor structure 408. Furthermore, according to some embodiments, since the voltage applied to the LV circuit 404 is between the voltages applied to the HV circuit 406 and the LLV circuit 402, the gate dielectric thickness of the transistors forming the LV circuit 404 is between the gate dielectric thickness of the transistors forming the HV circuit 406 and the gate dielectric thickness of the transistors forming the LLV circuit 402. For example, the gate dielectric thickness of the transistors forming the LV circuit 404 may be greater than the gate dielectric thickness of the transistors forming the LLV circuit 402 and less than the gate dielectric thickness of the transistors forming the HV circuit 406.

[0051] Based on different performance requirements (e.g., associated with different applied voltages), the peripheral circuitry 202 can be separated into at least two stacked semiconductor structures 408 and 410 in different planes. In some implementations, the I / O circuits in the interface 316 and / or data bus 318 (as LLV circuitry 402) and the logic circuits in the control logic 312 (as part of the LV circuitry) are located in the semiconductor structure 408, and the page buffer circuits in the page buffer 304 and the drive circuits in the row decoder / word line driver 308 and column decoder / bit line driver 306 are located in the semiconductor structure 410. For example, FIG. 7 shows a circuit diagram of the word line driver 308 and the page buffer 304 in accordance with some aspects of the present disclosure.

[0052] In some implementations, the page buffer 304 includes multiple page buffer circuits 702, each coupled to one NAND memory string 208 via a respective bit line 216. That is, the memory device 200 can include bit lines 216 each coupled to a NAND memory string 208, and the page buffer 304 can include page buffer circuits 702 each coupled to the bit lines 216 and the NAND memory string 208. Each page buffer circuit 702 can include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verify logic, sense circuits, etc. In some implementations, each page buffer circuit 702 is configured to store sense data corresponding to read data received from a respective bit line 216 and output the stored sense data during a read operation. Each page buffer circuit 702 is also configured to store program data and output the stored program data to a respective bit line 216 during a program operation.

[0053] In some implementations, the word line driver 308 includes a plurality of string drivers 704 (also known as drive circuits) each coupled to a word line 218. The word line driver 308 may also include a plurality of local word lines 706 (LWL) each coupled to a string driver 704. Each string driver 704 may include a gate coupled to a decoder (not shown), a source / drain coupled to a respective local word line 706, and another source / drain coupled to a respective word line 218. In some memory operations, the decoder may select a particular string driver 704, for example, by applying a voltage signal greater than the threshold voltage of the string driver 704 and a voltage (e.g., a program voltage, a pass voltage, or an erase voltage) to each local word line 706 such that a voltage is applied to a respective word line 218 by each selected string driver 704. In contrast, the decoder can also deselect a particular string driver 704, for example, by applying a voltage signal less than the threshold voltage of the string driver 704, such that each deselected string driver 704 causes its respective word line 218 to float during memory operations.

[0054] In some implementations, the page buffer circuit 702 includes a portion of the LV circuit 404 located in the semiconductor structure 408 and / or 410. In one example, the page buffer circuit 702 can be the semiconductor structure 408 and 410 because the number of page buffer circuits 702 increases as the number of bits increases and can occupy a large area for memory devices having a large number of memory cells. In some implementations, the string driver 704 includes a portion of the HV circuit 406 located in the semiconductor structure 410.

[0055] Consistent with the scope of the present disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (2D transistors, also known as planar transistors) or 3D (3D transistors) metal oxide semiconductor field effect transistors (MOSFETs). For example, Figures 5A and 5B show perspective and side views, respectively, of a planar transistor 500 according to some embodiments of the present disclosure, and Figures 6A and 6B show perspective and side views, respectively, of a 3D transistor 600 according to some embodiments of the present disclosure. Figure 5B shows a cross-sectional side view of the planar transistor 500 of Figure 5A in the BB plane, and Figure 6B shows a cross-sectional side view of the 3D transistor 600 of Figure 6A in the BB plane.

[0056] As shown in FIGS. 5A and 5B, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. To reduce current leakage, trench isolation 503, such as shallow trench isolation (STI), may be formed in the substrate 502 and between adjacent planar transistors 500. The trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some implementations, the high-k dielectric material includes any dielectric material having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, the trench isolation 503 comprises silicon oxide.

[0057] As shown in Figures 5A and 5B, the planar transistor 500 may also include a gate structure 508 on the substrate 502. In some implementations, the gate structure 508 is on the top surface of the substrate 502. As shown in Figure 5B, the gate structure 508 may include a gate dielectric 507 on the substrate 502, i.e., above and in contact with the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on the gate dielectric 507, i.e., above and in contact with the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, the gate dielectric 507 includes silicon oxide, i.e., a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some implementations, the gate electrode 509 includes doped polysilicon, i.e., a gate poly.

[0058] As shown in FIG. 5A, the planar transistor 500 may further include a pair of source and drain 506 in the substrate 502. The source and drain 506 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (Ar). The source and drain 506 may be separated in plan view by a gate structure 508. In other words, according to some implementations, the gate structure 508 is formed between the source and drain 506 in plan view. A channel of the planar transistor 500 in the substrate 502 may be formed laterally between the source and drain 506 under the gate structure 508 when a gate voltage applied to a gate electrode 509 of the gate structure 508 exceeds a threshold voltage of the planar transistor 500. As shown in FIGS. 5A and 5B, the gate structure 508 may contact above a top surface of a portion of the substrate 502 (active region) where a channel may be formed. That is, according to some implementations, the gate structure 508 contacts only one side of the active area, namely, in the plane of the top surface of the substrate 502. Although not shown in Figures 5A and 5B, it is understood that the planar transistor 500 can include additional components, such as wells and spacers.

[0059] As shown in FIGS. 6A and 6B, the 3D transistor 600 can be a MOSFET on a substrate 602, which can include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator SOI, or any other suitable material. In some implementations, the substrate 602 includes single crystal silicon. Trench isolation 603, such as STI, can be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some implementations, the trench isolation 603 includes silicon oxide.

[0060] As shown in FIGS. 6A and 6B, unlike the planar transistor 500, the 3D transistor 600 can further include a 3D semiconductor body 604 above the substrate 602. That is, in some implementations, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602 to expose not only the top surface of the 3D semiconductor body 604 but also two side surfaces. As shown in FIGS. 6A and 6B, for example, the 3D semiconductor body 604 can be a 3D structure also known as a "fin" that exposes three sides. According to some implementations, the 3D semiconductor body 604 is formed from the substrate 602 and thus has the same semiconductor material as the substrate 602. In some implementations, the 3D semiconductor body 604 includes single crystal silicon. The 3D semiconductor body 604 can be viewed as the active region of the 3D transistor 600 because the channel can be formed in the 3D semiconductor body 604 as opposed to the substrate 602.

[0061] 6A and 6B, the 3D transistor 600 may also include a gate structure 608 in the substrate 602. Unlike the planar transistor 500 in which the gate structure 508 contacts only one side of the active area, i.e., the plane of the top surface of the substrate 502, the gate structure 608 of the 3D transistor 600 may contact multiple side surfaces of the active area, i.e., multiple planes of the top and side surfaces of the 3D semiconductor body 604. In other words, the active area of ​​the 3D transistor 600, i.e., the 3D semiconductor body 604, may be at least partially surrounded by the gate structure 608.

[0062] The gate structure 608 may include a gate dielectric 607 on top of the 3D semiconductor body 604, for example, in contact with a top surface and two side surfaces of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 in contact with the top of the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some implementations, the gate electrode 609 includes doped polysilicon, i.e., a gate poly.

[0063] As shown in FIG. 6A, the 3D transistor 600 may further include a pair of source and drain 606 in the 3D semiconductor body 604. The source and drain 606 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. The source and drain 606 may be separated by a gate structure 608 in a plan view. In other words, according to some implementations, the gate structure 608 is formed between the source and drain 606 in a plan view. As a result, when a gate voltage applied to a gate electrode 609 of the gate structure 608 exceeds a threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 in the 3D semiconductor body 604 may be formed laterally between the source and drain 606 surrounded by the gate structure 608. Unlike the planar transistor 500, which may only form a single channel on the top surface of the substrate 502, the 3D transistor 600 may form multiple channels on the top and side surfaces of the 3D semiconductor body 604. In some implementations, the 3D transistor 600 includes a multi-gate transistor. Although not shown in FIGS. 6A and 6B, it is understood that the 3D transistor 600 can include additional components such as wells, spacers, and stressors (also known as flexure bodies) at the source and drain 606.

[0064] 6A and 6B show one example of a 3D transistor that may be used in the memory periphery circuitry, it being further understood that any other suitable 3D multi-gate transistors may also be used in the memory periphery circuitry, including, for example, gate-all-around (GAA) silicon-on-nothing (SON) transistors, multiple independent gate FETs (MIGETs), tri-gate FETs, gate FETs, and Ω-FETs, quadrupole gate FETs, cylindrical FETs, or multi-bridge / stacked nanowire FETs.

[0065] Each transistor, whether planar transistor 500 or 3D transistor 600, that is a memory peripheral circuit, can include a gate dielectric (e.g., gate dielectrics 507 and 607) having a thickness T (gate dielectric thickness, e.g., as shown in Figures 5B and 6B). The gate dielectric thickness T of a transistor can be designed to accommodate the voltage applied to the transistor. For example, referring back to Figures 4A and 4B, the gate dielectric thickness of a transistor in the HV circuit 406 (e.g., drive circuitry such as string driver 704) may be greater than the gate dielectric thickness of a transistor in the LV circuit 404 (e.g., page buffer circuitry 702 or logic circuitry in control logic 312), which in turn can be greater than the gate dielectric thickness of a transistor in the LLV circuit 402 (e.g., I / O circuitry in interface 316 and data bus 318). In some implementations, the difference between the gate dielectric thickness of a transistor in the HV circuit 406 and the dielectric thickness of a transistor in the LLV circuit 402 is at least 5 times, e.g., 5 times to 50 times. For example, the gate dielectric thickness of the transistors in the HV circuit 406 may be at least five times the gate dielectric thickness of the transistors in the LLV circuit 402.

[0066] In some implementations, the thickness of the dielectric of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). It is understood that the thickness can be comparable to the LLV voltage range applied to the LLV circuit 402, as detailed above, such as less than 2 V (e.g., 1.2 V). In some implementations, the thickness of the dielectric of the transistors in the LV circuitry 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). It is understood that the thickness may be commensurate with the LV voltage range applied to the LV circuitry 404, as detailed above, such as 2 V to 3.3 V (e.g., 3.3 V). In some implementations, the thickness of the dielectric of the transistors in the HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). It is understood that the thickness may be commensurate with the HV voltage range applied to the HV circuit 406, as detailed above, such as greater than 3.3 V (e.g., between 5 V and 30 V).

[0067] 9A and 9B show schematic cross-sectional views of 3D memory devices 900 and 901 having two stacked semiconductor structures according to various embodiments of the present disclosure. The 3D memory devices 900 and 901 may be examples of the 3D memory device 100 of FIG. 1A in which the memory array cells of the first semiconductor structure 102 are vertically disposed between the peripheral circuits of the first semiconductor structure 102 and the peripheral circuits of the second semiconductor structure 104. That is, two separate parts of the peripheral circuits can be disposed on either side of the vertical direction of the 3D memory device 900 or 901, respectively. As shown in FIGS. 9A and 9B, according to some embodiments, the second semiconductor structure 104 including some of the peripheral circuits is bonded to the first semiconductor structure 102 on the side having the memory cell array to form a bonded interface 103 between the second semiconductor structure 104 and the memory cell array of the first semiconductor structure 102.

[0068] Furthermore, as shown in Figures 9A and 9B, the 3D memory device 900 or 901 may further include a pad-out interconnect layer 902 for pad-out purposes, i.e., for interconnecting with external devices using contact pads to which bond wires can be soldered. In one example shown in Figure 9A, a second semiconductor structure 104 including some of the peripheral circuitry on one side of the 3D memory device 900 may include a pad-out interconnect layer 902. In another example shown in Figure 9B, a first semiconductor structure 102 including a memory cell array and some of the peripheral circuitry on another side of the 3D memory device 901 may include a pad-out interconnect layer 902 so that the 3D memory device 901 may be padded out from the other peripheral circuitry side. In either example, the 3D memory device 900 or 901 may be padded out from the peripheral circuitry side to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing the parasitic capacitance from the interconnection and improving the electrical performance of the 3D memory device 900 or 901.

[0069] FIG. 10 shows a schematic diagram of a cross section of the 3D memory device of FIGS. 9A and 9B according to some embodiments of the present disclosure. The 3D memory device 1000 can be an example of the 3D memory devices 900 and 901 of FIGS. 9A and 9B. As shown in FIG. 10, the 3D memory device 1000 can include stacked first and second semiconductor structures 102 and 104. In some implementations, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically between the polysilicon layer 106 and the bonding layer 1008, and a portion of a peripheral circuit vertically between the semiconductor layer 1002 and the polysilicon layer 106.

[0070] The memory cell array can include an array of NAND memory strings (e.g., NAND memory strings 208 as disclosed herein), the sources of which can be in contact with polysilicon layer 106 (e.g., as shown in FIG. 8). Polysilicon layer 106 can be a deposited polysilicon layer (e.g., either N-type doped, P-type doped, or undoped) suitable for a "floating gate" type NAND memory string, or a specific design of a channel structure (e.g., channel structure 812 in FIG. 8) in a "charge trap" type NAND memory string, suitable for, e.g., a GIDL erase operation. Bonding layer 1008 can include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts, which can be used, e.g., for hybrid junctions, as described in more detail below.

[0071] In some implementations, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not with the polysilicon layer 106. That is, the transistors of the peripheral circuitry (e.g., the planar transistor 500 and the 3D transistor 600) can be in contact with the semiconductor layer 1004. The semiconductor layer 1002 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1002 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. Direct, short-distance (e.g., sub-micron or micron level) electrical connections can be made between the memory cell array and the peripheral circuitry in the first semiconductor structure 102 via contacts (e.g., ILV / TSV) through the polysilicon layer 106.

[0072] In some implementations, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1010, and some of the peripheral circuitry of the memory cell array that is vertically between the semiconductor layer 1004 and the bonding layer 1010. Transistors of the peripheral circuitry (e.g., the planar transistors 500 and the 3D transistors 600) can be in contact with the semiconductor layer 1004. Like the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1004 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon that is desirable for transistor performance.

[0073] Similar to the bonding layer 1008 of the first semiconductor structure 102, the bonding layer 1010 may also include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts. According to some implementations, the bonding interface 103 is vertical between and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 may be disposed on either side of the bonding interface 103, and the bonding contacts of the bonding layer 1008 may contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, unlike through contacts (e.g., ILV / TSV), a large number (e.g., millions) of bonding contacts across the bonding interface 103 may create a direct, short-distance (e.g., micron-level) electrical connection between adjacent semiconductor structures 102 and 104.

[0074] 10, according to some embodiments, the first and second semiconductor structures 102 and 104 are bonded in a face-to-face manner (e.g., in FIG. 10, the semiconductor layer 1002 is disposed under the first semiconductor structure 102, while the semiconductor layer 1004 is disposed over the second semiconductor structure 104), so that the transistors of the peripheral circuits in the first and second semiconductor structures 102 and 104 are disposed opposite each other. Also, in the first semiconductor structure 102, there is a polysilicon layer 106 vertically between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on the polysilicon layer 106 and the semiconductor layer 1002, respectively, so that the memory cell array and the peripheral circuits face in the same direction (e.g., in the positive y direction in FIG. 10). It will be understood that the pad-out interconnect layer 902 of Figures 9A and 9B has been omitted from the 3D memory device 1000 of Figure 10 for ease of explanation, and may be included in the 3D memory device 1000 as described above with respect to Figures 9A and 9B.

[0075] As mentioned above, the first semiconductor structure 102 and the second semiconductor structure 104 can have peripheral circuits with transistors with different applied voltages. For example, the second semiconductor structure 104 can be an example of the semiconductor structure 408 including the LLV circuit 402 (and in some examples the LV circuit 404) of FIG. 4B, and the first semiconductor structure 102 can be an example of the semiconductor structure 410 including the HV circuit 406 (and in some examples the LV circuit 404) of FIG. 4B, or vice versa. Thus, in some implementations, the semiconductor layers 1002 and 1004 in the first and second semiconductor structures 102 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the first semiconductor structure 102 can include the HV circuit 406 and the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 in the first semiconductor structure 102 can be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Additionally, in some implementations, the gate dielectrics of the transistors in the first and second semiconductor structures 102 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the first semiconductor structure 102 may include the HV circuitry 406 and the second semiconductor structure 104 may include the LLV circuitry 402, and the gate dielectric thickness of the transistors in the first semiconductor structure 102 may be greater (e.g., at least five times) than the gate dielectric thickness of the transistors in the second semiconductor structure 104. The thicker gate dielectric can sustain a higher operating voltage applied to the transistors in the first semiconductor structure 102 than the transistors in the second semiconductor structure 104 to avoid failure during high voltage operation.

[0076] 11A and 11B show side views of various examples of the 3D memory device 1000 of FIG. 10 according to various aspects of the disclosure. As shown in FIG. 11A, as an example of the 3D memory device 1000 of FIG. 10, the 3D memory device 1100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of each other in different planes in the vertical direction (e.g., the y-direction in FIG. 11A), according to some implementations. According to some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 103 therebetween.

[0077] As shown in FIG. 11A, the first semiconductor structure 102 may include a semiconductor layer 1002 having a semiconductor material. In some implementations, the semiconductor layer 1002 is a silicon substrate having single crystal silicon. The first semiconductor structure 102 may also include a device layer 1102 above and in contact with the semiconductor layer 1002. In some implementations, the device layer 1102 includes a first peripheral circuit 1104 and a second peripheral circuit 1106. The first peripheral circuit 1104 may include HV circuits 406 such as drive circuits (e.g., string drivers 704 in row decoder / word line driver 308 and drivers in column decoder / bit line driver 306), and the second peripheral circuit 1106 may include LV circuits 404 such as page buffer circuits (e.g., page buffer circuit 702 in page buffer 304) and logic circuits (e.g., control logic 312). In some implementations, the first peripheral circuit 1104 includes a plurality of transistors 1108 in contact with the semiconductor layer 1002, and the second peripheral circuit 1106 includes a plurality of transistors 1110 in contact with the semiconductor layer 1002. The transistors 1108 and 1110 can include any transistor disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some implementations, each transistor 1108 or 1110 includes a gate dielectric, and because the voltage applied to the transistor 1108 is higher than that of the transistor 1110, the thickness of the gate dielectric of the transistor 1108 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistor 1110 (e.g., in the LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of the transistors 1108 and 1110) can also be formed on or in the semiconductor layer 1002.

[0078] In some implementations, the first semiconductor structure 102 further includes an interconnect layer 1112 on the device layer 1102 to transfer electrical signals between the peripheral circuits 1106 and 1104. As shown in FIG. 11A, the interconnect layer 1112 can be vertical between the polysilicon layer 106 and the device layer 1102 (including the transistors 1108 and 1110 of the peripheral circuits 1104 and 1106). The interconnect layer 1112 can include a plurality of interconnects (also referred to herein as "contacts") including horizontal lines and vias. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnects in the interconnect layer 1112 can be coupled to the transistors 1108 and 1110 of the peripheral circuits 1104 and 1106 in the device layer 1102. The interconnect layer 1112 may further include one or more interlevel dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which horizontal lines and vias may be formed. That is, the interconnect layer 1112 may include horizontal lines and vias in multiple ILD layers. In some implementations, the devices in the device layer 1102 are coupled to each other through interconnects in the interconnect layer 1112. For example, the peripheral circuit 1104 may be coupled to the peripheral circuit 1106 through the interconnect layer 1112. The interconnects in the interconnect layer 1112 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1112 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in interconnect layer 1112 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (low detection, eg, voids) among conductive metallic materials.

[0079] 11A, the first semiconductor structure may further include a polysilicon layer 106 over and in contact with the interconnect layer 1112. The polysilicon layer 106, according to some implementations, is a doped polysilicon layer over the interconnect layer 1112, as described in more detail below with respect to the manufacturing process. It is understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0080] As shown in FIG. 11A, the first semiconductor structure 102 may also include a memory cell array, such as an array of NAND memory strings 208 overlying and contacting the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some implementations, the polysilicon layer 106 is vertically between the NAND memory strings 208 and a device layer 1102 including transistors 1108 and 1110. In some implementations, each NAND memory string 208 is a “charge trap” type NAND memory string including any suitable channel structure disclosed herein, such as the channel structure 812 described in detail above with respect to FIG. 8. In some implementations, the NAND memory strings 208 are “floating gate” type NAND memory strings, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory strings.

[0081] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as stack structures, e.g., memory stack 1127. Memory stack 1127 may be an example of memory stack 804 of FIG. 8, and the conductive and dielectric layers in memory stack 1127 may be an example of gate conductive layer 806 and dielectric layer 808, respectively, in memory stack 804. According to some implementations, the interleaved conductive and dielectric layers in memory stack 1127 alternate vertically. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line and terminate in one or more staircase structures of memory stack 1127.

[0082] As shown in FIG. 11A, the first semiconductor structure 102 may further include an interconnect layer 1128 contacting above the NAND memory string 208 to transfer electrical signals to and from the NAND memory string 208. In some implementations, the memory stack 1127 and the NAND memory string 208 are vertically between the interconnect layer 1128 and the polysilicon layer 106. The interconnect layer 1128 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in the interconnect layer 1128 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1128 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 1128 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1128 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0083] As shown in FIG. 11A, the first semiconductor structure 102 may further include one or more contacts 1124 extending vertically through the polysilicon layer 106. In some implementations, the contacts 1124 couple the interconnects in the interconnect layer 1128 to the interconnects in the interconnect layer 1112 to form an electrical connection through the polysilicon layer 106 between the NAND memory string 208 and the transistors 1108 and 1110. The contacts 1124 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contacts 1124 include W. In some implementations, the contacts 1124 include a via surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the via from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contact 1124 may be an ILV having a depth (vertical direction) at the submicron level (e.g., 10 nm to 1 μm), or a TSV having a depth (vertical direction) at the micron or tens of microns level (e.g., 1 μm to 100 μm).

[0084] As shown in FIG. 11A, the first semiconductor structure 102 may further include a bonding layer 1008 at and above the bonding interface 103 and in contact with the interconnect layer 1128. The bonding layer 1008 may include a plurality of bonding contacts and a dielectric that electrically insulates the bonding contacts. The bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the bonding contacts of the bonding layer 1008 include Cu. The remaining regions of the bonding layer 1008 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric may be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive), and may simultaneously obtain a metal-metal (e.g., Cu-Cu) bond and a dielectric-dielectric (e.g., SiO2-SiO2) bond.

[0085] As shown in FIG. 11A, the second semiconductor structure 104 can be bonded in a face-to-face manner to the top of the first semiconductor structure 102 at the bonding interface 103. The second semiconductor structure 104 can also include a bonding layer 1010 at the bonding interface 103, for example, on the opposite side of the bonding interface 103 to the bonding layer 1008 of the first semiconductor structure 102. The bonding layer 1010 can include a plurality of bonding contacts and a dielectric that electrically insulates the bonding contacts. The bonding contacts can include a conductive material, such as Cu. The remaining area of ​​the bonding layer 1010 can be formed of a dielectric material, such as silicon oxide. The bonding contacts and the surrounding dielectric within the bonding layer 1010 can be used for hybrid bonding. In some implementations, the bonding interface 103 is where the bonding layers 1008 and 1010 meet and bond. In practice, the bonding interface 103 may be a layer having a certain thickness that includes the top surface of the bonding layer 1008 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1010 of the second semiconductor structure 104 .

[0086] As shown in FIG. 11A, the second semiconductor structure 104 may further include an interconnect layer 1126 on the bonding layer 1010 to transfer electrical signals. The interconnect layer 1126 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 1126 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 1126 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1126 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 1126 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below with respect to the manufacturing process, although Cu has a relatively low thermal budget (it is not compatible with high temperature processes), the fabrication of the interconnect layer 1126 can be performed after the high temperature processes in forming the device layer 1114 in the second semiconductor structure 104 and is isolated from the high temperature processes in forming the first semiconductor structure 102, making interconnection of the interconnect layer 1126 with Cu feasible.

[0087] 11A, the second semiconductor structure 104 may include a device layer 1114 that is in contact above an interconnect layer 1126. In some implementations, the interconnect layer 1126 is vertically between the bond interface 103 and the device layer 1114. In some implementations, the device layer 1114 includes a third peripheral circuit 1116 and a fourth peripheral circuit 1118. The third peripheral circuit 1116 may include an LLV circuit 402, such as an I / O circuit (e.g., in the interface 316 and the data bus 318), and the fourth peripheral circuit 1118 may include an LV circuit 404, such as a page buffer circuit (e.g., the page buffer circuit 702 in the page buffer 304) and a logic circuit (e.g., in the control logic 312). In some implementations, the third peripheral circuit 1116 includes a plurality of transistors 1120, and the fourth peripheral circuit 1118 also includes a plurality of transistors 1122. Transistors 1120 and 1122 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some implementations, each transistor 1120 or 1122 includes a gate dielectric, and because the voltage applied to transistor 1120 is lower than that of transistor 1122, the thickness of the gate dielectric of transistor 1120 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 1122 (e.g., in LV circuit 404).

[0088] Furthermore, different voltages applied to different transistors 1120, 1122, 1108, and 1110 in the second semiconductor structure 104 and the first semiconductor structure 102 may result in differences in device dimensions between the second semiconductor structure 104 and the first semiconductor structure 102. In some implementations, because the voltage applied to transistor 1108 is higher than that of transistor 1120, the gate dielectric thickness of transistor 1108 (e.g., in HV circuit 406) is greater than the gate dielectric thickness of transistor 1120 (e.g., in LLV circuit 402). In some implementations, because the same voltage is applied to transistor 1122 and transistor 1110, the gate dielectric thickness of transistor 1122 (e.g., in LV circuit 404) is the same as the gate dielectric thickness of transistor 1110 (e.g., in LV circuit 404). In some implementations, the thickness of the semiconductor layer 1002 in which the transistor 1108 (e.g., in the HV circuit 406) is formed is greater than the thickness of the semiconductor layer 1004 in which the transistor 1120 (e.g., in the LLV circuit 402) is formed because a higher voltage is applied to the transistor 1108 than to the transistor 1120.

[0089] As shown in FIG. 11A, the second semiconductor structure 104 can further include a semiconductor layer 1004 having a semiconductor material. In some implementations, the semiconductor layer 1004 is a thinned silicon substrate having single crystal silicon in which the transistors 1120 and 1122 can be formed. The semiconductor layer 1004 can be disposed above and in contact with the transistors 1120 and 1122 of the peripheral circuits 1116 and 1118 in the device layer 1114. In some implementations, the transistors 1120 and 1122 are disposed vertically between the junction interface 103 and the semiconductor layer 1004. Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of the transistors 1120 and 1122) can also be formed on or in the semiconductor layer 1004.

[0090] 11A, the second semiconductor structure 104 can further include a pad-out interconnect layer 902 over and in contact with the semiconductor layer 1004. In some implementations, the semiconductor layer 1004 is vertically disposed between the pad-out interconnect layer 902 and the transistors 1120 and 1122. The pad-out interconnect layer 902 can include interconnects, e.g., contact pads 1132, to one or more ILD layers. The pad-out interconnect layer 902 and the interconnect layer 1126 can be formed on either side of the semiconductor layer 1004. In some implementations, the interconnects in the pad-out interconnect layer 902 can transfer electrical signals between the 3D memory device 1100 and an external device, e.g., for pad-out purposes.

[0091] As shown in FIG. 11A, the second semiconductor structure 104 may further include one or more contacts 1130 extending vertically through the semiconductor layer 1004. In some implementations, the contacts 1130 couple the interconnects in the interconnect layer 1126 to contact pads 1132 in the pad-out interconnect layer 902 to provide electrical connection through the semiconductor layer 1004. The contacts 1130 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. In some implementations, the contacts 1130 include W. In some implementations, the contacts 1130 include vias surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 1130 may be ILVs with a submicron level depth (e.g., 10 nm to 1 μm) or TSVs with a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0092] As a result, the peripheral circuits 1104, 1106, 1116, and 1118 in the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 via various interconnect structures including the interconnect layers 1112, 1126, and 1128, the bonding layers 1008 and 1010, and the contacts 1124. Additionally, the peripheral circuits 1104, 1106, 1116, and 1118 as well as the NAND memory string 208 in the 3D memory device 1100 can be further coupled to external devices via the contacts 1130 and the pad-out interconnect layer 902.

[0093] It is also understood that the pad-out of the 3D memory device is not limited to being from the second semiconductor structure 104 having the peripheral circuitry 1116 as shown in FIG. 11A (corresponding to FIG. 9A), but may also be from the first semiconductor structure 102 having the peripheral circuitry 1104 (corresponding to FIG. 9B). For example, as shown in FIG. 11B, the 3D memory device 1101 may include a pad-out interconnect layer 902 in the first semiconductor structure 102. The pad-out interconnect layer 902 may contact the semiconductor layer 1002 of the first semiconductor structure 102 in which the transistors 1108 of the peripheral circuitry 1104 are formed. In some implementations, the first semiconductor structure 102 further includes one or more contacts 1134 extending vertically through the semiconductor layer 1002. In some implementations, the contacts 1134 couple the interconnects in the interconnect layer 1112 in the first semiconductor structure 102 to the contact pads 1132 in the pad-out interconnect layer 902 to provide an electrical connection through the semiconductor layer 1002. The contacts 1134 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. In some implementations, the contacts 1134 include W. In some implementations, the contacts 1134 include vias surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contacts 1134 may be ILVs (e.g., 10 nm to 1 μm) having a submicron level thickness, or TSVs (e.g., 1 μm to 100 μm) having a micron or tens of micron level depth. For ease of explanation, it is understood that details of the same components (e.g., materials, manufacturing processes, functions, etc.) in both the 3D memory devices 1100 and 1101 will not be repeated.

[0094] 12A-12G illustrate a manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the disclosure. FIG. 13A and 13B illustrate another manufacturing process for forming the 3D memory device of FIG. 10 according to some embodiments of the disclosure. FIG. 14 illustrates a flow chart of a method 1400 for forming the 3D memory device of FIG. 10 according to some embodiments of the disclosure. Examples of 3D memory devices illustrated in FIGS. 12A-12G, 13A, 13B, and 14 include 3D memory devices 1100 and 1101 illustrated in FIGS. 11A and 11B. FIGS. 12A-12G, 13A, 13B, and 14 are described collectively. It is understood that the operations illustrated in method 1400 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 14.

[0095] Referring to FIG. 14, the method 1400 begins with operation 1402, where a first transistor is formed in a first substrate. The first substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 12A, a silicon substrate 1202 has a plurality of transistors 1204, 1206 formed therein. The transistors 1204 and 1206 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 1202, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 1204 and 1206. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 1202 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1204 is different from the thickness of the gate dielectric of transistor 1206, for example, by depositing a thicker silicon oxide film in the region of transistor 1204 than in the region of transistor 1206, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1206. It is understood that the details of fabricating transistors 1204 and 1206 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of Figures 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0096] In some implementations, an interconnect layer 1208 is formed above the transistors on the first substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 12A, the interconnect layer 1208 can be formed above the transistors 1204 and 1206. The interconnect layer 1208 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1204 and 1206. In some implementations, the interconnect layer 1208 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1208 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in Figure 12A may be collectively referred to as an interconnect layer 1208. In some implementations, the interconnects in the interconnect layer 1208 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0097] The method 1400 proceeds to operation 1404, as shown in Figure 14, where a polysilicon layer is formed above the first transistor. As shown in Figure 12A, a polysilicon layer 1211 is formed above the interconnect layer 1208 and the transistors 1204 and 1206 on the first silicon substrate 1202. The polysilicon layer 1211 may be formed by depositing polysilicon on the interconnect layer 1208 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the polysilicon layer 1211 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0098] The method 1400 proceeds to operation 1406, as shown in FIG. 14, where an array of NAND memory strings is formed on the polysilicon layer. In some implementations, a memory stack is formed on the polysilicon layer to form the array of NAND memory strings. As shown in FIG. 12C, a stack structure such as a memory stack 1226 including interleaved conductive and dielectric layers is formed on the polysilicon layer 1211. To form the memory stack 1226, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1211. In some implementations, each sacrificial layer includes a layer of silicon nitride and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1226 can then be formed by replacing the sacrificial layer with a conductive layer using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer, and filling the resulting recess with the conductive layer. In some implementations, each conductive layer comprises a metal layer, such as a layer of W. It is understood that in some examples, the memory stack 1226 may be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide is formed between the memory stack 1226 and the polysilicon layer 1211.

[0099] As shown in FIG. 12C, NAND memory strings 1228 are formed above polysilicon layer 1211, each of which extends vertically through memory stack 1226 to contact polysilicon layer 1211. In some implementations, the fabrication process for forming NAND memory strings 1228 includes forming channel holes in polysilicon layer 1211 through memory stack 1226 (or dielectric stack) using dry etching and / or wet etching such as deep reactive ion etching (DRIE), and then filling the channel holes with multiple layers such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It is understood that the fabrication details of NAND memory strings 1228 may vary depending on the type of channel structure (e.g., channel structure 812 of FIG. 8) of NAND memory strings 1228, and therefore will not be detailed for ease of explanation.

[0100] In some implementations, an interconnect layer is formed above the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 12C, an interconnect layer 1230 is formed above the memory stack 1226 and the NAND memory strings 1228. The interconnect layer 1230 can include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the NAND memory strings 1228. In some implementations, the interconnect layer 1230 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 1230 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 12D may be collectively referred to as interconnect layer 1230.

[0101] In some implementations, contacts are formed through the polysilicon layer. As shown in FIG. 12C, one or more contacts 1224 are formed, each extending vertically through the polysilicon layer 1211. The contacts 1224 can couple the interconnects in the interconnect layers 1230 and 1208. The contacts 1224 can be formed by first patterning contact holes through the polysilicon layer 1211 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0102] In some implementations, a first bonding layer is formed on the interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As shown in FIG. 12C, a bonding layer 1232 is formed above the interconnect layer 1230. The bonding layer 1232 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the interconnect layer 1230 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer and in contact with the interconnects in the interconnect layer 1230 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0103] The method 1400 proceeds to operation 1408, as shown in FIG. 14, where a second transistor is formed on a second substrate. The second substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 12D, a plurality of transistors 1214, 1216 are formed on a silicon substrate 1210 of single crystal silicon. The transistors 1214, 1216 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 1210, for example, by ion implantation and / or thermal diffusion, which serve as wells and source / drain regions of the transistors 1214 and 1216. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 1210 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1214 is different from the thickness of the gate dielectric of transistor 1216, for example, by depositing a thicker silicon oxide film in the region of transistor 1214 than in the region of transistor 1216, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1216. It is understood that the details of fabricating transistors 1214 and 1216 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0104] In some implementations, an interconnect layer 1220 is formed above the transistors on the second substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 12D, the interconnect layer 1220 can be formed above the transistors 1214 and 1216. The interconnect layer 1220 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1214 and 1216. In some implementations, the interconnect layer 1220 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1220 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 12C may be collectively referred to as an interconnect layer 1220. Unlike the interconnect layer 1208, in some implementations, the interconnects in the interconnect layer 1220 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (not compatible with high temperature processes), the elimination of high temperature processes after fabrication of the interconnect layer 1220 may make it feasible to use Cu as the conductive material for the interconnects in the interconnect layer 1220.

[0105] In some implementations, a second bonding layer is formed on the interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As shown in FIG. 12D, a bonding layer 1222 is formed above the interconnect layer 1220. The bonding layer 1222 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the interconnect layer 1220 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer and in contact with the interconnects in the interconnect layer 1220 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0106] 14, the method 1400 continues to operation 1410 where a first substrate and a second substrate are bonded in a face-to-face manner. A first bonding contact of the first bonding layer can contact a second bonding contact of the second bonding layer at a bonding interface after bonding the first and second substrates. The bonding can include a hybrid bond.

[0107] As shown in Figure 12E, silicon substrate 1210 and components formed thereon (e.g., transistors 1214 and 1216) are flipped upside down. The downward bonding layer 1222 is bonded, i.e., bonded in a face-to-face manner, with the upward bonding layer 1232, thereby forming a bonding interface 1212. That is, silicon substrate 1210 and components formed thereon can be bonded in a face-to-face manner with silicon substrate 1202 and components formed thereon such that the bonding contacts of bonding layer 1232 contact the bonding contacts of bonding layer 1222 at bonding interface 1212. In some implementations, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces prior to bonding. Although not shown in FIG. 12E, it will be understood that in some examples, the silicon substrate 1202 and the components formed thereon (e.g., transistors 1204, 1206, memory stack 1226, and NAND memory string 1228) can be flipped upside down and the downward bonding layer 1232 can be bonded with the upward bonding layer 1222, i.e., in a face-to-face manner, thereby also forming a bonding interface 1212.

[0108] As a result of bonding, e.g., hybrid bonding, the bond contacts on either side of the bond interface 1212 can intermix. After bonding, according to some embodiments, the bond contacts of bonding layer 1232 and the bond contacts of bonding layer 1222 are aligned and in contact with each other, such that memory stack 1226 and NAND memory string 1228 formed therethrough, and transistors 1204 and 1206 can be coupled to transistors 1214 and 1216 via the bond contacts across bond interface 1212.

[0109] The method 1400 proceeds to optional operation 1412, as shown in FIG. 14, where the first substrate or the second substrate is thinned. In some implementations, as shown in FIG. 12F, the silicon substrate 1210 (shown in FIG. 12E) is thinned to a semiconductor layer 1234 having single crystal silicon. The silicon substrate 1210 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In some implementations, as shown in FIG. 13A, the silicon substrate 1202 (shown in FIG. 12E) is thinned to a semiconductor layer 1302 having single crystal silicon. Similarly, the silicon substrate 1202 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0110] The method 1400 proceeds to operation 1414, where a pad-out interconnect layer is formed, as shown in Figure 14. The pad-out interconnect layer may be formed on the thinned second substrate or on the thinned first substrate.

[0111] In some implementations, a pad-out interconnect layer 1236 is formed in the semiconductor layer 1234 (thinned silicon substrate 1210), as shown in FIG. 12G. The pad-out interconnect layer 1236 can include interconnects, such as contact pads 1238, formed in one or more ILD layers. The contact pads 1238 can include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, after bonding and thinning, contacts 1235 are formed that extend vertically through the semiconductor layer 1234, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor followed by wet / dry etching. The contacts 1235 can couple the contact pads 1238 in the pad-out interconnect layer 1236 to interconnects in the interconnect layer 1220. It will be appreciated that in some examples, the contacts 1235 may be formed in the silicon substrate 1210 prior to thinning (e.g., the formation of the semiconductor layer 1234 shown in FIG. 12D ) and exposed from the back surface of the silicon substrate 1210 after thinning (when thinning occurs).

[0112] In some implementations, a pad-out interconnect layer 1306 is formed in the semiconductor layer 1302 (thinned silicon substrate 1202), as shown in FIG. 13B. The pad-out interconnect layer 1306 can include interconnects, such as contact pads 1308, formed in one or more ILD layers. The contact pads 1308 can include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, after bonding and thinning, contacts 1304 are formed that extend vertically through the semiconductor layer 1302, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor followed by wet / dry etching. The contacts 1304 can couple the contact pads 1308 in the pad-out interconnect layer 1306 to interconnects in the interconnect layer 1208. It will be appreciated that in some examples, the contacts 1304 may be formed in the silicon substrate 1202 prior to thinning (formation of the semiconductor layer 1234) and exposed from the back surface of the silicon substrate 1202 after thinning (when thinning occurs).

[0113] 15A and 15B show schematic diagrams of cross sections of the 3D memory devices of FIGS. 9A and 9B according to various aspects of the disclosure. The 3D memory devices 1500 and 1501 can be examples of the 3D memory devices 900 and 901 of FIGS. 9A and 9B. As shown in FIG. 15A, the 3D memory device 1500 can include stacked first and second semiconductor structures 102 and 104. In some implementations, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically disposed between the polysilicon layer 106 and the bonding layer 1008, and a portion of a peripheral circuit vertically disposed between the semiconductor layer 1002 and the polysilicon layer 106.

[0114] The memory cell array can include an array of NAND memory strings (e.g., NAND memory strings 208 as disclosed herein), the sources of which can be in contact with polysilicon layer 106 (e.g., as shown in FIG. 8). Polysilicon layer 106 can be a deposited polysilicon layer (e.g., either N-type doped, P-type doped, or undoped) suitable for a "floating gate" type NAND memory string, or a specific design of a channel structure (e.g., channel structure 812 in FIG. 8) in a "charge trap" type NAND memory string, suitable for, e.g., a GIDL erase operation. Bonding layer 1008 can include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts, which can be used, e.g., for hybrid junctions, as described in more detail below.

[0115] In some implementations, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not with the polysilicon layer 106. That is, the transistors (e.g., the planar transistor 500 and the 3D transistor 600) of the peripheral circuitry can be in contact with the semiconductor layer 1002. The semiconductor layer 1002 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1002 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. Direct, short-distance (e.g., sub-micron or micron level) electrical connections can be made between the memory cell array and the peripheral circuitry in the first semiconductor structure 102 via contacts (e.g., ILV / TSV) through the polysilicon layer 106.

[0116] In some implementations, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1010, and some of the peripheral circuits of the memory cell array. The semiconductor layer 1004 may be vertically between the peripheral circuits and the bonding layer 1010. Transistors of the peripheral circuits (e.g., the planar transistors 500 and the 3D transistors 600) may be in contact with the semiconductor layer 1004. Like the semiconductor layer 1002, the semiconductor layer 1004 may include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1004 in which the transistors are formed may include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. The peripheral circuits and the bonding layer 1010 may be formed on either side of the semiconductor layer 1004 such that the semiconductor layer 1004 is vertically disposed between the peripheral circuits and the bonding layer 1010. In some embodiments, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1004 and the junction contacts of the junction layer 1010 are formed on the back side of the semiconductor layer 1004 .

[0117] Similar to the bonding layer 1008 of the first semiconductor structure 102, the bonding layer 1010 may also include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts. According to some implementations, the bonding interface 103 is perpendicular to and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 may be disposed on either side of the bonding interface 103, and the bonding contacts of the bonding layer 1008 may contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, the large number (e.g., millions) of bonding contacts across the bonding interface 103, in conjunction with through contacts (e.g., ILV / TSV) through the semiconductor layer 1004, may form a direct, short-distance (e.g., micron-level) electrical connection between adjacent semiconductor structures 102 and 104.

[0118] It is understood that in some examples, the first and second semiconductor structures 102 and 104 may not include bonding layers 1008 and 1010, respectively, disposed on either side of the bonding interface 103, as shown in FIG. 15A. In FIG. 15B, the semiconductor layer 1004 in the second semiconductor structure 104 of the 3D memory device 1501 may be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, and the bonding interface 103 between the first semiconductor structure 102 and the second semiconductor structure 104 may result from a transfer bond as opposed to a hybrid bond. A short-distance (e.g., sub-micron level) electrical connection may be formed directly between adjacent semiconductor structures 102 and 104 via contacts (e.g., ILV / TSV) that penetrate the semiconductor layer 1004 vertically between the first semiconductor structure 102 and the second semiconductor structure 104.

[0119] As shown in Figures 15A and 15B, according to some embodiments, the first and second semiconductor structures 102 and 104 are joined back to back (e.g., the semiconductor layers 1002 and 1004 are disposed on the bottom surfaces of the first and second semiconductor structures 102 and 104 in Figures 15A and 15B, respectively), so that the transistors of the peripheral circuits of the first and second semiconductor structures 102 and 104 are arranged to face in the same direction (e.g., in the positive y direction in Figures 15A and 15B). In addition, in the first semiconductor structure 102, the polysilicon layer 106 is vertically disposed between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on the polysilicon layer 106 and the semiconductor layer 1002, respectively, so that the memory cell array and the peripheral circuits face in the same direction (e.g., in the positive y direction in Figures 15A and 15B). It will be understood that the pad-out interconnect layer 902 of Figures 9A and 9B has been omitted from the 3D memory devices 1500 and 1501 of Figures 15A and 15B for ease of explanation, and may be included in the 3D memory devices 1500 and 1501 as described above with respect to Figures 9A and 9B.

[0120] As mentioned above, the first semiconductor structure 102 and the second semiconductor structure 104 can have peripheral circuits with transistors with different applied voltages. For example, the second semiconductor structure 104 can be an example of the semiconductor structure 408 including the LLV circuit 402 (and in some examples the LV circuit 404) of FIG. 4B, and the first semiconductor structure 102 can be an example of the semiconductor structure 410 including the HV circuit 406 (and in some examples the LV circuit 404) of FIG. 4B, or vice versa. Thus, in some implementations, the semiconductor layers 1002 and 1004 in the first and second semiconductor structures 102 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the first semiconductor structure 102 can include the HV circuit 406 and the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 in the first semiconductor structure 102 can be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Additionally, in some implementations, the gate dielectrics of the transistors in the first and second semiconductor structures 102 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the first semiconductor structure 102 may include the HV circuitry 406 and the second semiconductor structure 104 may include the LLV circuitry 402, and the gate dielectric thickness of the transistors in the first semiconductor structure 102 may be greater (e.g., at least five times) than the gate dielectric thickness of the transistors in the second semiconductor structure 104.

[0121] 16A and 16B show side views of various examples of the 3D memory devices 1500 and 1501 of FIGs. 15A and 15B according to various aspects of the disclosure. As shown in FIG. 16A, as an example of the 3D memory devices 1500 and 1501 of FIGs. 15A and 15B, the 3D memory device 1600 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of each other in different planes in the vertical direction (e.g., the y-direction in FIG. 16A), according to some implementations. According to some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 103 therebetween.

[0122] As shown in FIG. 16A, the first semiconductor structure 102 may include a semiconductor layer 1002 having a semiconductor material. In some implementations, the semiconductor layer 1002 is a silicon substrate having single crystal silicon. The first semiconductor structure 102 may also include a device layer 1602 above and in contact with the semiconductor layer 1002. In some implementations, the device layer 1602 includes a first peripheral circuit 1604 and a second peripheral circuit 1606. The first peripheral circuit 1604 may include HV circuits 406 such as drive circuits (e.g., string drivers 704 in row decoder / word line driver 308 and drivers in column decoder / bit line driver 306), and the second peripheral circuit 1606 may include LV circuits 404 such as page buffer circuits (e.g., page buffer circuit 702 in page buffer 304) and logic circuits (e.g., control logic 312). In some implementations, the first peripheral circuit 1604 includes a plurality of transistors 1608 in contact with the semiconductor layer 1002, and the second peripheral circuit 1606 includes a plurality of transistors 1610 in contact with the semiconductor layer 1002. The transistors 1608 and 1610 can include any transistor disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some implementations, each transistor 1608 or 1610 includes a gate dielectric, and because the voltage applied to the transistor 1608 is higher than that of the transistor 1610, the thickness of the gate dielectric of the transistor 1608 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistor 1610 (e.g., in the LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of the transistors 1608 and 1610) can also be formed on or in the semiconductor layer 1002.

[0123] In some implementations, the first semiconductor structure 102 further includes an interconnect layer 1612 on the device layer 1602 to transfer electrical signals between the peripheral circuits 1606 and 1604. As shown in FIG. 16A, the interconnect layer 1612 can be vertically between the polysilicon layer 106 and the device layer 1602 (including the transistors 1608 and 1610 of the peripheral circuits 1604 and 1606). The interconnect layer 1612 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnects in the interconnect layer 1612 can be coupled to the transistors 1608 and 1610 of the peripheral circuits 1604 and 1606 in the device layer 1602. The interconnect layer 1612 can further include one or more ILD layers in which horizontal lines and vias can be formed. That is, the interconnect layer 1612 can include horizontal lines and vias in multiple ILD layers. In some implementations, the devices in the device layer 1602 are coupled to each other through interconnects in the interconnect layer 1612. For example, the peripheral circuitry 1604 may be coupled to the peripheral circuitry 1606 through the interconnect layer 1612. The interconnects in the interconnect layer 1612 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1612 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 1612 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (less detectable, e.g., voids) among conductive metal materials.

[0124] 16A, the first semiconductor structure may further include a polysilicon layer 106 over and in contact with the interconnect layer 1612. The polysilicon layer 106, according to some implementations, is a doped polysilicon layer over the interconnect layer 1612, as described in more detail below with respect to the manufacturing process. It is understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0125] As shown in FIG. 16A, the first semiconductor structure 102 may also include a memory cell array, such as an array of NAND memory strings 208 overlying and contacting the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some implementations, the polysilicon layer 106 is vertically between the NAND memory strings 208 and a device layer 1602 including transistors 1608 and 1610. In some implementations, each NAND memory string 208 is a “charge trap” type NAND memory string including any suitable channel structure disclosed herein, such as the channel structure 812 described in detail above with respect to FIG. 8. In some implementations, the NAND memory strings 208 are “floating gate” type NAND memory strings, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory strings.

[0126] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as stack structures, e.g., memory stack 1627. Memory stack 1627 may be an example of memory stack 804 of FIG. 8, and the conductive and dielectric layers in memory stack 1627 may be an example of gate conductive layer 806 and dielectric layer 808, respectively, in memory stack 804. According to some implementations, the interleaved conductive and dielectric layers in memory stack 1627 alternate vertically. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line and terminate in one or more staircase structures of memory stack 1627.

[0127] As shown in FIG. 16A, the first semiconductor structure 102 may further include an interconnect layer 1628 contacting above the NAND memory string 208 to transfer electrical signals to and from the NAND memory string 208. In some implementations, the memory stack 1627 and the NAND memory string 208 are vertically between the interconnect layer 1628 and the polysilicon layer 106. The interconnect layer 1628 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in the interconnect layer 1628 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1628 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 1628 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1628 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0128] As shown in FIG. 16A, the first semiconductor structure 102 may further include one or more contacts 1624 extending vertically through the polysilicon layer 106. In some implementations, the contacts 1624 couple the interconnects in the interconnect layer 1628 to the interconnects in the interconnect layer 1612 to form an electrical connection through the polysilicon layer 106 between the NAND memory string 208 and the transistors 1608 and 1610. The contacts 1624 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contacts 1624 include W. In some implementations, the contacts 1624 include a via surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the via from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contacts 1624 can be ILVs having a submicron level depth (e.g., 10 nm to 1 μm) or TSVs having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0129] As shown in FIG. 16A, the first semiconductor structure 102 may further include a bonding layer 1008 at and above the bonding interface 103 and in contact with the interconnect layer 1628. The bonding layer 1008 may include a plurality of bonding contacts and a dielectric that electrically insulates the bonding contacts. The bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the bonding contacts of the bonding layer 1008 include Cu. The remaining regions of the bonding layer 1008 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric may be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive), and may simultaneously obtain a metal-metal (e.g., Cu-Cu) bond and a dielectric-dielectric (e.g., SiO2-SiO2) bond.

[0130] As shown in FIG. 16A, the second semiconductor structure 104 can be bonded back-to-back to the top of the first semiconductor structure 102 at the bond interface 103. The second semiconductor structure 104 can also include a bonding layer 1010 at the bond interface 103, e.g., on the opposite side of the bond interface 103 to the bonding layer 1008 of the first semiconductor structure 102. The bonding layer 1010 can include a plurality of bonding contacts and a dielectric that electrically insulates the bonding contacts. The bonding contacts can include a conductive material, such as Cu. The remaining area of ​​the bonding layer 1010 can be formed of a dielectric material, such as silicon oxide. The bonding contacts and the surrounding dielectric within the bonding layer 1010 can be used for hybrid bonding. In some implementations, the bond interface 103 is where the bonding layers 1008 and 1010 meet and bond. In practice, the bonding interface 103 may be a layer having a certain thickness that includes the top surface of the bonding layer 1008 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1010 of the second semiconductor structure 104 .

[0131] As shown in FIG. 16A, the second semiconductor structure 104 can further include a semiconductor layer 1004 having a semiconductor material. A bonding layer 1010 can be formed on the back surface of the semiconductor layer 1004 and can be vertically disposed between the semiconductor layer 1004 and the bonding interface 103. In some implementations, the semiconductor layer 1004 is a thinned silicon substrate having single crystal silicon. The second semiconductor structure 104 can also include a device layer 1614 in contact above the semiconductor layer 1004. In some implementations, the device layer 1614 includes a third peripheral circuit 1616 and a fourth peripheral circuit 1618 in contact above the semiconductor layer 1004. In some implementations, the semiconductor layer 1004 is vertically disposed between the bonding interface 103 and the device layer 1614 having the peripheral circuits 1616 and 1618. The third peripheral circuit 1616 can include LLV circuitry 402, such as I / O circuitry (e.g., in the interface 316 and data bus 318), and the fourth peripheral circuit 1618 can include LV circuitry 404, such as a page buffer circuit (e.g., the page buffer circuit 702 in the page buffer 304) and logic circuitry (e.g., in the control logic 312). In some implementations, the third peripheral circuit 1616 includes a plurality of transistors 1620, and the fourth peripheral circuit 1618 also includes a plurality of transistors 1622. The transistors 1620 and 1622 can include any transistor disclosed herein, such as the planar transistors 500 and the 3D transistors 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1620 or 1622 includes a gate dielectric, and because the voltage applied to transistor 1620 is lower than that of transistor 1622, the thickness of the gate dielectric of transistor 1620 (e.g., in LLV circuit 402) is smaller than the thickness of the gate dielectric of transistor 1622 (e.g., in LV circuit 404).

[0132] Furthermore, different voltages applied to different transistors 1620, 1622, 1608, and 1610 in the second semiconductor structure 104 and the first semiconductor structure 102 may result in differences in device dimensions between the second semiconductor structure 104 and the first semiconductor structure 102. In some implementations, because the voltage applied to transistor 1608 is higher than that of transistor 1620, the gate dielectric thickness of transistor 1620 (e.g., in HV circuit 406) is greater than the gate dielectric thickness of transistor 1608 (e.g., in LLV circuit 402). In some implementations, because the same voltage is applied to transistor 1622 and transistor 1610, the gate dielectric thickness of transistor 1622 (e.g., in LV circuit 404) is the same as the gate dielectric thickness of transistor 1610 (e.g., in LV circuit 404). In some implementations, the thickness of the semiconductor layer 1002 in which the transistor 1608 (e.g., in the HV circuit 406) is formed is greater than the thickness of the semiconductor layer 1004 in which the transistor 1620 (e.g., in the LLV circuit 402) is formed because a higher voltage is applied to the transistor 1608 than to the transistor 1620.

[0133] As shown in FIG. 16A, the second semiconductor structure 104 may further include an interconnect layer 1626 in contact above the device layer 1614 to transfer electrical signals to and from the transistors 1620 and 1622 of the peripheral circuits 1616 and 1618. The interconnect layer 1626 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 1626 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 1626 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1626 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 1626 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below with respect to the manufacturing process, although Cu has a relatively low thermal budget (not compatible with high temperature processes), the fabrication of the interconnect layer 1626 can be performed after the high temperature processes in forming the device layer 1614 in the second semiconductor structure 104 and is isolated from the high temperature processes in forming the first semiconductor structure 102, making interconnection of the interconnect layer 1626 with Cu feasible.

[0134] As shown in FIG. 16A, the second semiconductor structure 104 can also include one or more contacts 1630 that extend vertically through the semiconductor layer 1004. In some implementations, the contacts 1630, along with the junction contacts across the junction interface 103, couple the interconnects in the interconnect layer 1626 to the interconnects in the interconnect layer 1628 to form an electrical connection through the semiconductor layer 1004 between the NAND memory string 208 and the transistors 1620 and 1622. The contacts 1630 can include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, the contacts 1630 include Cu. In some implementations, the contacts 1630 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 1630 can be ILVs having a submicron level depth (e.g., 10 nm to 1 μm) or TSVs having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0135] As shown in FIG. 16A, the second semiconductor structure 104 can further include a pad-out interconnect layer 902 above the interconnect layer 1626 and the transistors 1620 and 1622. In some implementations, the transistors 1620 and 1622 are vertically disposed between the pad-out interconnect layer 902 and the semiconductor layer 1004. The pad-out interconnect layer 902 can include interconnects, e.g., contact pads 1632, to one or more ILD layers. The pad-out interconnect layer 902 and the interconnect layer 1626 can be formed on the same side of the semiconductor layer 1004. In some implementations, the interconnects in the pad-out interconnect layer 902 can transfer electrical signals between the 3D memory device 1600 and an external device, e.g., for pad-out purposes.

[0136] As a result, the peripheral circuits 1604, 1606, 1616, and 1618 of the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 of the first semiconductor structure 102 via various interconnect structures, including the interconnect layers 1612, 1626, and 1628, the bonding layers 1008 and 1010, and the contacts 1624 and 1630. Additionally, the peripheral circuits 1604, 1606, 1616, and 1618 and the NAND memory string 208 in the 3D memory device 1600 can be further coupled to external devices via the contacts 1630 and the pad-out interconnect layer 902.

[0137] It is understood that the pad-out of the 3D memory device is not limited to being from the second semiconductor structure 104 having the peripheral circuitry 1616 as shown in FIG. 16A (corresponding to FIG. 9A), but may also be from the first semiconductor structure 102 having the peripheral circuitry 1604 (corresponding to FIG. 9B). For example, as shown in FIG. 16B, the 3D memory device 1601 may include a pad-out interconnect layer 902 in the first semiconductor structure 102. The pad-out interconnect layer 902 may contact the semiconductor layer 1002 of the first semiconductor structure 102 in which the transistors 1608 of the peripheral circuitry 1604 are formed. In some implementations, the first semiconductor structure 102 further includes one or more contacts 1634 extending vertically through the semiconductor layer 1002. In some implementations, the contacts 1634 couple the interconnects in the interconnect layer 1612 in the first semiconductor structure 102 to the contact pads 1632 in the pad-out interconnect layer 902 to provide an electrical connection through the semiconductor layer 1002. The contact 1634 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, the contact 1634 includes W. In some implementations, the contact 1634 includes a via surrounded by a dielectric spacer (e.g., including silicon oxide) to electrically isolate the via from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contact 1634 may be an ILV having a submicron level depth (e.g., 10 nm to 1 μm) or a TSV having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0138] As shown in FIG. 16B, the second semiconductor structure 104 can further include a passivation layer 1650, which replaces the pad-out interconnect layer 902 of FIG. 16A, to protect and encapsulate the 3D memory device 1601 from the side of the second semiconductor structure 104 without the pad-out interconnect layer 902. The passivation layer 1650 can include a dielectric material such as silicon nitride and / or silicon oxide. In some implementations, the second semiconductor structure 104 of the 3D memory device 1601 further includes a handle / carrier substrate 1651 that contacts the passivation layer 1650 as a base substrate of the 3D memory device 1601 to provide support. It is understood that in some examples, the passivation layer 1650 may be omitted or combined with the handle substrate 1651 as a single layer for support and protection.

[0139] It is also understood that in some examples, the first and second semiconductor structures 102 and 104 of the 3D memory device 1601 may not include the bonding layers 1008 and 1010, respectively, as shown in FIG. 16B. The bonding interface 103 may result from a transfer bonding process, and the semiconductor layer 1004 may be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, as described in detail below with respect to the manufacturing process. In some implementations, a dielectric layer (e.g., a silicon oxide layer) is formed vertically between the bonding interface 103 and the semiconductor layer 1004 and / or between the bonding interface 105 and the interconnect layer 1628 to facilitate the transfer bonding of the semiconductor layer 1004 onto the interconnect layer 1628. Thus, it is understood that in some examples, the bonding interface 103 may include a surface of a dielectric layer. It is further understood that for ease of explanation, details of identical components (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 1600 and 1601 are not repeated.

[0140] 17A-17H illustrate a manufacturing process for forming the 3D memory device of FIG. 15A and 15B according to some embodiments of the present disclosure. FIG. 19 illustrates a flowchart of a method 1900 for forming the 3D memory device of FIG. 15A and 15B according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIG. 17A-17H and FIG. 19 includes the 3D memory device 1600 illustrated in FIG. 16A. FIGS. 17A-17H and FIG. 19 are described together. It is understood that the operations illustrated in method 1900 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 19.

[0141] Referring to FIG. 19, the method 1900 begins with operation 1902, where a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 17A, a silicon substrate 1702 has a plurality of transistors 1704, 1706 formed thereon. The transistors 1704, 1706 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 1702, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 1704 and 1706. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 1702 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1704 is different from the thickness of the gate dielectric of transistor 1706, for example, by depositing a thicker silicon oxide film in the region of transistor 1704 than in the region of transistor 1706, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1706. It is understood that the details of fabricating transistors 1704 and 1706 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0142] In some implementations, an interconnect layer 1708 is formed above the transistors on the first substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 17A, the interconnect layer 1708 can be formed above the transistors 1704 and 1706. The interconnect layer 1708 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1704 and 1706. In some implementations, the interconnect layer 1708 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1708 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 17A may be collectively referred to as an interconnect layer 1708. In some implementations, the interconnects in the interconnect layer 1708 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0143] The method 1900 continues with operation 1904, as shown in Figure 19, where a polysilicon layer is formed above the first transistor. As shown in Figure 17B, a polysilicon layer 1711 is formed above the interconnect layer 1708 and the transistors 1704 and 1706 on the first silicon substrate 1702. The polysilicon layer 1711 may be formed by depositing polysilicon on the interconnect layer 1708 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the polysilicon layer 1711 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0144] The method 1900 proceeds to operation 1906, as shown in FIG. 19, where an array of NAND memory strings is formed on the polysilicon layer. In some implementations, a memory stack is formed on the polysilicon layer to form the array of NAND memory strings. As shown in FIG. 17C, a stack structure such as a memory stack 1726 including interleaved conductive and dielectric layers is formed on the polysilicon layer 1711. To form the memory stack 1726, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1711. In some implementations, each sacrificial layer includes a layer of silicon nitride and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1726 can then be formed by replacing the sacrificial layer with a conductive layer using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer, and filling the resulting recess with the conductive layer. In some implementations, each conductive layer comprises a metal layer, such as a layer of W. It is understood that in some examples, the memory stack 1726 may be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide is formed between the memory stack 1726 and the polysilicon layer 1711.

[0145] As shown in FIG. 17C, NAND memory strings 1728 are formed above polysilicon layer 1711, each of which extends vertically through memory stack 1726 to contact polysilicon layer 1711. In some implementations, the fabrication process for forming NAND memory strings 1728 includes forming a channel hole in polysilicon layer 1711 through memory stack 1726 (or dielectric stack) using dry etching and / or wet etching such as DRIE, and then filling the channel hole with multiple layers such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. It is understood that the fabrication details of NAND memory strings 1728 may vary depending on the type of channel structure (e.g., channel structure 812 of FIG. 8) of NAND memory string 1728, and therefore will not be detailed for ease of explanation.

[0146] In some implementations, an interconnect layer is formed above the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 17C, an interconnect layer 1730 is formed above the memory stack 1726 and the NAND memory strings 1728. The interconnect layer 1730 can include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the NAND memory strings 1728. In some implementations, the interconnect layer 1730 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 1730 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 17C may be collectively referred to as interconnect layer 1730.

[0147] In some implementations, contacts are formed through the polysilicon layer. As shown in FIG. 17C, one or more contacts 1724 are formed, each extending vertically through the polysilicon layer 1711. The contacts 1724 can couple the interconnects in the interconnect layers 1730 and 1708. The contacts 1724 can be formed by first patterning contact holes through the polysilicon layer 1711 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0148] In some implementations, a first bonding layer is formed on the interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As shown in FIG. 12C, a bonding layer 1732 is formed above the interconnect layer 1730. The bonding layer 1732 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the interconnect layer 1730 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer and in contact with the interconnects in the interconnect layer 1730 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0149] The method 1900 continues to operation 1908, as shown in FIG. 19, where a second transistor is formed on the front side of a second substrate. The second substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 17D, a plurality of transistors 1714, 1716 are formed on the front side of a silicon substrate 1710 of single crystal silicon. The transistors 1714, 1716 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 1710, for example, by ion implantation and / or thermal diffusion, which serve as wells and source / drain regions of the transistors 1714 and 1716. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 1710 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1714 is different from the thickness of the gate dielectric of transistor 1716, for example, by depositing a thicker silicon oxide film in the region of transistor 1714 than in the region of transistor 1716, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1716. It is understood that the details of fabricating transistors 1714 and 1716 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0150] In some implementations, an interconnect layer is formed above the transistors on the second substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 17D, an interconnect layer 1720 can be formed above the transistors 1714 and 1716. The interconnect layer 1720 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1714 and 1716. In some implementations, the interconnect layer 1720 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1720 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 17D may be collectively referred to as an interconnect layer 1720. Unlike the interconnect layer 1708, in some implementations, the interconnects in the interconnect layer 1720 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (not compatible with high temperature processes), the elimination of high temperature processes after fabrication of the interconnect layer 1720 may make it feasible to use Cu as the conductive material for the interconnects in the interconnect layer 1720.

[0151] In some implementations, contacts are formed through the thinned second substrate. As shown in FIG. 17D, contacts 1718 are formed that extend vertically from the front side of the silicon substrate 1710 into the silicon substrate 1710. The contacts 1718 can be coupled to interconnects in the interconnect layer 1720. The contacts 1718 can be formed by first patterning contact holes in the silicon substrate 1710 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0152] In some implementations, the second substrate is thinned. As shown in FIG. 17E, a silicon substrate 1710 (shown in FIG. 17D) is thinned to a semiconductor layer 1709 having single crystal silicon. The silicon substrate 1710 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. The thickness of the semiconductor layer 1709 can be controlled to expose the contacts 1718 from the backside of the thinned silicon substrate 1710, for example, by controlling the duration of the CMP process. It is understood that in some examples, the contacts 1718 can be formed through the semiconductor layer 1709 from its backside after thinning, as opposed to the silicon substrate 1710 before thinning. In some implementations, a passivation layer 1721 is formed on the interconnect layer 1720 prior to thinning by depositing a dielectric material, such as silicon nitride, on the interconnect layer 1720 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The handle substrate 1701 can then be attached to the passivation layer 1721 prior to thinning, for example using adhesive bonding, to allow for subsequent backside processes on the silicon substrate 1710 such as thinning, contact formation, and bonding.

[0153] In some implementations, a second bonding layer is formed on the back side of the thinned second substrate. The second bonding layer can include a plurality of second bonding contacts. As shown in FIG. 17F, a bonding layer 1722 is formed on the back side of the semiconductor layer 1709 (i.e., the thinned silicon substrate 1710). The bonding layer 1722 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the back side of the semiconductor layer 1709 (opposite the front side where the transistors 1714 and 1716 are formed) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer to contact the contacts 1718 on the back side of the thinned silicon substrate 1710 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material of the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0154] 19, the method 1900 continues to operation 1910 where a first substrate and a second substrate are bonded in a back-to-back manner. A first bonding contact of the first bonding layer can contact a second bonding contact of the second bonding layer at a bonding interface after bonding the first and second substrates. The bonding can include a hybrid bond.

[0155] As shown in FIG. 17G, the silicon substrate 1702 and components formed thereon (e.g., transistors 1704 and 1706 and NAND memory string 1728) and the thinned silicon substrate 1710 (i.e., semiconductor layer 1709) and components formed thereon (e.g., transistors 1714 and 1716) are bonded (i.e., face-to-face) with the bonding layer 1732 facing the front side of the silicon substrate 1702 up and the bonding layer 1722 facing the back side of the thinned silicon substrate 1710 down to form a bonding interface 1712. That is, the silicon substrate 1702 and components formed thereon can be bonded back-to-back with the thinned silicon substrate 1710 and components formed thereon such that the bonding contacts of the bonding layer 1732 contact the bonding contacts of the bonding layer 1722 at the bonding interface 1712. In some implementations, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces before bonding. As a result of bonding, e.g., hybrid bonding, the bond contacts on either side of the bond interface 1712 can intermix. After bonding, according to some implementations, the bond contacts of bonding layer 1732 and the bond contacts of bonding layer 1722 are aligned and in contact with one another, such that memory stack 1726 and NAND memory string 1728 formed therethrough, as well as transistors 1704 and 1706, can be coupled to transistors 1714 and 1716 via the bond contacts across bond interface 1712.

[0156] The method 1900 continues to optional operation 1912, as shown in Figure 19, where the first substrate is thinned. As shown in Figure 17H, the silicon substrate 1702 (shown in Figure 17G) is thinned into a semiconductor layer 1703 having single crystal silicon. The silicon substrate 1702 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0157] The method 1900 proceeds to operation 1914, as shown in FIG. 19, in which a pad-out interconnect layer is formed. The pad-out interconnect layer may be formed on the thinned first substrate. As shown in FIG. 17H, a pad-out interconnect layer 1736 is formed on the semiconductor layer 1703 (thinned silicon substrate 1702). The pad-out interconnect layer 1736 may include interconnects such as contact pads 1938 formed on one or more ILD layers. The contact pads 1738 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, after bonding and thinning, contacts 1734 are formed that extend vertically through the semiconductor layer 1703, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor followed by wet / dry etching. The contacts 1734 can couple contact pads 1738 in the pad-out interconnect layer 1736 to interconnects in the interconnect layer 1708. It is understood that in some examples, the contacts 1734 can be formed in the silicon substrate 1702 prior to thinning (e.g., the formation of the semiconductor layer 1703 shown in FIG. 17G) and exposed from the back side of the silicon substrate 1702 after thinning (where thinning occurs).

[0158] In some implementations, after operation 1910, optional operation 1912 is skipped and method 1900 proceeds to operation 1914, as shown in Figure 19, where a pad-out interconnect layer is formed. The pad-out interconnect layer may be formed above the second transistor. Although not shown in Figure 17G, it is understood that in some examples, after removing handle substrate 1701 and passivation layer 1721, a pad-out interconnect layer having contact pads may be formed above interconnect layer 1720 and transistors 1716 and 1714.

[0159] 18A-18F illustrate another manufacturing process for forming the 3D memory device of FIG. 15A and 15B according to some embodiments of the present disclosure. FIG. 20 illustrates a flowchart of another method 2000 for forming the 3D memory device of FIG. 15A and 15B according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIG. 18A-18F and FIG. 20 includes the 3D memory device 1601 illustrated in FIG. 16B. FIGS. 18A-18F and FIG. 20 are described together. It is understood that the operations illustrated in method 2000 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 20.

[0160] Referring to FIG. 20, the method 2000 begins with operation 2002, where a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 18A, a silicon substrate 1802 has a plurality of transistors 1804, 1806 formed thereon. The transistors 1804, 1806 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 1802, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 1804 and 1806. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 1802 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1804 is different from the thickness of the gate dielectric of transistor 1806, for example, by depositing a thicker silicon oxide film in the region of transistor 1804 than in the region of transistor 1806, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1806. It is understood that the details of fabricating transistors 1804 and 1806 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0161] In some implementations, an interconnect layer 1808 is formed above the transistors on the first substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 18A, the interconnect layer 1808 can be formed above the transistors 1804 and 1806. The interconnect layer 1808 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1804 and 1806. In some implementations, the interconnect layer 1808 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1808 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 18A may be collectively referred to as an interconnect layer 1808. In some implementations, the interconnects in the interconnect layer 1808 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0162] The method 2000 proceeds to operation 2004, as shown in Figure 20, where a polysilicon layer is formed above the first transistor. As shown in Figure 18B, a polysilicon layer 1811 is formed above the interconnect layer 1808 and the transistors 1804 and 1806 on the first silicon substrate 1802. The polysilicon layer 1811 may be formed by depositing polysilicon on the interconnect layer 1808 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the polysilicon layer 1811 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0163] The method 2000 proceeds to operation 2006, as shown in FIG. 20, where an array of NAND memory strings is formed on the polysilicon layer. In some implementations, a memory stack is formed on the polysilicon layer to form the array of NAND memory strings. As shown in FIG. 18C, a stack structure such as a memory stack 1826 including interleaved conductive and dielectric layers is formed on the polysilicon layer 1811. To form the memory stack 1826, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1811. In some implementations, each sacrificial layer includes a layer of silicon nitride and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1826 can then be formed by replacing the sacrificial layer with a conductive layer using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer, and filling the resulting recess with the conductive layer. In some implementations, each conductive layer comprises a metal layer, such as a layer of W. It is understood that in some examples, the memory stack 1826 may be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide is formed between the memory stack 1826 and the polysilicon layer 1811.

[0164] As shown in FIG. 18C, NAND memory strings 1828 are formed above polysilicon layer 1811, each of which extends vertically through memory stack 1826 to contact polysilicon layer 1811. In some implementations, the fabrication process for forming NAND memory strings 1828 includes forming channel holes in polysilicon layer 1811 through memory stack 1826 (or dielectric stack) using dry etching and / or wet etching such as DRIE, and then filling the channel holes with multiple layers such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It is understood that the fabrication details of NAND memory strings 1828 may vary depending on the type of channel structure (e.g., channel structure 812 of FIG. 8) of NAND memory strings 1828, and therefore will not be detailed for ease of explanation.

[0165] In some implementations, an interconnect layer is formed above the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 18C, an interconnect layer 1830 is formed above the memory stack 1826 and the NAND memory strings 1828. The interconnect layer 1830 can include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the NAND memory strings 1828. In some implementations, the interconnect layer 1830 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 1830 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 18C may be collectively referred to as interconnect layer 1830.

[0166] In some implementations, contacts are formed through the polysilicon layer. As shown in FIG. 18C, one or more contacts 1817 are formed, each extending vertically through the polysilicon layer 1811. The contacts 1817 can couple the interconnects in the interconnect layers 1830 and 1808. The contacts 1817 can be formed by first patterning contact holes through the polysilicon layer 1811 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0167] The method 2000 proceeds to operation 2008, as shown in Figure 20, where a polysilicon layer is formed above the NAND memory string. The semiconductor layer can include single crystal silicon. In some implementations, another substrate is bonded to the first substrate in a face-to-face manner to form the semiconductor layer, and the other substrate is thinned to leave the semiconductor layer. The bonding can include transfer bonding. The other substrate can be a silicon substrate having single crystal silicon.

[0168] As shown in FIG. 18D, a semiconductor layer 1810, such as a single crystal silicon layer, is formed above the interconnect layer 1830 and the NAND memory string 1828. The semiconductor layer 1810 can be attached above the interconnect layer 1830 to form a bonded interface 1812 vertically between the semiconductor layer 1810 and the interconnect layer 1830. In some implementations, to form the semiconductor layer 1810, another silicon substrate (not shown in FIG. 18D) and the silicon substrate 1802 are bonded in a face-to-face manner (components such as the NAND memory string 1828 and transistors 1804 and 1806 are formed in the silicon substrate 1802 and face the other silicon substrate) using transfer bonding, thereby forming the bonded interface 1812. The other silicon substrate can then be thinned using any suitable process to leave the semiconductor layer 1810 attached above the interconnect layer 1830.

[0169] 34A-34D illustrate a manufacturing process for transfer bonding according to some embodiments of the present disclosure. As shown in FIG. 34A, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 can include device layers, interconnect layers, and / or any suitable layers disclosed herein, such as transistors 1804 and 1806, polysilicon layer 106, memory stack 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 of FIG. 18C. A transfer substrate 3406, such as a silicon substrate having single crystal silicon, is provided. In some implementations, the transfer substrate 3406 is a single crystal silicon substrate. As shown in FIG. 34B, the transfer substrate 3406 and base substrate 3402 (and the functional layer 3404 formed thereon) can be bonded in a face-to-face manner using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonded interface 3410 between the transfer substrate 3406 and the base substrate 3402. In one example, pressure and heat can be used to perform fusion bonding between layers of silicon to silicon, silicon to silicon oxide, or silicon oxide to silicon oxide. In another example, voltage, pressure, and heat can be used to perform anodic bonding between layers of silicon oxide (in ionic glass) to silicon. It is understood that depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) may be formed on one or both sides of the bonding interface 3410. For example, a silicon oxide layer can be formed on the top surface of both the transfer substrate 3406 and the functional layer 3404 to enable SiO2-SiO2 bonding using fusion bonding. Alternatively, a silicon oxide layer can be formed only on the functional layer 3404 to enable SiO2-Si bonding using anodic or fusion bonding. In some implementations where a silicon oxide layer is formed on the transfer substrate 3406 (e.g., as shown in FIG. 34B), the transfer substrate 3406 can be flipped up so that the silicon oxide layer on the transfer substrate 3406 faces downward toward the base substrate 3402 before bonding.

[0170] As shown in FIG. 34C, a cutting layer 3412 can be formed in the transfer substrate 3406 using, for example, ion implantation. In some implementations, light elements such as hydrogen ions can be implanted into the transfer substrate 3406 to a desired depth, for example by controlling the energy of the ion implantation process, to form the cutting layer 3412. As shown in FIG. 34D, the transfer substrate 3406 can be thinned to leave only the semiconductor layer 3414 vertically between the cutting layer 3412 and the bond interface 3410. In some implementations, the transfer substrate 3406 is split at the cutting layer 3412 by applying a mechanical force to the transfer substrate 3406, i.e., peeling the remaining portion of the transfer substrate 3406 from the semiconductor layer 3414. It is understood that the transfer substrate 3406 may be split at the cutting layer 3412 by any suitable means, such as but not limited to only mechanical forces, such as thermal means, acoustic means, or any combination thereof. As a result, the semiconductor layer 3414 can be transferred from the transfer substrate 3406 and bonded onto the base substrate 3402 (and the functional layer 3404) using a transfer bonding process. In some implementations, a planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor layer 3412 to polish and smooth the top surface of the semiconductor layer 3412 and adjust the thickness of the semiconductor layer 3412. Thus, the semiconductor layer 3414 can have the same material as the transfer substrate 3406, such as single crystal silicon. The thickness of the semiconductor layer 3414 can be determined by the depth of the cut layer 3412, for example, by adjusting the implantation energy and / or by the planarization process. Furthermore, the remaining portion of the transfer substrate 3406 can be reused in the same manner to form semiconductor layers bonded to other base substrates, thereby reducing the material cost of the transfer bonding process.

[0171] 35A-35D show another manufacturing process of transfer bonding according to some embodiments of the present disclosure. As shown in FIG. 35A, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 can include device layers, interconnect layers, and / or any suitable layers disclosed herein, such as the transistors 1804 and 1806, polysilicon layer 106, memory stack 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 of FIG. 18C. The SOI substrate 3502 including the base / handle layer 3504, buried oxide layer (BOx) 3506, and device layer 3508 can be flipped upside down toward the base substrate 3402. As shown in FIG. 35B, the SOI substrate 3502 and the base substrate 3402 (and the functional layer 3404 formed thereon) can be bonded in a face-to-face manner using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonded interface 3512 between the SOI substrate 3502 and the base substrate 3402. In one example, pressure and heat can be used to perform fusion bonding between layers of silicon to silicon, silicon to silicon oxide, or silicon oxide to silicon oxide. In another example, voltage, pressure, and heat can be used to perform anodic bonding between layers of silicon oxide (in ionic glass) to silicon. It is understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) may be formed on one or both sides of the bonded interface 3512. For example, a silicon oxide layer can be formed on the top surface of both the SOI substrate 3502 and the functional layer 3404 to enable SiO2-SiO2 bonding using fusion bonding. Alternatively, a silicon oxide layer may be formed only on the functional layer 3404, and SiO2-Si bonding may be performed by anodic bonding or fusion bonding.

[0172] As shown in FIGS. 35C and 35D, the SOI substrate 3502 (shown in FIG. 35B) can be thinned, for example, by sequentially removing the base / handle layer 3504 and the buried oxide layer 3506 using wet / dry etching and / or CMP processes to leave only the device layer 3508 (as a semiconductor layer) at the bonding interface 3512. As a result, the device layer 3508 can be transferred from the SOI substrate 3502 and bonded onto the base substrate 3402 (and the functional layer 3404) as a semiconductor layer using another transfer bonding process. Thus, the transferred semiconductor layer can have the same material as the device layer 3508, such as single crystal silicon. The thickness of the semiconductor layer can be the same as the thickness of the device layer 3508. It is understood that in some examples, the device layer 3508 can be further thinned using wet / dry etching and / or CMP processes such that the transferred semiconductor layer can be thinner than the device layer 3508.

[0173] Referring back to FIG. 20, the method 2000 proceeds to operation 2008 where a second transistor is formed in the semiconductor layer. As shown in FIG. 18E, a semiconductor layer 1810 having single crystal silicon has a plurality of transistors 1814, 1816 formed therein. The transistors 1814, 1816 may be formed by a number of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the semiconductor layer 1810, for example, by ion implantation and / or thermal diffusion to function as wells and source / drain regions of the transistors 1814 and 1816. In some implementations, isolation regions (e.g., STI) are also formed in the semiconductor layer 1810 by wet / dry etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 1814 is different from the thickness of the gate dielectric of transistor 1816, for example, by depositing a thicker silicon oxide film in the region of transistor 1814 than in the region of transistor 1816, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1816. It is understood that the details of fabricating transistors 1814 and 1816 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0174] In some implementations, an interconnect layer is formed above the transistors on the second substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 18E, an interconnect layer 1820 can be formed above the transistors 1814 and 1816. The interconnect layer 1820 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 1814 and 1816. In some implementations, the interconnect layer 1820 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 1820 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 17D may be collectively referred to as an interconnect layer 1820. Unlike the interconnect layer 1808, in some implementations, the interconnects in the interconnect layer 1820 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (not compatible with high temperature processes), the elimination of high temperature processes after fabrication of the interconnect layer 1820 may make it feasible to use Cu as the conductive material for the interconnects in the interconnect layer 1820.

[0175] In some implementations, contacts are formed that penetrate the semiconductor layer vertically. The contacts 1818 can extend vertically through the semiconductor layer 1810 from its front side. The contacts 1818 can be coupled to the interconnects of the interconnect layer 1820. The contacts 1818 can extend further through the dielectric layer (if any) on the back side of the semiconductor layer 1810 and align and contact the interconnects of the interconnect layer 1830 at the bonding interface 1812. Thus, the contacts 1818 couple the interconnects of the interconnect layer 1820 to the interconnects in the interconnect layer 1830 across the bonding interface 1812 through the semiconductor layer 1810. The contacts 1818 can be formed by first patterning contact holes in the semiconductor layer 1810 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material of the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (eg, a silicon oxide layer) before depositing the conductor.

[0176] The method 2000 skips optional operation 2012 and proceeds to operation 2014, as shown in FIG. 20, where a pad-out interconnect layer is formed. The pad-out interconnect layer may be formed above the second transistor. As shown in FIG. 18F, a pad-out interconnect layer 1836 is formed above the interconnect layer 1820 and the transistors 1814, 1816 on the semiconductor layer 1810. The pad-out interconnect layer 1836 may include interconnects such as contact pads 1838 formed in one or more ILD layers. The contact pads 1838 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0177] In some implementations, after operation 2010, the method 2000 proceeds to optional operation 2012, where the first substrate is thinned, as shown in FIG. 20, to form a pad-out interconnect layer in the first substrate. Although not shown, it is understood that in some examples, the silicon substrate 1802 (shown in FIG. 18E) can be thinned to a semiconductor layer having single crystal silicon using processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. After thinning, contacts can be formed that extend vertically through the thinned silicon substrate 1802, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor, followed by wet / dry etching. It is understood that in some examples, the contacts can be formed in the silicon substrate 1802 before thinning and exposed from the back side of the silicon substrate 1802 (where thinning occurs) after thinning.

[0178] The method 2000 continues to operation 2014, as shown in FIG. 20, where a pad-out interconnect layer is formed.

[0179] A pad-out interconnect layer can be formed on the thinned first substrate. Although not shown, it is understood that in some examples a pad-out interconnect layer having contact pads can be formed on the thinned silicon substrate 1802.

[0180] 21A and 21B show schematic cross-sectional views of 3D memory devices 2100 and 2101 having two stacked semiconductor structures according to various embodiments of the present disclosure. The 3D memory devices 2100 and 2101 may be examples of the 3D memory device 101 of FIG. 1B, where the peripheral circuitry of the first semiconductor structure 102 is vertically disposed between the memory cell array of the first semiconductor structure 102 and the peripheral circuitry of the second semiconductor structure 104. That is, two separate parts of the peripheral circuitry may be disposed vertically adjacent to each other. As shown in FIGS. 21A and 21B, according to some embodiments, the second semiconductor structure 104 including some of the peripheral circuitry is bonded to the first semiconductor structure 102 on the side having the peripheral circuitry to form a bonded interface 105 between the second semiconductor structure 104 and the peripheral circuitry of the first semiconductor structure 102.

[0181] Furthermore, as shown in FIG. 21A and FIG. 21B, the 3D memory device 2100 or 2101 can further include a pad-out interconnect layer 902 for pad-out purposes, i.e., for interconnecting with an external device using contact pads to which bond wires can be soldered. In one example shown in FIG. 21B, the second semiconductor structure 104 including some of the peripheral circuitry on one side of the 3D memory device 2101 can include a pad-out interconnect layer 902, so that the 3D memory device 2101 can be padded out from the peripheral circuitry side to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing the parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 2101. In another example shown in FIG. 21A, the first semiconductor structure 102 including the memory cell array and some of the peripheral circuitry on another side of the 3D memory device 2100 can include a pad-out interconnect layer 902 so that the 3D memory device 901 can be padded out from the memory cell array side.

[0182] 22A and 22B show schematic diagrams of cross sections of the 3D memory devices of FIGS. 21A and 21B according to various aspects of the disclosure. The 3D memory devices 2200 and 2201 can be examples of the 3D memory devices 2100 and 2101 of FIGS. 21A and 21B. As shown in FIG. 22A, the 3D memory device 2200 can include stacked first and second semiconductor structures 102 and 104. In some implementations, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some of the peripheral circuitry vertically between the semiconductor layer 1002 and the polysilicon layer 106, and a polysilicon layer 106 vertically between the memory cell array and the peripheral circuitry.

[0183] The memory cell array can include an array of NAND memory strings (e.g., NAND memory strings 208 as disclosed herein), whose sources can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., either N-type doped, P-type doped, or undoped) suitable for a "floating gate" type NAND memory string, or a specific design of a channel structure (e.g., channel structure 812 in FIG. 8) in a "charge trap" type NAND memory string, suitable for, for example, a GIDL erase operation. Direct, short-distance (e.g., sub-micron or micron level) electrical connections can be made between the memory cell array and peripheral circuits in the first semiconductor structure 102 via contacts (e.g., ILV / TSV) through the polysilicon layer 106. The bonding layer 1014 can include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts, which can be used, for example, for hybrid bonding, as described in more detail below.

[0184] In some implementations, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not with the polysilicon layer 106. That is, the transistors of the peripheral circuitry (e.g., the planar transistor 500 and the 3D transistor 600) can be in contact with the semiconductor layer 1002. The semiconductor layer 1002 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1002 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. The peripheral circuitry and the bonding layer 1014 can be formed on both sides of the semiconductor layer 1002 such that the semiconductor layer 1002 is vertically disposed between the peripheral circuitry and the bonding layer 1014. In some implementations, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1002 and the bonding contacts of the bonding layer 1014 are formed on the back side of the semiconductor layer 1002.

[0185] In some implementations, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1012, and some of the peripheral circuitry of the memory cell array that is vertically between the semiconductor layer 1004 and the bonding layer 1012. Transistors of the peripheral circuitry (e.g., the planar transistors 500 and the 3D transistors 600) can be in contact with the semiconductor layer 1004. Like the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1004 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon that is desirable for transistor performance.

[0186] Similar to the bonding layer 1014 of the first semiconductor structure 102, the bonding layer 1012 may also include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts. According to some implementations, the bonding interface 105 is perpendicular to and in contact with the bonding layers 1012 and 1014, respectively. That is, the bonding layers 1012 and 1014 may be disposed on either side of the bonding interface 105, and the bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, the large number (e.g., millions) of bonding contacts across the bonding interface 105, in combination with through contacts (e.g., ILV / TSV) through the semiconductor layer 1002, may form a direct, short-distance (e.g., micron-level) electrical connection between adjacent semiconductor structures 102 and 104.

[0187] It is understood that in some examples, the first and second semiconductor structures 102 and 104 may not include bonding layers 1014 and 1012, respectively, disposed on both sides of the bonding interface 105, as shown in FIG. 22A. In FIG. 22B, the semiconductor layer 1002 in the first semiconductor structure 102 of the 3D memory device 2201 may be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the top surface of the second semiconductor structure 104 by transfer bonding, and the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 may result from a transfer bond as opposed to a hybrid bond. A short-distance (e.g., sub-micron level) electrical connection may be formed directly between adjacent semiconductor structures 102 and 104 via contacts (e.g., ILV / TSV) that penetrate the semiconductor layer 1002 vertically between the first semiconductor structure 102 and the second semiconductor structure 104.

[0188] As shown in Figures 22A and 22B, according to some embodiments, the first and second semiconductor structures 102 and 104 are joined back to back (e.g., the semiconductor layers 1002 and 1004 are disposed on the bottom surfaces of the first and second semiconductor structures 102 in Figures 22A and 22B, respectively), so that the transistors of the peripheral circuits of the first and second semiconductor structures 102 and 104 are arranged to face in the same direction (e.g., in the positive y direction in Figures 12A and 12B). In addition, in the first semiconductor structure 102, the polysilicon layer 106 is vertically disposed between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on the polysilicon layer 106 and the semiconductor layer 1002, respectively, so that the memory cell array and the peripheral circuits face in the same direction (e.g., in the positive y direction in Figures 22A and 22B). It will be understood that the pad-out interconnect layer 902 of Figures 21A and 21B has been omitted from the 3D memory devices 2200 and 2201 of Figures 22A and 22B for ease of explanation, and may be included in the 3D memory devices 2200 and 2201 as described above with respect to Figures 21A and 21B.

[0189] As mentioned above, the first semiconductor structure 102 and the second semiconductor structure 104 can have peripheral circuits with transistors with different applied voltages. For example, the first semiconductor structure 102 can be an example of the semiconductor structure 408 including the LLV circuit 402 (and in some examples the LV circuit 404) of FIG. 4B, and the second semiconductor structure 104 can be an example of the semiconductor structure 410 including the HV circuit 406 (and in some examples the LV circuit 404) of FIG. 4B, or vice versa. Thus, in some implementations, the semiconductor layers 1002 and 1004 in the first and second semiconductor structures 102 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the second semiconductor structure 104 can include the HV circuit 406 and the first semiconductor structure 102 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 of the first semiconductor structure 102 can be less than the thickness of the semiconductor layer 1004 of the second semiconductor structure 104. Additionally, in some implementations, the gate dielectrics of the transistors in the first and second semiconductor structures 102 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the second semiconductor structure 104 may include the HV circuitry 406 and the first semiconductor structure 102 may include the LLV circuitry 402, and the gate dielectric thickness of the transistors in the second semiconductor structure 104 may be greater (e.g., at least five times) than the gate dielectric thickness of the transistors in the first semiconductor structure 102.

[0190] 23A and 23B show side views of various examples of the 3D memory devices 2200 and 2201 of FIGS. 22A and 22B according to various aspects of the disclosure. As shown in FIG. 23A, as an example of the 3D memory devices 2200 and 2201 of FIGS. 22A and 22B, the 3D memory device 2300 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of each other in different planes in the vertical direction (e.g., the y-direction in FIG. 23A), according to some implementations. According to some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 105 therebetween.

[0191] As shown in FIG. 23A, the second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some implementations, the semiconductor layer 1004 is a silicon substrate having single crystal silicon. The second semiconductor structure 104 may also include a device layer 2302 in contact with and above the semiconductor layer 1004. In some implementations, the device layer 2302 includes a first peripheral circuit 2304 and a second peripheral circuit 2306. The first peripheral circuit 2304 may include HV circuits 406 such as driving circuits (e.g., string drivers 704 in row decoder / word line driver 308 and drivers in column decoder / bit line driver 306), and the second peripheral circuit 2306 may include LV circuits 404 such as page buffer circuits (e.g., page buffer circuit 702 in page buffer 304) and logic circuits (e.g., control logic 312). In some implementations, the first peripheral circuit 2304 includes a plurality of transistors 2308 in contact with the semiconductor layer 1004, and the second peripheral circuit 2306 includes a plurality of transistors 2310 in contact with the semiconductor layer 1004. The transistors 2308 and 2310 can include any transistor disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some implementations, each transistor 2308 or 2310 includes a gate dielectric, and because the voltage applied to the transistor 2308 is higher than that of the transistor 2310, the thickness of the gate dielectric of the transistor 2308 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistor 2310 (e.g., in the LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of the transistors 2308 and 2310) can also be formed on or in the semiconductor layer 1004.

[0192] In some implementations, the second semiconductor structure 104 further includes an interconnect layer 2312 on the device layer 2302 to transfer electrical signals between the peripheral circuits 2306 and 2304. As shown in FIG. 23A, the interconnect layer 2312 can be vertically between the bond interface 105 and the device layer 2302 (including the transistors 2308 and 2310 of the peripheral circuits 2304 and 2306). The interconnect layer 2312 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnects in the interconnect layer 2312 can be coupled to the transistors 2308 and 2310 of the peripheral circuits 2304 and 2306 in the device layer 2302. The interconnect layer 2312 can further include one or more ILD layers in which horizontal lines and vias can be formed. That is, the interconnect layer 2312 can include horizontal lines and vias in multiple ILD layers. In some implementations, the devices in the device layer 2302 are coupled to each other through interconnects in the interconnect layer 2312. For example, the peripheral circuit 2304 may be coupled to the peripheral circuit 2306 through the interconnect layer 2312. The interconnects in the interconnect layer 2312 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2312 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 2312 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (less detectable, e.g., voids) among conductive metal materials.

[0193] As shown in FIG. 23A, the first semiconductor structure 102 can be bonded back-to-back to the top of the second semiconductor structure 104 at a bonding interface 105. The first semiconductor structure 102 can further include a semiconductor layer 1002 having a semiconductor material. In some implementations, the bonding interface 105 is where the semiconductor layer 1002 of the first semiconductor structure 102 and the interconnect layer 2312 of the second semiconductor structure 104 meet and bond. In practice, the bonding interface 105 can be a layer having a certain thickness that includes the top surface of the interconnect layer 2312 of the second semiconductor structure 104 and the bottom surface of the semiconductor layer 1002 of the first semiconductor structure 102. The bonding interface 105 can result from a transfer bonding process, where the semiconductor layer 1002 can be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, as described in detail below with respect to the manufacturing process. In some implementations, a dielectric layer (e.g., a silicon oxide layer) is formed vertically between bonding interface 105 and semiconductor layer 1002 and / or between bonding interface 105 and interconnect layer 2312 to facilitate transfer bonding of semiconductor layer 1002 onto interconnect layer 2312. It is therefore understood that in some examples, bonding interface 105 can include a surface of a dielectric layer.

[0194] As shown in FIG. 23A, the first semiconductor structure 102 may also include a device layer 2314 above and in contact with the semiconductor layer 1002. In some implementations, the device layer 2314 includes a third peripheral circuit 2316 and a fourth peripheral circuit 2318 above and in contact with the semiconductor layer 1002. In some implementations, the semiconductor layer 1002 is vertically disposed between the bond interface 105 and the device layer 2314 having the peripheral circuits 2316 and 2318. The third peripheral circuit 2316 may include an LLV circuit 402, such as an I / O circuit (e.g., in the interface 316 and the data bus 318), and the fourth peripheral circuit 2318 may include an LV circuit 404, such as a page buffer circuit (e.g., the page buffer circuit 702 in the page buffer 304) and a logic circuit (e.g., in the control logic 312). In some implementations, the third peripheral circuit 2316 includes a plurality of transistors 2320, and the fourth peripheral circuit 2318 also includes a plurality of transistors 2322. Transistors 2320 and 2322 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some implementations, each transistor 2320 or 2322 includes a gate dielectric, and because the voltage applied to transistor 2320 is lower than that of transistor 2322, the thickness of the gate dielectric of transistor 2320 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 2322 (e.g., in LV circuit 404).

[0195] Furthermore, different voltages applied to different transistors 2320, 2322, 2308 and 2310 of the first and second semiconductor structures 102 and 104 may result in differences in device dimensions between the first and second semiconductor structures 102 and 104. In some implementations, because the voltage applied to transistor 2308 is higher than that of transistor 2320, the gate dielectric thickness of transistor 2320 (e.g., in HV circuit 406) is greater than the gate dielectric thickness of transistor 2308 (e.g., in LLV circuit 402). In some implementations, because the same voltage is applied to transistor 2322 and transistor 2310, the gate dielectric thickness of transistor 2322 (e.g., in LV circuit 404) is the same as the gate dielectric thickness of transistor 2310 (e.g., in LV circuit 404). In some implementations, the thickness of the semiconductor layer 1004 in which the transistor 2308 (e.g., in the HV circuit 406) is formed is greater than the thickness of the semiconductor layer 1002 in which the transistor 2320 (e.g., in the LLV circuit 402) is formed because a higher voltage is applied to the transistor 2308 than to the transistor 2320.

[0196] As shown in FIG. 23A, the first semiconductor structure 102 may further include an interconnect layer 2326 in contact above the device layer 2314 to transfer electrical signals between the transistors 2320 and 2322 of the peripheral circuits 2316 and 2318. The interconnect layer 2326 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 2326 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 2326 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2326 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 2326 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (less detectable, e.g., voids) among conductive metal materials.

[0197] As shown in FIG. 23A, the first semiconductor structure 102 may also include one or more contacts 2330 extending vertically through the semiconductor layer 1002. In some implementations, the contacts 2330 may extend further through the dielectric layer (if any) on the backside of the semiconductor layer 1002 and contact the interconnects of the interconnect layer 2312 at the bond interface 105. Thus, the contacts 2330 may couple the interconnects of the interconnect layer 2326 to the interconnects of the interconnect layer 2312 to form an electrical connection through the semiconductor layer 1004 and across the bond interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104. The contacts 2330 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contacts 2330 include W. In some implementations, contact 2330 comprises a via surrounded by a dielectric spacer (e.g., comprising silicon oxide) to electrically isolate the via from semiconductor layer 1002. Depending on the thickness of semiconductor layer 1002, contact 2330 can be an ILV having a submicron level depth (e.g., 10 nm to 1 μm) or a TSV having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0198] 23A, the first semiconductor structure may further include a polysilicon layer 106 over and in contact with the interconnect layer 2326. The polysilicon layer 106, according to some implementations, is a doped polysilicon layer over the interconnect layer 2326, as described in more detail below with respect to the manufacturing process. It will be appreciated that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0199] As shown in FIG. 23A, the first semiconductor structure 102 may also include a memory cell array, such as an array of NAND memory strings 208, above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some implementations, the polysilicon layer 106 is vertically between the NAND memory strings 208 and a device layer 2314 that includes transistors 2320 and 2322. In some implementations, each NAND memory string 208 is a “charge trap” type NAND memory string that includes any suitable channel structure disclosed herein, such as the channel structure 812 described in detail above with respect to FIG. 8. In some implementations, the NAND memory strings 208 are “floating gate” type NAND memory strings, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory strings.

[0200] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as stack structures, e.g., memory stack 2327. Memory stack 2327 may be an example of memory stack 804 of FIG. 8, and the conductive and dielectric layers in memory stack 2327 may be an example of gate conductive layer 806 and dielectric layer 808, respectively, in memory stack 804. According to some implementations, the interleaved conductive and dielectric layers in memory stack 2327 alternate vertically. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line and terminate in one or more staircase structures of memory stack 2327.

[0201] As shown in FIG. 23A, the first semiconductor structure 102 may further include an interconnect layer 2328 contacting above the NAND memory string 208 to transfer electrical signals to and from the NAND memory string 208. In some implementations, the memory stack 2327 and the NAND memory string 208 are vertically between the interconnect layer 2328 and the polysilicon layer 106. The interconnect layer 2328 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in the interconnect layer 2328 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 2328 may further include one or more ILD layers in which horizontal lines and vias may be formed. The interconnects in the interconnect layer 2328 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2328 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0202] As shown in FIG. 23A, the first semiconductor structure 102 may further include one or more contacts 2324 extending vertically through the polysilicon layer 106. In some implementations, the contacts 2324 couple the interconnects in the interconnect layer 2328 to the interconnects in the interconnect layer 2326 to form an electrical connection through the polysilicon layer 106 between the NAND memory string 208 and the transistors 2320 and 2322. The contacts 2324 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contacts 2324 include W. In some implementations, the contacts 2324 include a via surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the via from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contacts 2324 can be ILVs having a submicron level depth (e.g., 10 nm to 1 μm) or TSVs having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0203] 23A, the first semiconductor structure 102 can further include a pad-out interconnect layer 902 above the interconnect layer 2328 and the NAND memory strings 208. In some implementations, the NAND memory strings 208 are vertically disposed between the pad-out interconnect layer 902 and the polysilicon layer 106. The pad-out interconnect layer 902 can include interconnects, e.g., contact pads 2332, to one or more ILD layers. In some implementations, the interconnects in the pad-out interconnect layer 902 can transfer electrical signals between the 3D memory device 2300 and an external device, e.g., for pad-out purposes.

[0204] As a result, the peripheral circuits 2304, 2306, 2316, and 2318 in the second semiconductor structure 104 and the first semiconductor structure 102 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 via various interconnect structures including the interconnect layers 2312, 2326, and 2328, and the contacts 2324, and 2330. Additionally, the peripheral circuits 2304, 2306, 2316, and 2318 and the NAND memory string 208 in the 3D memory device 2300 can be further coupled to external devices via the contacts 2330 and the pad-out interconnect layer 902.

[0205] It is understood that the pad-out of the 3D memory device is not limited to being from the first semiconductor structure 102 having the NAND memory strings 208 and the peripheral circuitry 2316 as shown in FIG. 23A (corresponding to FIG. 21A), but may also be from the second semiconductor structure 104 having the peripheral circuitry 2304 (corresponding to FIG. 21B). For example, as shown in FIG. 23B, the 3D memory device 2301 may include a pad-out interconnect layer 902 in the second semiconductor structure 104. The pad-out interconnect layer 902 may contact the semiconductor layer 1004 of the second semiconductor structure 104 in which the transistors 2308 of the peripheral circuitry 2304 are formed. In some implementations, the second semiconductor structure 104 further includes one or more contacts 2334 extending vertically through the semiconductor layer 1004. In some implementations, the contact 2334 couples an interconnect in the interconnect layer 2312 in the second semiconductor structure 104 to a contact pad 2332 in the pad-out interconnect layer 902 to provide an electrical connection through the semiconductor layer 1004. The contact 2334 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, the contact 2334 includes W. In some implementations, the contact 2334 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 2334 can be an ILV having a submicron level thickness (e.g., 10 nm to 1 μm) or a TSV having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0206] As shown in FIG. 23B, the first semiconductor structure 102 can further include a passivation layer 2350 instead of the pad-out interconnect layer 902 of FIG. 23A, to protect and encapsulate the 3D memory device 2301 from the side of the first semiconductor structure 102 without the pad-out interconnect layer 902. The passivation layer 2350 can include a dielectric material such as silicon nitride and / or silicon oxide. In some implementations, the first semiconductor structure 102 of the 3D memory device 2301 further includes a handle / carrier substrate 2351 in contact with the passivation layer 2350 as a base substrate of the 3D memory device 2301 to provide support. It is understood that in some examples, the passivation layer 2350 may be omitted or combined with the handle substrate 2351 as a single layer for support and protection.

[0207] It is also understood that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 of the 3D memory device 2301 can further include bonding layers 1012 and 1014, respectively, at the bonding interface 105 (on both sides of the bonding interface 105), as shown in FIG. 23B. That is, the bonding interface 105 can result from a hybrid bond, as opposed to a transfer bond. The bonding layer 1012 can be disposed between the bonding interface 105 and the interconnect layer 2312, and the bonding layer 1014 can be disposed between the bonding interface 105 and the semiconductor layer 1002. In some implementations, the bonding layer 1014 is formed on the back side (e.g., a thinned silicon substrate) of the semiconductor layer 1002, opposite the front side on which the device layer 2314 is formed. In practice, the bonding interface 105 can be a layer having a certain thickness that includes the top surface of the bonding layer 1012 of the second semiconductor structure 104 and the bottom surface of the bonding layer 1014 of the first semiconductor structure 102.

[0208] The bonding layers 1012 and 1014 may include a plurality of bonding contacts and a dielectric that electrically insulates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some implementations, the bonding contacts of the bonding layers 1012 and 1014 include Cu. The remaining regions of the bonding layers 1012 and 1014 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layers 1012 and 1014 and the surrounding dielectric may be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive), and may simultaneously obtain a metal-metal (e.g., Cu-Cu) bond and a dielectric-dielectric (e.g., SiO2-SiO2) bond.

[0209] 24A-24F illustrate a manufacturing process for forming the 3D memory device of FIG. 22A and 22B according to some embodiments of the present disclosure. FIG. 26 illustrates a flowchart of a method 2600 for forming the 3D memory device of FIG. 22A and 22B according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIG. 24A-24F and FIG. 26 includes the 3D memory device 2300 illustrated in FIG. 23A. FIGS. 24A-24F and FIG. 26 are described together. It is understood that the operations illustrated in the method 2600 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 26.

[0210] Referring to FIG. 26, the method 2600 begins with operation 2602, where a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 24A, a silicon substrate 2402 has a plurality of transistors 2404, 2406 formed thereon. The transistors 2404, 2406 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 2402, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 2404 and 2406. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 2404 is different from the thickness of the gate dielectric of transistor 2406, for example, by depositing a thicker silicon oxide film in the region of transistor 2404 than in the region of transistor 2406, or by etching back a portion of the silicon oxide film deposited in the region of transistor 2406. It is understood that the details of fabricating transistors 2404 and 2406 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of Figures 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0211] In some implementations, an interconnect layer 2408 is formed above the transistors on the first substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 24A, the interconnect layer 2408 can be formed above the transistors 2404 and 2406. The interconnect layer 2408 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 2404 and 2406. In some implementations, the interconnect layer 2408 includes multiple ILD layers and interconnects formed in multiple processes therein. For example, the interconnects in the interconnect layer 2408 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 24A may be collectively referred to as an interconnect layer 2408. In some implementations, the interconnects in the interconnect layer 2408 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0212] The method 2600 proceeds to operation 2604, as shown in Figure 26, where a polysilicon layer is formed above the first transistor. The semiconductor layer can include single crystal silicon. In some implementations, another substrate is bonded to the first substrate in a face-to-face manner to form the semiconductor layer, and the other substrate is thinned to leave the semiconductor layer. The bonding can include transfer bonding. The other substrate can be a silicon substrate having single crystal silicon.

[0213] As shown in FIG. 24B, a semiconductor layer 2410, such as a single crystal silicon layer, is formed above the interconnect layer 2408 and the transistors 2404 and 2406. The semiconductor layer 2410 can be attached above the interconnect layer 2408 to form a bonding interface 2412 vertically between the semiconductor layer 2410 and the interconnect layer 2408. In some implementations, a dielectric layer (e.g., a silicon oxide layer) is formed between the bonding interface 2412 and the semiconductor layer 2410 and / or between the bonding interface 2412 and the interconnect layer 2408 to facilitate transfer bonding of the semiconductor layer 2410. In some implementations, to form the semiconductor layer 2410, another silicon substrate (not shown in FIG. 24B) and the silicon substrate 2402 are bonded in a face-to-face manner (components such as transistors 2404 and 2406 are formed in the silicon substrate 2402 and face the other silicon substrate) using transfer bonding, thereby forming the bonding interface 2412. The other silicon substrate can then be thinned using any suitable process, leaving the semiconductor layer 2410 attached above the interconnect layer 2408. Details of the various transfer bonding processes have been described above with reference to Figures 34A-34D and 35A-35D and therefore will not be repeated for ease of explanation.

[0214] The method 2600 proceeds to operation 2606, where a second transistor is formed in the semiconductor layer. As shown in FIG. 24C, a plurality of transistors 2414, 2416 are formed on a semiconductor layer 2410 of single crystal silicon. The transistors 2414, 2416 can be formed by a number of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the semiconductor layer 2410, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 2414 and 2416. In some implementations, isolation regions (e.g., STI) are also formed in the semiconductor layer 2410 by wet / dry etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 2414 is different from the thickness of the gate dielectric of transistor 2416, for example, by depositing a thicker silicon oxide film in the region of transistor 2414 than in the region of transistor 2416, or by etching back a portion of the silicon oxide film deposited in the region of transistor 2416. It is understood that the details of fabricating transistors 2414 and 2416 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0215] In some implementations, an interconnect layer is formed above the transistors. The interconnect layer may include multiple interconnects in one or more ILD layers. As shown in FIG. 24C, an interconnect layer 2420 may be formed above the transistors 2414 and 2416. The interconnect layer 2420 may include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 2414 and 2416. In some implementations, the interconnect layer 2420 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 2420 may include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects may also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects shown in Figure 24C can be collectively referred to as interconnect layer 2420. In some implementations, the interconnects in interconnect layer 2420 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0216] In some implementations, contacts are formed through the semiconductor layer. The contacts 2418 can extend vertically through the semiconductor layer 2410 from its front side. The contacts 2418 can be coupled to the interconnects of the interconnect layer 2420. The contacts 2418 can extend further through the dielectric layer (if any) on the back side of the semiconductor layer 2410 to align and contact the interconnects of the interconnect layer 2408 at the bonding interface 2412. Thus, the contacts 2418 couple the interconnects of the interconnect layer 2408 to the interconnects in the interconnect layer 2420 across the bonding interface 2412 through the semiconductor layer 2410. The contacts 2418 can be formed by first patterning contact holes in the semiconductor layer 2410 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material of the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some implementations, filling the contact holes includes depositing a spacer (eg, a silicon oxide layer) before depositing the conductor.

[0217] The method 2600 proceeds to operation 2608, as shown in Figure 26, where a polysilicon layer is formed above the second transistor. As shown in Figure 24D, a polysilicon layer 2411 is formed above the interconnect layer 2420 and the transistors 2414 and 2416 on the semiconductor layer 2410. The polysilicon layer 2411 may be formed by depositing polysilicon on the interconnect layer 2420 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the polysilicon layer 2411 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0218] The method 2600 continues to operation 2010, as shown in FIG. 26, where an array of NAND memory strings is formed on the polysilicon layer. In some implementations, a memory stack is formed on the polysilicon layer to form the array of NAND memory strings. As shown in FIG. 24E, a stack structure such as a memory stack 2426 including interleaved conductive and dielectric layers is formed on the polysilicon layer 2411. To form the memory stack 2426, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2411. In some implementations, each sacrificial layer includes a layer of silicon nitride and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 2426 can then be formed by replacing the sacrificial layer with a conductive layer using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer, and filling the resulting recess with the conductive layer. In some implementations, each conductive layer comprises a metal layer, such as a layer of W. It is understood that in some examples, the memory stack 2426 may be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide is formed between the memory stack 2426 and the polysilicon layer 2411.

[0219] As shown in FIG. 24E, NAND memory strings 2428 are formed above polysilicon layer 2411, each of which extends vertically through memory stack 2426 to contact polysilicon layer 2411. In some implementations, the fabrication process for forming NAND memory strings 2428 includes forming channel holes in polysilicon layer 2411 through memory stack 2426 (or dielectric stack) using dry etching and / or wet etching such as DRIE, and then filling the channel holes with multiple layers such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It is understood that the fabrication details of NAND memory strings 2428 may vary depending on the type of channel structure (e.g., channel structure 812 of FIG. 8) of NAND memory string 2428, and therefore will not be detailed for ease of explanation.

[0220] In some implementations, an interconnect layer is formed above the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 24E, an interconnect layer 2430 is formed above the memory stacks 2426 and the NAND memory strings 2428. The interconnect layer 2430 can include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the NAND memory strings 2428. In some implementations, the interconnect layer 2430 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 2430 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 24E may be collectively referred to as interconnect layer 2430.

[0221] In some implementations, contacts are formed through the polysilicon layer. As shown in FIG. 24E, one or more contacts 2417 are formed, each extending vertically through the polysilicon layer 2411. The contacts 2417 can couple the interconnects in the interconnect layers 2430 and 2420. The contacts 2417 can be formed by first patterning contact holes through the polysilicon layer 2411 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0222] The method 2600 skips optional operation 2612 and proceeds to operation 2614, as shown in FIG. 26, where a pad-out interconnect layer is formed. The pad-out interconnect layer can be formed above an array of NAND memory strings. As shown in FIG. 24F, a pad-out interconnect layer 2436 is formed above the NAND memory strings 2428 of the interconnect layer 2430 and the polysilicon layer 2411. The pad-out interconnect layer 2436 can include interconnects such as contact pads 2438 formed in one or more ILD layers. The contact pads 2438 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0223] In some implementations, after operation 2610, the method 2600 proceeds to optional operation 2612, where the first substrate is thinned, as shown in FIG. 26, to form a pad-out interconnect layer in the first substrate. Although not shown, it is understood that in some examples, the silicon substrate 2402 (shown in FIG. 24E) can be thinned to a semiconductor layer having single crystal silicon using processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. After thinning, contacts can be formed that extend vertically through the thinned silicon substrate 2402, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor, followed by wet / dry etching. It is understood that in some examples, the contacts can be formed in the silicon substrate 2402 before thinning and exposed from the back side of the silicon substrate 2402 (where thinning occurs) after thinning.

[0224] The method 2600 proceeds to operation 2614, as shown in Figure 26, where a pad-out interconnect layer is formed. The pad-out interconnect layer may be formed on the thinned first substrate. Although not shown, it is understood that in some examples, a pad-out interconnect layer having contact pads may be formed on the thinned silicon substrate 2402.

[0225] 25A-25G illustrate another manufacturing process for forming the 3D memory device of FIG. 22A and 22B according to some embodiments of the present disclosure. FIG. 27 illustrates a flowchart of another method 2700 for forming the 3D memory device of FIG. 22A and 22B according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIG. 25A-25G and FIG. 27 includes the 3D memory device 2301 illustrated in FIG. 23B. FIGS. 25A-25G and FIG. 27 are described together. It is understood that the operations illustrated in method 2700 are not inclusive, and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than the order illustrated in FIG. 27.

[0226] Referring to FIG. 27, method 2700 begins with operation 2702, where a first transistor is formed on a front side of a first substrate. The first substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 25A, a silicon substrate 2510 has a plurality of transistors 2514 and 2516 formed on a front side thereof. The transistors 2514, 2516 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 2510, for example, by ion implantation and / or thermal diffusion, which function as wells and source / drain regions of the transistors 2514 and 2516. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 2510 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 2514 is different from the thickness of the gate dielectric of transistor 2516, for example, by depositing a thicker silicon oxide film in the region of transistor 2514 than in the region of transistor 2516, or by etching back a portion of the silicon oxide film deposited in the region of transistor 2516. It is understood that the details of fabricating transistors 2514 and 2516 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of FIGS. 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0227] In some implementations, an interconnect layer 2520 is formed above the transistors on the first substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 25A, the interconnect layer 2520 can be formed above the transistors 2514 and 2516. The interconnect layer 2520 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 2514 and 2516. In some implementations, the interconnect layer 2520 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 2520 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in Figure 25A may be collectively referred to as interconnect layer 2520. In some implementations, the interconnects in interconnect layer 2520 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0228] In some implementations, contacts are formed through the thinned first substrate. As shown in FIG. 25A, contacts 2518 are formed that extend vertically from the front side of the silicon substrate 2510 into the silicon substrate 2510. The contacts 2518 can be coupled to interconnects in the interconnect layer 2520. The contacts 2518 can be formed by first patterning contact holes in the silicon substrate 2510 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0229] The method 2700 continues to operation 2704, as shown in Figure 27, where a polysilicon layer is formed above the first transistor. As shown in Figure 25B, a polysilicon layer 2511 is formed above the interconnect layer 2520 and the transistors 2514 and 2516 on the first silicon substrate 2510. The polysilicon layer 2511 may be formed by depositing polysilicon on the interconnect layer 2520 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the polysilicon layer 2511 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0230] The method 2700 proceeds to operation 2706, as shown in FIG. 27, where an array of NAND memory strings is formed on the polysilicon layer. In some implementations, a memory stack is formed on the polysilicon layer to form the array of NAND memory strings. As shown in FIG. 25C, a stack structure such as a memory stack 2526 including interleaved conductive and dielectric layers is formed on the polysilicon layer 2511. To form the memory stack 2526, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2511. In some implementations, each sacrificial layer includes a layer of silicon nitride and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 2526 can then be formed by replacing the sacrificial layer with a conductive layer using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer, and filling the resulting recess with the conductive layer. In some implementations, each conductive layer comprises a metal layer, such as a layer of W. It is understood that in some examples, the memory stack 2526 may be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide is formed between the memory stack 2526 and the polysilicon layer 2511.

[0231] As shown in FIG. 25C, NAND memory strings 2528 are formed above polysilicon layer 2511, each of which extends vertically through memory stack 2526 to contact polysilicon layer 2511. In some implementations, the fabrication process of forming NAND memory strings 2528 includes forming channel holes in polysilicon layer 2511 through memory stack 2526 (or dielectric stack) using dry etching and / or wet etching such as DRIE, and then filling the channel holes with multiple layers such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It is understood that the fabrication details of NAND memory strings 2528 may vary depending on the type of channel structure (e.g., channel structure 812 of FIG. 8) of NAND memory strings 2528, and therefore will not be detailed for ease of explanation.

[0232] In some implementations, an interconnect layer is formed above the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 25C, an interconnect layer 2530 is formed above the memory stack 2526 and the NAND memory strings 2528. The interconnect layer 2530 can include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the NAND memory strings 2528. In some implementations, the interconnect layer 2530 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 2530 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 25C may be collectively referred to as interconnect layer 2530.

[0233] In some implementations, contacts are formed through the polysilicon layer. As shown in FIG. 25C, one or more contacts 2517 are formed, each extending vertically through the polysilicon layer 2511. The contacts 2517 can couple the interconnects in the interconnect layers 2530 and 2520. The contacts 2517 can be formed by first patterning contact holes through the polysilicon layer 2511 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some implementations, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0234] In some implementations, the first substrate is thinned. As shown in FIG. 25E, a silicon substrate 2510 (shown in FIG. 25C) is thinned to a semiconductor layer 2509 having single crystal silicon. The silicon substrate 2510 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. The thickness of the semiconductor layer 2509 can be controlled to expose the contacts 2518 from the backside of the thinned silicon substrate 2510, for example, by controlling the duration of the CMP process. It is understood that in some examples, the contacts 2518 can be formed through the semiconductor layer 2509 from its backside after thinning, as opposed to the silicon substrate 2510 before thinning. In some implementations, a passivation layer 2523 is formed on the interconnect layer 2530 prior to thinning by depositing a dielectric material, such as silicon nitride, on the interconnect layer 2530 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The handle substrate 2501 can then be attached to the passivation layer 2523 prior to thinning, for example using adhesive bonding, to allow for subsequent backside processes with the silicon substrate 2510 such as thinning, contact formation, and bonding.

[0235] In some implementations, a first bonding layer is formed on the back side of the thinned first substrate. The first bonding layer can include a plurality of first bonding contacts. As shown in FIG. 25E, a bonding layer 2522 is formed on the back side of the semiconductor layer 2509 (i.e., the thinned silicon substrate 2510). The bonding layer 2522 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the back side of the semiconductor layer 2509 (opposite the front side where the transistors 2514 and 2516 are formed) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer to contact the contacts 2518 on the back side of the thinned silicon substrate 2510 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material of the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a glue layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0236] The method 2700 proceeds to operation 2708, as shown in FIG. 27, where a second transistor is formed on a second substrate. The second substrate may be a silicon substrate having single crystal silicon. As shown in FIG. 25D, a plurality of transistors 2504, 2506 are formed on a silicon substrate 2502 of single crystal silicon. The transistors 2504, 2506 may be formed by a plurality of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the silicon substrate 2502, for example, by ion implantation and / or thermal diffusion, which serve as wells and source / drain regions of the transistors 2504 and 2506. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 2502 by dry / wet etching and thin film deposition. In some implementations, the thickness of the gate dielectric of transistor 2504 is different from the thickness of the gate dielectric of transistor 2506, for example, by depositing a thicker silicon oxide film in the region of transistor 2504 than in the region of transistor 2506, or by etching back a portion of the silicon oxide film deposited in the region of transistor 2506. It is understood that the details of fabricating transistors 2504 and 2506 may vary depending on the type of transistor (e.g., planar transistor 500 or 3D transistor 600 of Figures 5A, 5B, 6A, 6B) and therefore will not be detailed for ease of explanation.

[0237] In some implementations, an interconnect layer is formed above the transistors on the second substrate. The interconnect layer can include multiple interconnects in one or more ILD layers. As shown in FIG. 25D, an interconnect layer 2508 can be formed above the transistors 2504 and 2506. The interconnect layer 2508 can include MEOL and / or BEOL interconnects in multiple ILD layers to make electrical connections with the transistors 2504 and 2506. In some implementations, the interconnect layer 2508 includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects in the interconnect layer 2508 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, dry / wet etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 25D may be collectively referred to as an interconnect layer 2520. Unlike the interconnect layer 2520, in some implementations, the interconnects in the interconnect layer 2508 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (not compatible with high temperature processes), the elimination of high temperature processes after fabrication of the interconnect layer 2508 may make it feasible to use Cu as the conductive material for the interconnects in the interconnect layer 2508.

[0238] In some implementations, a second bonding layer is formed above the interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As shown in FIG. 25D, a bonding layer 2521 is formed above the interconnect layer 2508. The bonding layer 2521 can include a plurality of bonding contacts surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the interconnect layer 2508 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts can then be formed through the dielectric layer and in contact with the interconnects in the interconnect layer 2508 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0239] 27, the method 2700 proceeds to operation 2710 where the first and second substrates are bonded in a back-to-back contact manner. A first bonding contact of the first bonding layer can contact a second bonding contact of the second bonding layer at a bonding interface after bonding the first and second substrates. The bonding can include a hybrid bond.

[0240] As shown in FIG. 25F, the thinned silicon substrate 2510 (i.e., semiconductor layer 2509) and components formed thereon (e.g., transistors 2514 and 2516 and NAND memory string 2528) and the silicon substrate 2502 and components formed thereon (e.g., transistors 2504 and 2506) are bonded (i.e., face-to-face) with a bonding layer 2521 facing up on the front side of the silicon substrate 2502 and a bonding layer 2522 facing down on the back side of the thinned silicon substrate 2510 to form a bonding interface 2524. That is, the thinned silicon substrate 2510 and components formed thereon can be bonded back-to-back with the silicon substrate 2502 and components formed thereon such that the bonding contacts of the bonding layer 2521 contact the bonding contacts of the bonding layer 2522 at the bonding interface 2524. In some implementations, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces before bonding. As a result of bonding, e.g., hybrid bonding, the bond contacts on either side of bond interface 2524 can intermix. After bonding, according to some embodiments, the bond contacts of bonding layer 2521 and the bond contacts of bonding layer 2522 are aligned and in contact with each other, such that memory stack 2526 and NAND memory string 2528 formed therethrough, as well as transistors 2514 and 2516, can be coupled to transistors 2504 and 2506 via the bond contacts across bond interface 2524.

[0241] The method 2700 continues to optional operation 2712, as shown in Figure 27, where the second substrate is thinned. As shown in Figure 25F, the silicon substrate 2502 (shown in Figure 25E) is thinned into a semiconductor layer 2503 having single crystal silicon. The silicon substrate 2502 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0242] The method 2700 proceeds to operation 2714, as shown in FIG. 27, in which a pad-out interconnect layer is formed above the semiconductor layer. The pad-out interconnect layer can be formed on the thinned second substrate. As shown in FIG. 25F, a pad-out interconnect layer 2536 is formed on the semiconductor layer 2503 (thinned silicon substrate 2502). The pad-out interconnect layer 2536 can include interconnects such as contact pads 2538 formed on one or more ILD layers. The contact pads 2538 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, after bonding and thinning, contacts 2534 are formed that extend vertically through the semiconductor layer 2503, for example, by depositing a dielectric material as a spacer and a conductive material as a conductor followed by wet / dry etching. The contacts 2534 can couple contact pads 2538 in the pad-out interconnect layer 2536 to interconnects in the interconnect layer 2508. It is understood that in some examples, the contacts 2534 can be formed in the silicon substrate 2502 prior to thinning (e.g., the formation of the semiconductor layer 2503 shown in FIG. 25F) and exposed from the backside of the silicon substrate 2502 after thinning (where thinning occurs).

[0243] In some implementations, after operation 2710, optional operation 2712 is skipped and method 2700 proceeds to operation 2714, where a pad-out interconnect layer is formed, as shown in Figure 27. The pad-out interconnect layer may be formed above the array of NAND memory strings. Although not shown in Figure 25F, it is understood that in some examples, after removing the handle substrate 2501 and the passivation layer 2523, a pad-out interconnect layer having contact pads may be formed above the interconnect layer 2530 and the NAND memory strings 2528.

[0244] 28A and 28B show schematic diagrams of cross sections of the 3D memory devices of FIGS. 21A and 21B according to various aspects of the disclosure. The 3D memory devices 2800 and 2801 can be examples of the 3D memory devices 2100 and 2101 of FIGS. 21A and 21B. As shown in FIG. 28A, the 3D memory device 2800 can include stacked first and second semiconductor structures 102 and 104. In some implementations, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some of the peripheral circuitry vertically between the semiconductor layer 1002 and the polysilicon layer 106, and a polysilicon layer 106 vertically between the memory cell array and the peripheral circuitry.

[0245] The memory cell array can include an array of NAND memory strings (e.g., NAND memory strings 208 as disclosed herein), whose sources can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., either N-type doped, P-type doped, or undoped) suitable for a "floating gate" type NAND memory string, or a specific design of a channel structure (e.g., channel structure 812 in FIG. 8) in a "charge trap" type NAND memory string, suitable for, for example, a GIDL erase operation. Direct, short-distance (e.g., sub-micron or micron level) electrical connections can be made between the memory cell array and peripheral circuits in the first semiconductor structure 102 via contacts (e.g., ILV / TSV) through the polysilicon layer 106. The bonding layer 1014 can include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts, which can be used, for example, for hybrid bonding, as described in more detail below.

[0246] In some implementations, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not with the polysilicon layer 106. That is, the transistors of the peripheral circuitry (e.g., the planar transistor 500 and the 3D transistor 600) can be in contact with the semiconductor layer 1002. The semiconductor layer 1002 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1002 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. The peripheral circuitry and the bonding layer 1014 can be formed on both sides of the semiconductor layer 1002 such that the semiconductor layer 1002 is vertically disposed between the peripheral circuitry and the bonding layer 1014. In some implementations, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1002 and the bonding contacts of the bonding layer 1014 are formed on the back side of the semiconductor layer 1002.

[0247] In some implementations, the second semiconductor structure 104 includes a bonding layer 1012, some of the peripheral circuits of the memory cell array, and a semiconductor layer 1004 vertically between the peripheral circuits and the bonding layer 1012. The transistors of the peripheral circuits (e.g., the planar transistors 500 and the 3D transistors 600) can be contacted to the front side of the semiconductor layer 1004. Like the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material such as single crystal silicon (e.g., a silicon substrate or a thinned silicon substrate). It is understood that in some examples, unlike the polysilicon layer 106 of the first semiconductor structure 102, the semiconductor layer 1004 in which the transistors are formed can include single crystal silicon rather than polysilicon due to the superior carrier mobility of single crystal silicon, which is desirable for transistor performance. The peripheral circuits and the bonding layer 1012 can be formed on either side of the semiconductor layer 1004 such that the semiconductor layer 1004 is vertically disposed between the peripheral circuits and the bonding layer 1012. In some implementations, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1004 and the junction contacts of the junction layer 1012 are formed on the back side of the semiconductor layer 1004 .

[0248] Similar to the bonding layer 1014 of the first semiconductor structure 102, the bonding layer 1012 may also include conductive bonding contacts (not shown) and a dielectric that electrically insulates the bonding contacts. According to some implementations, the bonding interface 105 is perpendicular to and in contact with the bonding layers 1012 and 1014, respectively. That is, the bonding layers 1012 and 1014 may be disposed on either side of the bonding interface 105, and the bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, the large number (e.g., millions) of bonding contacts across the bonding interface 105, in conjunction with through contacts (e.g., ILV / TSV) through the semiconductor layers 1002 and 1004, may form a direct, short-distance (e.g., micron-level) electrical connection between the adjacent semiconductor structures 102 and 104.

[0249] It is understood that in some examples, the first and second semiconductor structures 102 and 104 may not include bonding layers 1014 and 1012, respectively, disposed on either side of the bonding interface 105, as shown in FIG. 28A. In FIG. 28B, the semiconductor layer 1004 in the second semiconductor structure 104 of the 3D memory device 2801 may be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the bottom surface of the first semiconductor structure 102 by a transfer bond, and the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 may result from a transfer bond as opposed to a hybrid bond. A short-distance (e.g., sub-micron level) electrical connection may be formed directly between adjacent semiconductor structures 102 and 104 via contacts (e.g., ILV / TSV) that penetrate the semiconductor layers 1002 and 1004 vertically between the first semiconductor structure 102 and the second semiconductor structure 104.

[0250] As shown in Figures 28A and 28B, according to some embodiments, the first and second semiconductor structures 102 and 104 are bonded back-to-back (e.g., as shown in Figures 28A and 28B, the semiconductor layer 1002 is disposed under the first semiconductor structure 102, while the semiconductor layer 1004 is disposed over the second semiconductor structure 104), so that the transistors of the peripheral circuits in the first and second semiconductor structures 102 and 104 are disposed away from each other. Also, in the first semiconductor structure 102, there is a polysilicon layer 106 vertically between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on the polysilicon layer 106 and the semiconductor layer 1002, respectively, so that the memory cell array and the peripheral circuits face in the same direction (e.g., in the positive y direction in Figures 28A and 28B). It will be understood that the pad-out interconnect layer 902 of Figures 21A and 21B has been omitted from the 3D memory devices 2800 and 2801 of Figures 28A and 28B for ease of explanation, and may be included in the 3D memory devices 2800 and 2801 as described above with respect to Figures 21A and 21B.

[0251] As mentioned above, the first semiconductor structure 102 and the second semiconductor structure 104 can have peripheral circuits with transistors with different applied voltages. For example, the second semiconductor structure 104 can be an example of the semiconductor structure 408 including the LLV circuit 402 (and in some examples the LV circuit 404) of FIG. 4B, and the first semiconductor structure 102 can be an example of the semiconductor structure 410 including the HV circuit 406 (and in some examples the LV circuit 404) of FIG. 4B, or vice versa. Thus, in some implementations, the semiconductor layers 1002 and 1004 in the first and second semiconductor structures 102 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the first semiconductor structure 102 can include the HV circuit 406 and the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 in the first semiconductor structure 102 can be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Additionally, in some implementations, the gate dielectrics of the transistors in the first and second semiconductor structures 102 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the first semiconductor structure 102 may include the HV circuitry 406 and the second semiconductor structure 104 may include the LLV circuitry 402, and the gate dielectric thickness of the transistors in the first semiconductor structure 102 may be greater (e.g., at least five times) than the gate dielectric thickness of the transistors in the second semiconductor structure 104.

[0252] 29A and 29B show side views of various examples of the 3D memory devices 2800 and 2801 of FIGS. 28A and 28B according to various aspects of the disclosure. As shown in FIG. 29A, as an example of the 3D memory devices 2800 and 2801 of FIGS. 28A and 28B, the 3D memory device 2900 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of each other in different planes in the vertical direction (e.g., the y-direction in FIG. 29A), according to some implementations. According to some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 105 therebetween.

[0253] As shown in FIG. 29A, the second semiconductor structure 104 can include a semiconductor layer 1004 having a semiconductor material. In some implementations, the semiconductor layer 1004 is a silicon substrate having single crystal silicon. The second semiconductor structure 104 can also include a device layer 2902 above and in contact with the semiconductor layer 1004. In some implementations, the device layer 2902 includes a first peripheral circuit 2904 and a second peripheral circuit 2906. The first peripheral circuit 2904 can include an LLV circuit 402, such as an I / O circuit (e.g., in the interface 316 and the data bus 318), and the second peripheral circuit 2906 can include an LV circuit 404, such as a page buffer circuit (e.g., the page buffer circuit 702 in the page buffer 304) and a logic circuit (e.g., in the control logic 312). In some implementations, the first peripheral circuit 2904 includes a plurality of transistors 2908 in contact with the semiconductor layer 1004, and the second peripheral circuit 2906 includes a plurality of transistors 2910 in contact with the semiconductor layer 1004. The transistors 2908 and 2910 can include any transistor disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some implementations, each transistor 2908 or 2910 includes a gate dielectric, and because the voltage applied to the transistor 2908 is lower than that of the transistor 2910, the thickness of the gate dielectric of the transistor 2908 (e.g., in the LLV circuit 402) is less than the thickness of the gate dielectric of the transistor 2910 (e.g., in the LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of the transistors 2908 and 2910) can also be formed on or in the semiconductor layer 1004.

[0254] In some implementations, the second semiconductor structure 104 further includes an interconnect layer 2912 on the device layer 2902 to transfer electrical signals between the peripheral circuits 2906 and 2904. As shown in FIG. 29A, the device layer 2902 (including the transistors 2908 and 2910 of the peripheral circuits 2904 and 2906) may be vertical between the bond interface 105 and the interconnect layer 2912. The interconnect layer 2912 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnects in the interconnect layer 2912 may be coupled to the transistors 2908 and 2910 of the peripheral circuits 2904 and 2906 in the device layer 2902. The interconnect layer 2912 may further include one or more ILD layers in which horizontal lines and vias may be formed. That is, the interconnect layer 2912 may include horizontal lines and vias in multiple ILD layers. In some implementations, the devices in device layer 2902 are coupled to each other via interconnects in interconnect layer 2912. For example, peripheral circuitry 2904 may be coupled to peripheral circuitry 2906 via interconnect layer 2912. The interconnects in interconnect layer 2912 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer 2912 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0255] In some implementations, the interconnects of the interconnect layer 2912 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below with respect to the manufacturing process, although Cu has a relatively low thermal budget (competitive for high temperature processes), the fabrication of the interconnect layer 2912 may occur after high temperature processes in forming the device layer 2902 and the NAND memory strings 208 in the first semiconductor structure 102, making the interconnects of the interconnect layer 1126 with Cu feasible.

[0256] As shown in FIG. 29A, the second semiconductor structure 104 may further include one or more contacts 2931 extending vertically through the semiconductor layer 1004. In some implementations, the contacts 2931 further extend through a dielectric layer (if present) on the backside of the semiconductor layer 1004 to the bond interface 105. The contacts 2931 may be coupled to interconnects of the interconnect layer 2912. The contacts 2931 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contacts 2931 include W. In some implementations, the contacts 2931 include a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 2931 can be ILVs having a submicron level depth (e.g., 10 nm to 1 μm) or TSVs having a micron or tens of microns level depth (e.g., 1 μm to 100 μm).

[0257] As shown in FIG. 29A, the first semiconductor structure 102 can be bonded back-to-back to the top of the second semiconductor structure 104 at a bonding interface 105. The first semiconductor structure 102 can further include a semiconductor layer 1002 having a semiconductor material. In some implementations, the bonding interface 105 is where the semiconductor layer 1002 of the first semiconductor structure 102 and the semiconductor layer 1004 of the second semiconductor structure 104 meet and bond. In practice, the bonding interface 105 can be a layer having a certain thickness that includes the top surface of the semiconductor layer 1004 of the second semiconductor structure 104 and the bottom surface of the semiconductor layer 1002 of the first semiconductor structure 102. The bonding interface 105 can result from a transfer bonding process, and the semiconductor layer 1004 can be a layer of single crystal silicon transferred from a silicon substrate or an SOI substrate and attached to the bottom surface of the first semiconductor structure 102 by transfer bonding, as described in detail below with respect to the manufacturing process. In some implementations, to facilitate transfer bonding of the semiconductor layer 1004 onto the semiconductor layer 1002, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1002 and / or between the bonding interface 105 and the semiconductor layer 1004. It is therefore understood that in some examples, the bonding interface 105 can include a surface of a dielectric layer.

[0258] As shown in FIG. 29A, the first semiconductor structure 102 may also include a device layer 2914 below and in contact with the semiconductor layer 1002. In some implementations, the device layer 2914 includes a third peripheral circuit 2916 and a fourth peripheral circuit 2918 below and in contact with the semiconductor layer 1002. In some implementations, the semiconductor layer 1002 is vertically disposed between the bonding interface 105 and the device layer 2914 having the peripheral circuits 2916 and 2918. The third peripheral circuit 2916 may include HV circuits 406 such as drive circuits (e.g., string drivers 704 in row decoder / word line driver 308 and drivers in column decoder / bit line driver 306), and the fourth peripheral circuit 2918 may include LV circuits 404 such as page buffer circuits (e.g., page buffer circuit 702 in page buffer 304) and logic circuits (e.g., control logic 312). In some implementations, the third peripheral circuit 2916 includes a plurality of transistors 2920, and the fourth peripheral circuit 2918 also includes a plurality of transistors 2922. The transistors 2920 and 2922 may include any transistor disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some implementations, each transistor 2920 or 2922 includes a gate dielectric, and because the voltage applied to the transistor 2920 is higher than that of the transistor 2922, the thickness of the gate dielectric of the transistor 2920 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistor 2922 (e.g., in the LV circuit 404).

[0259] Furthermore, different voltages applied to different transistors 2920, 2922, 2908 and 2910 of the first and second semiconductor structures 102 and 104 may result in differences in device dimensions between the first and second semiconductor structures 102 and 104. In some implementations, because the voltage applied to transistor 2908 is lower than that of transistor 2920, the gate dielectric thickness of transistor 2908 (e.g., in ...

Claims

1. 1. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a bonding interface between the first semiconductor structure and the second semiconductor structure; The first semiconductor structure further comprises contacts extending through the polysilicon layer and coupling the array of memory cells to the first peripheral circuitry.

2. 10. The 3D memory device of claim 1, wherein the array of memory cells, the first peripheral circuitry, and the second peripheral circuitry are stacked on top of one another.

3. the array of memory cells comprises an array of NAND memory strings; 3. The 3D memory device of claim 1, wherein the polysilicon layer is in contact with sources of the array of NAND memory strings.

4. the first semiconductor structure further comprising a first semiconductor layer in contact with the first transistor; 4. The 3D memory device of claim 1, wherein the first transistor is between the first semiconductor layer and the polysilicon layer.

5. 5. The 3D memory device of claim 4, wherein the second semiconductor structure further comprises a second semiconductor layer in contact with the second transistor.

6. 6. The 3D memory device of claim 5, wherein each of the first and second semiconductor layers comprises single crystal silicon.

7. 7. The 3D memory device of claim 5 or 6, wherein the first and second semiconductor layers have different thicknesses.

8. the first transistor comprises a first gate dielectric; the second transistor comprises a second gate dielectric; 8. The 3D memory device of claim 1, wherein the first gate dielectric and the second gate dielectric have different thicknesses.

9. A three-dimensional (3D) memory device comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a bonding interface between the first semiconductor structure and the second semiconductor structure; the first transistor comprises a first gate dielectric; the second transistor comprises a second gate dielectric; 13. A 3D memory device, wherein a difference between a thickness of the first gate dielectric and a thickness of the second gate dielectric is at least a factor of five.

10. the first semiconductor structure further comprises a third peripheral circuit of the array of memory cells, the third peripheral circuit comprising a third transistor having a third gate dielectric; 10. The 3D memory device of claim 8 or 9, wherein the second semiconductor structure further comprises a fourth peripheral circuit of the array of memory cells, the fourth peripheral circuit comprising a fourth transistor comprising a fourth gate dielectric.

11. 11. The 3D memory device of claim 10, wherein the third gate dielectric and the fourth gate dielectric have the same thickness.

12. 12. The 3D memory device of claim 11, wherein a thickness of the third gate dielectric and the fourth gate dielectric is between a thickness of the first gate dielectric and the second gate dielectric.

13. 13. The 3D memory device of claim 10, wherein the third and fourth peripheral circuits comprise at least one of a page buffer circuit or a logic circuit.

14. the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the first transistor; 14. The 3D memory device of claim 1, wherein the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the second transistor.

15. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a bonding interface between the first semiconductor structure and the second semiconductor structure; the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the first transistor; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the second transistor; The 3D memory device, wherein the first and second interconnects have different materials.

16. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a bonding interface between the first semiconductor structure and the second semiconductor structure; the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the first transistor; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the second transistor; The first semiconductor structure comprises: a third interconnect layer comprising a third interconnect coupled to the array of memory cells; a contact passing through the polysilicon layer and coupling the third interconnect to the first interconnect.

17. 17. The 3D memory device of claim 1, wherein the first peripheral circuitry comprises drive circuitry and the second peripheral circuitry comprises input / output (I / O) circuitry, or vice versa.

18. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a bonding interface between the first semiconductor structure and the second semiconductor structure; a first voltage source coupled to the first peripheral circuit and configured to supply a first voltage to the first peripheral circuit; and a second voltage source coupled to the second peripheral circuit and configured to supply a second voltage to the second peripheral circuit; The 3D memory device, wherein the first voltage is different from the second voltage.

19. the first semiconductor structure further comprises a first bonding layer comprising a first bonding contact; the second semiconductor structure further comprising a second bonding layer comprising a second bonding contact; 19. The 3D memory device of claim 1, wherein the first bond contact contacts the second bond contact at the bond interface.

20. 1. A system comprising:

1. A memory device configured to store data, comprising: a first semiconductor structure comprising an array of memory cells, a first peripheral circuit for the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit, the first peripheral circuit comprising a first transistor; a second semiconductor structure comprising a second peripheral circuit of the array of memory cells, the second peripheral circuit comprising a second transistor; a memory device comprising a bonding interface between the first semiconductor structure and the second semiconductor structure; and a memory controller coupled to the memory device and configured to control the array of memory cells via the first peripheral circuit and the second peripheral circuit; The first semiconductor structure further comprises contacts extending through the polysilicon layer and coupling the array of memory cells to the first peripheral circuitry.

Images