Display device and method for manufacturing the same

Abstract

A display device (2) comprises: an insulation layer (IM) that is positioned in the gap between a first electrode (22) and a second electrode (24) and includes a coating-type insulation material; and an oxide semiconductor layer (SC1) that contacts an upper surface of the insulation layer (IM) and functions at least in part as the channel of a first transistor (Tr1).

Description

[Technical field]

[0001] The present invention relates to a display device and a method for manufacturing a display device. [Background technology]

[0002] Patent Document 1 discloses a configuration in which, in a top-gate transistor, a source electrode and a drain electrode are formed on a base insulating film containing silicon oxynitride, and an oxide semiconductor is formed so as to fill the gap between these electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2013-058738 (Published March 28, 2013) [Patent Document 2] Patent Publication No. 2013-77815 (released April 25, 2013) Summary of the Invention [Problem to be solved by the invention]

[0004] The conventional configuration as disclosed in Patent Document 1 has a problem in that the transistor characteristics cannot be improved. [Means for solving the problem]

[0005] A display device according to one embodiment of the present disclosure is a display device comprising a substrate and a first transistor located above the substrate, the display device comprising: a first electrode and a second electrode located above the substrate and spaced apart in a direction perpendicular to a normal direction of the substrate; an insulating layer located in the gap between the first electrode and the second electrode and including a coating type insulating material; and an oxide semiconductor layer, at least a portion of which functions as a channel of the first transistor and in contact with an upper surface of the insulating layer. Effect of the Invention

[0006] According to one aspect of the present disclosure, transistor characteristics are improved compared to conventional techniques. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing a configuration example of a display device according to the present disclosure. [Diagram 2] 2 is a schematic cross-sectional view showing a configuration example of a first transistor according to the present disclosure shown in FIG. 1. [Diagram 3] FIG. 11 is a schematic cross-sectional view showing a configuration example of a display device according to a comparative example. [Figure 4] 4 is a schematic cross-sectional view showing a configuration of a first transistor of the comparative example shown in FIG. [Diagram 5] 4 is a schematic cross-sectional view showing a step of patterning the oxide semiconductor layer of the comparative example shown in FIG. 3. [Figure 6] 13 is a diagram showing the difference in voltage-current characteristics of the second semiconductor depending on whether or not the third metal layer is patterned. FIG. [Figure 7] 3A to 3C are schematic cross-sectional views showing an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 8] 4A to 4C are schematic plan views illustrating an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 9] 3A to 3C are schematic cross-sectional views showing an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 10] 4A to 4C are schematic plan views illustrating an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 11] 3A to 3C are schematic cross-sectional views showing an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 12] 4A to 4C are schematic plan views illustrating an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 13] 3A to 3C are schematic cross-sectional views showing an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 14] 4A to 4C are schematic plan views illustrating an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 15]3A to 3C are schematic cross-sectional views showing an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 16] 4A to 4C are schematic plan views illustrating an example of a process for forming a thin film transistor layer according to the present disclosure. [Figure 17] 4 is a schematic cross-sectional view illustrating a configuration example of a first transistor according to an embodiment of the present disclosure. FIG. [Figure 18] 4 is a schematic cross-sectional view illustrating a configuration example of a first transistor according to an embodiment of the present disclosure. FIG. [Figure 19] 19 is a schematic cross-sectional view showing an example of a process for forming the first transistor shown in FIG. 18. [Figure 20] 19 is a schematic cross-sectional view showing an example of a process for forming the first transistor shown in FIG. 18. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In this disclosure, "same layer" means that it is formed in the same process (film formation process), "lower layer" means that it is formed in an earlier process than the layer being compared, and "upper layer" means that it is formed in a later process than the layer being compared.

[0009] In the following, when it is written "Put Y on top of X", "Put Y above X", or "Put Y above X", X and Y may or may not be directly adjacent to each other.

[0010] [Embodiment 1] (Display Device Configuration) Fig. 1 is a schematic cross-sectional view showing a configuration example of a display device 2 according to the present disclosure. As shown in Fig. 1, the display device 2 according to the present disclosure includes a resin substrate 10, a base coat layer BC above the resin substrate 10, a thin film transistor layer 12 above the base coat layer BC, a light emitting element layer 14 above the thin film transistor layer 12, and a sealing layer 18 above the light emitting element layer 14.

[0011] The display device 2 includes a plurality of pixel circuits PC and light-emitting elements Ed connected to each pixel circuit PC.

[0012] The resin substrate 10 may be a rigid substrate or a flexible substrate. The resin substrate 10 is a substrate made of a resin such as polyimide.

[0013] The thin-film transistor layer 12 in this embodiment includes, in this order from bottom to top, a silicon-based semiconductor layer SC2, a gate insulating film GI, a gate electrode GE (second gate electrode), a first interlayer insulating film ILD1 (inorganic insulating film), a metal layer M3, an insulating layer IM, an oxide semiconductor layer SC1, a gate insulating film TGI, a gate electrode TGE (first gate electrode), a second interlayer insulating film ILD2, a metal layer SE, and an organic planarization film PL.

[0014] The thin film transistor layer 12 includes a first transistor Tr1 and a second transistor Tr2. The first transistor Tr1 and the second transistor Tr2 are included in a pixel circuit PC.

[0015] The first transistor Tr1 will be described later.

[0016] The second transistor Tr2 includes a silicon-based semiconductor layer SC2, a gate insulating film GI on the silicon-based semiconductor layer SC2, and a gate electrode GE on the gate insulating film GI.

[0017] The silicon-based semiconductor layer SC2 may include any one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The oxide semiconductor layer SC1 includes an oxide semiconductor. An example of the oxide semiconductor is indium gallium zinc oxide (InGaZnO).

[0018] The insulating layer IM is formed by applying and solidifying a liquid 20 (see FIG. 9) containing a coating type insulating material. The insulating layer IM includes a coating type insulating material. For example, the insulating layer IM may include at least one of an SOG (spin on glass) material, an oxide containing an alkaline earth metal, and an oxide containing a lanthanoid. The insulating layer IM will be described later.

[0019] The light emitting element layer 14 has a pixel electrode PE, a bank BK above the pixel electrode PE, an active layer 16 above the bank BK, and a common electrode CE above the active layer 16.

[0020] The active layer 16 includes at least a light-emitting layer. Here, the types of the display device 2 include an OLED display device in which the light-emitting layer is an organic light-emitting layer, and a QLED display device in which the light-emitting layer is a quantum dot light-emitting layer. The active layer 16 may further include one or more of a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like.

[0021] The display device 2 according to the present disclosure is not limited to the above. For example, the display device 2 may include a glass substrate instead of the resin substrate 10. For example, the display device 2 may be a liquid crystal display device including an active matrix substrate including a substrate and a thin film transistor layer 12. For example, the display device 2 may be a rigid display device or a flexible display device.

[0022] (Configuration of the first transistor) 2 is a schematic cross-sectional view showing a configuration example of the first transistor Tr1 according to the present disclosure shown in FIG. 2. As shown in FIG. 2, the first transistor Tr1 is a thin film transistor (TFT) and has (1) a first electrode 22 and a second electrode 24 spaced apart from each other in a direction perpendicular to the normal direction of the upper surface of the resin substrate 10, (2) an oxide semiconductor layer SC1 in contact with the upper surface of the insulating layer IM and the first electrode 22 and the second electrode 24, (3) a gate insulating film TGI on the oxide semiconductor layer SC1, and (4) a gate electrode TGE (first gate electrode) on the gate insulating film TGI. The first electrode 22 and the second electrode 24 are in the same layer and are included in the metal layer M3. One of the first electrode 22 and the second electrode 24 is a source electrode, and the other is a drain electrode.

[0023] The oxide semiconductor layer SC1 has at least a channel portion 30, and can additionally have a first low resistance portion and a second low resistance portion .

[0024] The channel portion 30 functions as a channel of the first transistor Tr1. The channel portion 30 is in contact with the upper surface of the insulating layer IM and overlaps with the gate electrode TGE in a plan view.

[0025] The first low resistance section 26 is located on the first electrode 22 side with respect to the channel section 30, and has a smaller electrical resistance value than the channel section 30. The first low resistance section 26 contacts the upper surface of the first electrode 22. The first low resistance section 26 may also contact the side surface of the first electrode 22.

[0026] The second low resistance section 28 is located on the second electrode 24 side with respect to the channel section 30, and has a smaller electrical resistance value than the channel section 30. The second low resistance section 28 contacts at least one of the upper surface and the side surface of the second electrode 24. The second low resistance section 28 may also contact the side surface of the second electrode 24.

[0027] (insulating layer IM) The insulating layer IM is formed at least in the gap between the first electrode 22 and the second electrode 24 of the first transistor Tr1. The insulating layer IM is in contact with both side surfaces of the first electrode 22 and the second electrode 24. In addition, the insulating layer IM may be formed so as to surround each of the first electrode 22 and the second electrode 24 of the first transistor Tr1 in a plan view.

[0028] The upper surface of the insulating layer IM is approximately flat. The distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 is smaller than the distance from the upper surfaces of the first electrode 22 and the second electrode 24 of the first transistor Tr1 to the upper surface of the resin substrate 10. The insulating layer IM, the first electrode 22, and the second electrode 24 are provided on the first interlayer insulating film ILD1. Therefore, the upper surface of the insulating layer IM is located between the upper surface of the first electrode 22 and the upper surface of the first interlayer insulating film ILD1, or between the upper surface of the second electrode 24 and the upper surface of the first interlayer insulating film ILD1.

[0029] (Comparative Example) Fig. 3 is a schematic cross-sectional view showing a configuration example of a display device 102 according to a comparative example. As shown in Fig. 3, the display device 102 according to the comparative example has a similar configuration to the display device 2 according to the present disclosure shown in Fig. 1, except that there is no insulating layer IM between the first interlayer insulating film ILD1 and the oxide semiconductor layer SC1 of the thin film transistor layer 112.

[0030] Fig. 4 is a schematic cross-sectional view showing the configuration of the first transistor Tr101 shown in Fig. 3. As shown in Fig. 4, in the first transistor Tr101 according to the comparative example, the oxide semiconductor layer SC1 is in contact with the side surfaces of the first electrode 22 and the second electrode 24 and the upper surface of the first interlayer insulating film ILD1 between the first electrode 22 and the second electrode 24. The oxide semiconductor layer SC1 in contact with the side surfaces of the first electrode 22 and the second electrode 24 tends to be formed thinner than the oxide semiconductor layer SC1 in contact with the upper surface of the first interlayer insulating film ILD1.

[0031] (Comparison between the configuration according to the present disclosure and the configuration of the comparative example) 5 is a schematic cross-sectional view showing a process of patterning the oxide semiconductor layer SC1 shown in FIG. 3. As shown in FIG. 5, when the oxide semiconductor layer SC1 according to the comparative example is patterned, a photoresist layer PR is formed on the oxide semiconductor layer SC1. At this time, a cavity CV may be generated between the oxide semiconductor layer SC1 and the photoresist layer PR at a position corresponding to the corner between the upper surface of the first interlayer insulating film ILD1 and the inclined side surface of the source electrode or the drain electrode. Then, an etching solution for etching the oxide semiconductor layer SC1 seeps into the cavity CB. For this reason, the oxide semiconductor layer SC1 is likely to be interrupted (so-called "step discontinuity") by a step between the first interlayer insulating film ILD1 and the source electrode or the drain electrode.

[0032] In addition, the upper surface of the first interlayer insulating film ILD1 may be deteriorated when the metal layer M3 is patterned, or a residue of the metal layer M3 may remain on the upper surface.

[0033] 6 shows, in a semi-logarithmic graph, the current-voltage characteristics of the first transistor Tr101 in the following cases: (1) the metal layer M3 is patterned to form the first transistor Tr101 (with M3 patterning), and (2) the oxide semiconductor layer SC1 is patterned without forming the metal layer M3, and the oxide semiconductor layer SC1 is connected to the source electrode and the drain electrode by a top contact (without M3 patterning). The vertical axis in FIG. 6 is a logarithmic scale.

[0034] 6, it can be seen that the rise characteristics of the first transistor Tr101 deteriorate (the S value increases) when M3 patterning is performed. This deterioration is considered to be caused by deterioration of the upper surface of the first interlayer insulating film ILD1 and residues of the metal layer M3.

[0035] As shown in FIG. 2, in the first transistor Tr1 according to the present disclosure, the gap between the first electrode 22 and the second electrode 24 is filled with the insulating layer IM. The step between the upper surface of the insulating layer IM and the upper surface of the first electrode 22 or the second electrode 24 is smaller than the step between the upper surface of the first interlayer insulating film ILD1 and the upper surface of the first electrode 22 or the second electrode 24. Therefore, the oxide semiconductor layer SC1 in the configuration according to the present disclosure shown in FIG. 2 is less likely to be broken by a step, compared to the configuration of the comparative example shown in FIG. 4. Furthermore, since the oxide semiconductor layer SC1 does not contact the upper surface of the first interlayer insulating film ILD1, deterioration of the upper surface of the first interlayer insulating film ILD1 and residues of the metal layer M3 do not affect the oxide semiconductor layer SC1, and the rise characteristics of the first transistor Tr1 do not deteriorate.

[0036] Therefore, when the first transistor Tr1 according to the present disclosure is compared with the first transistor Tr101 of the comparative example, the first transistor Tr1 according to the present disclosure has better transistor characteristics.

[0037] (Manufacturing method) The method for manufacturing the display device 2 according to the present disclosure includes the steps of forming a base coat layer BC, a thin film transistor layer 12, a light emitting element layer 14, and a sealing layer 18 on a resin substrate 10 in this order.

[0038] Figures 7, 9, 11, 13, and 15 are schematic cross-sectional views showing an example of a process for forming the thin film transistor layer 12 according to the present disclosure, and Figures 8, 10, 12, 14, and 16 are schematic plan views showing an example of a process for forming the thin film transistor layer 12 according to the present disclosure.

[0039] As shown in FIGS. 7 and 8, first, a silicon-based semiconductor layer SC2, a gate insulating film GI, a gate electrode GE, a first interlayer insulating film ILD1, and a metal layer M3 are formed in this order on a base coat layer BC, and then appropriately patterned.

[0040] In forming and patterning the metal layer M3, the first electrode 22 and the second electrode 24 are formed so that they are spaced apart from each other in a direction perpendicular to the normal direction of the upper surface of the resin substrate 10.

[0041] 9 and 10, next, a liquid 20 containing a coating type insulating material is coated over the entire surface so as to cover the first interlayer insulating film ILD1 and the metal layer M3, forming a coating film. Here, the liquid 20 is coated in the gap between the first electrode 22 and the second electrode 24.

[0042] The liquid 20 containing the coating type insulating material may be an insulator when solidified (i.e., when it becomes the insulating layer IM), and the liquid 20 itself may be either a conductor or an insulator. The liquid 20 containing the coating type insulating material may be any liquid, such as a liquid in which insulating material powder is dispersed in a solvent. The coating method may be any method, such as a spin coating method, a bar coating method, or a spraying method.

[0043] Next, the coating of the liquid 20 is baked to form an insulating layer IM. The insulating layer IM is formed on the first electrode 22 and the second electrode 24, in the gap between them, and around the first electrode 22 and the second electrode 24. Here, the thickness of the portion of the insulating layer IM formed on the first electrode 22 and the second electrode 24 is thinner than the thickness of the portion of the insulating layer IM formed in the gap between them.

[0044] 11 and 12, the insulating layer IM is then etched so that the upper surfaces of both the first electrode 22 and the second electrode 24 are exposed from the insulating layer IM and the insulating layer IM remains at least in the gap between the first electrode 22 and the second electrode 24. In this embodiment, the insulating layer IM is etched until a part of the side surface of the first electrode 22 and a part of the side surface of the second electrode 24 are exposed. As a result, the distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 is smaller than the distance from the upper surface of the first electrode 22 and the upper surface of the second electrode 24 to the upper surface of the resin substrate 10.

[0045] The etching method may be dry etching or wet etching. When the first interlayer insulating film ILD1 is etched, the thickness, material, and etching conditions of the first interlayer insulating film ILD1 are set so that the gate electrode of the second transistor Tr2 remains covered with the first interlayer insulating film ILD1 even after etching.

[0046] As shown in FIGS. 13 and 14, next, an oxide semiconductor layer SC1 is formed and patterned on the metal layer M3 and the insulating layer IM.

[0047] 15 and 16, next, a gate insulating film TGI and a gate electrode TGE are formed in this order on the oxide semiconductor layer SC1. In addition, a process of doping or reducing the oxide semiconductor layer SC1 may be performed. By this process, a region including a portion of the oxide semiconductor layer SC1 overlapping under the gate electrode TGE remains as the channel section 30, and the other regions are made low-resistance and become the first low-resistance section 26 and the second low-resistance section 28.

[0048] Next, the second interlayer insulating film ILD2 is formed, contact holes are appropriately formed, and the metal layer SE and the organic planarizing film PL are formed, thereby forming the thin film transistor layer 12.

[0049] The manufacturing method of the display device 2 according to the present disclosure is not limited to this. For example, when the resin substrate 10 is flexible, a laminate including the thin film transistor layer 12 may be formed on a rigid substrate other than the resin substrate 10, and the laminate may be peeled off from the rigid substrate and attached to the resin substrate 10.

[0050] [Embodiment 2] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals are given to components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0051] 17 is a schematic cross-sectional view showing a configuration example of the first transistor Tr1 according to the present embodiment. As shown in FIG. 17, the display device 2 according to the present embodiment is the same as the display device 2 according to the above-described embodiment 1, except that the distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 is the same as the distance from the upper surfaces of both the first electrode 22 and the drain electrode of the first transistor Tr1 to the upper surface of the resin substrate 10.

[0052] Such an insulating layer IM can be realized by adjusting the etching conditions when etching the insulating layer IM.

[0053] [Embodiment 3] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals are given to components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0054] 18 is a schematic cross-sectional view showing a configuration example of the first transistor Tr1 according to this embodiment. As shown in FIG. 18, the display device 2 according to this embodiment is the same as the display device 2 according to the above-described embodiment 1, except that the distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 is not uniform.

[0055] When the liquid 20 containing the coating type insulating material is applied, the upper surface of the liquid 20 containing the coating type insulating material may become uneven due to surface tension. Also, when the liquid 20 containing the coating type insulating material is solidified, the liquid 20 containing the coating type insulating material or the insulating layer IM may expand and / or contract due to temperature changes and / or a change in state from liquid to solid, causing the upper surface to become uneven. In such cases, the distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 may become uneven.

[0056] 19 is a schematic cross-sectional view showing an example of a process for forming the first transistor Tr1 shown in FIG. 18. As shown in FIG. 19, after the liquid 20 containing the coating-type insulating material is solidified, the upper surface of the insulating layer IM may be formed in a valley shape in the gap between the first electrode 22 and the second electrode 24 of the first transistor Tr1. Specifically, the insulating layer IM may be formed so that the distance from the upper surface of the portion of the insulating layer IM formed in the gap between the first electrode 22 and the second electrode 24 to the upper surface of the resin substrate 10 is smaller than the distance from the upper surface of the portion of the insulating layer IM formed on the first electrode 22 and the second electrode 24 to the upper surface of the resin substrate 10. With respect to the portion formed in the gap, the entire upper surface may be inclined or curved, or only the upper surface of the portion near the side surface of the first electrode 22 and the second electrode 24 may be inclined or curved.

[0057] Fig. 20 is a schematic cross-sectional view showing an example of a process for forming the first transistor Tr1 shown in Fig. 18. When the insulating layer IM is formed in a valley shape as shown in Fig. 20, the upper surface of the insulating layer IM remains in the valley shape at the gap even after the insulating layer IM is etched. Specifically, the insulating layer IM is formed so that the distance from the upper surface of the insulating layer IM to the upper surface of the resin substrate 10 is smaller at the midpoint between the first electrode 22 and the second electrode 24 than the distance at the edge where the upper surface of the insulating layer IM contacts the first electrode 22 and the second electrode 24.

[0058] Therefore, in the cross-sectional view of the display device 2, the upper surface of the insulating layer IM according to the present embodiment may have a valley shape in the gap between the first electrode 22 and the second electrode 24. However, the upper surface of the insulating layer IM may have another shape, such as a mountain shape or a wave shape, in the gap.

[0059] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Furthermore, new technical features can be formed by combining the technical means disclosed in the respective embodiments. [Explanation of symbols]

[0060] 2 Display device 10 Resin substrate (substrate) 22 1st electrode 24 2nd electrode 26 1st low resistance section 28 2nd low resistance section 30 Channel section GE Gate electrode (second gate electrode) ILD1 First interlayer insulating film (inorganic insulating film) IM Insulation Layer PC pixel circuit SC1 Oxide semiconductor layer SC2 Silicon-based semiconductor layer TGI Gate Insulator TGE Gate electrode (first gate electrode) Tr1 First transistor Tr2 Second transistor

Claims

1. A display device comprising a substrate and a first transistor located above the substrate, a first electrode and a second electrode located above the substrate and spaced apart in a direction perpendicular to a normal direction of the substrate; an insulating layer located in a gap between the first electrode and the second electrode and including a coating type insulating material; an oxide semiconductor layer, at least a portion of which functions as a channel of the first transistor and which is in contact with an upper surface of the insulating layer.

2. the oxide semiconductor layer includes a channel portion that functions as the channel, and first and second low-resistance portions that have an electrical resistance value smaller than that of the channel portion; The display device according to claim 1 , wherein the first low resistance portion is in contact with an upper surface of the first electrode, and the second low resistance portion is in contact with an upper surface of the second electrode.

3. The display device according to claim 2 , wherein the first low resistance portion is in contact with a side surface of the first electrode, and the second low resistance portion is in contact with a side surface of the second electrode.

4. 4. The display device according to claim 1, wherein the insulating layer is in contact with side surfaces of the first electrode and the second electrode.

5. 4. The display device according to claim 1, wherein a distance from an upper surface of the insulating layer to an upper surface of the substrate is smaller than a distance from upper surfaces of the first electrode and the second electrode to an upper surface of the substrate.

6. The display device according to claim 1 , wherein the distance from the upper surface of the insulating layer to the upper surface of the substrate is the same as the distance from the upper surfaces of the first electrode and the second electrode to the upper surface of the substrate.

7. 5. The display device according to claim 1, wherein the upper surface of the insulating layer has a valley shape.

8. 8. The display device according to claim 1, wherein the insulating layer includes at least one of a spin-on glass material, an oxide containing an alkaline earth metal, and an oxide containing a lanthanoid.

9. 9. The display device according to claim 1, wherein the first transistor includes a gate insulating film located on an oxide semiconductor layer, and a first gate electrode located on the gate insulating film.

10. 10. The display device according to claim 1, wherein each of the first electrode and the second electrode is surrounded by the insulating layer.

11. 11. The display device according to claim 1, further comprising an inorganic insulating film below the insulating layer.

12. a second transistor including a silicon-based semiconductor layer and a second gate electrode located above the silicon-based semiconductor layer; The display device according to claim 11 , wherein the second gate electrode is covered with the inorganic insulating film.

13. forming a first electrode and a second electrode spaced apart above a substrate in a direction perpendicular to a normal to the substrate; forming an insulating layer located in a gap between the first electrode and the second electrode and including a coating type insulating material; forming an oxide semiconductor layer, at least a portion of which functions as a channel of a first transistor and which is in contact with an upper surface of the insulating layer.

14. The method for manufacturing a display device according to claim 13 , further comprising applying a liquid containing the coating type insulating material onto the first electrode, the second electrode, and in the gap to form a coating film.

15. 15. The method of claim 14, further comprising the steps of: baking the coating film; and etching the baked coating film so that upper surfaces of the first electrode and the second electrode are exposed, thereby forming the insulating layer. method.

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