Quantum Devices

Abstract

To provide a quantum device that can improve the cooling performance.SOLUTION: A quantum device (1) includes a quantum chip (10) that performs information processing using quantum states, and an interposer (20) with a quantum chip (10) mounted, the quantum chip (10) is placed inside a recess 31 formed in a sample stage (30) having a cooling function, a part of the interposer (20) is in contact with a sample stage (30). The quantum chip (10) includes a first side (11) mounted on the interposer (20) and a second side (12) opposite the first side (11), and at least a part of the second surface (12) may contact the inner surface of the recess (31).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to quantum devices. [Background technology]

[0002] Patent Document 1 describes a quantum device in which a quantum chip utilizing a quantum state is flip-chip mounted on an interposer. In order to use such a quantum device in a superconducting state, it is considered to fix the surface of the interposer on which the quantum chip is not mounted on a sample stage having a cooling function. In this case, the quantum chip is cooled from the sample stage via the interposer and kept at a predetermined temperature. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 212041 Summary of the Invention [Problem to be solved by the invention]

[0004] In the quantum device described above, one side of the interposer is used for cooling by the sample stage, so there is a limit to the number of terminals that can be drawn out. On the other hand, since performance cannot be obtained unless the quantum chip is cooled to a certain temperature, it is necessary to achieve both cooling and an increase in the number of terminals.

[0005] The object of the present disclosure is to solve such problems, and to provide a quantum device that can improve the cooling function while ensuring the number of terminals. [Means for solving the problem]

[0006] The quantum device according to the present disclosure comprises a quantum chip that performs information processing using quantum states, and an interposer on which the quantum chip is mounted, the quantum chip being placed inside a recess formed in a sample stage having a cooling function, and a portion of the interposer being in contact with the sample stage. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a quantum device that can improve the cooling effect while ensuring the number of terminals. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a quantum device according to a first embodiment. [Diagram 2] 1 is an exploded perspective view illustrating a quantum device according to a first embodiment. FIG. [Diagram 3] 1 is a cross-sectional view illustrating a quantum device according to a comparative example. [Figure 4] 1 is a cross-sectional view illustrating an adhesive layer or bonding layer according to a first modified example of the first embodiment. [Diagram 5] 11 is a cross-sectional view illustrating a space between a quantum chip and an inner surface of a recess according to a second modification of the first embodiment. [Figure 6] 13 is a perspective view illustrating a recess and a pressing member of a sample stage according to a third modified example of the first embodiment. FIG. [Figure 7] 13 is a plan view illustrating a recess and a pressing member of the sample stage according to the third modification of the first embodiment. FIG. [Figure 8] 13 is a cross-sectional view illustrating a cooling member and thermal vias according to a fourth modified example of the first embodiment. FIG. [Figure 9] 13 is a cross-sectional view illustrating a recess formed at the bottom of a recess of a sample stage according to Modification 5 of Embodiment 1. FIG. [Figure 10] 13 is a plan view illustrating a recess formed at the bottom of a recess of a sample stage according to Modification 5 of Embodiment 1. FIG. [Figure 11] 13 is a cross-sectional view illustrating a recess formed at the bottom of the recess of the sample stage according to the sixth modified example of the first embodiment. FIG. [Figure 12] 13 is a cross-sectional view illustrating a recess formed at the bottom of the recess of the sample stage according to the seventh modified example of the first embodiment. FIG. [Figure 13] 13 is a cross-sectional view illustrating a recess and pillars formed at the bottom of a recess of a sample stage according to Modification 8 of Embodiment 1. FIG. [Figure 14] 13 is a cross-sectional view illustrating a through hole formed in the bottom of a recess of a sample stage according to a ninth modified example of the first embodiment. FIG. [Figure 15] 13 is a cross-sectional view illustrating a recess of a sample stage according to a tenth modification of the first embodiment. FIG. [Figure 16] 10 is a cross-sectional view illustrating a quantum device according to a second embodiment. FIG. [Figure 17] FIG. 11 is a cross-sectional view illustrating a quantum device according to a third embodiment. [Figure 18] 13 is a plan view illustrating a recess and a countersink of the sample stage according to the third embodiment. FIG. [Figure 19] FIG. 11 is a cross-sectional view illustrating a quantum device according to a fourth embodiment. [Figure 20] 13 is a cross-sectional view illustrating a spacer according to a modified example of the fourth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In addition, in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Embodiment 1) A quantum device according to embodiment 1 will be described. Fig. 1 is a cross-sectional view illustrating the quantum device according to embodiment 1. Fig. 2 is an exploded perspective view illustrating the quantum device according to embodiment 1. As shown in Figs. 1 and 2, the quantum device 1 includes a quantum chip 10 and an interposer 20.

[0011] The quantum chip 10 includes a chip substrate 15 and a wiring layer 16. The chip substrate 15 includes, for example, silicon (Si). Note that the chip substrate 15 is not limited to one including silicon, and may include other electronic materials such as sapphire and compound semiconductor materials (groups IV, III-V, and II-VI) as long as the quantum chip 10 can perform information processing using a quantum state. In addition, a single crystal is preferable, but polycrystalline or amorphous may also be acceptable.

[0012] The chip substrate 15 is, for example, plate-shaped, and has one surface and another surface opposite to the one surface. One surface is called the first surface 11, and the other surface is called the second surface 12. Thus, the quantum chip 10 and the chip substrate 15 have the first surface 11 and the second surface 12. For example, the first surface 11 and the second surface 12 are rectangular. In the quantum device 1, the first surface 11 faces the interposer 20. The first surface 11 is mounted on the interposer 20 by bumps BP.

[0013] The wiring layer 16 is provided on the first surface 11 side of the chip substrate 15. The wiring layer 16 includes a superconducting material such as niobium (Nb). Note that the superconducting material used for the wiring layer 16 is not limited to niobium (Nb), but may be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), or an alloy containing at least one of these materials.

[0014] The wiring layer 16 includes a quantum circuit 17. In the quantum circuit 17, a resonator 17c is formed having a loop circuit 17b in which a superconducting material is connected in a ring shape by a Josephson junction 17a. The material used for the Josephson junction is preferably Al, but other superconducting materials may be used. The quantum circuit 17 performs information processing using the resonator 17c in a quantum state in superconductivity. In this way, the quantum chip 10 includes the quantum circuit 17 and performs information processing using the quantum state.

[0015] The wiring layer 16 is mounted on the interposer 20 via the bumps BP. Thus, the quantum chip 10 is flip-chip mounted on the interposer 20.

[0016] The bump BP may include the above-mentioned superconducting material. The bump BP may include the same superconducting material as the wiring layer 16, or may include a different superconducting material from the wiring layer 16. In addition, when the bump BP includes a plurality of metal layers, it is preferable that at least one layer includes a superconducting material. The bump BP may be a layer including Nb (wiring surface of the quantum chip 10) / In (Sn, Pb, and an alloy including at least one of them) / Ti / Nb (wiring surface of the interposer 20) / Cu, or may be a layer including Nb (wiring surface of the quantum chip 10) / Nb (wiring surface of the interposer 20) / Cu, or may be a layer including Nb (wiring surface of the quantum chip 10) / In (Sn, Pb, and an alloy including at least one of them) / Ta (wiring surface of the interposer 20) / Cu. In addition, in the case of the bump BP including Al and In, TiN may be used as a barrier layer to prevent alloying between Al and In. In this case, the bump BP may be a layer including Al (wiring surface of the quantum chip 10) / Ti / TiN / In (Sn, Pb, and an alloy containing at least one of these) / TiN / Ti / Al (wiring surface of the interposer 20) / Cu. Here, Ti is an adhesion layer. A preferred flip chip connection is Nb (wiring of the quantum chip 10) / In / Ti / Nb (wiring surface of the interposer 20) / Cu, or Nb (wiring of the quantum chip 10) / Nb (wiring surface of the interposer 20) / Cu. It is preferred to provide a bump of φ100 μm by adding 2 to 10 μm to the thickness of the interposer wiring layer 23, which is 2 μm thick.

[0017] The interposer 20 includes interposer wiring layers 23 and 24, an interposer substrate 25, and through vias (hereinafter referred to as TVs 26). Note that the TVs 26 are omitted in FIG. 1 to avoid complicating the drawing.

[0018] The interposer substrate 25 is, for example, plate-shaped. The interposer substrate 25 contains, for example, silicon (Si). Note that the interposer substrate 25 is not limited to one containing silicon, and may contain other electronic materials such as sapphire, compound semiconductor materials (group IV, group III-V, group II-VI), glass, ceramics, etc., as long as the quantum chip 10 can be mounted thereon. The surface of the interposer substrate 25 is covered with a silicon oxide film (SiO 2 It is preferable that the interposer substrate 25 is covered with a TEOS film or the like. The interposer substrate 25 and the interposer 20 have a mounting surface 21 on which the quantum chip 10 is mounted, and an opposite surface 22 opposite to the mounting surface 21.

[0019] Here, for ease of explanation of the quantum device 1, XYZ orthogonal coordinate axes are introduced. A plane parallel to the opposite surface 22 of the interposer 20 is defined as the XY plane, and a direction perpendicular to the opposite surface 22 is defined as the Z axis direction. The +Z axis direction is defined as the upward direction, and the -Z axis direction is defined as the downward direction. Note that upward and downward are defined for ease of explanation, and do not indicate the directions in which the quantum device 1 will be placed when actually used.

[0020] For example, the quantum chip 10 is disposed on the −Z-axis direction side of the interposer 20. The wiring layer 16 disposed on the +X-axis direction side of the quantum chip 10 and the mounting surface 21 disposed on the −Z-axis direction side of the interposer 20 are connected via bumps BP.

[0021] The interposer wiring layer 23 is formed on the mounting surface 21 side of the interposer 20, i.e., on the -Z-axis direction side of the interposer 20. The interposer wiring layer 23 contains the above-mentioned superconducting material. The interposer wiring layer 23 may contain the same superconducting material as the wiring layer 16, or may contain a different superconducting material from that of the wiring layer 16. For example, the interposer wiring layer 23 preferably contains Nb (0.1 [μm] thick) on the surface, Cu (2 [μm] thick) below the Nb, and Ti below the Cu. For example, when the interposer substrate 25 contains silicon, the mounting surface 21 side of the interposer 20 may be made of Nb / Cu / Ti / SiO 2 / Si (interposer substrate 25) is preferable. The interposer wiring layer 23 is connected to the wiring layer 16 of the quantum chip 10 via bumps BP.

[0022] The interposer wiring layer 23 may be a single layer or a multilayer. The interposer wiring layer 23 may include a magnetic field application circuit 23a and a readout unit 23b. The magnetic field application circuit 23a generates a magnetic field to be applied to the loop circuit 17b. By applying a magnetic field to the loop circuit 17b, the quantum circuit 17 can function as an oscillator. The readout unit 23b reads information from the quantum circuit 17.

[0023] The interposer wiring layer 24 is formed on the opposite surface 22 of the interposer substrate 25, that is, on the +Z-axis direction side of the interposer 20. The interposer wiring layer 24 may include the above-mentioned superconducting material. The interposer wiring layer 24 may include the same superconducting material as the wiring layer 16 and the interposer wiring layer 23, or may include a different superconducting material from the wiring layer 16 and the interposer wiring layer 23. The interposer wiring layer 24 may also include a normal conductive material. The normal conductive material is, for example, copper (Cu), silver (Ag), gold (Au), platinum (Pt), or an alloy containing at least one of these. For example, it is preferable that the interposer wiring layer 24 has a surface made of Cu and contains Ti below the Cu. For example, when the interposer substrate 25 contains silicon, the opposite surface 22 of the interposer 20 may be made of Cu / Ti / SiO 2 / Si (interposer substrate 25) is preferable.

[0024] The interposer wiring layer 24 may be a single layer or a multilayer. The interposer wiring layer 24 includes a terminal 24a for extracting information from the quantum chip 10. In the quantum device 1 of this embodiment, the opposite surface 22 may not be in contact with the sample stage 30 having a cooling function. This allows the opposite surface 22 to be used to the maximum extent as the terminal 24a for extracting information.

[0025] The TV penetrates the interposer substrate 25 from the mounting surface 21 to the opposite surface 22. The interposer wiring layer and the interposer wiring layer are connected by the TV .

[0026] The TV 26 may include the above-mentioned superconducting material. The TV 26 may include the same superconducting material as the wiring layer 16, etc., or may include a different superconducting material from the wiring layer 16, etc. The TV 26 may also include the above-mentioned normal conductive material. The TV 26 may include the same normal conductive material as the interposer wiring layer 24, or may include a different normal conductive material from the interposer wiring layer 24. For example, the TV 26 may include SiO 2 (For example, a thermal oxide film) is formed, and then filled with Cu using Ti as an adhesion layer.

[0027] The sample stage 30 has a cooling function. For example, the sample stage 30 is a cold stage that can be cooled to an extremely low temperature of about 10 [mK] by a refrigerator. The sample stage 30 preferably contains a metal such as Cu, a Cu alloy, or Al. In the case of a sample stage 30 containing Al, insulation may be performed by anodizing. The quantum device 1 of this embodiment uses a superconducting phenomenon at an extremely low temperature of 9.2 [K] or less when Nb is contained as the superconducting material of the quantum chip 10, and 1.2 [K] or less when Al is contained. For this reason, a sample stage 30 that can be cooled to such an extremely low temperature is used.

[0028] A recess 31 is formed in the sample stage 30. For example, the recess 31 is formed in a predetermined surface 32 of the sample stage 30. The predetermined surface 32 is, for example, an upper surface facing the +Z axis direction. The recess 31 opens on the +Z axis direction side. When viewed from above, the recess 31 is, for example, rectangular.

[0029] When viewed from above through the interposer 20, the quantum chip 10 is smaller than the recess 31. On the other hand, when viewed from above, the interposer 20 is larger than the recess 31. The quantum chip 10 is disposed inside the recess 31 formed in the sample stage 30 having a cooling function. On the other hand, a portion of the interposer 20 is in contact with the sample stage 30. For example, a portion of the mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted is in contact with the upper surface of the sample stage 30.

[0030] An insulating film may be formed or an insulating spacer may be arranged on the portion of the mounting surface 21 of the interposer 20 that contacts the sample stage 30 in order to prevent electrical conduction with the sample stage 30. Moreover, the interposer wiring layer 23 may not be formed on the portion of the mounting surface 21 that contacts the sample stage 30.

[0031] By contacting at least a part of the interposer 20 with the sample stage 30, the interposer 20 can be used as a heat flow path to cool the quantum circuit 17 in the quantum chip 10 to an extremely low temperature, thereby making it possible to utilize the superconducting phenomenon. Furthermore, by contacting the second surface 12 of the quantum chip 10 with the inner surface of the recess 31, the cooling performance can be further improved. In order to improve the thermal insulation that reduces the temperature change around the quantum chip, it is preferable to make the surroundings of the quantum chip 10 a vacuum state or a reduced pressure atmosphere.

[0032] Next, a comparative example will be described. After that, the effect of the quantum device 1 of the present embodiment will be described by comparing it with the comparative example. FIG. 3 is a cross-sectional view illustrating a quantum device according to the comparative example. As shown in FIG. 3, a quantum device 101 of the comparative example has a quantum chip 110 and an interposer 120. A first surface 111 of the quantum chip 110 is mounted on a mounting surface 121 of the interposer 120 via bumps BP. A predetermined surface 132 of a sample stage 130 is in contact with an opposite surface 122 of the interposer 120.

[0033] In the quantum device 101 of the comparative example, the quantum chip 110 is cooled through the interposer 120 by the sample stage 130 having a cooling function. In addition, the upper side of the quantum chip 110 is not surrounded by the sample stage 130 having a cooling function. Therefore, the cooling performance for cooling the quantum chip 110 cannot be improved beyond a certain level. In addition, since the opposite surface 122 of the interposer 120 is in contact with the sample stage 130, the terminals 124a must be formed on the mounting surface 121, and the terminals 124a cannot be formed on the opposite surface 122. Therefore, there is a limit to the number of terminals 124a that can be drawn out.

[0034] In contrast to the comparative example, in the quantum device 1 of this embodiment, the quantum chip 10 is disposed inside the sample stage 30 having a cooling function. In addition, the second surface 12 of the quantum chip 10 is in contact with the inner surface of the recess 31 of the sample stage 30. At least a part of the second surface 12 may be in contact with the inner surface of the recess 31. With this configuration, the quantum chip 10 can be cooled from the second surface 12 side by the thermal conduction of the sample stage 30, and the cooling performance can be improved. Therefore, the quantum circuit 17 in the quantum chip 10 can be stably operated.

[0035] Furthermore, by having the second surface 12 movably contact the inner surface of the recess 31, it is possible to suppress stress and distortion caused by the difference in contraction between the quantum chip 10 and the sample stage 30 due to a temperature change to an extremely low temperature.

[0036] At least a portion of the interposer 20 is in contact with the sample stage 30, so that the quantum chip 10 can be cooled by thermal conduction of the sample stage 30 via the interposer 20, thereby improving the cooling performance.

[0037] The opposite surface 22 of the interposer 20 can be used to the maximum extent as the terminals 24a for extracting information from the quantum chip 10. This makes it possible to increase the number of information extraction terminals.

[0038] (Variation 1) Next, a first modification of the first embodiment will be described. This modification has an adhesive layer or a bonding layer between the quantum chip 10 and the inner surface of the recess 31. FIG. 4 is a cross-sectional view illustrating an adhesive layer or a bonding layer according to the first modification of the first embodiment. As shown in FIG. 4, in the quantum device 1a of the first modification, at least a part of the second surface 12 of the quantum chip 10 may be adhered or bonded to the inner surface of the recess 31. For example, the second surface 12 may be adhered to the sample stage 30 by an adhesive layer BL such as varnish or grease. The second surface 12 may also be bonded by a bonding layer ML such as a metal layer formed between the chip substrate 15 and the sample stage 30. With this configuration, the installation stability of the quantum chip 10 can be improved, and the positional accuracy can be improved. In addition, the thermal connection with the sample stage 30 can be improved.

[0039] The adhesive layer BL or the joining layer ML may be disposed over the entire surface of the second surface 12, or may be disposed on at least a part of the second surface 12, such as the peripheral portion of the second surface 12 or the central portion of the second surface 12. For example, the adhesive layer BL or the joining layer ML may be formed so as to avoid the area in which the quantum circuit 17 is formed, as viewed from above. If the adhesive layer BL is made of an insulating material, it may resonate with the quantum circuit 17 as a capacitor, resulting in a loss of overall energy. By disposing the adhesive layer BL so as to avoid the area in which the quantum circuit 17 is formed, it is possible to suppress the resonance.

[0040] Furthermore, if the bonding layer ML has conductivity like a metal layer, the ground potential of the quantum chip 10 may be obtained from the sample stage 30 via the bonding layer ML, or a potential specified by the sample stage 30 may be obtained.

[0041] (Variation 2) Next, a second modification of the first embodiment will be described. In this modification, there is a space between the quantum chip 10 and the inner surface of the recess 31. FIG. 5 is a cross-sectional view illustrating the space between the quantum chip 10 and the inner surface of the recess 31 according to the second modification of the first embodiment. As shown in FIG. 5, in the quantum device 1b of the second modification, the quantum chip 10 does not need to contact the sample stage 30. That is, the second surface 12 of the quantum chip 10 may be disposed with a space between it and the inner surface of the recess 31 of the sample stage 30. With this configuration, it is possible to suppress stress and distortion caused by the difference in contraction between the quantum chip 10 and the sample stage 30 caused by a temperature change to an extremely low temperature.

[0042] (Variation 3) Next, a third modification of the first embodiment will be described. This modification has a pressing member on the predetermined surface 32 of the sample stage 30. FIG. 6 is a perspective view illustrating the recess 31 and pressing member of the sample stage 30 according to the third modification of the first embodiment. FIG. 7 is a plan view illustrating the recess 31 and pressing member of the sample stage 30 according to the third modification of the first embodiment. As shown in FIGS. 6 and 7, in the quantum device 1c of the second modification, the recess 31 is formed on the predetermined surface 32 of the sample stage 30, for example, on the upper surface of the sample stage 30. A plurality of pressing members 33 are provided on the predetermined surface 32 around the recess 31. For example, four pressing members 33 are provided on the predetermined surface 32.

[0043] At least a portion of the side surface of the interposer 20 contacts a pressing member 33 provided on a predetermined surface 32. For example, if the interposer 20 is rectangular when viewed from above, the multiple pressing members 33 press the side surfaces near each corner of the interposer 20 with their flat portions. With this configuration, the multiple pressing members 33 can press the side surfaces of the interposer 20 discontinuously and with their flat portions at the diagonal portions. Therefore, when the interposer 20 or the pressing members 33 shrink at low temperatures, they can slide linearly, making it possible to equalize the shrinkage.

[0044] (Variation 4) Next, a fourth modification of the first embodiment will be described. This modification has a cooling member on the opposite surface 22 of the interposer 20 and a thermal via inside the interposer 20. FIG. 8 is a cross-sectional view illustrating a cooling member and a thermal via according to the fourth modification of the first embodiment. In FIG. 8, the TV 26 of the interposer 20 is omitted so as not to make the figure complicated. As shown in FIG. 8, in a quantum device 1d of the fourth modification, the opposite surface 22 of the interposer 20 may be in contact with a cooling member 34. The cooling member 34 has a cooling function. For example, the cooling member 34 may have a cooling function by being connected to the sample stage 30. With this configuration, the opposite surface 22 of the interposer 20 can be cooled by the thermal conduction of the cooling member 34, and the cooling performance can be improved.

[0045] The interposer 20 may also include a thermal via 27. The thermal via 27 may be a member extending in a direction perpendicular to the mounting surface 21 of the interposer substrate 25. For example, the thermal via 27 may penetrate the interposer substrate 25. In this manner, the interposer 20 may include a thermal via 27 penetrating from the mounting surface 21 side to the opposite surface 22 side of the interposer substrate 25. The thermal via 27 may be, for example, a columnar or rectangular columnar shape having a central axis extending in a direction perpendicular to the mounting surface 21. The thermal via 27 can transfer heat between the mounting surface 21 side and the opposite surface 22 side.

[0046] The thermal via 27 preferably contains a material with high thermal conductivity. The thermal via 27 may contain the above-mentioned superconducting material. The thermal via 27 may contain the same superconducting material as the wiring layer 16, etc., or may contain a different superconducting material from the wiring layer 16, etc. The thermal via 27 may also contain the above-mentioned normal conductive material. The thermal via 27 may contain the same normal conductive material as the interposer wiring layer 24, etc., or may contain a different normal conductive material from the interposer wiring layer 24, etc. The thermal via 27 may also contain a ceramic with high thermal conductivity, such as aluminum nitride.

[0047] Thermal vias 27 may be connected to cooling member 34. Such a configuration can improve the cooling performance of quantum device 1d. Note that quantum device 1d may not be provided with thermal vias 27 and may be provided with only cooling member 34, or may not be provided with cooling member 34 and may be provided with only thermal vias 27. Alternatively, both cooling member 34 and thermal vias 27 may be provided.

[0048] Also, as shown in the balloon in the figure, the thermal via 27 may include a portion in which a taper is formed in which the diameter on the opposite surface 22 side is larger than the diameter on the mounting surface 21 side. That is, the thermal via 27 may include a portion in the shape of a truncated cone in which the cross section of the via becomes larger toward the opposite surface 22 side. The inclusion of a tapered shape increases the heat capacity, and can mitigate sudden temperature changes. Thus, the stability of the thermal via 27 against temperature can be improved. In addition, when the thermal via 27 is brought into contact with the cooling member 34, the thermal bonding area with the cooling member 34 increases. Thus, it is possible to promote heat transfer more effectively. Note that, when the temperature is changed from room temperature to an extremely low temperature at the interface between the thermal via 27 and the through hole, the adhesive force at the interface may decrease. For example, when a force greater than the adhesive force is applied at the interface between the thermal via 27 and the through hole due to thermal contraction, or when a material with a low elastic modulus is used for the wall surface, the elastic modulus increases (molecules do not move) at an extremely low temperature, and the adhesive force is lost, which may cause peeling. In the case of peeling, it is expected that the position of the thermal via 27 will move, but by including a tapered shape, it is possible to maintain the contact surface at the interface between the thermal via 27 and the through hole even if the vertical position moves. In the case where the thermal via 27 moves, a convex shape that maintains contact with the cooling member 34 may be formed in advance on the cooling member 34, so that the contact between the cooling member 34 and the thermal via 27 can be maintained.

[0049] Furthermore, as shown in another balloon in the figure, the interposer 20 may include a common connection member 28 that connects the multiple thermal vias 27. For example, the multiple thermal vias 27 may be connected by a plate-like connection member 28 that is parallel to the mounting surface 21. The connection member 28 preferably includes a material with high thermal conductivity, and may include the same material as the thermal vias 27. The multiple thermal vias 27 connected by the connection member 28 can increase the heat capacity and suppress temperature changes.

[0050] Also, a constant potential may be applied to the multiple thermal vias 27 connected by the connection members 28. For example, a ground potential may be applied. This allows the quantum chip 10 or the interposer 20 to obtain the ground potential from the thermal vias 27. In this case, it is preferable that the thermal vias 27 and the connection members 28 have high thermal conductivity and contain a conductive material.

[0051] In the interposer 20, the region where the wiring or signal line connected to the quantum circuit 17 is mounted generates more heat than the other regions. Therefore, it is preferable to make the density of the thermal vias 27 in such a region greater than the density in the other regions. For example, when the interposer substrate 25 is viewed from above and the quantum chip 10 is mounted in the center of the interposer 20, the density of the thermal vias 27 in the central region is made greater than the density of the thermal vias 27 in the peripheral region. Also, in the interposer 20, it is preferable to make the density of the thermal vias 27 in the vicinity of the TV 26 that transmits the signal from the quantum circuit 17 greater than the density in the other regions. This can improve the cooling performance.

[0052] (Variation 5) Next, a fifth modification of the first embodiment will be described. In this modification, the sample stage 30 has a recess at the bottom of the recess 31. FIG. 9 is a cross-sectional view illustrating a recess formed at the bottom of the recess 31 of the sample stage 30 according to the fifth modification of the first embodiment. FIG. 10 is a plan view illustrating a recess formed at the bottom of the recess 31 of the sample stage 30 according to the fifth modification of the first embodiment. As shown in FIGS. 9 and 10, in the quantum device 1e of the fifth modification, a recess 35 is formed at the bottom of the recess 31. As shown in FIG. 10, when viewed from above, the region of the recess 35 is larger than the region 18 in which the quantum circuit 17 is formed. Therefore, the region 18 in which the quantum circuit 17 is formed is included in the region of the recess 35. The peripheral portion of the second surface 12 of the quantum chip 10 may contact the bottom of the recess 31. The central portion of the second surface 12 of the quantum chip 10 covers the recess 35.

[0053] Viewed from above, the area of ​​the recess 35 may be larger than the quantum chip 10. In this case, the second surface 12 of the quantum chip 10 does not contact the bottom of the recess 31.

[0054] In the quantum device 1e, when viewed from above, the area of ​​the recess 35 is larger than the area 18 in which the quantum circuit 17 is formed, so that the distance between the area 18 in which the quantum circuit 17 is formed and the sample stage 30 including a metal or the like can be increased. This makes it possible to suppress the generation of a pseudo capacitor and reduce the effect of resonance occurring in the main material such as silicon of the chip substrate 15. Therefore, the effect on the operating frequency of the quantum circuit 17 can be reduced.

[0055] (Variation 6) Next, a sixth modification of the first embodiment will be described. In this modification, the periphery of the second surface 12 of the quantum chip 10 is bonded or joined to the periphery of the recess 35. FIG. 11 is a cross-sectional view illustrating a recess formed at the bottom of the recess of the sample stage according to the sixth modification of the first embodiment. As shown in FIG. 11, in the quantum device 1f of the sixth modification, the periphery of the second surface 12 of the quantum chip 10 may be bonded to the bottom of the recess 31 by an adhesive layer BL, or may be joined by a joining layer ML such as a metal layer. With this configuration, it is possible to improve the installation stability of the quantum chip 10 and improve the positional accuracy while reducing the effect of resonance. In addition, it is possible to improve the thermal connection with the sample stage 30.

[0056] (Variation 7) Next, a seventh modification of the first embodiment will be described. In this modification, there is a space between the periphery of the second surface 12 of the quantum chip 10 and the periphery of the recess 35. FIG. 12 is a cross-sectional view illustrating a recess formed at the bottom of the recess of the sample stage according to the seventh modification of the first embodiment. As shown in FIG. 12, in the quantum device 1g of the seventh modification, the periphery of the second surface 12 of the quantum chip 10 does not need to contact the sample stage 30. That is, the periphery of the second surface 12 of the quantum chip 10 may be disposed with a space between it and the bottom of the recess 31. With this configuration, it is possible to suppress the stress and strain caused by the contraction difference between the quantum chip 10 and the sample stage 30 caused by the temperature change to an extremely low temperature while reducing the effect of resonance.

[0057] (Variation 8) Next, an eighth modification of the first embodiment will be described. This modification has a pillar in the recess 35. FIG. 13 is a cross-sectional view illustrating a recess and pillars formed at the bottom of the recess of the sample table according to the eighth modification of the first embodiment. As shown in FIG. 13, in the quantum device 1h of the eighth modification, a recess 35 is formed at the bottom of the recess 31. One or more pillars 36 are provided in the recess 35. The pillar 36 extends in a direction perpendicular to the first surface 11 and the second surface 12. One end of the pillar 36 is connected to the bottom of the recess 35, and the other end of the pillar 36 is in contact with the second surface 12 of the quantum chip 10. In this way, the quantum chip 10 is in contact with the pillar 36 extending from the bottom of the recess 35 in a direction perpendicular to the first surface 11. The pillar 36 may be cylindrical or columnar. The one or more pillars 36 and the second surface 12 may be bonded by an adhesive layer BL or may be joined by a metal layer.

[0058] In the quantum device 1h, the area of ​​the recess 35 is larger than the area 18 in which the quantum circuit 17 is formed when viewed from above, so that the distance between the area 18 in which the quantum circuit 17 is formed and the sample stage 30 including a metal or the like can be increased. This can reduce the effect of resonance occurring in the main material such as silicon of the chip substrate 15. At the same time, the pillars 36 contact the second surface 12 of the quantum chip 10, so that the cooling performance can be improved.

[0059] (Variation 9) Next, a ninth modification of the first embodiment will be described. In this modification, the sample stage 30 has a through hole at the bottom of the recess 31. FIG. 14 is a cross-sectional view illustrating a through hole formed at the bottom of the recess 31 of the sample stage 30 according to the ninth modification of the first embodiment. As shown in FIG. 14, in the quantum device 1i of the ninth modification, a through hole 37 is formed at the bottom of the recess 31. When viewed from above, the area of ​​the through hole 37 is larger than the area 18 in which the quantum circuit 17 is formed. Therefore, the area 18 in which the quantum circuit 17 is formed is included in the area of ​​the through hole 37. The peripheral portion of the second surface 12 of the quantum chip 10 may be in contact with the bottom of the recess 31, or may be bonded or joined to the bottom of the recess 31. The center portion of the second surface 12 of the quantum chip 10 covers the through hole 37.

[0060] In the quantum device 1i, the area of ​​the through hole 37 is larger than the area 18 in which the quantum circuit 17 is formed when viewed from above, so that the distance between the area 18 in which the quantum circuit 17 is formed and the sample stage 30 including a metal or the like can be increased. This can reduce the effect of resonance occurring in the main material such as silicon of the chip substrate 15. Therefore, the effect on the operating frequency of the quantum circuit 17 can be reduced.

[0061] (Variation 10) Next, a tenth modification of the first embodiment will be described. In this modification, the quantum chip 10 fits into the recess 31 at an extremely low temperature. FIG. 15 is a cross-sectional view illustrating the recess 31 of the sample stage 30 according to the tenth modification of the first embodiment. As shown in FIG. 15, in the quantum device 1j of the tenth modification, the quantum chip 10 fits into the recess 31 at an extremely low temperature. Therefore, the side of the quantum chip 10 is in contact with the inner surface of the recess 31. As a result, the quantum chip 10 is cooled by thermal conduction from the side, thereby improving the cooling performance.

[0062] When the quantum device 1j is cooled from room temperature to an extremely low temperature of several mK, the quantum chip 10, the interposer 20, and the sample stage 30 undergo volumetric changes. Therefore, taking into consideration the volumetric changes in advance, the side of the quantum chip 10 is arranged to contact the recess 31 at an extremely low temperature. In addition, the ground potential of the quantum chip 10 may be obtained from the sample stage 30 via the side of the quantum chip 10. Some of the first to tenth modifications of the first embodiment may be combined as appropriate.

[0063] (Embodiment 2) Next, a quantum device according to a second embodiment will be described. In the quantum device of this embodiment, the side surface of the interposer 20 contacts the inner surface of the recess 31. FIG. 16 is a cross-sectional view illustrating a quantum device according to the second embodiment. As shown in FIG. 16, the quantum device 2 of this embodiment is similar to the first embodiment in that it includes a quantum chip 10 and an interposer 20. However, in the quantum device 2, at least a portion of the side surface of the interposer 20 contacts the inner surface of the recess 31.

[0064] With this configuration, the mounting surface 21 of the interposer 20 does not need to be in contact with the sample stage 30, so that the mounting surface 21 can be utilized to the maximum extent. For example, the interposer wiring layer 23 can be formed to the maximum extent on the mounting surface 21. Other configurations and effects are included in the description of the first embodiment. In addition, some of the first to tenth modifications of the first embodiment may be combined with the configuration of the second embodiment.

[0065] (Embodiment 3) Next, a quantum device according to a third embodiment will be described. In the quantum device according to the present embodiment, a recess 31 is formed with a countersunk groove. FIG. 17 is a cross-sectional view illustrating a quantum device according to the third embodiment. FIG. 18 is a plan view illustrating the recess 31 and the countersunk groove of the sample stage 30 according to the third embodiment. As shown in FIGS. 17 and 18, in the quantum device 3, the recess 31 of the sample stage 30 is formed on a predetermined surface 32 of the sample stage 30. Then, a countersunk groove 38 is formed around the opening of the recess 31. As a result, a step surface 39 having a step with the predetermined surface 32 is formed around the opening of the recess 31. Therefore, the countersunk groove 38 includes the step surface 39.

[0066] The step surface 39 is, for example, parallel to the predetermined surface 32. The step surface 39 is formed around the recess 31. The step surface 39 surrounds the recess 31. The quantum chip 10 is disposed inside the recess 31. A portion of the mounting surface 21 of the interposer 20 contacts the step surface 39.

[0067] An insulating film may be formed on a portion of the mounting surface 21 of the interposer 20 that contacts the step surface 39 in order to prevent electrical conduction with the step surface 39. Moreover, the interposer wiring layer 23 may not be formed on the portion of the mounting surface 21 that contacts the step surface 39.

[0068] As shown in Fig. 18, the recess 31 may have spaces on all four sides so that the quantum chip 10 can be placed therein. The recess 31 may also have a shape with rounded or circular corners added to the four corners. This makes it possible to suppress the occurrence of stress and distortion due to volumetric changes when cooled to extremely low temperatures. In particular, it is possible to avoid stress concentration at the four corners due to right-angle and acute-angle shapes.

[0069] In the quantum device 3 of this embodiment, the interposer 20 is disposed inside the countersink 38 and is therefore surrounded by the sample stage 30. This improves the cooling performance. In addition, a part of the mounting surface 21 of the interposer 20 is in contact with the step surface 39, which also improves the cooling performance. In addition, the step between the predetermined surface 32 and the opposite surface 22 can be reduced, which improves the degree of freedom in arranging the quantum device 3. Other configurations and effects are included in the description of the first and second embodiments. Note that some of the first to tenth modifications of the first embodiment may be combined with the configuration of the third embodiment.

[0070] (Embodiment 4) Next, a quantum device according to a fourth embodiment will be described. In the quantum device of this embodiment, the interposer 20 is in contact with the side surface of the countersunk portion 38. FIG. 19 is a cross-sectional view illustrating a quantum device according to the fourth embodiment. As shown in FIG. 19, in the quantum device 4, the recess 31 of the sample stage 30 is formed on a predetermined surface 32 of the sample stage 30. Then, the countersunk portion 38 is formed around the opening of the recess 31. As a result, a step surface 39 having a step with the predetermined surface 32 is formed around the opening of the recess 31.

[0071] In the quantum device 4 of this embodiment, at least a part of the side of the interposer 20 contacts a side of the countersunk 38 between the step surface 39 and the predetermined surface 32. A part of the mounting surface 21 of the interposer 20 is disposed with a space between it and the step surface 39. This allows the mounting surface 21 of the interposer 20 to be used to the maximum extent possible since it is not necessary for the mounting surface 21 to contact the sample stage 30. Other configurations and effects are included in the description of the first to third embodiments. Note that some of the first to tenth modifications of the first embodiment may be combined with the configuration of the fourth embodiment.

[0072] (Modification) Next, a modified example of the fourth embodiment will be described. This modified example has a spacer between the mounting surface 21 and the step surface 39 of the interposer 20. FIG. 20 is a cross-sectional view illustrating a spacer according to the modified example of the fourth embodiment. As shown in FIG. 20, in the quantum device 4a, a part of the mounting surface 21 of the interposer 20 is disposed between the step surface 39 and a spacer SP interposed therebetween. That is, the spacer SP is disposed between the mounting surface 21 and the step surface 39. The spacer SP preferably includes an insulating material having high thermal conductivity, such as aluminum nitride, silicon carbide, sapphire, silicon, alumina, or the like.

[0073] Since the quantum device 4a has the spacer SP, it is possible to improve the installation stability of the quantum chip 10 and improve the positional accuracy. It is also possible to improve the thermal connection with the sample stage 30. Furthermore, by forming the interposer wiring layer 23, it is possible to make the most of the mounting surface 21.

[0074] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments and can be modified as appropriate without departing from the spirit of the invention. For example, a quantum device in which multiple quantum chips 10 are mounted on one interposer 20 is also included in the scope of the technical idea of ​​the present embodiment. In addition, an assembly of each configuration of the first to fourth embodiments and each modified example is also included in the scope of the technical idea of ​​the present embodiment.

[0075] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes.

[0076] (Appendix 1) A quantum chip that performs information processing using quantum states; an interposer on which the quantum chip is mounted; Equipped with The quantum chip is disposed inside a recess formed in a sample stage having a cooling function; A portion of the interposer is in contact with the sample stage. Quantum devices.

[0077] (Appendix 2) the quantum chip has a first surface mounted on the interposer and a second surface opposite the first surface; At least a portion of the second surface is in contact with the inner surface of the recess. 2. The quantum device of claim 1.

[0078] (Appendix 3) the quantum chip has a first surface mounted on the interposer and a second surface opposite the first surface; At least a portion of the second surface is adhered or bonded to the inner surface of the recess. 2. The quantum device of claim 1.

[0079] (Appendix 4) the quantum chip has a first surface mounted on the interposer and a second surface opposite the first surface; The second surface is disposed with a space between it and the inner surface of the recess. 2. The quantum device of claim 1.

[0080] (Appendix 5) The recess is formed on a predetermined surface of the sample stage, A part of the mounting surface of the interposer on which the quantum chip is mounted is in contact with the predetermined surface, 5. The quantum device according to claim 1.

[0081] (Appendix 6) At least a portion of a side surface of the interposer is in contact with a plurality of holding members provided on the predetermined surface. 6. The quantum device of claim 5.

[0082] (Appendix 7) the interposer is rectangular when viewed in a direction perpendicular to the mounting surface, the plurality of pressing members pressing the side surfaces of the interposer near the respective corners with flat portions thereof; 7. The quantum device of claim 6.

[0083] (Appendix 8) The interposer has a mounting surface on which the quantum chip is mounted and an opposite surface opposite to the mounting surface, The opposite surface is in contact with a cooling member having a cooling function. 8. The quantum device according to claim 1,

[0084] (Appendix 9) The interposer has a mounting surface on which the quantum chip is mounted and an opposite surface opposite to the mounting surface, The interposer includes an interposer substrate and a thermal via that penetrates from the mounting surface side to the opposite surface side of the interposer substrate. 9. The quantum device according to any one of claims 1 to 8.

[0085] (Appendix 10) the thermal via includes a tapered portion having a diameter on the opposite surface side larger than a diameter on the mounting surface side; 10. The quantum device of claim 9.

[0086] (Appendix 11) The interposer further includes a common connection member that connects a plurality of the thermal vias. 11. The quantum device of claim 9 or 10.

[0087] (Appendix 12) The quantum chip includes a quantum circuit in which a resonator having a loop circuit in which a superconducting material is connected in a ring shape by Josephson junctions is formed, A depression is formed at the bottom of the recess, When viewed from a direction perpendicular to the first surface of the quantum chip mounted on the interposer, the region in which the quantum circuit is formed is included in the recessed region, 12. The quantum device according to claim 1.

[0088] (Appendix 13) The quantum chip is in contact with a pillar extending from the bottom of the recess in a direction perpendicular to the first surface. 13. The quantum device of claim 12.

[0089] (Appendix 14) The quantum chip includes a quantum circuit in which a resonator having a loop circuit in which a superconducting material is connected in a ring shape by Josephson junctions is formed, A through hole is formed in the bottom of the recess, When viewed from a direction perpendicular to the first surface of the quantum chip mounted on the interposer, the region in which the quantum circuit is formed is included in the region of the through hole, 12. The quantum device according to claim 1.

[0090] (Appendix 15) The side surface of the quantum chip is in contact with the inner surface of the recess. 15. The quantum device according to any one of claims 1 to 14.

[0091] (Appendix 16) The recess is formed on a predetermined surface of the sample stage, At least a portion of a side surface of the interposer is in contact with an inner surface of the recess. 16. The quantum device according to any one of claims 1 to 15.

[0092] (Appendix 17) The recess is formed on a predetermined surface of the sample stage, a step surface having a step with respect to the predetermined surface is formed around the periphery of the opening of the recess, A part of the mounting surface of the interposer on which the quantum chip is mounted is in contact with the step surface, 16. The quantum device according to any one of claims 1 to 15.

[0093] (Appendix 18) The recess is formed on a predetermined surface of the sample stage, a step surface having a step with respect to the predetermined surface is formed around the periphery of the opening of the recess, At least a part of a side surface of the interposer is in contact with a side surface between the step surface and the predetermined surface. 16. The quantum device according to any one of claims 1 to 15.

[0094] (Appendix 19) A part of the mounting surface of the interposer on which the quantum chip is mounted is disposed with a space between the mounting surface and the step surface, 19. The quantum device of claim 18.

[0095] (Appendix 20) A part of the mounting surface of the interposer on which the quantum chip is mounted is disposed between the step surface and a spacer interposed therebetween. 19. The quantum device of claim 18. [Explanation of symbols]

[0096] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j Quantum Devices 2, 3, 4, 4a Quantum Devices 10. Quantum Chip 11 Page 1 12 Side 2 15 Chip Substrate 16 wiring layer 17 Quantum circuit 17a Josephson junction 17b Loop circuit 17c resonator 18 areas 20 Interposer 21 Mounting surface 22 Opposite side 23 Interposer wiring layer 23a Magnetic field application circuit 23b Readout section 24 Interposer wiring layer 24a terminal 25 Interposer Board 26 TV 27 Thermal via 28 Connection parts 30 Sample stage 31 Recess 32 Specified surface 33 Retaining member 34 Cooling material 35 Dent 36 Pillar 37 Through hole 38 Countersink 39 Step surface 101 Quantum Devices 110 Quantum Chip 111 Page 1 112 Side 2 120 Interposer 121 Mounting surface 122 opposite side 124a Terminal 130 Sample stage 132 Specified surface BL adhesive layer BP Bump ML metal layer SP Spacer

Claims

1. Quantum chips and an interposer on which the quantum chip is mounted; A sample stage having an opening and a cooling function; Equipped with The interposer is disposed in the opening, and a portion of the interposer is connected to the sample stage; The opening is formed in a predetermined surface of the sample stage, A step surface having a step with respect to the predetermined surface is formed within the opening, A part of a mounting surface of the interposer on which the quantum chip is mounted is connected to the step surface. Quantum devices.

2. The opening is formed in a predetermined surface of the sample stage, A step surface having a step with respect to the predetermined surface is formed within the opening, At least a part of a side surface of the interposer is connected to a side surface in the opening, the side surface having a different surface direction from the step surface. The quantum device of claim 1 .

3. A part of the mounting surface of the interposer on which the quantum chip is mounted is disposed between the step surface and a spacer interposed therebetween. The quantum device according to claim 1 or 2.

4. The spacer is made of an insulating material. The quantum device of claim 3.

5. The quantum chip has a first surface mounted on the interposer and a second surface opposite the first surface; At least a portion of the second surface is in contact with the bottom of the opening. The quantum device of claim 1 .

6. The quantum chip has a first surface mounted on the interposer and a second surface opposite the first surface; At least a portion of the second surface is disposed with a space between it and a bottom of the opening. The quantum device of claim 1 .

7. The quantum chip includes a quantum circuit in which a resonator having a loop circuit in which a superconducting material is connected in a ring shape by Josephson junctions is formed, A recess is formed at the bottom of the opening, When viewed from a direction perpendicular to the first surface of the quantum chip mounted on the interposer, the region in which the quantum circuit is formed is included in the recessed region. The quantum device according to any one of claims 1 to 5.

8. The quantum chip is in contact with a pillar extending from the bottom of the recess in a direction perpendicular to the first surface. The quantum device of claim 7.

9. The quantum chip includes a quantum circuit in which a resonator having a loop circuit in which a superconducting material is connected in a ring shape by Josephson junctions is formed, A through hole is formed at the bottom of the opening, When viewed from a direction perpendicular to the first surface of the quantum chip mounted on the interposer, the region in which the quantum circuit is formed is included in the region of the through hole. The quantum device according to any one of claims 1 to 5.

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