Semiconductor Device

Abstract

To prevent an overcurrent situation of a power semiconductor element and errors in notification of overcurrent detection to a superior control unit.SOLUTION: A semiconductor device includes: a power semiconductor element; an overcurrent detection circuit 160; and a logic circuit 10 having a function to output an off signal to the power semiconductor element when the overcurrent detection circuit 160 detects an overcurrent. The logic circuit 10 includes a pulse generation circuit 40 which, upon an input of an input signal that instructs to turn on the power semiconductor element, generates and outputs a pulse, and when the overcurrent detection circuit 160 detects an overcurrent continuously from before the pulse is output, outputs a signal output that instructs to turn on the power semiconductor element for a predetermined period after the start of the output of the pulse.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power semiconductor element, which is a voltage-driven power control element, and a semiconductor device including a circuit for driving and protecting the power semiconductor element. [Background technology]

[0002] Automobiles are equipped with many semiconductor devices that perform switching control of loads such as motors. For such on-board semiconductor devices, IPS (Intelligent Power Switch) is used, which integrates a power semiconductor element that supplies power to the load and its control circuit on the same chip. For this IPS, especially for automotive electrical equipment applications, a high-side IPS is generally used, which is placed between the power source and the load from the viewpoint of safety during maintenance of the load.

[0003] Semiconductor products used in the automotive field are required to be designed to withstand any damage under any circumstances. In a high-side IPS, if the load is in an overcurrent state, an excessive current greater than that during normal operation flows through the load, which may cause failure of the power semiconductor element and the surrounding circuits.

[0004] A technique has been proposed for controlling the current to be limited when an overcurrent state is detected, or for adjusting the overcurrent detection threshold for limiting the current (see, for example, Patent Document 1). In particular, the overcurrent protection circuit in Patent Document 1 is a technique that ensures both instantaneous current during normal operation and overcurrent protection according to the load.

[0005] Next, we will explain a general high-side IPS and its specific operation when it detects an overcurrent state, which is different from the overcurrent protection circuit in Patent Document 1. This general high-side IPS is based on the configuration described in Non-Patent Document 1.

[0006] FIG. 9 is a diagram showing an example of the configuration of a conventional IPS, FIG. 10 is a block diagram showing an example of the function of a logic circuit when an overcurrent is detected, and FIG. 11 is a diagram showing an example of a timing decision circuit. FIG. 12 is a time chart of a first operation example of the timing decision circuit, where (A) shows the case where an overcurrent is detected during an ON operation, and (B) shows the case where an overcurrent is detected before an ON operation. FIG. 13 is a waveform diagram of the first operation example when an overcurrent is detected, where (A) shows the case where an overcurrent is detected during an ON operation, and (B) shows the case where an overcurrent is detected before an ON operation. FIG. 14 is a time chart of a second operation example of the timing decision circuit, where (A) shows the case where an overcurrent is detected during an ON operation, and (B) shows the case where an overcurrent is detected before an ON operation. FIG. 15 is a waveform diagram of the second operation example when an overcurrent is detected, where (A) shows the case where an overcurrent is detected during an ON operation, and (B) shows the case where an overcurrent is detected before an ON operation. In the explanation of FIG. 9, the same symbols may be used for the terminal names and the voltages, signals, etc. at those terminals.

[0007] As shown in Fig. 9, the conventional IPS 100 includes a main MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 110, a logic circuit 120, and a driver circuit 130. The main MOSFET 110 may be a circuit that combines an IGBT (Insulated Gate Bipolar Transistor), which is a voltage-driven power control element, and an FWD (Free Wheeling Diode). The IPS 100 also includes a low-voltage detection circuit 140, a short-circuit detection circuit 150, an overcurrent detection circuit 160, an overheat detection circuit 170, an N-channel MOSFET 180, a constant current circuit 182, an operational amplifier 190, and gain setting resistors 191, 192, 193, and 194.

[0008] The IPS 100 has an IN terminal, a VCC terminal, an OUT terminal, an IN+ terminal, an IN- terminal, an AMP terminal, and a GND terminal. The IN terminal and the AMP terminal of the IPS 100 are connected to a microcomputer 200, which is a higher-level control device, and the microcomputer 200 generates a signal for turning the main MOSFET 110 on and off based on the load current obtained from the AMP terminal of the IPS 100, and supplies the signal to the IN terminal of the IPS 100. In the illustrated example, the signal for turning the main MOSFET 110 on has a potential of 5 volts (V), and the signal for turning the main MOSFET 110 off has a potential of 0V.

[0009] The IN terminal of the IPS 100 is connected to the input terminal of the logic circuit 120, the output terminal of the logic circuit 120 is connected to the input terminal of the driver circuit 130 having a level shift function, and the output terminal of the driver circuit 130 is connected to the gate terminal of the main MOSFET 110. The drain terminal of the main MOSFET 110 is connected to the VCC terminal, and the VCC terminal is connected to the positive terminal of the power supply 210. The negative terminal of the power supply 210 is connected to the reference potential (GND). The source terminal of the main MOSFET 110 is connected to the OUT terminal, and the OUT terminal is connected to one terminal of the load 220. The other terminal of the load 220 is connected to one terminal of the shunt resistor 230, and the other terminal of the shunt resistor 230 is connected to the reference potential. The shunt resistor 230 has one terminal connected to the IN+ terminal of the IPS 100, and the other terminal connected to the IN- terminal. The GND terminal of the IPS 100 is connected to the reference potential.

[0010] The VCC terminal of the IPS 100 is connected to an input terminal of the low voltage detection circuit 140, and the output terminal of the low voltage detection circuit 140 is connected to the logic circuit 120. The VCC terminal of the IPS 100 is connected to one input terminal of the short circuit detection circuit 150, the other input terminal of the short circuit detection circuit 150 is connected to the OUT terminal, and the output terminal of the short circuit detection circuit 150 is connected to the logic circuit 120. The VCC terminal of the IPS 100 is connected to a drain terminal of a MOSFET 180, and the gate terminal of the MOSFET 180 is connected to an output terminal of the driver circuit 130. The source terminal of the MOSFET 180 is connected to one terminal of the constant current circuit 182 and one input terminal of the overcurrent detection circuit 160, the other input terminal of the overcurrent detection circuit 160 is connected to the OUT terminal, and the output terminal of the overcurrent detection circuit 160 is connected to the logic circuit 120. The output terminal of the overheat detection circuit 170 is connected to the logic circuit 120. The IN+ terminal of the IPS 100 is connected to one terminal of a gain setting resistor 191, and the other terminal of the gain setting resistor 191 is connected to one terminal of a gain setting resistor 192 and a non-inverting input terminal of an operational amplifier 190. The other terminal of the gain setting resistor 192 is connected to a GND terminal. The IN- terminal of the IPS 100 is connected to one terminal of a gain setting resistor 193, and the other terminal of the gain setting resistor 193 is connected to one terminal of a gain setting resistor 194 and an inverting input terminal of the operational amplifier 190. The output terminal of the operational amplifier 190 is connected to the other terminal of the gain setting resistor 194 and the AMP terminal of the IPS 100.

[0011] The low voltage detection circuit 140 monitors whether the voltage VCC at the VCC terminal is equal to or higher than a predetermined voltage that enables the operation of the IPS 100, and when the voltage VCC drops below the predetermined voltage, it notifies the logic circuit 120 of the abnormal drop in voltage VCC. When the logic circuit 120 is notified of the abnormal drop in voltage VCC, it outputs a signal to the driver circuit 130 to stop the operation of the main MOSFET 110 and MOSFET 180 so that the IPS 100 does not perform abnormal operation.

[0012] The short circuit detection circuit 150 detects a short circuit in the load 220 from the difference between the voltage VCC at the VCC terminal and the voltage at the OUT terminal when the main MOSFET 110 is on. When the short circuit detection circuit 150 detects a short-circuit state in the load 220, it notifies the logic circuit 120. Upon receiving the notification, the logic circuit 120 outputs a signal to the driver circuit 130 to lower the gate voltages of the main MOSFET 110 and the MOSFET 180.

[0013] The overcurrent detection circuit 160 allows a constant current to flow through the constant current circuit 182 when the MOSFET 180 is turned on, and detects an overcurrent from a potential difference due to the on-resistance of the main MOSFET 110 and the MOSFET 180 when the main MOSFET 110 and the MOSFET 180 are turned on. When the overcurrent detection circuit 160 detects an overcurrent state of the load 220, it notifies the logic circuit 120. When the logic circuit 120 is notified of the overcurrent state of the load 220, it stops the operation of the main MOSFET 110 and the MOSFET 180 and controls the main MOSFET 110 and the MOSFET 180 to be turned on periodically for a short period of time. This control of turning on the main MOSFET 110 and the MOSFET 180 periodically for a short period of time is intended to detect whether the load 220 has returned to a normal state after the detection of an overcurrent. During this operation, the logic circuit 120 outputs a signal to stop the operation of the main MOSFET 110 and the MOSFET 180. The load current threshold at which the overcurrent detection circuit 160 determines an overcurrent is set lower than the load current threshold at which the short circuit detection circuit 150 determines a short circuit.

[0014] The overheat detection circuit 170 detects the temperature of the main MOSFET 110 or IPS 100, and when the temperature of the main MOSFET 110 or IPS 100 reaches or exceeds a predetermined temperature, it notifies the logic circuit 120 of the overheat state of the main MOSFET 110 or IPS 100. When the logic circuit 120 is notified of the overheat state, it outputs a signal to the driver circuit 130 to stop the operation of the main MOSFET 110 and MOSFET 180 in order to prevent a breakdown of the IPS 100.

[0015] The operational amplifier 190 and gain setting resistors 191, 192, 193, and 194 constitute a current detection circuit that detects the value of a current flowing through the load 220 and notifies the microcomputer 200. The current flowing through the load 220 is converted to a voltage by the shunt resistor 230, and the voltage is amplified by the operational amplifier 190 and supplied to the AMP terminal. The gain of the operational amplifier 190 at this time is set by the gain setting resistors 191, 192, 193, and 194.

[0016] 10 showing the functions during overcurrent detection, the logic circuit 120 includes an input circuit 121, an oscillation signal generating circuit 122, and a timing decision circuit 123. The input circuit 121 is a circuit that inputs an input signal IN that is received at an IN terminal and turns on / off the main MOSFET 110. An output terminal of the input circuit 121 is connected to a first input terminal of the oscillation signal generating circuit 122, and a second input terminal of the oscillation signal generating circuit 122 is connected to an output terminal of the overcurrent detection circuit 160. An output terminal of the oscillation signal generating circuit 122 is connected to an input terminal of the timing decision circuit 123.

[0017] The input circuit 121 shapes the waveform of the input signal IN that is input, and supplies the result to the oscillation signal generating circuit 122. When the input circuit 121 receives an overcurrent detection signal from the overcurrent detection circuit 160 while the input circuit 121 is receiving the input signal IN that turns on the main MOSFET 110, the oscillation signal generating circuit 122 generates an oscillation signal signal1 and supplies the generated signal signal1 to the timing decision circuit 123. Alternatively, when the input circuit 121 receives an input signal IN that turns on the main MOSFET 110 while the input circuit 121 is receiving an overcurrent detection signal from the overcurrent detection circuit 160, the oscillation signal generating circuit 122 generates an oscillation signal signal1 and supplies the generated signal signal1 to the timing decision circuit 123. The timing decision circuit 123 outputs a signal output that determines the timing for periodically turning on the main MOSFET 110 for a short period of time from the signal signal1.

[0018] As shown in Fig. 11, the timing decision circuit 123 includes T flip-flops TFF1, TFF2, and TFF3, NOR circuits NOR1 and NOR2, and a NAND circuit NAND1. An input terminal of the timing decision circuit 123 that receives a signal signal1 is connected to an input terminal of the T flip-flop TFF1 and one input terminal of the NOR circuit NOR1. An output terminal of the T flip-flop TFF1 is connected to an input terminal of the T flip-flop TFF2 and the other input terminal of the NOR circuit NOR1. An output terminal of the T flip-flop TFF2 is connected to an input terminal of the T flip-flop TFF3 and one input terminal of the NOR circuit NOR2. An output terminal of the T flip-flop TFF3 is connected to the other input terminal of the NOR circuit NOR2. The output terminal of the NOR circuit NOR1 is connected to one input terminal of the NAND circuit NAND1, the output terminal of the NOR circuit NOR2 is connected to the other input terminal of the NAND circuit NAND1, and the output terminal of the NAND circuit NAND1 constitutes the output terminal of the timing decision circuit 123.

[0019] When the timing decision circuit 123 receives the signal signal1 from the oscillation signal generation circuit 122, the signal signal1 is divided in sequence by a down counter circuit consisting of three stages of T flip-flops TFF1, TFF2, and TFF3. That is, the T flip-flop TFF1 outputs a signal signal2 with a period double that of the signal signal1, the T flip-flop TFF2 outputs a signal signal3 with a period double that of the signal signal2, and the T flip-flop TFF3 outputs a signal signal4 with a period double that of the signal signal3. The NOR circuit NOR1 receives the signals signal1 and signal2 and outputs a high (H) level signal when both are low (L) level, and the NOR circuit NOR2 receives the signals signal3 and signal4 and outputs an H level signal when both are L level. The NAND circuit NAND1 outputs an L level signal output only when it receives H level signals from the NOR circuits NOR1 and NOR2. Thus, the timing decision circuit 123 has a function of outputting an L-level signal output at the timing when the signals signal1, signal2, signal3, and signal4 are all at L level. This L-level signal output is logically inverted when input to the driver circuit 130 during the period in which an overcurrent is detected, and becomes a signal that periodically turns on the main MOSFET 110 for a short period of time.

[0020] The above-mentioned timing decision circuit 123 operates according to the signal signal1 supplied from the oscillation signal creation circuit 122, but the timing at which the signal signal1 is created may differ depending on the overcurrent detection signal or the input signal IN from the overcurrent detection circuit 160. That is, the oscillation signal creation circuit 122 may create the signal signal1 as a signal that rises in synchronization with the overcurrent detection signal or the input signal IN (first operation example), or as a signal that rises half a cycle after the overcurrent detection or input of the input signal IN (second operation example). First, the operation of the timing decision circuit 123 and the IPS 100 in the first operation example will be described.

[0021] Fig. 12(A) and Fig. 13(A) show the case where the timing of overcurrent detection by overcurrent detection circuit 160 is during input of input signal IN. Fig. 12(A) shows, from the top, input signal IN, the overcurrent detection state of overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the signal output output by timing decision circuit 123. Fig. 13(A) shows, from the top, input signal IN, output signal OUT at OUT terminal, load current IL, and signal AMP at AMP terminal.

[0022] 12A, when an H-level input signal IN is input and the main MOSFET 110 is turned on, the overcurrent detection circuit 160 outputs an L-level signal because it has not yet detected an overcurrent state. At this time, the oscillation signal creation circuit 122 outputs an L-level signal signal1, and the T flip-flops TFF1, TFF2, and TFF3 of the timing decision circuit 123 are in a reset state, so they output L-level signals signal2, signal3, and signal4. Therefore, the timing decision circuit 123 outputs an L-level signal output, and the driver circuit 130 maintains the output of a signal that turns on the main MOSFET 110.

[0023] When the main MOSFET 110 is in an on-state, an output signal OUT is output to the OUT terminal as shown in Fig. 13(A) . As a result, a load current IL starts to flow through the load 220, and the signal AMP at the AMP terminal has a signal waveform corresponding to the load current IL.

[0024] Next, when the overcurrent detection circuit 160 detects an overcurrent state and outputs an H-level overcurrent detection signal while the main MOSFET 110 is in an ON operation, the oscillation signal creation circuit 122 outputs a signal signal1 that rises in synchronization with the rising edge of the H-level signal. In the timing decision circuit 123, the remaining signals signal2, signal3, and signal4 also go to H level when the H-level signal signal1 is input. As a result, the timing decision circuit 123 outputs an H-level signal output.

[0025] 13A, when the overcurrent detection circuit 160 detects an overcurrent, the main MOSFET 110 turns off and the output signal OUT at the OUT terminal drops to approximately 0 V. This causes the load current IL flowing through the load 220 to drop, and the signal AMP at the AMP terminal also drops. At this time, the load current IL does not drop instantly, so the signal AMP at the AMP terminal also drops to approximately 0 V with a delay after the overcurrent is detected. This allows the microcomputer 200 to know that the overcurrent detection circuit 160 has detected an overcurrent with a delay after the actual overcurrent is detected.

[0026] When the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal creation circuit 122 and the timing decision circuit 123 operate to periodically output the signal output. That is, as shown in Fig. 12(A), the signal signal1 is divided in sequence, and the signal output becomes L level during the output effective period in which all the signals signal1, signal2, signal3, and signal4 are L level. Since the main MOSFET 110 turns on every time this L level signal output is output, the output signal OUT is output to the OUT terminal, and the load current IL flows during that time. This allows the IPS 100 to periodically check whether the state of the load 220 has returned to the normal state after the overcurrent detection.

[0027] 13A shows a case where the overcurrent state of the load 220 has already been released when the third signal output is output after the overcurrent detection. In this case, normal current flow to the load 220 is resumed. At this time, after an overcurrent recovery delay, a signal AMP having a magnitude according to the load current IL is output to the AMP terminal.

[0028] Finally, when the input signal IN goes to the L level, the main MOSFET 110 turns off, and the output signal OUT at the OUT terminal drops to approximately 0 V. As a result, the load current IL of the load 220 starts to decrease, and the signal AMP at the AMP terminal also starts to decrease.

[0029] Next, with reference to Fig. 12(B) and Fig. 13(B), a case will be described where the timing of overcurrent detection by overcurrent detection circuit 160 is before the input signal IN is input. Fig. 12(B) shows, from the top, the input signal IN, the overcurrent detection state of overcurrent detection circuit 160, signals signal1, signal2, signal3, and signal4, and the signal output output by timing decision circuit 123. Fig. 13(B) shows, from the top, the input signal IN, the output signal OUT at the OUT terminal, the load current IL, and the signal AMP at the AMP terminal.

[0030] When an H-level input signal IN is input while the overcurrent detection signal is being output, the oscillation signal generating circuit 122 outputs a signal signal1 that rises at the timing when the input signal IN is input. After the H-level signal signal1 is output, the timing determining circuit 123 operates in the same manner as in FIG. 12(A).

[0031] 13B, when an H-level input signal IN is input while an overcurrent is detected, first, the main MOSFET 110 turns on and an output signal OUT is output to the OUT terminal. At this time, a load current IL starts to flow through the load 220, and a signal AMP having a magnitude according to the load current IL is also output to the AMP terminal.

[0032] At the time when the H-level input signal IN is input, the circuit is already in an overcurrent detection state, so immediately after that time the main MOSFET 110 is turned off and the output signal OUT at the OUT terminal drops to approximately 0 V. Immediately after this, the load current IL drops and the signal AMP at the AMP terminal also drops immediately. When the signal AMP drops to approximately 0 V, the microcomputer 200 learns that the overcurrent detection circuit 160 has detected an overcurrent with a delay from the time when the H-level input signal IN was input.

[0033] During the period in which the H-level input signal IN is subsequently input, the signal output is periodically performed to check whether the overcurrent state of the load 220 has returned to normal, and the operation of the load 220 after the overcurrent is released is the same as that shown in FIG. 13(A).

[0034] Next, the operation of the timing decision circuit 123 and the IPS 100 in a second operation example in which the oscillation signal creation circuit 122 sets the signal signal1 to a signal that rises half a cycle after the detection of an overcurrent or the input of the input signal IN will be described.

[0035] Fig. 14(A) and Fig. 15(A) show the case where the timing of overcurrent detection by overcurrent detection circuit 160 is during input of input signal IN. Fig. 14(A) shows, from the top, input signal IN, the overcurrent detection state of overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the signal output output by timing decision circuit 123. Fig. 15(A) shows, from the top, input signal IN, output signal OUT at OUT terminal, load current IL, and signal AMP at AMP terminal.

[0036] 14(A), when an H-level input signal IN is input and the main MOSFET 110 turns on, the overcurrent detection circuit 160 outputs an L-level signal because it has not yet detected an overcurrent state. At this time, the oscillation signal creation circuit 122 outputs an L-level signal signal1, the timing decision circuit 123 outputs an L-level signal output, and the driver circuit 130 outputs a signal to turn on the main MOSFET 110.

[0037] 15A, the main MOSFET 110 is turned on, and an output signal OUT is output to the OUT terminal. As a result, a load current IL starts to flow through the load 220, and the signal AMP at the AMP terminal has a signal waveform corresponding to the load current IL.

[0038] Next, when the overcurrent detection circuit 160 detects an overcurrent state and outputs an H-level overcurrent detection signal, the oscillation signal creation circuit 122 outputs a signal signal1 that rises half a cycle after the rising edge of the H-level overcurrent detection signal. After the H-level signal signal1 is output, the same operation as in the first operation example shown in Fig. 12(A) and Fig. 13(A) is performed.

[0039] Next, with reference to Fig. 14(B) and Fig. 15(B), a case where the timing of overcurrent detection by overcurrent detection circuit 160 is before input of input signal IN will be described. Fig. 14(B) shows, from the top, input signal IN, the overcurrent detection state of overcurrent detection circuit 160, signals signal1, signal2, signal3, and signal4, and the signal output output by timing decision circuit 123. Fig. 15(B) shows, from the top, input signal IN, output signal OUT at OUT terminal, load current IL, and signal AMP at AMP terminal.

[0040] When an H-level input signal IN is input while the overcurrent detection signal is being output, the oscillation signal generating circuit 122 generates a signal signal1 that starts at an L level from the timing when the input signal IN is input. Therefore, since the signal signal1 rises to an H level after a half cycle, the signal output output by the timing decision circuit 123 is valid until then, and the main MOSFET 110 performs an ON operation. After the signal signal1 first goes to an H level, the same operation as in the cases of Figures 14(A) and 15(A) is performed.

[0041] In Figures 12 and 14, when the input signal IN is at an L level, the signal output is at an H level. This is because a circuit (not shown) is configured so that when the input signal IN is at an L level, the signal output is at an H level. [Prior art documents] [Patent documents]

[0042] [Patent Document 1] International Publication No. 2017 / 187785 [Non-patent literature]

[0043] [Non-Patent Document 1] Sho Nakagawa, Takatomo Oe, and Motomitsu Iwamoto, "One-chip IPS for Linear Control "F5106H"," Fuji Electric Technical Review, December 30, 2013, Vol. 86, No. 4, pp. 43-46 Summary of the Invention [Problem to be solved by the invention]

[0044] However, in the first operation example, particularly when an overcurrent is detected before the input signal IN is input, the main MOSFET 110 is turned on and off immediately after the input signal IN of H level is input, as shown in FIG. 13(B). Therefore, since the width of the signal AMP at the AMP terminal is short, the microcomputer 200 receiving the signal AMP may not only be unable to detect the load current IL resulting from the instruction to turn on the main MOSFET 110, but may also be unable to know that an overcurrent has been detected. On the other hand, in the second operation example, when an overcurrent is detected after the input signal IN is input, there is a period in which an overcurrent flows in addition to a normal load current, as shown in FIG. 15(A). Therefore, the main MOSFET 110 is likely to be overheated, which may lead to a failure.

[0045] The present invention has been made in consideration of these points, and aims to provide a semiconductor device in which the main power semiconductor element is less likely to overheat and which does not erroneously notify a host control device of overcurrent detection. [Means for solving the problem]

[0046] In order to solve the above problems, the present invention provides, in one aspect, a semiconductor device including a power semiconductor element, an overcurrent detection circuit, and a logic circuit having a function of outputting an OFF signal to the power semiconductor element when the overcurrent detection circuit detects an overcurrent. The logic circuit generates a pulse when an input signal instructing the power semiconductor element to be turned on is input. and generates an oscillation signal synchronized with the rising edge of the input signal. When the overcurrent detection circuit detects an overcurrent continuously before the pulse is output, of the half period of the oscillation signal During this period, a signal instructing the power semiconductor element to be turned on is output. Effect of the Invention

[0047] In the semiconductor device having the above configuration, when an overcurrent is detected while the power semiconductor element is in an on-state, the power semiconductor element is immediately turned off, thereby preventing the power semiconductor element from reaching an overheated state. Also, if an overcurrent is detected at least during the period when the pulse generating circuit is outputting a pulse, an on signal is output to the power semiconductor element for a predetermined period, thereby ensuring a sufficient period for notifying the upper control device of the overcurrent detection, and preventing erroneous notification.

[0048] The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention. [Brief description of the drawings]

[0049] [Figure 1] FIG. 2 is a block diagram showing an example of the configuration of a logic circuit of a high-side IPS according to the present invention. [Diagram 2] 4 is a circuit diagram showing an example of an input circuit and a pulse generating circuit. FIG. [Diagram 3] FIG. 1 is a circuit diagram illustrating an example of a gated latch circuit. [Figure 4] FIG. 2 is a circuit diagram illustrating an example of an overcurrent mode switching circuit. [Diagram 5] FIG. 2 is a circuit diagram showing an example of a timing determination circuit. [Figure 6]5 is a time chart showing an operation of a logic circuit when an overcurrent detection state occurs after an input signal is input. [Figure 7] 5 is a time chart showing an operation of a logic circuit when an overcurrent detection state occurs before an input signal is input. [Figure 8] 11 is a time chart showing the operation of a logic circuit when an overcurrent is detected while a pulse generating circuit is outputting a pulse. [Figure 9] FIG. 1 is a diagram illustrating an example of the configuration of a conventional IPS. [Figure 10] 11 is a block diagram showing an example of the function of a logic circuit when an overcurrent is detected; FIG. [Figure 11] FIG. 13 is a diagram illustrating an example of a timing determination circuit. [Figure 12] 1 is a time chart of a first operation example of the timing determination circuit, in which (A) shows a case where an overcurrent is detected during an ON operation, and (B) shows a case where an overcurrent is detected before an ON operation. [Figure 13] FIG. 11 is a waveform diagram of a first operation example when an overcurrent is detected, where (A) shows when an overcurrent is detected during an ON operation, and (B) shows when the overcurrent is detected before an ON operation. [Figure 14] 11 is a time chart of a second operation example of the timing determination circuit, in which (A) shows a case where an overcurrent is detected during an ON operation, and (B) shows a case where an overcurrent is detected before an ON operation. [Figure 15] FIG. 11 is a waveform diagram of a second operation example when an overcurrent is detected, where (A) shows when an overcurrent is detected during an ON operation, and (B) shows when the overcurrent is detected before an ON operation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] The following describes in detail an embodiment of the present invention as applied to a high-side IPS with reference to the drawings. Note that the basic configuration of the high-side IPS is the same as that described above in Fig. 9, so Fig. 9 may be referred to for explanations of other components except for the logic circuit, which is a characteristic part of the present invention.

[0051] Fig. 1 is a block diagram showing an example of the configuration of a logic circuit of a high-side IPS according to the present invention, Fig. 2 is a circuit diagram showing an example of an input circuit and a pulse generation circuit, Fig. 3 is a circuit diagram showing an example of a gated latch circuit, Fig. 4 is a circuit diagram showing an example of an overcurrent mode switching circuit, and Fig. 5 is a circuit diagram showing an example of a timing decision circuit. Note that in the explanation of the figures, the same symbols may be used for terminal names and the voltages and signals at those terminals.

[0052] As shown in FIG. 1, the logic circuit 10 of the high-side IPS according to the present invention includes an input circuit 20, an oscillation signal generating circuit 30, a pulse generating circuit 40, a gated latch circuit 50, an overcurrent mode switching circuit 60, and a timing determination circuit 70.

[0053] The input circuit 20 has an input terminal connected to the IN terminal of the high-side IPS, and an output terminal of the input circuit 20 is connected to a first input terminal of the oscillation signal generating circuit 30 and an input terminal of the pulse generating circuit 40. The second input terminal of the oscillation signal generating circuit 30 is connected to an output terminal of the overcurrent detection circuit 160. The output terminal of the pulse generating circuit 40 is connected to an enable terminal of the gated latch circuit 50. The other input terminal of the gated latch circuit 50 is connected to the output terminal of the overcurrent detection circuit 160, and the output terminal of the gated latch circuit 50 is connected to an input terminal for inputting a switching signal of the overcurrent mode switching circuit 60. The input terminal for inputting an oscillation signal of the overcurrent mode switching circuit 60 is also connected to the output terminal of the oscillation signal generating circuit 30. The output terminal of the overcurrent mode switching circuit 60 is connected to an input terminal of the timing determination circuit 70. The timing determination circuit 70 is configured to also receive the first overcurrent detection signal OCDS1 output by the overcurrent detection circuit 160.

[0054] 2, the input circuit 20 includes a non-inverting Schmitt trigger circuit 21. An input terminal of the Schmitt trigger circuit 21 is connected to the IN terminal of the high-side IPS, and an output terminal of the Schmitt trigger circuit 21 is connected to the input terminal of the pulse generating circuit 40. The input circuit 20 can shape the waveform of the input signal IN, which includes noise and is supplied from the microcomputer 200.

[0055] The pulse generating circuit 40 includes inverter circuits INV11, INV12, and INV13, a NAND circuit NAND11, a P-channel MOSFET 41, N-channel MOSFETs 42 and 43, and a capacitor 44. The MOSFET 42 is a depletion-type MOSFET.

[0056] The input terminal of the pulse generating circuit 40 is connected to the input terminal of the inverter circuit INV11 and one of the input terminals of the NAND circuit NAND11. The output terminal of the inverter circuit INV11 is connected to the gate terminals of the MOSFETs 41 and 43, the source terminal of the MOSFET 41 is connected to the power supply line, and the source terminal of the MOSFET 43 is connected to the ground line. The drain terminal of the MOSFET 41 is connected to the drain terminal of the MOSFET 42, and the gate terminal and source terminal of the MOSFET 42 are connected to the drain terminal of the MOSFET 43, one terminal of the capacitor 44, and the input terminal of the inverter circuit INV12. The other terminal of the capacitor 44 is connected to the ground line. The output terminal of the inverter circuit INV12 is connected to the other input terminal of the NAND circuit NAND11, and the output terminal of the NAND circuit NAND11 is connected to the input terminal of the inverter circuit INV13. The output terminal of the inverter circuit INV13 constitutes the output terminal of this pulse generating circuit 40.

[0057] When an L-level input signal is input to the input terminal of the pulse generating circuit 40, the L-level input signal is inverted to H-level by the inverter circuit INV11. As a result, a H-level gate voltage is applied to the gate terminals of the MOSFETs 41 and 43, the MOSFET 41 is turned off, and the MOSFET 43 is turned on, so that the charge of the capacitor 44 is discharged by the MOSFET 43. At this time, the inverter circuit INV12 outputs an H-level signal and applies it to the other input terminal of the NAND circuit NAND11, and the L-level input signal input to the pulse generating circuit 40 is applied to one input terminal of the NAND circuit NAND11. Therefore, the NAND circuit NAND11 outputs an H-level signal, and this H-level signal is inverted to L-level by the inverter circuit INV13 and supplied to the output terminal of the pulse generating circuit 40.

[0058] When an H-level input signal is input to the input terminal of the pulse generating circuit 40, the H-level input signal is inverted to an L-level by the inverter circuit INV11. As a result, an L-level gate voltage is applied to the gate terminals of the MOSFETs 41 and 43, the MOSFET 41 is turned on, and the MOSFET 43 is turned off. At this time, a constant current flows in the depression type MOSFET 42 when the gate-source voltage is 0V, and the capacitor 44 is charged. At the time of starting charging, the voltage of the capacitor 44 has not reached the threshold voltage of the inverter circuit INV12, so the inverter circuit INV12 outputs an H-level signal. As a result, the NAND circuit NAND11 receives H-level signals at both input terminals, so it outputs an L-level signal, and this L-level signal is inverted to an H-level by the inverter circuit INV13 and supplied to the output terminal of the pulse generating circuit 40.

[0059] Thereafter, when the charging voltage of the capacitor 44, which is charged by the MOSFET 42 with a constant current, reaches the threshold voltage of the inverter circuit INV12, the inverter circuit INV12 outputs an L-level signal. Therefore, the other input terminal of the NAND circuit NAND11 becomes L-level, and the NAND circuit NAND11 outputs an H-level signal. This H-level signal is inverted to L-level by the inverter circuit INV13 and supplied to the output terminal of the pulse generating circuit 40.

[0060] That is, when an input signal IN instructing the main MOSFET 110 to turn on is input to the IN terminal, the pulse generating circuit 40 generates and outputs an H-level pulse of a fixed duration determined by a depletion-type MOSFET 42, a capacitor 44, and an inverter circuit INV12.

[0061] 3, the gated latch circuit 50 includes NAND circuits NAND12 and NAND13 constituting a gate circuit, and NAND circuits NAND14 and NAND15 constituting a latch circuit. One input terminal of the NAND circuit NAND12 is connected to a set terminal S of the gated latch circuit 50, one input terminal of the NAND circuit NAND13 is connected to a reset terminal R of the gated latch circuit 50, and the other input terminals of the NAND circuits NAND12 and NAND13 are connected to an enable terminal E of the gated latch circuit 50. The output terminal of the NAND circuit NAND12 is connected to one input terminal of the NAND circuit NAND14, and the output terminal of the NAND circuit NAND13 is connected to one input terminal of the NAND circuit NAND15. The other input terminal of the NAND circuit NAND14 is connected to an output terminal of the NAND circuit NAND15, and the other input terminal of the NAND circuit NAND15 is connected to an output terminal of the NAND circuit NAND14. An output terminal of the NAND circuit NAND14 is connected to an output terminal Q of the gated latch circuit 50, and an output terminal of the NAND circuit NAND15 is connected to an inverted output terminal NQ of the gated latch circuit 50.

[0062] A first overcurrent detection signal OCDS1 from the overcurrent detection circuit 160 is input to a set terminal S of the gated latch circuit 50, and a second overcurrent detection signal OCDS2 from the overcurrent detection circuit 160 is input to a reset terminal R of the gated latch circuit 50. In this embodiment, the first overcurrent detection signal OCDS1 is a signal that goes to H level when the overcurrent detection circuit 160 detects an overcurrent, and the second overcurrent detection signal OCDS2 is an inverted signal of the first overcurrent detection signal OCDS1. An enable terminal E of the gated latch circuit 50 is connected to the output terminal of the pulse generating circuit 40.

[0063] When the gated latch circuit 50 receives an H-level pulse at its enable terminal E from the pulse generating circuit 40, it latches the first overcurrent detection signal OCDS1 at its set terminal S and the second overcurrent detection signal OCDS2 at its reset terminal R, thereby holding the overcurrent detection state of the overcurrent detection circuit 160. When the overcurrent detection circuit 160 is not in an overcurrent detection state, it outputs the first overcurrent detection signal OCDS1 at an L level and outputs the second overcurrent detection signal OCDS2 at an H level. When the overcurrent detection circuit 160 is in an overcurrent detection state, it outputs the first overcurrent detection signal OCDS1 at an H level and outputs the second overcurrent detection signal OCDS2 at an L level.

[0064] If the gated latch circuit 50 is not in an overcurrent detection state when it receives an H-level pulse, it holds the first overcurrent detection signal OCDS1 at an L level and outputs the first switching signal SWS1 at an L level to the output terminal Q, and holds the second overcurrent detection signal OCDS2 at an H level and outputs the second switching signal SWS2 at an H level to the inverted output terminal NQ. If the gated latch circuit 50 is in an overcurrent detection state when it receives an H-level pulse, it holds the first overcurrent detection signal OCDS1 at an H level and outputs the first switching signal SWS1 at an H level to the output terminal Q, and holds the second overcurrent detection signal OCDS2 at an L level and outputs the second switching signal SWS2 at an L level to the inverted output terminal NQ.

[0065] 4, the overcurrent mode switching circuit 60 includes inverter circuits INV14, INV15, and INV16, and transmission gates 61 and 62 that configure a switch circuit. The overcurrent mode switching circuit 60 has an input terminal that receives the signal generated by the oscillation signal generating circuit 30, and an input terminal that receives the first switching signal SWS1 and the second switching signal SWS2 output by the gated latch circuit 50. The overcurrent mode switching circuit 60 also has output terminals that output signals signal0 and signal1 generated based on the signal signal.

[0066] An input terminal of the signal "signal" is connected to a first terminal of the transmission gate 61 and an input terminal of the inverter circuit INV14. An output terminal of the inverter circuit INV14 is connected to a first terminal of the transmission gate 62 and an output terminal of the signal "signal1". A second terminal of the transmission gate 61 and a second terminal of the transmission gate 62 are connected to an input terminal of the inverter circuit INV15. An output terminal of the inverter circuit INV15 is connected to an input terminal of the inverter circuit INV16, and an output terminal of the inverter circuit INV16 is connected to an output terminal of the signal "signal0". An input terminal for receiving the first switching signal SWS1 is connected to an inverting control terminal of the transmission gate 61 and a control terminal of the transmission gate 62. An input terminal for receiving the second switching signal SWS2 is connected to a control terminal of the transmission gate 61 and an inverting control terminal of the transmission gate 62.

[0067] When the overcurrent detection circuit 160 is not in an overcurrent detection state, the first switching signal SWS1 received from the gated latch circuit 50 is at L level, and the second switching signal SWS2 is at H level. At this time, in the overcurrent mode switching circuit 60, the transmission gate 61 is conductive and the transmission gate 62 is non-conductive. Therefore, the signal "signal" generated when the input signal IN is input passes through the transmission gate 61 and the inverter circuits INV15 and INV16, and a signal "signal0" having the same phase as the signal "signal" is output. At this time, the signal "signal" also passes through the inverter circuit INV14, so that the signal "signal1" has an opposite phase to the signal "signal."

[0068] On the other hand, when the overcurrent detection circuit 160 is in an overcurrent detection state, the first switching signal SWS1 received from the gated latch circuit 50 is at H level and the second switching signal SWS2 is at L level, so that the transmission gate 61 is non-conductive and the transmission gate 62 is conductive. Here, when the input signal IN is input and the signal signal is input from the oscillation signal creation circuit 30, an inverted signal of the signal signal is output as the signals signal0 and signal1.

[0069] As shown in Fig. 5, the timing decision circuit 70 includes T flip-flops TFF11, TFF12, and TFF13, NOR circuits NOR11 and NOR12, NAND circuits NAND16 and NAND17, and an inverter circuit INV17. An input terminal for receiving a signal signal0 is connected to an input terminal of the T flip-flop TFF11, an input terminal for receiving a signal signal1 is connected to one input terminal of the NOR circuit NOR1, and an input terminal for receiving a first overcurrent detection signal OCDS1 is connected to one input terminal of the NAND circuit NAND17. An output terminal of the T flip-flop TFF11 is connected to an input terminal of the T flip-flop TFF12 and the other input terminal of the NOR circuit NOR11. An output terminal of the T flip-flop TFF12 is connected to an input terminal of the T flip-flop TFF13 and one input terminal of the NOR circuit NOR12. The output terminal of the T flip-flop TFF13 is connected to the other input terminal of the NOR circuit NOR12. The output terminal of the NOR circuit NOR11 is connected to one input terminal of the NAND circuit NAND16, and the output terminal of the NOR circuit NOR12 is connected to the other input terminal of the NAND circuit NAND16. The output terminal of the NAND circuit NAND16 is connected to the other input terminal of the NAND circuit NAND17, and the output terminal of the NAND circuit NAND17 is connected to the input terminal of the inverter circuit INV17. The output terminal of the inverter circuit INV17 constitutes the output terminal of the timing determination circuit 70. The NOR circuits NOR11 and NOR12 and the NAND circuit NAND16 constitute a first logic operation circuit, and the NAND circuit NAND17 and the inverter circuit INV17 constitute a second logic operation circuit.

[0070] When the timing decision circuit 70 receives the signal signal0 from the overcurrent mode switching circuit 60, the signal signal0 is divided in sequence by a down counter circuit consisting of three stages of T flip-flops TFF11, TFF12, and TFF13. That is, the T flip-flop TFF11 outputs a signal signal2 having a period double that of the signal signal0, the T flip-flop TFF12 outputs a signal signal3 having a period double that of the signal signal2, and the T flip-flop TFF13 outputs a signal signal4 having a period double that of the signal signal3. The NOR circuit NOR11 receives the signals signal1 and signal2 and outputs an H-level signal when both are at the L-level, and the NOR circuit NOR12 receives the signals signal3 and signal4 and outputs an H-level signal when both are at the L-level. The NAND circuit NAND16 outputs an L-level signal (a match signal) only when it receives H-level signals from both the NOR circuits NOR11 and NOR12. The L-level signal output by the NAND circuit NAND16 serves as a signal that periodically turns on the main MOSFET 110 for a short period of time.

[0071] However, immediately after the H-level input signal IN is input when the overcurrent detection circuit 160 is not detecting an overcurrent, the signal signal1 remains at H level, so the NAND circuit NAND16 outputs an H-level signal. Therefore, even though the H-level input signal IN is being input, the NAND circuit NAND16 cannot output an L-level signal that turns on the main MOSFET 110.

[0072] Therefore, the timing determination circuit 70 is provided with a NAND circuit NAND17 and an inverter circuit INV17, and when the overcurrent detection circuit 160 does not detect an overcurrent, it outputs an L-level signal to turn on the main MOSFET 110 in synchronization with the input signal IN. That is, the output signal of the NAND circuit NAND16 and the first overcurrent detection signal OCDS1 are input to the NAND circuit NAND17. When the first overcurrent detection signal OCDS1 of L level, which indicates that an overcurrent is not detected, is input, the NAND circuit NAND17 outputs an H-level signal regardless of the logic level of the output signal of the NAND circuit NAND16, and the inverter circuit INV17 outputs an L-level signal output. That is, the NAND circuit NAND17 becomes effective when the NAND circuit NAND16 outputs a match signal or the first overcurrent detection signal OCDS1 is at L level, and the main MOSFET 110 is turned on only during the output effective section.

[0073] Next, the operation of logic circuit 10 will be described with reference to FIGS. Fig. 6 is a time chart showing the operation of the logic circuit when an overcurrent detection state occurs after an input signal is input, Fig. 7 is a time chart showing the operation of the logic circuit when an overcurrent detection state occurs before an input signal is input, and Fig. 8 is a time chart showing the operation of the logic circuit when an overcurrent detection state occurs during a period when the pulse generating circuit is outputting a pulse. Note that Figs. 6 to 8 show, from the top, the input signal IN, the pulse generating circuit output, the first overcurrent detection signal OCDS1, the second overcurrent detection signal OCDS2, the first switching signal SWS1, the second switching signal SWS2, the signal signal, the signal signal0, the signal signal1, the signal signal2, the signal signal3, the signal signal4, and the signal output, respectively.

[0074] 6, when an H-level input signal IN is input, the pulse generating circuit 40 generates a pulse that rises in synchronization with the rising edge of the input signal IN. At this time, the overcurrent detection circuit 160 does not detect an overcurrent, so it outputs an L-level first overcurrent detection signal OCDS1 and an H-level second overcurrent detection signal OCDS2.

[0075] Upon receiving a pulse from the pulse generating circuit 40, the gated latch circuit 50 latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the L level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the H level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0076] In the overcurrent mode switching circuit 60, the transmission gate 61 is placed in a conductive state and the transmission gate 62 is placed in a non-conductive state by the first switching signal SWS1 and the second switching signal SWS2.

[0077] Thereafter, when the overcurrent detection circuit 160 detects an overcurrent, the first overcurrent detection signal OCDS1 goes to H level and the second overcurrent detection signal OCDS2 goes to L level. However, at this time, pulse generation has finished, the gated latch circuit 50 is in a disabled state, and the holding state does not change, so the logic levels of the first switching signal SWS1 and the second switching signal SWS2 do not change either.

[0078] When the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal creation circuit 30 outputs a signal that rises in synchronization with the rising edge of the first overcurrent detection signal OCDS1. At this time, the overcurrent mode switching circuit 60 does not switch the overcurrent mode, so the signal passes through the transmission gate 61 and the inverter circuits INV15 and INV16, and is output as a signal signal0 that is in phase with the signal signal. In addition, the signal passes through the inverter circuit INV14, and is output as a signal signal1 that is in phase opposite to the signal signal.

[0079] In the timing decision circuit 70, when the H-level signals signal0 and signal1 are input, the NAND circuit NAND16 outputs an H-level signal. At this time, since the first overcurrent detection signal OCDS1 is at H level, the NAND circuit NAND17 outputs an L-level signal, and the inverter circuit INV17 outputs an H-level signal output.

[0080] Thereafter, in the timing decision circuit 70, upon receiving the signal signal0, the signals signal2, signal3, and signal4 are generated in sequence. Then, every time a match signal is output from the NAND circuit NAND16, the output of the NAND circuit NAND16 goes to L level, so that the output of the NAND circuit NAND17 goes to H level, and the inverter circuit INV17 outputs a signal output of L level. This signal output turns on the main MOSFET 110 only during the output effective section where the signal output is L level.

[0081] In this way, if an overcurrent detection state occurs while the input signal IN is being input, the output valid period of the signal output ends immediately at that timing, so that the main MOSFET 110 can be safely protected from overheating due to an overcurrent.

[0082] Next, as shown in FIG. 7, when the overcurrent detection circuit 160 detects an overcurrent while the input signal IN is at an L level before it is input, the overcurrent detection circuit 160 outputs a first overcurrent detection signal OCDS1 at an H level and outputs a second overcurrent detection signal OCDS2 at an L level.

[0083] Thereafter, when an H-level input signal IN is input, the pulse generating circuit 40 generates a pulse that rises in synchronization with the rising edge of the input signal IN and supplies the pulse to the gated latch circuit 50 .

[0084] Upon receiving a pulse from the pulse generating circuit 40, the gated latch circuit 50 latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the H level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the L level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0085] In the overcurrent mode switching circuit 60, the transmission gate 61 is placed in a non-conductive state and the transmission gate 62 is placed in a conductive state by the first switching signal SWS1 and the second switching signal SWS2. Therefore, the signal "signal" generated in synchronization with the rising edge of the input signal IN passes through the inverter circuit INV14, the transmission gate 62, and the inverter circuits INV15 and INV16 to become the signal "signal0". The signal "signal" also passes through the inverter circuit INV14 to become the signal "signal1". The signals "signal0" and "signal1" are in opposite phase to the signal "signal".

[0086] In the timing decision circuit 70, when the signal signal0 is received, the signals signal1, signal2, signal3, and signal4 are all at L level, so the NAND circuit NAND16 outputs a match signal at L level. Therefore, the NAND circuit NAND17 outputs a signal at H level, and the inverter circuit INV17 outputs a signal output at L level, and the main MOSFET 110 is turned on only during the output effective section.

[0087] Thereafter, the down counter circuit sequentially generates signals signal2, signal3, and signal4 with a half cycle delay from the signal signal. Every time the NAND circuit NAND16 outputs a match signal of L level, the main MOSFET 110 is turned on.

[0088] In this way, when an input signal IN is input during an overcurrent detection state, the timing at which the counter circuit for generating the signal output starts counting is delayed by a half cycle of the signal. This ensures that the output valid section of the signal output is set to a half cycle of the signal signal from the timing at which the input signal IN is input, so that the microcomputer 200 can secure sufficient time to receive the signal AMP when an overcurrent is detected.

[0089] It is preferable that the output effective period when the input signal IN is input, that is, the period of a half cycle of the signal output by the oscillation signal creation circuit 30, is equal to or longer than the period during which the pulse generation circuit 40 outputs a pulse. This allows the logic circuit 10 to output an on signal for the main MOSFET 110 at least during the period during which the pulse generation circuit 40 outputs a pulse, regardless of whether an overcurrent is detected at the time when the input signal IN is input.

[0090] 8, when an H-level input signal IN is input, the pulse generating circuit 40 outputs a pulse. At this time, the overcurrent detection circuit 160 does not detect an overcurrent and outputs an L-level first overcurrent detection signal OCDS1. Therefore, in the timing determination circuit 70, the NAND circuit NAND17 receives the L-level first overcurrent detection signal OCDS1, so the NAND circuit NAND17 outputs an H-level signal and the inverter circuit INV17 outputs an L-level signal output.

[0091] When the overcurrent detection circuit 160 detects an overcurrent while the pulse generating circuit 40 is outputting a pulse, in the overcurrent detection circuit 160, the first overcurrent detection signal OCDS1 changes to an H level and the second overcurrent detection signal OCDS2 changes to an L level.

[0092] At this time, the gated latch circuit 50 still receives pulses from the pulse generating circuit 40, and therefore latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2 whose logical levels have changed. The gated latch circuit 50 outputs the H level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the L level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0093] In the overcurrent mode switching circuit 60, the transmission gate 61 is placed in a non-conductive state and the transmission gate 62 is placed in a conductive state by the first switching signal SWS1 and the second switching signal SWS2. Therefore, the signal "signal" generated in synchronization with the rising edge of the first overcurrent detection signal OCDS1 passes through the inverter circuit INV14, the transmission gate 62, and the inverter circuits INV15 and INV16 to become the signal "signal0". The signal "signal" also passes through the inverter circuit INV14 to become the signal "signal1". The signals "signal0" and "signal1" are in opposite phase to the signal "signal".

[0094] In the timing determination circuit 70, immediately after the input signal IN of H level is input, the first overcurrent detection signal OCDS1 is at L level, so the NAND circuit NAND17 outputs a signal of H level, and the inverter circuit INV17 outputs a signal output of L level. Immediately after the overcurrent detection circuit 160 detects an overcurrent and the first overcurrent detection signal OCDS1 becomes H level, the signal signal output by the oscillation signal creation circuit 30 becomes H level. As a result, the signals signal0, signal1, signal2, signal3, and signal4 all become L level. Therefore, the NAND circuit NAND16 outputs a match signal of L level, so the NAND circuit NAND17 outputs a signal of H level, and the inverter circuit INV17 continues to output the signal output of L level.

[0095] Thereafter, when the output valid period elapses with a delay of a half cycle from the signal signal, the down counter circuit sequentially generates the signals signal2, signal3, and signal4. Every time the NAND circuit NAND16 outputs an L-level match signal, the output valid period becomes valid and the main MOSFET 110 is turned on.

[0096] In this way, in the timing decision circuit 70, when the overcurrent detection circuit 160 detects an overcurrent, the counter circuit starts counting with a delay of half a period of the signal from that timing. Since the output valid section is extended until the counting starts, the microcomputer 200 can secure a sufficient time to receive the signal AMP when an overcurrent is detected.

[0097] In Figures 6 to 8, when the input signal IN is at an L level, the signal output is at an H level. This is because a circuit (not shown) is configured so that when the input signal IN is at an L level, the signal output is at an H level.

[0098] In the above embodiment, the oscillation signal generating circuit 30 uses a signal that rises when both the input signal IN and the first overcurrent detection signal OCDS1 are at H level, but this is not limited to this. For example, when both the input signal IN and the first overcurrent detection signal OCDS1 are at H level, a signal that starts from L level is generated, and in the overcurrent mode switching circuit 60, the input positions of the first switching signal SWS1 and the second switching signal SWS2 may be replaced with those in FIG. 4. In addition, the timing determination circuit 70 is configured with a counter circuit of three stages of T flip-flops TFF11, TFF12, and TFF13, but the number of stages is not limited to this number. In addition, instead of the MOSFET 42 of the pulse generating circuit 40, a resistor or a diode-connected MOSFET may be used. Furthermore, instead of the NAND circuit, a NOR circuit may be used. In addition, the gated latch circuit 50 is configured with a NAND circuit, but may be configured with a NOR circuit.

[0099] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes are possible to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention according to the appended claims and their equivalents. [Explanation of symbols]

[0100] 10 Logic Circuits 20 Input circuit 21 Schmitt trigger circuit 30 Oscillation signal generating circuit 40 Pulse Generator Circuit 41,42,43 MOSFET 44 Capacitor 50 Gated Latch Circuit 60 Overcurrent mode switching circuit 61,62 Transmission gate 70 Timing decision circuit 160 Overcurrent detection circuit INV11, INV12, INV13, INV14, INV15, INV16, INV17 inverter circuit NAND11, NAND12, NAND13, NAND14, NAND15, NAND16, NAND17 NAND circuit NOR11, NOR12 NOR circuit TFF11, TFF12, TFF13 T flip-flop

Claims

1. A semiconductor device including a power semiconductor element, an overcurrent detection circuit, and a logic circuit having a function of outputting an off signal to the power semiconductor element when the overcurrent detection circuit detects an overcurrent, the logic circuit generates a pulse when an input signal instructing an ON operation of the power semiconductor element is input, and generates an oscillation signal synchronized with a rising edge of the input signal; the semiconductor device outputs a signal instructing the power semiconductor element to turn on for a half cycle of the oscillation signal after the output of the pulse starts when the overcurrent detection circuit has continuously detected an overcurrent before the pulse is output.

2. 2. The semiconductor device according to claim 1, wherein even if said overcurrent is detected, said logic circuit outputs an ON signal to said power semiconductor element at least during a period during which said logic circuit outputs said pulse.

3. 3. The semiconductor device according to claim 1, wherein said logic circuit generates a pulse which continues for a set fixed period of time when said input signal is input.

4. 2. The semiconductor device according to claim 1, wherein a period of the half cycle is longer than a period during which the overcurrent detection circuit outputs a signal instructing an on operation of the power semiconductor element when the overcurrent detection circuit detects an overcurrent after a period during which the pulse is output has elapsed.

5. 2. The semiconductor device according to claim 1, wherein when said overcurrent detection circuit detects an overcurrent during the period in which said pulse is being output, said semiconductor device outputs a signal instructing said power semiconductor element to be turned on for a predetermined period after the detection of the overcurrent.

6. A semiconductor device comprising: a power semiconductor element; an overcurrent detection circuit; and a logic circuit having a function of outputting an off signal to the power semiconductor element when the overcurrent detection circuit detects an overcurrent, the logic circuit includes a pulse generating circuit that generates and outputs a pulse when an input signal instructing an ON operation of the power semiconductor element is input, When the overcurrent detection circuit detects an overcurrent continuously from before the pulse is output, a signal instructing an ON operation of the power semiconductor element is output for a predetermined period after the start of output of the pulse, the predetermined period is longer than a period during which the overcurrent detection circuit outputs a signal instructing the power semiconductor element to be turned on when the overcurrent detection circuit detects an overcurrent after the period during which the pulse is output has elapsed. Semiconductor device.

7. A semiconductor device as described in claim 6, wherein even if the overcurrent is detected, the pulse generating circuit outputs an on signal to the power semiconductor element at least for the period during which the pulse is output.

8. A semiconductor device as described in claim 6 or 7, wherein the pulse generating circuit generates a pulse that continues for a certain period of time that is set when the input signal is input.

9. A semiconductor device as described in claim 6, wherein when the overcurrent detection circuit detects an overcurrent during the period in which the pulse is being output, it outputs a signal instructing the power semiconductor element to turn on for a predetermined period of time after the overcurrent is detected.

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