Method for creating an equivalent circuit model of a multi-terminal capacitor, program for creating an equivalent circuit model, storage medium storing the program for creating an equivalent circuit model, simulation method, and simulation device

Abstract

The present invention derives an equivalent circuit model of a multi-terminal capacitor with three or more terminals. Provided is a method for creating an equivalent circuit model of a multi-terminal capacitor in which external electrode terminal rows of positive polarity and external electrode terminal rows of negative polarity are arranged in parallel alternately, the method comprising: a step of measuring an S parameter of the multi-terminal capacitor; a step of deriving an overall impedance of the multi-terminal capacitor on the basis of the measured value of the S parameter; a step of creating an equivalent circuit model of two terminals from the derived overall impedance of the multi-terminal capacitor; a step of deriving an equivalent circuit model of a unit cell from the created equivalent circuit model of two terminals; a step of combining the derived equivalent circuit model of a unit cell and an equivalent circuit model of a parasitic component to create a topology of a two-dimensional lattice shape; and a step of setting terminals of the multi-terminal capacitor at nodes of the created topology of the two-dimensional lattice.

Description

[Technical field]

[0001] The present disclosure relates to an equivalent circuit model creating method for a multi-terminal capacitor, an equivalent circuit model creating program, a storage medium storing an equivalent circuit model creating program, a simulation method, and a simulation device. [Background technology]

[0002] A method for deriving an equivalent circuit model of a capacitor is disclosed in Patent Document 1. The method disclosed in Patent Document 1 targets a two-terminal capacitor. In other words, the method disclosed in Patent Document 1 is premised on deriving an equivalent circuit model for a two-terminal capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-259482 A Summary of the Invention [Problem to be solved by the invention]

[0004] The method disclosed in Patent Document 1 cannot derive an equivalent circuit model for a capacitor having more than two terminals, i.e., three or more terminals.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide an equivalent circuit model creating method, an equivalent circuit model creating program, a storage medium storing the equivalent circuit model creating program, a simulation method, and a simulation apparatus, which are capable of deriving an equivalent circuit model of a multi-terminal capacitor having three or more terminals. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, an equivalent circuit model creation method according to an embodiment of the present disclosure is a method for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a row of positive external electrode terminals and a row of negative external electrode terminals are arranged alternately in parallel, the method including: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of creating a two-dimensional lattice-like topology by combining the equivalent circuit model of the unit cell derived in the fourth step and an equivalent circuit model of a parasitic component; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step.

[0007] In order to solve the above-mentioned problems and achieve the object, an equivalent circuit model creation program according to an embodiment of the present disclosure is an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a row of positive external electrode terminals and a row of negative external electrode terminals are arranged alternately in parallel, the equivalent circuit model creation program causing a computer to execute the following steps: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component to create a two-dimensional lattice-like topology; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step.

[0008] In order to solve the above-mentioned problems and achieve the object, a storage medium according to an embodiment of the present disclosure is a storage medium storing an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a row of positive external electrode terminals and a row of negative external electrode terminals are arranged alternately in parallel, the storage medium storing the equivalent circuit model creation program for causing a computer to execute the following steps: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component to create a two-dimensional lattice-like topology; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step.

[0009] In order to solve the above-mentioned problems and achieve the objective, a simulation method according to one aspect of the present disclosure utilizes an equivalent circuit model of a multi-terminal capacitor created using the above-mentioned equivalent circuit model creation method to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor.

[0010] In order to solve the above-mentioned problems and achieve the objective, a simulation device according to an embodiment of the present disclosure uses an equivalent circuit model of a multi-terminal capacitor created using the above-mentioned equivalent circuit model creation method to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor. Effect of the Invention

[0011] According to the present disclosure, it is possible to derive an equivalent circuit model of a capacitor having three or more terminals. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a flowchart showing an example of a method for creating an equivalent circuit model of a multi-terminal capacitor according to the present disclosure. [Diagram 2] FIG. 2 is a plan view showing a configuration example of a multi-terminal capacitor. [Diagram 3] FIG. 3 is a cross-sectional view of a portion of FIG. [Figure 4] FIG. 4 is an enlarged view of a portion of a cross section of a multi-terminal capacitor. [Diagram 5] FIG. 5 is an enlarged view of a portion of a cross section of a multi-terminal capacitor. [Figure 6] FIG. 6 is a diagram showing a jig for measuring the S parameters. [Figure 7] FIG. 7 is a cross-sectional view of a portion of FIG. [Figure 8] FIG. 8 is a cross-sectional view of a portion of FIG. [Figure 9] FIG. 9 is a diagram showing an equivalent circuit of a substrate including a multi-terminal capacitor. [Figure 10] FIG. 10 is a diagram showing the basic form of an equivalent circuit. [Figure 11] FIG. 11 is a diagram showing an equivalent circuit for fitting the low frequency range. [Figure 12] FIG. 12 is a diagram showing an equivalent circuit for fitting the entire frequency band including the low frequency range. [Figure 13] FIG. 13 is a table showing the values ​​of each element included in each of the circuits shown in FIGS. [Figure 14] FIG. 14 is a diagram showing an example of a change in impedance with respect to frequency. [Figure 15] FIG. 15 is a diagram showing an example of a change in equivalent series resistance with respect to frequency. [Figure 16] FIG. 16 is a flowchart showing an example of the fitting process. [Figure 17]FIG. 17 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 18] FIG. 18 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 19] FIG. 19 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 20] FIG. 20 is a diagram showing an example of a unit cell. [Figure 21] FIG. 21 is a diagram showing an image of the overall impedance. [Figure 22] FIG. 22 is a diagram showing an example of an arrangement of unit cells corresponding to the overall impedance. [Figure 23] FIG. 23 is a diagram showing a state in which the impedance of a unit cell is placed between the nodes of a two-dimensional lattice. [Figure 24] FIG. 24 is a diagram showing an example of an equivalent circuit model of a multi-terminal capacitor. [Diagram 25] FIG. 25 is a table showing examples of symbols that represent an equivalent circuit model of a multi-terminal capacitor. [Figure 26] FIG. 26 is a diagram showing a multi-terminal capacitor with a terminal arrangement of 3 rows and 3 columns. [Figure 27] FIG. 27 is a diagram showing a multi-terminal capacitor represented by the symbol shown in FIG. [Figure 28] FIG. 28 is a diagram showing a multi-terminal capacitor with a terminal arrangement of 3 rows and 5 columns. [Figure 29] FIG. 29 is a diagram showing an equivalent circuit of a substrate including a multi-terminal capacitor. [Diagram 30] FIG. 30 is a diagram showing the simulation results of the S parameters. [Diagram 31] FIG. 31 is a diagram for explaining an example of a simulation in the time domain. [Diagram 32] FIG. 32 is a diagram showing changes in the current value of the current source in FIG. [Diagram 33]FIG. 33 is a diagram showing an example of a change in the load voltage. [Diagram 34] FIG. 34 is a diagram illustrating an example of the configuration of a simulation device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment, the same or equivalent components as those in other embodiments are given the same reference numerals, and their description will be simplified or omitted. The present invention is not limited to each embodiment. In addition, the components of each embodiment include those that are replaceable and easy for a person skilled in the art, or those that are substantially the same. The configurations described below can be appropriately combined. In addition, the configurations can be omitted, replaced, or modified within the scope of the gist of the invention.

[0014] Fig. 1 is a flowchart showing an example of a method for creating an equivalent circuit model of a multi-terminal capacitor according to the present disclosure. As shown in Fig. 1, first, a multi-terminal capacitor is mounted on a board, and S parameters of the multi-terminal capacitor are measured (step ST1). For example, a jig having a board on which a capacitor is mounted is prepared, and the S parameters are measured using the jig.

[0015] Next, the impedance of the entire multi-terminal capacitor is calculated based on the S-parameters measured in step ST1 (step ST2). Furthermore, a two-terminal equivalent circuit model is created from the entire impedance calculated in step ST2 (step ST3). At this time, the two-terminal equivalent circuit model is created by a fitting process. The fitting process will be described later.

[0016] An equivalent circuit model of a unit cell is derived from the two-terminal equivalent circuit model created in step ST3 (step ST4). At this time, the equivalent circuit model of the unit cell is derived from the two-terminal equivalent circuit model based on the periodic structure.

[0017] Next, the equivalent circuit model of the unit cell derived in step ST4 and the equivalent circuit model of the parasitic components are combined to create a two-dimensional lattice topology (step ST5). Then, terminals of a multi-terminal capacitor are set at the nodes of the two-dimensional lattice created in step ST5 (step ST6).

[0018] (Example of multi-terminal capacitor configuration) Fig. 2 to Fig. 5 are diagrams showing an example of the configuration of a multi-terminal capacitor. Fig. 2 is a plan view showing an example of the configuration of a multi-terminal capacitor. Fig. 3 is a diagram showing a cross section of part A1-A1 in Fig. 2. Figs. 4 and 5 are enlarged views showing a part of the cross section of the multi-terminal capacitor.

[0019] 2, the multi-terminal capacitor 1 of this example is formed on a substrate 10. On the substrate 10, negative electrodes NE1 and NE2 and a positive electrode PE1 are formed.

[0020] For ease of explanation, the mutually orthogonal X-axis, Y-axis, and Z-axis directions are defined. The longitudinal direction in which the positive electrode PE1, negative electrodes NE1, and NE2 extend is defined as the Y-axis direction. With reference to FIG. 2, the negative electrode NE1, positive electrode PE1, and negative electrode NE2 are arranged in this order. This arrangement direction is defined as the X-axis direction. The depth direction of the substrate 10 is defined as the Z-axis direction.

[0021] As shown in FIG. 2, the positive electrode PE1, the negative electrodes NE1 and NE2 extend in parallel to each other in the Y-axis direction. Therefore, the positive electrode PE1, the negative electrodes NE1 and NE2 are arranged in a striped pattern in a plan view. The negative electrode NE1 has terminals T1, T2 and T3. The negative electrode NE2 has terminals T4, T5 and T6. The positive electrode PE1 has terminals T7, T8 and T9.

[0022] The positive electrode PE1 has extensions PE10 and PE20 that extend in the X-axis direction toward the negative electrodes NE1 and NE2. The negative electrode NE1 has an extension NE10 that extends in the X-axis direction toward the positive electrode PE1. The negative electrode NE2 has an extension NE20 that extends in the X-axis direction toward the positive electrode PE1. In the region between the positive electrode PE1 and the negative electrode NE1, the extensions PE10 and NE10 are alternately arranged in the Y-axis direction. In the region between the positive electrode PE1 and the negative electrode NE2, the extensions PE20 and NE20 are alternately arranged in the Y-axis direction.

[0023] A trench formation region VH1 is provided in the region between the positive electrode PE1 and the negative electrode NE1. A trench formation region VH2 is provided in the region between the positive electrode PE1 and the negative electrode NE2. A via hole extending in the Z-axis direction is provided in the portion of each of the extensions PE10, NE10, PE20, and NE20 located in the trench formation region VH1 and VH2. For example, via holes V11 and V12 are provided in the portion of the extension PE20 located in the trench formation region VH2, and via holes V21 and V22 are provided in the portion of the extension NE20 located in the trench formation region VH2.

[0024] Fig. 4 is an enlarged view of a trench formation region VH2 in the cross section of A1-A1 in Fig. 2. Referring to Fig. 4, the via holes V11 and V12 are connected to the positive electrode PETR inside the substrate 10. This electrically connects the extension portion PE20 and the positive electrode PETR.

[0025] Fig. 5 is an enlarged view of a trench formation region VH2 in the cross section of A2-A2 in Fig. 2. Referring to Fig. 5, the via holes V21 and V22 are connected to the negative electrode NETR inside the substrate 10. This electrically connects the extension NE20 and the negative electrode NETR.

[0026] 4 and 5, the positive electrode PETR and the negative electrode NETR have portions extending in the Z-axis direction along the trenches TR11, TR12, TR21, and TR22 extending in the Z-axis direction. This allows the area of ​​the portion where the positive electrode PETR and the negative electrode NETR face each other to be as large as possible, and the capacitance value between the positive electrode PETR and the negative electrode NETR to be as large as possible. Note that a dielectric is provided between the positive electrode PETR and the negative electrode NETR.

[0027] 2 to 5 show an example of a multi-terminal capacitor using silicon capacitors, in which a row of positive electrodes and a row of negative electrodes are arranged in parallel. As long as a row of positive electrodes and a row of negative electrodes are arranged in parallel, the multi-terminal capacitor may be a multilayer ceramic capacitor or the like.

[0028] (S-parameter measurement) Fig. 6 is a diagram for explaining a method for measuring S parameters of a multi-terminal capacitor. Fig. 6 is a diagram showing a jig for measuring S parameters. Fig. 7 is a diagram showing a cross section taken along the line B1-B1 in Fig. 6. Fig. 8 is a diagram showing a cross section taken along the line B2-B2 in Fig. 6.

[0029] 6, jig 11 has a substrate 10a. Substrate 10a is a substrate for evaluating multi-terminal capacitor 1. Multi-terminal capacitor 1 is mounted on substrate 10a.

[0030] The multi-terminal capacitor 1 has nine terminals T1 to T9. The terminals T1 to T3 and the terminals T4 to T6 arranged in the Y-axis direction are electrically connected to the negative electrode inside the substrate 10a. The terminals T7 to T9 arranged in the Y-axis direction are electrically connected to the positive electrode inside the substrate 10a. For example, as shown in FIG. 7, the terminal T2 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole V2. The terminal T2 is not connected to the positive electrode PE inside the substrate 10a. The terminal T5 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole V5. The terminal T5 is not connected to the positive electrode PE inside the substrate 10a. The terminal T8 is electrically connected to the positive electrode PE inside the substrate 10a by a via hole V8.

[0031] The row of terminals T1 to T3 arranged in a straight line, the row of terminals T4 to T6 arranged in a straight line, and the row of terminals T7 to T9 arranged in a straight line are arranged in parallel to each other. The row of terminals T7 to T9 is sandwiched between the row of terminals T1 to T3 and the row of terminals T4 to T6. The row of terminals T1 to T3 is provided on one side of the row of terminals T7 to T9 in the X-axis direction, and the row of terminals T4 to T6 is provided on the other side. Therefore, the multi-terminal capacitor 1 has a configuration in which a row of electrodes connected to a positive electrode and a row of electrodes connected to a negative electrode are alternately provided.

[0032] The substrate 10a has ports PO1 and PO2. The port PO1 is provided on one side of the multi-terminal capacitor 1 in the Y-axis direction, and the port PO2 is provided on the other side. The port PO1 has a positive electrode PO11 and a negative electrode PO12. The port PO2 has a positive electrode PO21 and a negative electrode PO22.

[0033] When measuring the S-parameters, a resistor RA is electrically connected between the positive pole PO11 and the negative pole PO12 of the port PO1. Similarly, a resistor RB is electrically connected between the positive pole PO21 and the negative pole PO22 of the port PO2. The resistors RA and RB are, for example, 50Ω chip resistors.

[0034] As shown in FIG. 8, the positive electrode PO11 of the port PO1 is electrically connected to the positive electrode PE inside the substrate 10a by a via hole VP1. The negative electrode PO12 of the port PO1 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole VN1. The negative electrode PO12 is not connected to the positive electrode PE inside the substrate 10a. Similar to the port PO1, the positive electrode PO21 of the port PO2 is electrically connected to the positive electrode PE inside the substrate 10a, and the negative electrode PO22 of the port PO2 is electrically connected to the negative electrode NE inside the substrate 10a.

[0035] 6 to 8, the impedance when the positive terminal and the negative terminal are electrically connected can be reflected in the equivalent circuit model by mounting on the board using the jig 11. Furthermore, by mounting on the board, the characteristics due to the parasitic components at the connection part of the terminals can be reflected in the equivalent circuit model.

[0036] FIG. 9 is a diagram showing an equivalent circuit of a substrate 10a including a multi-terminal capacitor 1. As shown in FIG. 9, a positive electrode PO11 of a port PO1 is electrically connected to a positive electrode PE. A positive electrode PO21 of a port PO2 is electrically connected to a positive electrode PE. A negative electrode PO12 of a port PO1 is electrically connected to a negative electrode NE. A negative electrode PO22 of a port PO2 is electrically connected to a negative electrode NE. Terminals T1 to T6 are negative electrode terminals and are electrically connected to the negative electrode NE. Terminals T7 to T9 are positive electrode terminals and are electrically connected to the positive electrode PE.

[0037] In the equivalent circuit shown in Figure 9, S-parameters are measured according to the shunt-through method. In this case, for example, a network analyzer is used to measure the S-parameters. S-parameters (Scattering parameters), also called scattering matrices or scattering parameters, are parameters that express the transmitted and reflected power characteristics of a circuit network.

[0038] Based on the S-parameter measurement results, the impedance Z of the entire circuit is calculated. total The impedance value Z is calculated using the following formula (1). Z total =(Z0 / 2)×{S21 / (1-S 21 )} …(1)

[0039] In addition, Z0 in the above formula (1) is the characteristic impedance. S 21 is the power gain when the impedance of the source and load is Z0.

[0040] (Fitting process) Next, the fitting process will be described. The fitting process is carried out by calculating the impedance value Z total The fitting process is a process for deriving an equivalent circuit that corresponds to the measured value. The fitting process is a process for matching the simulation value with the measured value. Specifically, in order to match the impedance simulation value by the SPICE (Simulation Program with Integrated Circuit Emphasis) model with the measured value, an equivalent circuit is derived by combining resistive elements, inductive elements, and capacitive elements.

[0041] Figures 10 to 12 show the impedance Z of the entire circuit. total FIG. 10 is a diagram showing an example of an equivalent circuit for the measured value of FIG. 10. FIG. 10 is a diagram showing a basic form of an equivalent circuit. The equivalent circuit shown in FIG. 10 includes resistive elements R1 and R3, a capacitive element C1, and an inductive element L2. The capacitive element C1, the inductive element L2, and the resistive element R3 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1. The resistive element R1 is an insulation resistor.

[0042] Fig. 11 is a diagram showing an equivalent circuit for fitting a low frequency range. The equivalent circuit shown in Fig. 11 includes resistive elements R1, R3 to R6, capacitive elements C1, C4 to C6, and an inductive element L2. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, and R6 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1, the capacitive element C4 to the resistive element R4, the capacitive element C5 to the resistive element R5, and the capacitive element C6 to the resistive element R6. The resistive element R1 is an insulation resistor.

[0043] Fig. 12 is a diagram showing an equivalent circuit for fitting the entire frequency band including the low frequency band. The equivalent circuit shown in Fig. 12 includes resistive elements R1, R3 to R8, capacitive elements C1, C4 to C6, and inductive elements L2, L7, and L8. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, R6, R7, and R8 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1, the capacitive element C4 to the resistive element R4, the capacitive element C5 to the resistive element R5, the capacitive element C6 to the resistive element R6, the inductive element L7 to the resistive element R7, and the inductive element L8 to the resistive element R8. The resistive element R1 is an insulation resistor.

[0044] FIG. 13 is a table showing the values ​​of each element included in the circuits shown in FIGS. 10 to 12. That is, the table in FIG. 13 shows examples of the capacitance value [F] of each capacitive element C, the inductance value [H] of each inductive element L, and the resistance value [Ω] of each resistive element R. The numbers 1 to 8 in the "No." column in the leftmost column in the table, and the codes combined with the capacitive element C, the inductive element L, or the resistive element R correspond to the codes of the elements included in the circuits shown in FIGS. 10 to 12. For example, the capacitance value of the capacitive element C1 is 8.455×10 -8 [F], the inductance value of the inductive element L2 is 1.005×10 -11 [H], the resistance value of resistor element R1 is 1.000×10 8 [Ω], the resistance value of resistor element R3 is 9.780×10 -3 [Ω]. The values ​​of other elements are as shown in the table of Fig. 13. Note that the circuits shown in Figs. 10 to 13 are merely examples, and other elements may also be used.

[0045] Fig. 14 is a diagram showing an example of change in impedance with respect to frequency. In Fig. 14, the horizontal axis is frequency [Hz], and the vertical axis is impedance [Ω]. For example, as shown in Figs. 10 to 12, by combining a capacitance element C, an inductance element L, and a resistance element R, it is possible to make the simulation value SM1 of the impedance by the SPICE model coincide with the measured value ME1. That is, an equivalent circuit is created by connecting the capacitance element C, the inductance element L, and the resistance element R so that the simulation value SM1 of the SPICE model coincides with the measured value ME1.

[0046] FIG. 15 is a diagram showing an example of the change in equivalent series resistance (ESR) with respect to frequency. In FIG. 15, the horizontal axis is frequency [Hz], and the vertical axis is equivalent series resistance [Ω]. For example, as shown in FIG. 10 to FIG. 12, by combining a capacitance element C, an inductance element L, and a resistance element R, it is possible to make the simulation value SM2 of the equivalent series resistance by the SPICE model coincide with the measured value ME2. That is, an equivalent circuit is created by connecting the capacitance element C, the inductance element L, and the resistance element R so that the simulation value SM2 of the SPICE model coincides with the measured value ME2.

[0047] Fig. 16 is a flowchart showing an example of fitting processing. In Fig. 16, first, a circuit model to which a resistive element, an inductive element, or a capacitive element is added is created (step ST31). Then, a simulation is performed using the circuit model to which a resistive element, an inductive element, or a capacitive element is added (step ST32).

[0048] Next, it is determined whether or not a simulation value based on a circuit model to which a resistive element, an inductive element, or a capacitive element is added matches the measured value (step ST33). If the result of the determination in step ST33 is that the simulation value matches the measured value (Yes in step ST33), a circuit model corresponding to the simulation value is created as an equivalent circuit model corresponding to the measured value of the impedance value of the entire circuit (step ST34).

[0049] On the other hand, if the result of the judgment in step ST33 is that the simulation value does not match the measured value (No in step ST33), the process returns to step ST31, and a new circuit model is created by further adding a resistive element, an inductive element, or a capacitive element. A simulation is performed using the new circuit model (step ST32), and it is judged whether the simulation value using the circuit model matches the measured value (step ST33). The above process is repeated until the simulation value using the circuit model matches the measured value. By repeating the above process, the simulation value gradually approaches the measured value, and it is possible to finally make the simulation value match the measured value. The simulation value that matches the measured value is set as an equivalent circuit model. By performing a fitting process using basic circuit elements, i.e., resistive elements, inductive elements, and capacitive elements, it is possible to provide an equivalent circuit model (e.g., a SPICE netlist) that can be used in a general-purpose circuit simulator.

[0050] (Determining whether it matches or not) In step ST33 of FIG. 16, whether or not the simulation value matches the measured value may be determined, for example, as follows. That is, the measured value is not constant, but has a range of variation as shown in FIG. 14 and FIG. 15. When the entire simulation value is included in the range of variation of this measured value, it can be determined that the simulation value matches the measured value. That is, as shown in FIG. 14, the measured impedance value ME1 has a range of variation, and when the entire simulation value SM1 is included in the range of variation of the measured value ME1, it can be determined that the simulation value matches the measured value. Also, as shown in FIG. 15, the measured equivalent series resistance (ESR) value ME2 has a range of variation, and when the entire simulation value SM2 is included in the range of variation of the measured value ME2, it can be determined that the simulation value matches the measured value.

[0051] Also, a frequency range may be divided, and if the simulation value is included in the range of change of the measurement value within that frequency range, it may be determined that the simulation value matches the measurement value. For example, if the frequency band to be used is known in advance, a frequency range may be divided, and it may be determined whether or not the simulation value matches the measurement value within that frequency range.

[0052] 17 to 19 are diagrams showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance (ESR). In FIG. 17 to FIG. 19, the horizontal axis is frequency [Hz], and the vertical axis is impedance [Ω]. By sequentially adding and combining elements as in the circuits shown in FIG. 10 to FIG. 12, a process is performed in which the simulation value SM1 is made to match the impedance measurement value ME1 and the simulation value SM2 is made to match the equivalent series resistance (ESR) measurement value ME2, i.e., a fitting process. At this time, by sequentially combining elements from the low frequency band to the high frequency band, the waveforms of the simulation values ​​SM1 and SM2 are made to match the measurement values ​​ME1 and ME2.

[0053] Figure 17 corresponds to the equivalent circuit in Figure 10. The equivalent circuit in Figure 10 uses one resistive element for the equivalent series resistance and one inductive element for the equivalent series inductance. Since the equivalent series resistance has a small number of elements, it has flat characteristics that do not have frequency dependency, as shown in Figure 17.

[0054] Figure 18 corresponds to the equivalent circuit in Figure 11. The equivalent circuit in Figure 11 is an equivalent circuit in which three CR parallel circuits are added in series to the equivalent circuit in Figure 10. As shown in Figure 18, the frequency characteristics of the equivalent series resistance in the low range are reflected.

[0055] Figure 19 corresponds to the equivalent circuit in Figure 12. The equivalent circuit in Figure 12 is an equivalent circuit in which two LR parallel circuits are added in series to the equivalent circuit in Figure 11. As shown in Figure 19, the frequency characteristics of the impedance and equivalent series resistance in a frequency range higher than the self-resonant frequency are reflected.

[0056] In other words, the accuracy of matching the simulation values ​​with the measured values ​​is higher in the case of FIG. 18, in which the equivalent circuit of FIG. 11 is added, than in the case of FIG. 17, in which the equivalent circuit of FIG. 10 is added. The accuracy of matching the simulation values ​​with the measured values ​​is higher in the case of FIG. 19, in which the equivalent circuit of FIG. 12 is added, than in the case of FIG. 18, in which the equivalent circuit of FIG. 11 is added. As described above, by adding resistive elements, inductive elements, and capacitive elements, the accuracy of matching the simulation values ​​with the measured values ​​can be improved.

[0057] As described above, a unit cell shown in FIG. 20 can be obtained by fitting the measured values ​​to the simulation values. FIG. 20 is a diagram showing an example of a unit cell. The unit cell shown in FIG. 20 includes resistive elements R1, R3 to R9, capacitive elements C1, C4, C5, C7, C8, and inductive elements L2, L7 to L10. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, R6, R7, R8, and R9 are connected in series. The resistive element R1 is connected to the capacitive element C1, the capacitive element C4 is connected to the resistive element R4, the capacitive element C5 is connected to the resistive element R5, the inductive element L7 is connected to the resistive element R6, the inductive element L8 is connected to the resistive element R7, the capacitive element C7 and the inductive element L9 are connected to the resistive element R8, and the capacitive element C8 and the inductive element L10 are connected to the resistive element R9 in parallel. The resistive element R1 is an insulation resistor.

[0058] (Unit cell array) Figure 21 shows the overall impedance Z total FIG. 22 shows an image of the overall impedance Z total FIG. 13 is a diagram showing an example of an arrangement of unit cells corresponding to

[0059] In Figure 21, the overall impedance Z total One terminal is positive (+) and the other terminal is negative (-). Next, the total impedance Z total is converted to an array of m rows and n columns (m and n are natural numbers). In this example, when the array is m rows and n columns, the impedance Z unit Let us consider the total impedance Z totalis defined as the impedance Z of the unit cell multiplied by the number of unit cells K=m(n-1). unit is defined by the following equation (2). Z unit =K Z total …(2) As can be seen from equation (2), the overall impedance Z total From the impedance of the unit cell, Z unit can be derived by a simple calculation.

[0060] Using the above formula, the impedance of a unit cell is derived from the overall impedance based on the periodic structure of the array. For example, as shown in FIG. 22, when the array is 3×3, m=3 and n=3, so the number of unit cells K=3·(3-1)=6. Therefore, as shown in FIG. 22, six unit cells (i.e., K=6) are connected in parallel. Therefore, the overall impedance Z total To divide it into six unit cells connected in parallel, the resistance and inductance are multiplied by 6, and the capacitance is multiplied by 1 / 6. That is, the resistance value R of the unit cell is unit is expressed by the following equation (3), the induction value L of the unit cell unit is expressed by the following equation (4), the capacitance value of the unit cell C unit is expressed as follows: R unit =K R total …(3) L unit =K L total …(4) C unit =C total / K …(5)

[0061] In formula (3), R total is the resistance value of the resistor element before it is divided into unit cells. In equation (4), L total is the inductance value of the inductive element before it is divided into unit cells. In equation (5), C total is the capacitance value of the capacitive element before being divided into unit cells.

[0062] In other words, to divide it into K unit cells connected in parallel, the resistance and induction values ​​are multiplied by K, and the capacitance value is multiplied by 1 / K. In this way, the value of each element is multiplied by K or 1 / K and then distributed to the unit cells.

[0063] By determining the values ​​of each element as shown in the above equations (3) to (5), the impedance obtained by combining all the elements is the original impedance Z total become.

[0064] 23 is a diagram showing a state in which the impedances of unit cells are arranged between the nodes of a two-dimensional lattice arranged in m rows and n columns. In this example, the impedances Z of six unit cells are arranged between nodes S1 to S9 arranged in 3 rows and 3 columns. unit1 ~Z unit6 The three nodes S7 to S9 correspond to the positive poles, and the nodes S1 to S3 and S4 to S6 correspond to the negative poles.

[0065] FIG. 24 is a diagram showing an example of an equivalent circuit model of a multi-terminal capacitor. The equivalent circuit model in FIG. 24 has an impedance Z unit1 ~Z unit6 and an equivalent circuit model of the parasitic component PP are combined in a two-dimensional lattice, and further positive or negative terminals T1 to T9 are set at nodes S1 to S9 of the two-dimensional lattice. The parasitic component PP is a parasitic component caused by the board on which the multi-terminal capacitor is mounted. The parasitic component PP is, for example, a series connection of a resistive element and an inductive element. By combining the parasitic components PP, an equivalent circuit model can be created that reflects parasitic components such as the inductance and stray capacitance of the wiring. As described above, an equivalent circuit model having a topology corresponding to the structure of the multi-terminal capacitor can be provided.

[0066] (Example of symbols) The equivalent circuit model of a multi-terminal capacitor can be represented by symbols. Fig. 25 is a table showing examples of symbols that represent the equivalent circuit model of a multi-terminal capacitor.

[0067] FIG. 25 shows symbols for cells with two types of poles, i.e. positive pole P and negative pole N. Item (a) in FIG. 25 is a symbol for an interior cell of the array, i.e. a cell that is not at a corner and not at an end. Item (b) in FIG. 25 is a symbol for an end cell that is not at a corner and has a different type of pole than its neighbors on either side. Item (c) in FIG. 25 is a symbol for an end cell that is not at a corner and has the same type of pole as its neighbors on either side. Item (d) in FIG. 25 is a symbol for a corner cell.

[0068] In FIG. 25, the symbol of the positive electrode P is composed of a white rectangle RE0, a rectangle RE1 arranged in the upper right of the rectangle RE0, a hook H1 extending from the rectangle RE1 to the lower left of the rectangle RE0, a black rectangle TS arranged outside the rectangle RE0, and a line segment TSS connecting the rectangle RE0 and the rectangle TS. The black rectangle TS indicates a terminal connected to an adjacent cell. The rectangle TS is four in item (a) of FIG. 25, indicating that it has four terminals. The rectangle TS is three in items (b) and (c) of FIG. 25, indicating that it has three terminals. The rectangle TS is two in item (d) of FIG. 25, indicating that it has two terminals.

[0069] In FIG. 25, the symbol of the negative electrode N is composed of a white rectangle RE0, a rectangle RE2 arranged in the lower left of the rectangle RE0, a hook H2 extending from the rectangle RE2 toward the upper right of the rectangle RE0, a black rectangle TS arranged outside the rectangle RE0, and a line segment TSS connecting the rectangle RE0 and the rectangle TS. The black rectangle TS indicates a terminal connected to an adjacent cell. The rectangle TS is four in item (a) of FIG. 25, indicating that it has four terminals. The rectangle TS is three in items (b) and (c) of FIG. 25, indicating that it has three terminals. The rectangle TS is two in item (d) of FIG. 25, indicating that it has two terminals.

[0070] FIG. 25 shows an example of setting symbols divided into lattice-shaped regions, and other symbols may be used.

[0071] 26 is a diagram showing a multi-terminal capacitor with a terminal arrangement of 3 rows and 3 columns. With reference to FIG. 26, an impedance Z unit1 The unit cell of this circuit has an impedance Z between terminals T8 and T2. unit2 The unit cell of this circuit has an impedance Z between terminals T9 and T3. unit3 The unit cell of this circuit has an impedance Z between terminals T7 and T4. unit4 The unit cell of this circuit has an impedance Z between terminals T8 and T5. unit5 The unit cell of this circuit has an impedance Z between terminals T9 and T6. unit6 The unit cells are connected to each other.

[0072] Fig. 27 is a diagram showing a multi-terminal capacitor represented by the symbol shown in Fig. 25. Fig. 27 is a diagram showing a multi-terminal capacitor 1a equivalent to the multi-terminal capacitor shown in Fig. 26.

[0073] The impedance Z of the unit cell between terminals T7 and T1 in FIG. unit1 is evenly distributed to the symbols of terminals T7 and T1 at the same positions in FIG. 27. That is, the impedance Z unit1 / 2 is set to the symbol at terminal T7 and the symbol at terminal T1.

[0074] The impedance Z of the unit cell between terminals T8 and T2 in FIG. unit2 is evenly distributed to the symbols of terminals T8 and T2 at the same positions in FIG. 27. That is, the impedance Z unit2 / 2 is set to the symbol at terminal T8 and the symbol at terminal T2.

[0075] Impedance Z of the unit cell between terminals T9 and T3 in FIG. unit3 is evenly distributed to the symbols of terminals T9 and T3 at the same positions in FIG. 27. That is, the impedance Z unit3 / 2 is set to the symbol at terminal T9 and the symbol at terminal T3.

[0076] The impedance Z of the unit cell between terminals T7 and T4 in FIG. unit4 is evenly distributed to the symbols of terminals T7 and T4 at the same positions in FIG. 27. That is, the impedance Z unit4 / 2 is set to the symbol at terminal T7 and the symbol at terminal T4.

[0077] The impedance Z of the unit cell between terminals T8 and T5 in FIG. unit5 is evenly distributed to the symbols of terminals T8 and T5 at the same positions in FIG. 27. That is, the impedance Z unit5 / 2 is set to the symbol at terminal T8 and the symbol at terminal T5.

[0078] Impedance Z of the unit cell between terminals T9 and T6 in FIG. unit6 is evenly distributed to the symbols of terminals T9 and T6 at the same positions in FIG. 27. That is, the impedance Z unit6 / 2 is set to the symbol at terminal T9 and the symbol at terminal T6.

[0079] As described with reference to FIG. 26 and FIG. 27, by setting symbols corresponding to elements constituting a multi-terminal capacitor, editing of a circuit diagram in a circuit simulator, such as changing the terminal arrangement, is easy. For example, it is easy to change from a multi-terminal capacitor 1a with a terminal arrangement of 3 rows and 3 columns shown in FIG. 27 to a multi-terminal capacitor 1b with a terminal arrangement of 3 rows and 5 columns shown in FIG. 28. FIG. 28 is a diagram showing a multi-terminal capacitor with a terminal arrangement of 3 rows and 5 columns. The multi-terminal capacitor 1b shown in FIG. 28 has 15 terminals T1 to T15. In this example, the impedance of the symbol corresponding to the terminal T4 is evenly distributed to the symbol of the terminal T10 and the symbol of the terminal T13, the impedance of the symbol corresponding to the terminal T5 is evenly distributed to the symbol of the terminal T11 and the symbol of the terminal T14, and the impedance of the symbol corresponding to the terminal T6 is evenly distributed to the symbol of the terminal T12 and the symbol of the terminal T15. In this way, it is possible to change from the multi-terminal capacitor 1a with a terminal arrangement of 3 rows and 3 columns to the multi-terminal capacitor 1b with a terminal arrangement of 3 rows and 5 columns.

[0080] FIG. 29 is a diagram showing an equivalent circuit of the substrate 10a including the multi-terminal capacitor 1 described with reference to FIG. 6. In FIG. 29, the multi-terminal capacitor 1a is expressed by the symbols described with reference to FIG. 25. In the multi-terminal capacitor 1a of FIG. 29, the terminals T7 to T8 corresponding to the three symbols corresponding to the positive poles are electrically connected to the positive pole PO11 of the port PO1 and the positive pole PO21 of the port PO2. The terminals T1 to T6 corresponding to the six symbols corresponding to the negative poles are electrically connected to a reference potential, for example, a ground. A resistor RA is electrically connected between the positive pole PO11 and the negative pole PO12 of the port PO1. A resistor RB is electrically connected between the positive pole PO21 and the negative pole PO22 of the port PO2. By connecting as in FIG. 29, an S parameter for impedance evaluation based on the shunt-through method can be obtained for the multi-terminal capacitor 1a.

[0081] Fig. 30 is a diagram showing an example of a simulation result of S parameters. In Fig. 30, the horizontal axis indicates frequency [Hz], and the vertical axis indicates S parameter values ​​[dB]. Fig. 30 shows S11 and S21 among the S parameters. S11 is a value obtained by dividing the power reflected from port PO1 by the power incident on port PO1. S21 is a power gain when the impedance of the power supply and the load is set to 50Ω.

[0082] (Example of application of multi-terminal capacitor) FIG. 31 is a diagram for explaining an example of a simulation in the time domain. In this example, power is supplied from a DC power supply 20 to a load 30 via a substrate 10. A voltage Vdc of the DC power supply 20 is applied to the load 30 via the substrate 10. In this example, a current source Idc is provided that is connected in parallel to the load 30. The connections of the resistive element and the inductive element, and the connections of the resistive element, the inductive element and the capacitive element in FIG. 31 are equivalent circuits of the substrate 10. The load 30 is, for example, a semiconductor chip such as a controller or a processor.

[0083] Fig. 32 is a diagram showing changes in the current value of the current source Idc in Fig. 31. In Fig. 32, the horizontal axis represents the rise time Ti of the current value, and the vertical axis represents the amplitude Ai.

[0084] Fig. 33 is a diagram showing an example of changes in the load voltage. In Fig. 33, the horizontal axis is time [ns] and the vertical axis is voltage [V]. The dashed line in Fig. 33 shows voltage V0 when multi-terminal capacitor 1a is not provided. The solid line in Fig. 33 shows voltage V1 when multi-terminal capacitor 1a is provided.

[0085] 31 to 33, the current value of the current source Idc may increase or the load voltage may drop due to the operation of the load 30. For example, as shown in FIG. 33, the load voltage may drop and then change to rise. Even in such a case, the fluctuation in the load voltage can be reduced or suppressed by charging and discharging the multi-terminal capacitor 1a provided on the substrate 10. As shown in FIG. 33, the voltage V1 when the multi-terminal capacitor 1a is provided fluctuates less than the voltage V0 when the multi-terminal capacitor 1a is not provided.

[0086] (Simulation device) Fig. 34 is a diagram showing a configuration example of a simulation device of the present disclosure. The simulation device 100 shown in Fig. 34 is a simulation device equipped with a program for calculating the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. In Fig. 34, the simulation device includes an input unit 101, a calculation unit 102, an output unit 103, a storage unit 104, and a storage unit 105.

[0087] Data such as conditions for setting an equivalent circuit model is input through the input unit 101. The input unit 101 includes, for example, a keyboard and a mouse.

[0088] The calculation unit 102 executes a program based on the data input by the input unit 101. The calculation unit 102 includes, for example, a CPU (Central Processing Unit).

[0089] The output unit 103 displays the calculation results from the calculation unit 102, the waveforms of characteristics from a simulator, etc. The output unit 103 is realized by, for example, a display device.

[0090] The storage unit 104 stores data of an equivalent circuit model. The data of the equivalent circuit model stored in the storage unit 104 is, for example, data of a multi-terminal capacitor 1a shown in FIG. 27 or data of a multi-terminal capacitor 1b shown in FIG. 28. The storage unit 105 stores a program for executing a simulator. The simulator stored in the storage unit 105 calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. The storage units 104 and 105 may be realized by a magnetic disk device or a semiconductor memory.

[0091] 34, data input from an input unit 101 and data of an equivalent circuit model are stored in a storage unit 104. A calculation unit 102 executes a program stored in a storage unit 105 to start a simulator. The calculation unit 102 performs calculations using the simulator. An output unit 103 outputs the waveform of characteristics obtained as a result of the calculations of the calculation unit 102 in a format such as a graph display.

[0092] The simulation device shown in FIG. 34 is provided with a program for calculating the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. By using a simulation device provided with data and a program of an equivalent circuit model capable of calculating the characteristics of a multi-terminal capacitor, it is possible to efficiently and accurately design a circuit for an electronic device using a multi-terminal capacitor. This provides an efficient design environment for designers. In addition, by providing a simulation device that simplifies the operation of displaying the characteristics of a multi-terminal capacitor and comparing the characteristics, it is possible to make the part selection work of a designer more efficient. For example, when a desired multi-terminal capacitor is constructed by a user's operation on a Web page, the S-parameters of the multi-terminal capacitor can be measured, and an element for realizing the waveform of the frequency characteristic of the S-parameter can be selected, and an equivalent circuit model corresponding to the above waveform can be created by combining the selected elements. Then, the created equivalent circuit model of the multi-terminal capacitor can be used to calculate the characteristics of the multi-terminal capacitor or the characteristics of a circuit including the multi-terminal capacitor.

[0093] That is, the simulation device shown in FIG. 34 is a device that calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit including a multi-terminal capacitor by using an equivalent circuit model of a multi-terminal capacitor created by using the above-mentioned equivalent circuit model creation method. This simulation device can realize a simulation method that calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit including a multi-terminal capacitor by using an equivalent circuit model of a multi-terminal capacitor created by using the above-mentioned equivalent circuit model creation method. The characteristics of a multi-terminal capacitor and the characteristics of a circuit having a multi-terminal capacitor, such as a circuit to which a multi-terminal capacitor is connected, can be evaluated by various methods such as the frequency domain and the time domain. By providing various equivalent circuit models of a multi-terminal capacitor as a library, the characteristics of a multi-terminal capacitor can be evaluated in a simulation environment specified by a user. In addition, by providing a dedicated simulation device, input operations such as model setting and output operations such as graph display are facilitated, improving user convenience.

[0094] (Equivalent circuit model creation program) A program for executing the equivalent circuit model creation method described with reference to Fig. 1 may be created and executed by a computer. This program is an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a positive external electrode terminal row and a negative external electrode terminal row are alternately arranged in parallel, and causes a computer to execute the following steps: a first step of measuring S parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on the measured values ​​of the S parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of creating a two-dimensional lattice topology by combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step. This equivalent circuit model creation program is stored in, for example, a storage unit 105 in Fig. 34. This equivalent circuit model creation program is read out from the storage unit 105 by the calculation unit 102 in Fig. 34 and executed, for example. Note that this equivalent circuit model creation program may be stored in a storage medium removable from the computer. For example, the equivalent circuit model creation program may be stored in a USB flash drive (Universal Serial Bus flash drive), that is, a so-called USB memory.

[0095] (summary) According to the above method, it is possible to create an equivalent circuit model of a multi-terminal capacitor in which the external electrode terminals are arranged in a grid pattern. In addition, it is possible to arrange the rows of positive and negative electrodes of the external electrode terminals in a striped pattern, alternating in parallel. Furthermore, the impedance of the multi-terminal capacitor is derived from the measured values ​​of two-port S parameters when mounted on a board. Since a two-port measurement method is used instead of a multi-port method, the man-hours required for measurement and evaluation can be reduced.

[0096] In addition, a two-terminal equivalent circuit model can be created by fitting processing based on the derived overall impedance. The impedance of a unit cell can be derived from the overall impedance based on the periodic structure of the lattice-like equivalent circuit model. A two-dimensional lattice-like topology is created by combining the unit cell equivalent circuit model and the wiring equivalent circuit model as circuit elements, and an overall equivalent circuit model can be created by setting terminals at the nodes of the lattice. This makes it possible to create an equivalent circuit model with a topology corresponding to the structure of a multi-terminal capacitor. In addition, the amount of calculations required for circuit simulation can be reduced by repeatedly using the characteristics of the unit cell. Furthermore, a SPICE model with high accuracy and low calculation costs in both the time domain and the frequency domain can be provided. [Explanation of symbols]

[0097] 1, 1a, 1b Multi-Terminal Capacitor 10, 10a Board 11 Jig 100 Simulation device 101 Input section 102 Arithmetic section 103 Output section 104, 105 Storage section PO1 port PO2 port T1~T15 terminals

Claims

1. 1. A method for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a positive external electrode terminal row and a negative external electrode terminal row are alternately arranged in parallel, comprising the steps of: a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component to create a two-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step; The present invention relates to a method for creating an equivalent circuit model.

2. 2. The method for creating an equivalent circuit model according to claim 1, wherein in the third step, the two-terminal equivalent circuit model is created by a fitting process for bringing simulation values ​​closer to measured values ​​of the S parameters.

3. 3. The method for creating an equivalent circuit model according to claim 2, wherein in the fitting process, the two-terminal equivalent circuit model is created by successively connecting circuit elements so as to match the measured values ​​of the S parameters.

4. 4. The method for creating an equivalent circuit model according to claim 1, wherein in the fourth step, in order to divide the circuit into K unit cells connected in parallel, the resistance value and the induction value are multiplied by K and the capacitance value is multiplied by 1 / K to allocate the resistance value and the induction value to the unit cells.

5. 2. The method for creating an equivalent circuit model according to claim 1, wherein in the first step, the S parameters are measured using a jig having a substrate on which the multi-terminal capacitor is mounted.

6. 1. An equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a positive external electrode terminal row and a negative external electrode terminal row are alternately arranged in parallel, comprising: On the computer, a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component to create a two-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step; An equivalent circuit model creation program for executing the above.

7. A storage medium storing an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which a positive external electrode terminal row and a negative external electrode terminal row are alternately arranged in parallel, On the computer, a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining the equivalent circuit model of the unit cell derived in the fourth step with an equivalent circuit model of a parasitic component to create a two-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the two-dimensional lattice topology created in the fifth step; A storage medium storing an equivalent circuit model creation program for executing the above.

8. 2. A simulation method for calculating characteristics of a multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor, by using an equivalent circuit model of the multi-terminal capacitor created by using the equivalent circuit model creation method according to claim 1.

9. 2. A simulation device that uses an equivalent circuit model of a multi-terminal capacitor created by using the equivalent circuit model creation method according to claim 1 to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor.

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