Semiconductor processing chamber for deposition and etching

Abstract

An exemplary semiconductor substrate support may include a pedestal having a shaft and a platen. The semiconductor substrate support may include a cover plate. The cover plate may be connected to the platen along a first surface of the cover plate. The cover plate may define a recessed channel in a second surface of the cover plate opposite the first surface. The semiconductor substrate support may include a puck connected to the second surface of the cover plate. The puck may incorporate an electrode. The puck may define a plurality of apertures extending vertically through the puck to provide fluid access to the recessed channel defined in the cover plate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 014,177, entitled "SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH," filed Sep. 8, 2020, the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology is related to the following applications, all filed simultaneously on September 8, 2020, entitled SINGLE CHAMBER FLOWABLE FILM FORMATION AND TREATMENTS, Attorney Docket No. 44018206US01 (1190509), and SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH, Attorney Docket No. 44018155US01 (1190407), each of which is incorporated by reference in its entirety for all purposes. [Background technology]

[0003]

[0003] The present technology relates to semiconductor processing, and more particularly, to systems and methods for depositing and processing materials, including flowable films.

[0004]

[0004] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming and removing exposed materials. As devices become smaller, material formation can impact subsequent operations. For example, in gap-fill operations, material can be formed or deposited to fill trenches or other features formed on a semiconductor substrate. These fill operations can be challenging because the features can be characterized by high aspect ratios and reduced critical dimensions. For example, deposition can occur on top of and along the sidewalls of the features, so continued deposition can pinch off the feature, including between the sidewalls within the feature, creating voids within the feature. This can impact device performance and subsequent processing operations.

[0005]

[0005] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technique. Summary of the Invention

[0006] An exemplary semiconductor substrate support may include a pedestal having a shaft and a platen. The semiconductor substrate support may include a cover plate. The cover plate may be connected to the platen along a first surface of the cover plate. The cover plate may define a recessed channel in a second surface of the cover plate opposite the first surface. The semiconductor substrate support may include a puck connected to the second surface of the cover plate. The puck may incorporate an electrode. The puck may define a plurality of apertures extending vertically through the puck to provide fluid access to the recessed channel defined in the cover plate.

[0007] In some embodiments, the platen may define a fluid channel through the platen. The recessed channel may be a first recessed channel and the cover plate may define a second recessed channel radially outward of the first recessed channel. The first recessed channel may be fluidly accessed from a first side channel defined in the cover plate. The second recessed channel may be fluidly accessed from a second side channel defined in the cover plate. The support may include a first channel cover mounted on the first recessed channel. The first channel cover may define a plurality of apertures through the first channel cover. Each aperture of the plurality of apertures through the first channel cover may be aligned with a corresponding aperture of the plurality of apertures extending vertically through the pack. The support may include a lift pin assembly extending through the platen, the cover plate, and the pack. The lift pin assembly may include a lift pin, a liner, a holder, and a counterweight. An exhaust path may be defined around the liner and through the holder. The support may include an RF rod extending through the shaft of the pedestal. The RF rod may be electrically connected to the electrode by a conductive connector disposed inside the puck. The support may include a rod insulator extending around the RF rod along its length. The pedestal may be mounted within the hub and the rod insulator may extend through the hub. The support may include a puck insulator extending around the conductive connector in the puck. The rod insulator may be at least partially mounted within the puck insulator. The pedestal and cover plate may define a purge path extending at the cover plate to the rod insulator. The purge path may continue along the interior and exterior of the rod insulator.

[0008]

[0008] Some embodiments of the present technology may include a semiconductor processing system. The system may include a chamber body. The system may include a substrate support configured to support a semiconductor substrate. The substrate support may include a pedestal having a shaft and a platen. The substrate support may include a cover plate. The cover plate may be connected to the platen along a first surface of the cover plate. The cover plate may define a recessed channel in a second surface of the cover plate opposite the first surface. The substrate support may include a puck connected to the second surface of the cover plate. The puck may incorporate an electrode. The puck may define a plurality of apertures extending vertically through the puck and may fluidly access the recessed channel defined in the cover plate. The system may include a face plate. The chamber body, the substrate support, and the face plate may define a processing region. The chamber may include a high frequency plasma source connected to the face plate. The system may include a low frequency plasma source connected to the substrate support.

[0009] In some embodiments, the substrate support may include an electrostatic chuck. The semiconductor processing system may also include a DC power source connected to the substrate support. The low frequency plasma source may be configured to operate at about 2 MHz or less. The high frequency plasma source may be configured to operate at about 13.56 MHz or greater, with a pulse frequency of about 20 kHz or less, at a duty cycle of about 20% or less. The high frequency plasma source may be configured to generate plasma at an effective power of about 5 W or less. The concave channel may be a first concave channel. The cover plate may define a second concave channel radially outward of the first concave channel. The first concave channel may be fluidly accessed from a first side channel defined in the cover plate. The second concave channel may be fluidly accessed from a second side channel defined in the cover plate. The system may include a first channel cover disposed on the first concave channel. The first channel cover may define a plurality of apertures therethrough. Each aperture of the plurality of apertures through the first channel cover may be aligned with a corresponding aperture of the plurality of apertures extending vertically through the puck. The system may include a first LC filter connected to the substrate support and configured to virtually ground the high frequency plasma source through the substrate support. The system may include a second LC filter connected to the faceplate and configured to virtually ground the low frequency plasma source to the chamber body.

[0010]

[0010] Such techniques may provide numerous advantages over conventional systems and techniques. For example, improved cooling and plasma management may be provided by utilizing a substrate support in accordance with the present techniques. Additionally, repeatable plasma generation may be achieved during the deposition process by performing deposition in accordance with embodiments of the present techniques. These and other embodiments, together with their many advantages and features, are described in more detail in the following description and accompanying drawings.

[0011] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0012] [Figure 1] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2]

[0013] 1 shows a schematic partial cross-sectional view of a chamber in accordance with some embodiments of the present technique; [Diagram 3]

[0014] 1 shows a schematic partial cross-sectional view of a substrate support assembly, in accordance with some embodiments of the present technique; [Figure 4A]

[0015] FIG. 1 shows a schematic exploded perspective view of a cover plate according to some embodiments of the present technology. [Figure 4B]

[0016] 1 shows a schematic partial cross-sectional view of a cover plate in accordance with some embodiments of the present technology. [Figure 5A]

[0017] 1 shows a schematic partial cross-sectional view of a substrate support assembly, in accordance with some embodiments of the present technique; [Figure 5B]

[0018] 1 shows a schematic diagram of a holder according to some embodiments of the present technology. [Figure 6A]

[0019] 1 shows a schematic partial cross-sectional view of a substrate support assembly, in accordance with some embodiments of the present technique; [Figure 6B]

[0020] 1 shows a schematic partial cross-sectional view of an insulator according to some embodiments of the present technology; [Figure 7]

[0021] 1 illustrates exemplary steps in a processing method according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0022] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0014]

[0023] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any one of the similar components having the same first reference number, regardless of the letter.

[0015]

[0024] Amorphous silicon may be used in semiconductor device fabrication for many structures and processes, including as a sacrificial material, e.g., as a dummy gate material, or as a trench fill material. In gap-filling steps, some processes utilize a flowable film formed under process conditions to limit the conformality of the deposition, allowing the deposited material to better fill features on the substrate. Flowable silicon materials may be characterized by a relatively high amount of hydrogen and may be less dense than other formed films. As a result, subsequent processing steps may be performed to harden the resulting film. Conventional techniques may utilize a UV curing process to remove hydrogen and treat the film. However, UV curing may cause significant film shrinkage, which may create voids in the structure as well as stress the features. In addition, the processing is performed in a separate chamber from the deposition chamber, which increases processing time and reduces throughput.

[0016]

[0025] As feature sizes continue to shrink, flowable films can be a challenge for narrow features that may be further characterized by higher aspect ratios. For example, deposition on the sidewalls of the feature may more easily result in pinching of the feature, and smaller feature sizes may further restrict further flow into the feature, resulting in voids. Some conventional flowable film formation may be performed by generating radicals in a remote capacitively coupled plasma region or a remote plasma source unit connected to the chamber. However, for cyclical formation of high aspect ratio features, this process may provide unreliable deposition. For example, as radicals pass through chamber parts such as the faceplate, recombination may cause problems with consistent delivery of radical effluent. In addition, remote plasma sources may not be able to limit the amount of deposition in small pitch features. This may result in excessive deposition in the feature, limiting or preventing complete penetration of processing effluent. This may cause damage during subsequent processing and may result in scrapping of the substrate.

[0017]

[0026] The present technology overcomes these limitations by separating high and low frequency power sources and utilizing triggering sequences that can perform short periods of repeatable plasma generation at low power. This can limit deposition during trench filling to tightly controlled amounts as well as ensure complete processing during subsequent processing steps. In addition, the present technology can incorporate a substrate support assembly that can better control temperature drift during processing steps to better ensure stable and repeatable temperatures at each deposition cycle. After describing the general aspects of the chamber according to some embodiments of the present technology in which the plasma processing steps described below may be performed, specific chamber configurations and methods may be described. It is understood that the present technology is not intended to be limited to the specific films, chambers, or processes described, as the techniques described may be used to improve numerous film formation processes for any number of materials and may be applicable to a variety of processing chambers and processes.

[0018]

[0027] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technique. The diagram may provide an overview of a system incorporating one or more aspects of the present technique and / or that may perform one or more deposition or other processing steps according to embodiments of the present technique. Additional details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and confining the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be located on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 about which the shaft 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated for rotation as needed during the deposition process.

[0019]

[0028] A plasma profile modulator 111 may be disposed in the process chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 includes a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the process chamber 100 surrounding the process space 120 or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor, for example.

[0020]

[0029] The one or more isolators 110a, 110b may be a dielectric material such as ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be connected to a processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0021]

[0030] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, but the face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be connected to ground in some embodiments.

[0022]

[0031] The first electrode 108 may be connected to a first tuned circuit 128 that may control a ground path of the process chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuned circuit 128 may be or may include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the process space 120 during processing. In some illustrated embodiments, the first tuned circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node coupling both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage sensor or a current sensor and can be connected to the first electronic controller 134 to allow some closed-loop control of the plasma conditions inside the process space 120.

[0023]

[0032] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or may be connected to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136, for example, by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138, a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the process space 120.

[0024]

[0033] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to the substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other sources. In some embodiments, the second power source 150 may be RF bias power.

[0025]

[0034] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 may perform real-time control of plasma conditions within the processing space 120. The substrate 103 may be placed on the substrate support 104, and process gases may flow through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may be exhausted from the processing chamber 100 through the outlet 152. Power may be connected to the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 124.

[0026]

[0035] Upon exciting a plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134 and 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and center-to-edge plasma density uniformity. In an embodiment in which both electronic controllers may be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize the thickness non-uniformity.

[0027]

[0036] Each of the tuning circuits 128 and 136 may have a variable impedance that may be adjusted using the respective electronic controllers 134 and 140. If the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high. This results in a plasma shape that has a minimum aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, thus effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls, reducing the aerial coverage of the substrate support. The second electronic controller 140 may have a similar effect, so that as the capacitance of the second electronic controller 140 changes, the aerial coverage of the plasma above the substrate support increases or decreases.

[0028]

[0037] Electronic sensors 130 and 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor. The sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the shape of the plasma may be selected and dynamically controlled during processing. Although the above description is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic components having adjustable characteristics may be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0038] 2 illustrates a schematic partial cross-sectional view of a processing chamber 200 in accordance with some embodiments of the present technique. The chamber 200 may include any of the features, components, or characteristics of the processing chamber 100 described above, and may exhibit additional features of the chamber, including certain power sources in communication with the chamber. For example, the chamber 200 may include a chamber body 205. The chamber may include a substrate support 210, which may be configured to support a substrate during semiconductor processing. The chamber may include a faceplate 215, which, together with a pedestal and the chamber body, may define a processing region above a substrate during processing.

[0030]

[0039] Some conventional processing systems may generate a plasma within the processing region by applying power to the faceplate while grounding the pedestal, or by applying source power to the pedestal and grounding the faceplate. In some systems, an additional bias power may be connected to the pedestal to enhance directionality of the plasma effluents. It should be understood that a separate DC power supply for electrostatic chucking may be connected to the pedestal and operated to further bias the plasma generated within the processing chamber in addition to chucking the substrate, as described above with respect to the processing chamber 100. The present technique may differ from conventional configurations by connecting two separate plasma power sources to the showerhead and pedestal as shown. For example, a first plasma power source 220 may be connected to the showerhead and a second plasma power source 230 may be connected to the pedestal. In some embodiments, the first plasma power source 220 may be a high frequency plasma power source and the second plasma power source 230 may be a low frequency plasma power source. In some embodiments, the low frequency plasma power supply 230 is separate from the DC power supply, which may be used to electrostatically couple the substrate to the pedestal.

[0031]

[0040] The low frequency plasma power source operates at a first frequency that is about 2 MHz or less, and may operate at about 1.5 MHz or less, about 1.0 MHz or less, about 800 kHz or less, about 600 kHz or less, about 500 kHz or less, about 400 kHz or less, about 350 kHz or less, about 300 kHz or less, about 250 kHz or less, about 200 kHz or less, or less. The high frequency plasma power source operates at a second frequency that is about 2 MHz or more, and may be about 10 MHz or more, about 13 MHz or more (such as about 13.56 MHz), about 15 MHz or more, about 20 MHz or more, about 40 MHz or more, or more.

[0032]

[0041] Additional aspects of the plasma source may be used to further tailor the plasma generated within the processing region. For example, chambers according to embodiments of the present technology may be used to fill high aspect ratio features, where a discreet amount of deposition may be produced to limit void formation within the features being filled. Conventional chambers may be limited in reducing plasma power based on an inability to generate repeatable low power plasma for a limited period of time. The present technology may be used to produce material layers characterized by thicknesses of about 10 nm or less per cycle. To achieve this limited deposition, either the deposition period may be limited or the power used during deposition may be reduced. Conventional systems may not be able to reduce plasma power to about 100 W or less, which increases the amount of deposited material, and shortening the formation period to accommodate this higher power may limit the ability to generate reproducible plasma during multiple cycles of deposition.

[0033]

[0042] The present technology overcomes these problems by generating a low power deposition plasma, which is characterized by an effective plasma power of about 20 W or less, and may be characterized by an effective plasma power of about 15 W or less, about 10 W or less, about 8 W or less, about 6 W or less, about 5 W or less, about 4 W or less, about 3 W or less, or less. To generate this low power plasma during the deposition process, the system may operate a high frequency plasma power at a pulse frequency of about 200 kHz or less, and operate the plasma power at a pulse frequency of about 150 kHz or less, about 100 kHz or less, about 80 kHz or less, about 70 kHz or less, about 60 kHz or less, about 50 kHz or less, about 40 kHz or less, about 30 kHz or less, about 20 kHz or less, about 10 kHz or less, or less. Additionally, at any of the listed pulse frequencies, the radio frequency plasma power source can be operated at a reduced duty cycle of about 50% or less, about 45% or less, about 40% or less, about 35% or less, about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, about 5% or less, or less.

[0034]

[0043] In some embodiments, the pulse frequency and duty cycle may be reduced to address plasma generation in a consistent manner. A low power plasma, once generated, may generate a slow deposition rate to limit deposition per cycle, but ignition may be problematic. Thus, in some embodiments, the plasma power may be operated in a trigger sequence to facilitate plasma generation during deposition. For example, as described above, in some embodiments, the deposition process may be performed without a low frequency plasma power source. However, in some embodiments, the low frequency plasma power source may be operated during the deposition process to facilitate ignition. In addition, the low frequency plasma power source may not be operated, and a power spike may be applied with the high frequency plasma power source to facilitate ignition. The power spike may be applied directly by the power management or through level-by-level operation of the high frequency plasma power source.

[0035]

[0044] The low frequency plasma power source may also operate to control the plasma formation and ion directionality during processing. By supplying low frequency plasma power through the pedestal, the plasma sheath formed by this powered electrode may benefit the directionality of ions to the features being densified. Although the low frequency plasma power source may operate at any of the power levels or pulse frequencies described above, in some embodiments, the second power source 230 may operate at a plasma power greater than the first power source 220 during processing steps. For example, the plasma power supplied by the second power source during processing may be about 50 W or more, about 100 W or more, about 200 W or more, about 300 W or more, about 400 W, about 500 W or more, about 600 W or more, about 700 W or more, about 800 W or more, or more. By increasing the plasma power of the low frequency power source during processing plasma formation, a greater amount of plasma effluent may be generated. By applying more low frequency power from the pedestal, the directionality of the supply perpendicular to the plane across the substrate may be increased.

[0036]

[0045] Additional adjustments can be made to further increase etching of the deposited material along the sidewalls of the feature by adjusting one or more characteristics of the supplied plasma power or bias power. For example, in some embodiments, both the plasma power source and the bias power source can be operated in a continuous wave mode. In addition, one or both of the power sources can be operated in a pulsed mode. In some embodiments, during processing, the high frequency source power can be operated in a continuous wave mode or a pulsed mode, while the low frequency power can be operated in a pulsed mode. The pulse frequency of the low frequency plasma power source can be about 1,000 Hz or less, and can be about 900 Hz or less, about 800 Hz or less, about 700 Hz or less, about 600 Hz or less, about 500 Hz or less, about 400 Hz or less, about 300 Hz or less, about 200 Hz or less, about 100 Hz or less, or less. The duty cycle of the second power source is about 50% or less, and the low frequency plasma power may be operated at a duty cycle of about 45% or less, about 40% or less, about 35% or less, about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, about 5%, or less. By operating the low frequency power at a reduced duty cycle, such as an on-time duty of about 50% or less, the longer time per cycle may result in a more isotropic etch in the feature based on the operation of the high frequency power source, which may allow for better removal of material from the sidewalls during the densification operation.

[0037]

[0046] The first plasma power source 220 may be connected to ground substantially through the pedestal. For example, as shown, a first LC filter 225 may be connected to the pedestal to substantially ground the high frequency plasma source through the pedestal. Similarly, the second plasma power source 230 may be connected to ground through the chamber. For example, a second LC filter may be connected to the faceplate, which may substantially ground the low frequency plasma source, such as the chamber body or an external ground. By separating the high frequency and low frequency power sources, improved plasma generation and operation may be provided.

[0038]

[0047] 3 shows a schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technique. As mentioned above, the present technique can be used in some embodiments to perform low temperature deposition and curing inside a single chamber. A semiconductor support assembly configured for low temperature operation with low plasma power can face many challenges. For example, when an electrostatic chuck is used, the substrate support surface or puck can be a dielectric material that includes an electrode. The electrode, which can include multiple electrodes, can be one or both of a chuck electrode to which a DC power source can be connected, and a plasma generating electrode to which an RF power source can be connected.

[0039]

[0048] The substrate support assembly according to some embodiments of the present technique may include a low frequency power source connected to the substrate support assembly as described above. The substrate support assembly may also be configured to maintain the substrate at a temperature for both deposition and processing steps. While the pedestal may operate to maintain the substrate temperature, the dielectric puck may generate a temperature gradient from the underlying cooling channels to at least partially insulate the puck and reduce cooling. In addition, plasma performance may also affect the substrate temperature. For example, the present technique may include cyclic formation and processing of a flowable film. Conventional techniques move the substrate between two chambers that perform deposition and processing separately, which may facilitate ensuring that the substrate is maintained at a set point temperature during each deposition step. Because temperature may affect deposition rate and film flow characteristics, maintaining a constant substrate temperature during each deposition cycle may improve film formation through the feature.

[0040]

[0049] Because the technology may generate the processing plasma in the same processing chamber where deposition occurs, cooling the substrate back down to the deposition set point can be problematic due to plasma exposure during processing. While the deposition plasma may be generated at low plasma power, processing may be performed at higher plasma power from the source plasma. This may be 10 times or more the plasma power, increasing the heat load on the substrate. This may cause the substrate temperature during the processing step to be much higher than that experienced during deposition. The substrate support assembly may operate to cool the substrate back down to the deposition set point, but the dielectric material of the pack, such as ceramic, may slow the cooling rate and areas of the substrate may not be easily cooled between the processing step and the subsequent deposition step. Current technology can overcome these problems by increasing heat transfer to the backside of the substrate.

[0041]

[0050] The substrate support assembly 300 is similar to the substrate support 104 or the substrate support 210 and may include any of the features, components, or characteristics of those supports described above, including any associated components or power sources. The substrate support assembly 300 includes a pedestal 305, which may include a shaft 307 and a platen 308. The platen 308 may define one or more fluid channels 309 in a surface of the platen. The fluid channels 309 may connect to a fluid source through inlet and outlet channels through the shaft. They may include one or more channels, such as a spiral or other circuitous pattern. The fluid source may include a cooled or heated fluid in embodiments that include a chiller to further reduce the fluid temperature. The substrate support may be configured to maintain a temperature of about 100° C. or less, and in some embodiments may be configured to maintain a temperature of about 80° C. or less, about 60° C. or less, about 40° C. or less, about 20° C. or less, about 0° C. or less, about −5° C. or less, about −10° C. or less, about −15° C. or less, about −20° C. or less, about −25° C. or less, or lower.

[0042]

[0051] A cover plate 310 may be placed on the platen to overlie the fluid channels. The cover plate 310 may be placed and connected to the platen 308 on a first surface 312 of the cover plate. The cover plate 310 may be further characterized by a second surface 314 opposite the first surface. The second surface 314 may define one or more channels 315, which may be recessed channels defined in the second surface 314 of the cover plate 331. The second surface 314 may also define a peripheral recess 317, which may define an interior platform on which the puck 320 may be placed. The recess 317 may provide protection against particle ingress between the puck 320 and the cover plate 310. By surrounding the area where the components are bonded or connected, the recess may limit gaps or breaks along the edges that may allow material ingress. The pedestal 305 and the cover plate 310 may each be made of a conductive material, such as a metal like aluminum, or any other material that may be thermally conductive. The puck 320 may include a chuck electrode for electrostatic chucking. Thus, in some embodiments, the puck 320 may be a dielectric material, such as aluminum nitride or some other ceramic. Thus, the puck 320 may be adhesively connected to the second surface 314 of the cover plate 310 in some embodiments of the present technology. As described further below, the puck may define a number of apertures extending vertically through the puck. The apertures may fluidly access the recessed channel 315 and form a fluid path through the puck. This may allow additional zone temperature control in a first region accessible from the fluid channel 315a and a second region accessible from the fluid channel 315b. In some embodiments of the present technology, any number of fluid channels may be formed.

[0043]

[0052] The substrate support assembly 300 may include one or more lift pin assemblies 325 that extend through the platen, cover plate, and puck. In some embodiments, an edge ring 330 may rest on a concave ledge defined on the puck and extending around the outer edge of the puck. As shown, the edge ring 330 may rest on the outer ledge of the cover plate 310. The edge ring connecting the cover plate and pedestal, which may all be of conductive material, provides a more symmetrical ground path for the high frequency plasma power supply, which may improve plasma uniformity in some embodiments. RF rods 335 may extend through the platen and connect to the RF match of the low frequency power supply as described above. The pedestal 305 may rest on a hub 340 through which the RF rods 335 may extend. The RF rod 335 may have a rod insulator 345 that extends around the RF rod and may extend with the RF rod through each of the hub 340, the pedestal 305, the cover plate 310, and the puck 320. By extending the rod insulator 345 along the length of the RF rod and through the hub, an RF leakage path to the pedestal may be prevented at the hub.

[0044]

[0053] At the opposite end of the RF rod 335, the RF rod may be connected to an electrode disposed inside the puck 320. A conductive connector 350, such as molybdenum or other conductive material, may connect with the RF rod 335 and the electrode. The connection may be made with any connector type, including a Multilam or other multiple contact connector on the RF rod. An additional puck insulator 355, which may be mounted in a recess defined in the puck, may extend around the conductive connector 350. The RF rod 335 and rod insulator 345 may be at least partially mounted within the puck insulator 355. The puck insulator and rod insulator may operate to completely surround the RF rod 335 through components of the substrate support assembly that extend into the processing chamber, further shortening or limiting leakage paths that may otherwise lead to stray arcing. These components are further described below.

[0045]

[0054] FIG. 4A shows a schematic exploded perspective view of a cover plate 400 according to some embodiments of the present technology. The cover plate 400 may include any of the features, components, or characteristics of the cover plate 310 described above. For example, the cover plate 400 may include a material that defines a first recessed channel 405a extending around the cover plate. The cover plate 400 may also define a second recessed channel 405b, as well as any number of additional recessed channels in some embodiments. The second recessed channel 405b may be radially outward of the first recessed channel. Although shown as annular channels, the channels may be characterized by any shape around the cover plate. An aperture 407 may be formed through each recessed channel extending into the plate to access a side channel, as described below. The recessed channel may be an annular channel defined around the cover plate. The recessed channels 405 may include channel covers 410 placed over the recessed channels to define one or more flow paths from the channels. A channel cover 410a may be disposed over a first recessed channel 405a, and a channel cover 410b may be disposed over a second recessed channel 405b. As shown, each channel cover may define one or more, such as a plurality of apertures 412 extending through the channel cover. The apertures may be spaced around the channel cover to provide access from the recessed channels. The apertures through the channel covers may align with apertures extending vertically through a puck of a substrate support assembly to define fluid channels extending to the backside of a substrate being processed.

[0046]

[0055] The cover plate 400 defines one or more apertures 415 extending therethrough, which may provide access to the lift pin assemblies extending through the plate, as described further below. The cover plate 400 defines a central aperture 420 therethrough, which may allow access to the RF rods and rod insulators, as previously described. The central aperture 420 may define a recessed ledge upon which a purge cover 425 may rest. As described further below, the purge cover 425 may extend through the cover plate and over a purge channel that extends through the cover plate to the central aperture 420. A protrusion on the purge cover may extend over the formed channel. Additional apertures 428 may be formed outside the central aperture to provide fluid access to side channels 430 that extend outwardly through the plate along a radius to access the recessed channel.

[0047]

[0056] 4B shows a schematic partial cross-sectional view of a cover plate 400 according to some embodiments of the present technology. As shown, the cover plate 400 may define recessed channels 405 in which a channel cover 410 may be placed. The channel cover may be characterized by a U-shape or other shape to form a closed channel for fluid flow. Access from the channel may be provided by an aperture 412 defined through the channel cover. The aperture 412 is recessed as shown, which may allow for placement of a porous plug within the recess in some embodiments. As described above, each recessed channel 405 may include an aperture 407 defined through the cover plate, which may extend partially into the cover plate to access a side channel 430 defined within the plate. A single side channel may provide fluid access to both or all of the recessed channels, and in some embodiments, each recessed channel may be accessed by a separate side channel through the plate. A flow of fluid, such as a gas stream of helium, argon, or some other gas, may flow through the cover plate 400 along the side channels 430. The fluid may flow through the apertures 407 into the recessed channels 405 and around the recessed channels. The fluid flow may then extend up through apertures 412 and through the pucks through corresponding apertures to provide access to the backside of the substrate. The gas may facilitate cooling of the substrate from the backside of the substrate, as the fluid may be cooled during delivery through the substrate support assembly.

[0048]

[0057] Thus, by adjusting the flow of fluid through the puck, improved cooling may be provided over conductive cooling from the support assembly alone. For example, by increasing the flow of fluid during and / or after a processing step, the temperature of the substrate may be more easily returned to the deposition set point temperature. By providing multiple recessed channels that provide separate fluid flow paths, different regions may be cooled at different rates to address non-uniform temperature distribution across the substrate. As a result, heat load issues that arise during processing steps may be addressed with the substrate support assembly according to the present technique, improving the uniformity of the deposition process by ensuring a consistent substrate temperature with each deposition cycle.

[0049]

[0058] 5A illustrates a schematic partial cross-sectional view of a substrate support assembly 300 in accordance with some embodiments of the present technique, which may show additional aspects of the lift pin assembly 325 described above, as well as additional features of the support assembly. As illustrated, the substrate support assembly 300 may include a pedestal platen 308. A cover plate 310 rests on the platen, the cover plate defining one or more recessed channels 315, and may include a channel cover 410 disposed within the channel. The substrate support assembly 300 may include a puck 320 and an edge ring 330, as previously described.

[0050]

[0059] The puck 320 may have an electrode 505 built into the puck and configured to operate as a chuck electrode and / or plasma electrode as described above. Additional chuck electrodes may also be included below the plasma generating electrode 505 as described above. The puck 320 defines several protrusions or mesas 515 that may facilitate JR chucking of a substrate surface that may rest on the protrusions. Thus, by resting on an offset, a backside gap may be formed between the puck and the substrate. Thus, as described above, fluid may flow upward through apertures 510 that are defined vertically through the chuck and aligned with apertures through the cover plate channel cover as described above. This may facilitate cooling of the substrate as described above.

[0051]

[0060] The lift pin assembly 325 may extend through the platen 308, cover plate 310, and puck 320 as shown. The lift pin assembly may be configured to limit plasma generation inside the lift pin holes and to limit entrapment of helium that may flow through the puck and into the apertures. As shown, counterbore apertures are formed through the puck with smaller diameter aperture portions extending to the puck surface. The lift pins 520 may be characterized by a reduced diameter at the substrate contact end and positioned just below the access from the apertures through the puck. For example, the lift pins 520 may be recessed about 2 mm or less from the surface of the puck, and may be recessed about 1 mm or less, about 800 μm or less, about 700 μm or less, about 600 μm or less, about 500 μm or less, about 400 μm or less, about 300 μm or less, about 200 μm or less, or less from the surface of the puck.

[0052]

[0061] The liner 525 may fit into an aperture through the puck and rest against an O-ring 527 or other stopper resting against the puck surface to limit contact from the liner during translation of the lift pin. The liner may define an interior path through which the lift pin may extend and may define a stop distance that may be contacted by a ledge defined on the lift pin as shown. The liner may be held in place by a holder 530 that may fit into the platen 308 and define an opposite stop distance for the lift pin as shown. A counterweight 535 may be connected to the end of the lift pin 520 opposite the substrate contacting end and may maintain the lift pin in a concave position during substrate processing. The lift pin assembly is passive during operation and may be actuated by a vertically concave substrate support assembly. The counterweight may be contacted from below when the substrate support is retracted from the operating position and may cause the lift pin to extend upward through the assembly to lift the substrate from the support. Some embodiments of the present technology may include any number of lift pin assemblies.

[0053]

[0062] As mentioned above, helium from the backside cooling may enter the lift pin assembly and become trapped if no purge path is provided. Thus, in some embodiments, a gap space is formed around the end of the liner and lift pin, which allows helium or other cooling fluid to flow into the lift pin assembly. In addition, the holder 530 may be configured to allow the fluid to escape while maintaining the lift pin in place. FIG. 5B shows a schematic diagram of a holder 530 according to some embodiments of the present technology. As shown, the holder 530 defines an aperture 532 through which the lift pin may extend. The radius of at least a portion of the aperture 532 may be sized to ensure that the lift pin ledge may rest on the holder when the lift pin is in the retracted position. In addition, the holder may define an exhaust path 534 around the aperture that extends from the liner and allows the cooling fluid to escape from the lift pin assembly. In this manner, trapped gas may not build up pressure or ignite during processing steps.

[0054]

[0063] 6A shows a schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technique, and may show additional features of a purge path extending through the assembly. The processing region of the chamber may be maintained at vacuum pressure, while the internal components within the pedestal shaft may be maintained near atmospheric pressure. During low temperature operation, condensation may occur within these regions, which may lead to arcing at the RF rods or other corrosion within the substrate support assembly. Therefore, in some embodiments, additional purge paths may be formed that extend around the RF rods and associated components to ensure that condensation within the system is limited or prevented.

[0055]

[0064] As shown, the purge path 605 may extend through the pedestal shaft and platen 308 and connect with the cover plate 310. The purge path 605 may then extend laterally into the central region where the RF rod extends through the shaft. As mentioned above, the purge cover 425 may rest on the passage to direct the flow into the central aperture. In some embodiments, a gap may be formed between the RF rod insulator 345 and other components in the pack 320, including the puck insulator 355 and the conductive connector 350. As shown, when the purge flow, which may be nitrogen or other material, strikes the rod insulator 345, the flow may branch vertically up and down, as well as to the periphery of the rod insulator. The purge path may extend down along the exterior of the rod insulator and up between the rod insulator and the puck insulator 355. The flow may then extend down along the interior surface of the rod insulator, such as between the rod insulator and the conductive connector, as well as between the rod insulator and the RF rod. This ensures that air is purged from the substrate support assembly to protect against condensation.

[0056]

[0065] FIG. 6B shows a schematic partial cross-sectional view of a rod insulator 345 according to some embodiments of the present technology. As shown, the rod insulator 345 may define a ledge 610 along the inner surface to reduce the inner diameter from the end that may extend around the conductive connector as described above. The diameter may then be reduced as the rod insulator extends along the length of the RF rod through the pedestal. Additionally, the rod insulator 345 may define one or more recesses 615 at the end of the rod insulator where it may abut the puck insulator. The recesses 615 may ensure that purge gas extends from the outside to the inside of the rod insulator to purge along the RF rod. Access may be formed in the recessed area inside the puck insulator so that RF leakage may be controlled or prevented.

[0057]

[0066] The processing chamber 100 and / or the processing chamber 200 may be utilized in some embodiments of the present technology for processing methods that may include forming, etching, or curing materials for semiconductor structures. The chambers may include any of the substrate support assembly components or features described above. It should be understood that the described chambers should not be considered limiting and any chamber that may be configured to perform the operations as described may be used as well. FIG. 7 illustrates exemplary steps in a processing method 700 according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 100 or the processing chamber 200 described above, and in one or more mainframes or tools. The method 700 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader scope of structure formation, but are not critical to the present technology or may be performed by alternative methodologies that will be readily understood.

[0058]

[0067] Method 700 may include additional steps prior to the initiation of the recited steps. For example, the additional processing steps may include forming structures on the semiconductor substrate, which may include both the formation and removal of materials. For example, transistor structures, memory structures, or any other structures may be formed. The prior processing steps may be performed in the chamber in which method 700 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to one or more semiconductor processing chambers in which method 700 may be performed. Nevertheless, method 700 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or to another chamber that may include components as described above. The substrate is deposited on a substrate support, which may be a pedestal, such as substrate support 210, which may be or include substrate support assembly 300, and which may be present in a processing region of a chamber, such as processing space 120 described above.

[0059]

[0068] The substrate being processed may be or include any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials, and may be a substrate or a material formed on a substrate. The features may be characterized by any shape or configuration according to the present technology. In some embodiments, the features may be or include trench structures or openings formed within the substrate. The features may be characterized by any shape or size, but in some embodiments, the features may be characterized by a higher aspect ratio, or the ratio of the depth of the feature to the width across the feature. For example, in some embodiments, the features may be characterized by an aspect ratio of about 5:1 or greater, and may be characterized by an aspect ratio of about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or greater. Additionally, the feature may be characterized by a narrow width or diameter across the feature, including between two sidewalls, such as a dimension of about 20 nm or less, and may be characterized by a width across the feature of about 15 nm or less, about 12 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, less than about 5 nm or less, or less.

[0060]

[0069] In some embodiments, method 700 may include optional processing steps, such as pre-treatment, that may be performed to prepare the surface of the substrate for deposition. Once prepared, method 700 may include supplying one or more precursors to a processing region of a semiconductor processing chamber housing the structure. The precursors may include one or more silicon-containing precursors, as well as one or more diluents or carrier gases, such as inert gases or other gases, that are supplied with the silicon-containing precursors. Although the method is described in the context of producing flowable silicon films, it should be understood that the described method and / or chamber may be used to produce any number of materials in accordance with embodiments of the present technology. At step 705, a plasma may be formed from the deposition precursors, including the silicon-containing precursors. The plasma may be formed in the processing region, which may allow a deposited material to be deposited on the substrate. For example, in some embodiments, a capacitively coupled plasma may be formed in the processing region by applying plasma power to a face plate as described above. For example, the radio frequency power source described above may be operated at a reduced effective plasma power to deposit material within features on the substrate.

[0061]

[0070] At step 710, a silicon-containing material may be deposited on the substrate from the plasma effluent of the silicon-containing precursor. The material, in some embodiments, is a flowable silicon-containing material and may be or include amorphous silicon. The deposited material may at least partially flow into a feature on the substrate to provide bottom-up gap filling. As shown, the deposited material may flow to the bottom of the feature, although an amount of material may remain on the sidewalls of the substrate. Although the amount deposited may be relatively small, the material remaining on the sidewalls may limit subsequent flow.

[0062]

[0071] The power applied during deposition may be a low power plasma to limit dissociation and maintain hydrogen incorporation into the deposited material. This incorporation of hydrogen may contribute to the flowability of the deposited material. Thus, in some embodiments, the plasma power source may provide a plasma power of about 100 W or less to the faceplate, and may provide a power of about 90 W or less, about 80 W or less, about 70 W or less, about 60 W or less, about 50 W or less, or less. This power may be further attenuated by operating the high frequency power source at a pulse frequency and duty cycle as previously described to produce an effective power of about 10 W or less, or about 5 W or less, as described above.

[0063]

[0072] Following the deposition amount, in some embodiments of the present technology, a treatment or curing process configured to densify the formed material may be formed, advantageously cleaning or etching back the material on the sidewalls of the feature. This process may be performed in the same chamber as the deposition and may be performed in a cyclic process to fill the feature. In some embodiments, the flow of the silicon-containing precursor may be stopped and the processing region may be purged. Following the purge, a processing precursor may be flowed into the processing region of the processing chamber. The processing precursor may be or may include hydrogen, helium, argon, or another inert material that may not chemically react with the film. In step 715, a processing plasma may be formed, which may also be a capacitively coupled plasma formed inside the processing region. The deposition plasma may be formed by applying a high frequency plasma power to a faceplate or showerhead, but in some embodiments may not include a separate power source engaged. The processing may utilize both a high frequency power source and a low frequency power source connected to the substrate support as described above. During processing, the high frequency power source may operate at a first power level and the low frequency power source may operate at a second power level. In embodiments of the present technology, the two power levels may be similar or different.

[0064]

[0073] The high frequency power source may be operated at a pulsed low effective power during deposition plasma, but in a continuous wave configuration during processing. This may be done at any of the plasma powers previously described. The low frequency power source may be operated in a pulsed mode during processing. This may be done at any of the pulse frequencies and / or duty cycles previously described.

[0065]

[0074] During the deposition steps, the low frequency power supply may not be operated. As described above, to allow repeatable plasma generation at low power, a trigger sequence may be utilized to ensure plasma generation during each deposition step. The trigger sequence may include a first period and a second period, which together form a deposition period. In some embodiments, to limit deposition, the deposition period may be about 30 seconds or less, about 20 seconds or less, about 15 seconds or less, about 10 seconds or less, about 8 seconds or less, about 6 seconds or less, about 5 seconds or less, about 4 seconds or less, or less. The first period may be shorter than the second period, and the first period may be used to ensure plasma generation while limiting the impact on the deposition process. Thus, in some embodiments, the first period of time is about 2 seconds or less, and can be about 1 second or less, about 0.5 seconds or less, about 0.4 seconds or less, about 0.3 seconds or less, about 0.2 seconds or less, about 0.1 seconds or less, about 0.09 seconds or less, about 0.08 seconds or less, about 0.07 seconds or less, about 0.06 seconds or less, about 0.05 seconds or less, or less.

[0066]

[0075] In some embodiments, a first power is applied by the high frequency power source during a first period, which can be higher than a second power applied by the high frequency power source during a second period. For example, during the first period, the first power can be about 50 W or more, about 80 W or more, about 100 W or more, about 120 W or more, about 140 W, about 160 W or more, about 180 W or more, about 200 W or more, or more. The high frequency power source can then apply power during a second period at any of the above-mentioned effective powers for the remainder of the deposition time. In addition, the high frequency power source can operate consistently during the deposition time, but during the first period, a low frequency power source can be applied at any of the power levels above to ensure ignition. In another example, the high frequency power source can operate in a multi-level pulse configuration during the first period before switching to the desired effective power during the second period. A multi-level pulse may include several pulses, each of which may be less than 0.1 seconds, and may occur during a first period of time, such as, for example, about 50 microseconds or less, about 40 microseconds or less, about 30 microseconds or less, about 20 microseconds or less, or less. The pulse may include a first pulse that is higher in a first fraction of the pulse, followed by a second pulse that is lower in a second fraction of the pulse. The two portions of the pulse may occur at any of the power levels discussed above.

[0067]

[0076] During processing, the substrate support assembly may be used to maintain the temperature of the substrate at step 720, and temperature control may continue prior to a subsequent deposition step. For example, in addition to conductive cooling through the substrate support assembly, in some embodiments, a backside gas may be supplied and adjusted to further control the substrate temperature during high power processing operations. Simultaneously, or in addition, the more directionally supplied plasma effluents may penetrate the remaining film formed at the bottom of the feature, reducing hydrogen uptake to densify the film at step 725. Following processing, the backside gas may continue to flow to reduce the temperature to the deposition set point prior to the subsequent deposition cycle.

[0068]

[0077] Although the deposits can be formed to a few nanometers or more, by performing the etching process as described above, the thickness of the densified material can be controlled to a thickness of about 100 Å or less, and can be about 90 Å or less, about 80 Å or less, about 70 Å or less, about 60 Å or less, about 50 Å or less, about 40 Å or less, about 30 Å or less, about 20 Å or less, about 10 Å or less, or less. By controlling the thickness of the deposited material, conversion through the entire thickness can be more easily performed and can solve penetration issues common to conventional processes. This process can then be repeated in any number of complete cycles to continue to generate densified material down to the feature.

[0069]

[0078] With regard to the deposition precursors used during any of the formation steps, any number of precursors may be used in the present technology. Silicon-containing precursors that may be used may include, but are not limited to, silane (SiH4), disilane (Si2H6), or other organosilanes, including cyclohexasilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and other silicon-containing precursors that may be used for silicon-containing film formation. Silicon-containing materials may be nitrogen-free, oxygen-free, and / or carbon-free in some embodiments. One or more additional precursors may be included in any of the steps, such as inert precursors that may include Ar, diatomic hydrogen, He, or other materials such as nitrogen, ammonia, or other precursors.

[0070]

[0079] Temperature and pressure can also affect the operation of the technique. For example, in some embodiments, the process is performed at a temperature of about 20° C. or less to facilitate film flow, and may be performed at a temperature of about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, about −30° C. or less, or less. The temperature may be maintained in any of these ranges throughout the method, including during processing and densification. The pressure inside the chamber is kept relatively low, such as a chamber pressure of about 10 Torr or less, for any of the processes, and the pressure may be maintained at about 8 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. Additionally, in some embodiments, the pressure may be maintained at different levels during deposition and processing. For example, the pressure can be maintained at about 1 Torr or more (such as about 2 Torr or more, about 3 Torr or more, or more) during deposition, and the pressure can be maintained at about 1 Torr or less (such as about 0.8 Torr or less, about 0.5 Torr or less, about 0.1 Torr or less, or less) during deposition. By performing processes according to some embodiments of the present technique, improved filling of narrow features utilizing silicon-containing or other flowable materials can be produced while ensuring adequate temperature control of the substrate within a single processing chamber.

[0071]

[0080] In the preceding description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0072]

[0081] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be interpreted as limiting the scope of the present technology. Furthermore, although a method or process may be described sequentially or stepwise, it should be understood that the steps may be performed simultaneously or in a different order than that listed.

[0073]

[0082] Where a range of values ​​is given, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any smaller ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included or excluded from the range. Each range in which either or both limits are included in the narrower range, or neither is included in the narrower range, is also encompassed by this technology and covers any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0074]

[0083] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0075]

[0084] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. a pedestal having a shaft and a platen; A cover plate, a cover plate connected to the platen along a first surface of the cover plate; defining a recessed channel in a second surface of the cover plate opposite the first surface; defining at least one side channel disposed at a depth within the cover plate between a bottom surface of the recessed channel and the first surface; and a cover plate defining a plurality of apertures fluidly connecting the at least one side channel with separate portions of the recessed channel; a puck connected to the second surface of the cover plate, the puck incorporating electrodes and defining a plurality of apertures extending vertically through the puck for fluid access to the recessed channel defined in the cover plate; A semiconductor substrate support comprising:

2. The semiconductor substrate support of claim 1 , wherein the platen defines a fluid channel across the platen.

3. 2. The semiconductor substrate support of claim 1, wherein the recessed channel is a first recessed channel and the cover plate defines a second recessed channel radially outward of the first recessed channel, the first recessed channel being fluidly accessed from a first side channel defined in the cover plate and the second recessed channel being fluidly accessed from a second side channel defined in the cover plate.

4. a first channel cover disposed on the first recessed channel, the first channel cover defining a plurality of apertures therethrough; 4. The semiconductor substrate support of claim 3, further comprising: each aperture of the plurality of apertures through the first channel cover aligned with a corresponding aperture of the plurality of apertures extending vertically through the puck.

5. A lift pin assembly extending through the platen, the cover plate, and the puck. the lift pin assembly further comprising: A lift pin; Raina and A holder and Counterweight and The semiconductor substrate support of claim 1 , comprising:

6. The semiconductor substrate support of claim 5 , wherein an exhaust path is defined around the liner and through the holder.

7. an RF rod extending through the shaft of the pedestal and electrically connected to the electrode by a conductive connector disposed within the puck; The semiconductor substrate support of claim 1 further comprising:

8. A rod insulator extending around the RF rod along the length of the RF rod. The semiconductor substrate support of claim 7 further comprising:

9. The semiconductor substrate support of claim 8 , wherein the pedestal is mounted within a hub and the rod insulator extends through the hub.

10. a pack insulator extending around the conductive connector within the pack 9. The semiconductor substrate support of claim 8, further comprising: said rod insulator being at least partially mounted within said puck insulator.

11. The semiconductor substrate support of claim 10 , wherein the pedestal and the cover plate define a purge path that extends in the cover plate to the rod insulator.

12. The semiconductor substrate support of claim 11 , wherein the purge path runs along the interior and exterior of the rod insulator.

13. A chamber body; A substrate support configured to support a semiconductor substrate, comprising: a pedestal having a shaft and a platen; A cover plate, a cover plate connected to the platen along a first surface of the cover plate; defining a recessed channel in a second surface of the cover plate opposite the first surface; defining at least one side channel disposed at a depth within the cover plate between a bottom surface of the recessed channel and the first surface; and a cover plate defining a plurality of apertures fluidly connecting the at least one side channel with separate portions of the recessed channel; a puck connected to the second surface of the cover plate, the puck incorporating electrodes and defining a plurality of apertures extending vertically through the puck for fluid access to the recessed channel defined in the cover plate; a substrate support comprising: a faceplate, wherein the chamber body, the substrate support, and the faceplate define a processing region; and a radio frequency plasma source connected to the face plate; a low frequency plasma source connected to the substrate support; A semiconductor processing system comprising:

14. the substrate support comprises an electrostatic chuck, and the semiconductor processing system comprises: A DC power supply connected to the substrate support. The semiconductor processing system of claim 13 further comprising:

15. 14. The semiconductor processing system of claim 13, wherein the low frequency plasma source is configured to operate at about 2 MHz or less and the high frequency plasma source is configured to operate at about 13.56 MHz or greater, with a pulse frequency of about 20 kHz or less, at a duty cycle of about 20% or less.

16. 16. The semiconductor processing system of claim 15, wherein the radio frequency plasma source is configured to generate a plasma with an effective power of about 5 W or less.

17. 14. The semiconductor processing system of claim 13, wherein the recessed channel is a first recessed channel and the cover plate defines a second recessed channel radially outward of the first recessed channel, the first recessed channel being fluidly accessed from a first side channel defined in the cover plate and the second recessed channel being fluidly accessed from a second side channel defined in the cover plate.

18. a first channel cover disposed on the first recessed channel, the first channel cover defining a plurality of apertures therethrough; 20. The semiconductor processing system of claim 17, further comprising: wherein each aperture of the plurality of apertures through the first channel cover is aligned with a corresponding aperture of the plurality of apertures extending vertically through the puck.

19. a first LC filter connected to the substrate support and configured to substantially ground the high frequency plasma source through the substrate support; The semiconductor processing system of claim 13 further comprising:

20. a second LC filter connected to the faceplate and configured to substantially ground the low frequency plasma source to the chamber body; 20. The semiconductor processing system of claim 19 further comprising:

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