Time-interleaved digital-to-analog converter system and time-interleaved digital-to-analog converter calibration method

Abstract

To reduce linear and non-linear distortions and mismatches between the channels of a TI DAC system.SOLUTION: A time-interleaved DAC system 100 includes a digital pre-distortion unit 104 configured to receive an input digital signal 102 and an error signal 122 and output a distorted digital signal. A time-interleaved DAC 108 has a first sample rate and is configured to convert the distorted digital signal to an analog signal 112. A calibration system includes an ADC 114 having a second sample rate equal to or lower than the first sample rate. The ADC 114 is configured to receive the analog signal 112 and covert the analog signal to a down-sampled digital signal. A discrete time linear model unit 106 is configured to receive the input digital signal 102 and the error signal 122 and output a model signal. A combiner 120 is configured to subtract the down-sampled digital signal from the model signal to generate the error signal 122.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to systems and methods for Time Interleaved (TI) Digital-to-Analog Converters (DACs), and more particularly to systems and methods for calibrating pre-processing digital signal processing (DSP) filters for TI DACs. [Background technology]

[0002] DACs are used to convert digital signals to analog signals. However, the bandwidth of a DAC may be limited by the analog bandwidth or sample rate of the DAC. To obtain a higher effective DAC sample rate, a TI DAC system with multiple time-interleaved DAC channels may be used instead of a single DAC. Each DAC channel receives an input signal and outputs an analog signal that is offset in time within one DAC sampling period. By adding or multiplexing these analog signals together, the sampling rate of the entire DAC system can be effectively increased by several times. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6258573 [Patent Document 2] U.S. Pat. No. 7,474,972 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the TI DAC system may suffer from linear and nonlinear distortions and mismatches between different channels of the TI DAC system, and the resulting analog output signal may not be accurate.

[0005] Embodiments of the present invention address these and other deficiencies of the prior art. [Means for solving the problem]

[0006] An embodiment of the present invention includes background or foreground calibration for the correction of linear and nonlinear distortions in a Time Interleaved (TI) Digital-to-Analog Converter (DAC). As described in more detail below, the correction is performed through digital pre-distortion (DPD) of the TI DAC's input data using background or foreground calibration. That is, the calibration may be performed in the foreground using a known signal, or in the background during normal operation of the TI DAC. The output signal of the TI DAC is captured by an Analog-to-Digital Converter (ADC) and compared to the appropriately processed DAC's input signal to form an error signal, which is used for least mean squares (LMS) adaptation of the DPD coefficients.

[0007] BRIEF DESCRIPTION OF THE DRAWINGS Aspects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a time-interleaved digital-to-analog converter system according to some embodiments of the present invention. [Diagram 2] FIG. 2 is a block diagram of an example of the digital pre-distortion unit of FIG. [Diagram 3] FIG. 3 is a block diagram of an example of a delay line with second order products of FIG. [Figure 4] FIG. 4 is a block diagram of another example delay line having second order products of FIG. [Diagram 5]FIG. 5 is a block diagram of an example of the multiplication adaptive processing block of FIG. [Figure 6] FIG. 6 is a block diagram of an example of the coefficient adaptation processing block of FIG. [Figure 7] FIG. 7 is a block diagram of an example of the multiplication processing block of FIG. [Figure 8] FIG. 8 is a block diagram of an alternative multiplicative adaptive processing block of FIG. [Figure 9] FIG. 9 is a block diagram of an example of the MIMO coefficient adaptation processing block of FIG. [Figure 10] FIG. 10 is a block diagram of an example of the MIMO block of FIG. [Figure 11] FIG. 11 is a block diagram of an example of a discrete-time linear model of the DAC and ADC of FIG. [Figure 12] FIG. 12 is a block diagram of another time-interleaved digital-to-analog converter system according to some embodiments of the present invention. [Figure 13] FIG. 13 is a block diagram of another time-interleaved digital-to-analog converter system according to some embodiments of the present invention. [Figure 14] FIG. 14 is a block diagram of a test and measurement instrument in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] FIG. 1 illustrates an example of a TI DAC system 100 according to some embodiments of the present invention. A digital input signal 102, denoted as x, is received at the input and sent to a DPD unit 104 and a discrete time (DT) linear model unit 106 of DAC and ADC (referred to herein as DT linear model unit 106). The digital input signal processed by the DPD unit 104 is sent to M parallel TI DAC channels 109 (with index m=1,...,M, where M is an integer equal to or greater than 1) of a TI DAC 108. The output signals of each of the DAC channels 109 are summed together by a summer 110 or, instead of the summer 110, are sequentially selected by a multiplexer and output as one analog signal 112. If the TI DAC system 100 is used as part of a test and measurement instrument, the analog signal 112 may be output to a device under test via a port of the test and measurement instrument. The analog signal 112 is also sent to an ADC 114 , which is used to calibrate the DPD unit 104 .

[0010] The sampling rate of the ADC 114 is L times lower compared to the rate of the TI DAC 108, which is shown as the downsampler 116 in Figure 1. The bandwidth of the ADC 114 is matched to the bandwidth of the TI DAC 108 to capture the entire spectrum of the output signal. The same result can also be achieved by using a presampler component in front of a narrower bandwidth ADC. The downsampling rate L is chosen to be relatively prime to M, so that all phases of the TI samples are covered by the error waveform and the resulting adaptation process. That is, L and M have no common factor other than 1.

[0011] The output signal of the DT Linear Model unit 106 is downsampled by a factor L by a downsampler 118. The output signal of the ADC 114 is then subtracted from the output signal of the downsampler 118 by a combiner 120 to generate an error signal 122. The error signal 122 is sent to both the DT Model unit 106 and the DPD 104, which will be described in more detail below.

[0012] Having described the system in general, Figures 2-11 describe the individual components of system 100. Figure 2 illustrates an example of a DPD 104 in accordance with some embodiments of the present invention. The DPD 104 receives a digital signal 102 and routes the digital signal to a number of delay lines. P delay lines are provided, where P is greater than 1. For example, in Figure 2, a first order delay line 200, a second order delay line 202, and a Pth order delay line 204 are shown.

[0013] Each of the delay lines 200, 202, and 204 has a different order of multiplication and uses memory to generate the different orders of nonlinearity. The delay lines 200, 202, and 204 are multiplicative adaptive (MULTwA) processes. Mult iplication w ith A2. The delay lines 200 are used in combination with a multiplication and adaptation block 208 to compensate for nonlinearities of corresponding orders and time-interleaved linear and nonlinear mismatches between the TI DAC channels 109. A first-order delay line 200 is shown in FIG. 2. Each of the delay blocks 206 represents a delay of one clock cycle of the input data of the TI DAC 108. The delay line 202 with second-order product block and the delay line 204 with P-th order product block each consist of a plurality of delay lines and exactly two or P terms of products of delay line components, each of which is derived by a constant summation or multiplication operation. The output signal of each delay line 200, 202 and 204 is sent to a multiplication and adaptation block 208. The error signal 122 is also applied to the multiplication and adaptation block 208. The output signals of each multiplication adaptive processing block 208 are summed together by a combiner 210 and output as a signal y that is sent to the TI DAC 108 .

[0014] 3 and 4 show a second order delay line 20 2 This shows a possible example of a P-th order delay line 20 4 The delay line can also be modified to use the Pth order. If all possible output signals of multiple delay lines are used to form all possible Pth order products, a Pth order Volterra model is derived. However, the full Volterra model may be too complex to realize, so simplified versions, such as those shown in Figures 3 and 4, may be used. Suitable simplified nonlinear models using storage devices can be derived through analysis of specific TI DAC108 models and their simulations. These models do not need to be exact, as they are augmented with adaptive coefficients that compensate for the actual nonlinearities of the TI DAC108.

[0015] 5 is a block diagram of an example of the multiplication adaptive processing block 208. The demultiplexer 500 receives the signal u from one of the delay lines 200, 202, and 204, and demultiplexes the M continuous scalar data u input to the block 208 at a rate equal to the rate of the TI DAC 108 into a vector um where m is an integer value from 1 to M. The data vector u m is delayed by delay block 502 to match the delay introduced by the TI DAC 108 and ADC 114 circuitry in the combiner 120. This delayed data vector v m is further downsampled by a factor L by a downsampler 504 to match the undersampled ADC 114. The output signal of the downsampler 504 is sent to a coefficient adaptation processing block 506. The error signal 122 is also received by a demultiplexer 508, which divides the error signal into a vector e m where m is an integer value from 1 to M, which is then passed to coefficient adaptation block 506, which performs LMS adaptation on a single TI DAC channel 109 to obtain vector t m Output the vector t m is multiplied by the vector u m is multiplied to give the combined vector w m The multiplexer 512 outputs the combined vector w m The m data are converted into scalar data w, which is output to the combiner 210.

[0016] As mentioned above, the coefficient adaptation processing block 506 performs the LMS adaptation processing, which is shown for one of the TI DAC channels 109 in Figure 6. The LMS operation can also be described by the following equation (1):

[0017] t m (Ln)=t m (Ln-L)+μv m (Ln)e m (Ln) (1)

[0018] Here, t m (Ln) is the updated coefficient value at the Lnth clock cycle for a single TI DAC channel 109 sample period, while t m(Ln-L) is the value before decimation in L clock cycles. m (Ln) and e m (Ln) are the mth components of data and error, respectively, at the nLth clock cycle coincidentally. The constant μ is the adaptation constant of the LMS algorithm. Although the standard LMS operation is shown in Figure 6, other types of LMS algorithms may also be used, such as normalized LMS, LMS with a time-varying adaptation step, leaky LMS, etc.

[0019] FIG. 7 shows the vector t m and the input data vector u m In some embodiments, such as that shown in FIG. 7, multiplier 510 multiplies input data vector u by point-wise multiplication. m Then, the coefficient t m In the example of Figure 7, M is equal to 4. This point-by-point multiplication can also be explained by the following equation (2):

[0020] w m (n)=t m u m (n), m=1,2,…,M (2)

[0021] 8 is a block diagram illustrating an alternative multiplicative adaptive processing block 800 that may be implemented in some embodiments. This circuit may be used in place of multiplicative adaptive processing block 208 of FIG. 2. Similar to multiplicative adaptive processing block 208, a demultiplexer 802 receives a signal u from one of delay lines 200, 202, and 204 and demultiplexes M continuous scalar data u input to block 800 at a rate equal to the rate of the TI DAC 108 into a vector u m where m is an integer value from 1 to M. The data vector u mis delayed by delay block 804 to match the delay introduced by the DAC and ADC circuits in combiner 120. This delayed data vector v m is fed to a MIMO (multiple input multiple output) coefficient adaptation processing block 806, an example of which is shown in FIG. 9. The MIMO coefficient adaptation processing block 806 further k which is output by the demultiplexer 808 based on the received error signal 122, where k is an integer value from 1 to M. Each coefficient of the MIMO coefficient adaptation processing block 806 may be determined by implementing a standard LMS algorithm, which can be described by equation (3).

[0022] t (s) km (Ln)=t (s) km (Ln-L)+μv m (Ln-s+1)e k (Ln), k,m=1,…,M;s=1,…,S (3)

[0023] As with the coefficient adaptation processing block 208, other LMS algorithms may also be used.

[0024] The output signal t (s) km are fed to a MIMO block 810, which is shown in FIG. 10 for the situation where M is equal to 2. The MIMO block 810 has M inputs and M outputs, 2 The input / output relationship of the MIMO block 810 is given by the following equation (4).

[0025]

number

[0026] Here, um (n) is the mth input data, and t km is the input u m is a vector of S coefficients of the FIR of , whose output is connected to the k-th output terminal of the MIMO block 810 structure. Similar to multiplexer 512, multiplexer 812 also receives the combined vector w k is converted into scalar data W and output to the combiner 210.

[0027] Since the MIMO block 810 includes storage (memory) for the delay lines of M FIR filters, if the multiplicative adaptive processing block 208 is replaced by the alternative multiplicative adaptive processing block 800, some of the lines connecting the delay lines 200, 202 and 204 to the multiplicative adaptive processing block 208 become redundant.

[0028] As described above, the TI DAC system 100 can compensate for TI DAC linear and nonlinear mismatches so that the output signal of the TI DAC system 100 looks like a linear time invariant (LTI) system. To do this, the output signal of the actual TI DAC may be compared to the output signal of a desired LTI system that models the behavior of an ideal TI DAC. The structure of the DT linear model unit 106 is shown in FIG. 11. The DT linear model unit 106 handles the linear aspects of both the TI DAC 108 and the ADC 114 that are not intended to be modified in the DPD unit 104.

[0029] As seen in FIG. 11, the DT Linear Model unit 106 has an FIR filter with LMS adaptation function that is composed of the coefficients of the FIR filter. The adaptation process of the DT Linear Model unit 106 allows it to track the changes in the linear part of the TI DAC channel 108 and the ADC 114. However, at least one tap of the FIR filter is made non-adaptive and fixed to a constant value to avoid a situation where all the coefficients of the DPD unit 104 are concentrated to zero values. Although FIG. 11 shows a conventional direct form FIR filter embodiment for the DT Linear Model unit 106, other known structures such as transposed, cascade, fast FIR, lattice FIR, frequency domain, etc. may be used. Similarly, as mentioned above, the LMS operation can be implemented in various ways.

[0030] In some embodiments, the above calibration may be performed in the background while the TI DAC system 100 is generating the desired output signal. However, depending on the type of input signal, there may be a linear dependency between the components of this error signal 122 for the error waveform resulting from the input signal used in the adaptive processing block, due to the ability of the correction structure of the DPD unit 104 to handle various impairment types, which may result in multiple states of the adaptive coefficients to achieve the same LMS optimization for that particular input signal 102. Since these adaptive processing states are not equal, if the characteristics of the input signal 102 change, the multiple adaptive processing states may result in large errors until the TI DAC system 100 responds to the new input signal and converges to the appropriate coefficients for the new input signal. A simple example of this is a constant non-zero input signal 102, where mismatch between the outputs of the TI DAC channels 109 can be corrected with DC offset, gain and non-linear terms for each of the DAC channels 109.

[0031] For static coefficient contributions, i.e., memoryless components of the DPD unit 104, the key to good convergence in background calibration using parallel LMS adaptation functions to determine multiple coefficients is to have sufficient diversity in the amplitude values ​​of the input waveform (e.g., a sufficient number of distinct amplitude values) after taking into account down-sampling by the under-sampled ADC 114.

[0032] Regarding the dynamic coefficients, i.e., frequency dependent components included in the delay line of the DPD unit 104 structure, after taking into account the down-sampling by the undersampled ADC 114, in addition to having sufficient diversity in the amplitude values ​​of the input waveform, it is also important for good convergence of the background calibration, which uses parallel LMS adaptation functions to determine multiple coefficients, that the spectral content of the input signal has sufficient diversity (i.e., a sufficient number of separate frequency domain components in the spectrum).

[0033] Mathematically, the criterion for good convergence in the background calibration involves being able to solve the simultaneous equations for the various impairments modeled in the DPD unit 104 across multiple TI DAC channel 109 input samples and ADC 114 output samples for all unknown coefficient values ​​such that the LMS solution minimizes the residual error between the estimated overall waveform as determined based on the input waveform and DPD unit coefficient values ​​and the actual impairments in the waveform captured by the undersampled ADC 114.

[0034] Consider the following equation (5).

[0035]

number

[0036] where ê is a vector for the estimated total residual error waveform after considering the effect of the current DPD unit 104 correction coefficients, which is the sum of the errors due to each impairment type in the output signal of the undersampled ADC 114 for each cycle. The variable U is the impairment matrix of the input waveform before scaling by the parallel multiplicative adaptive processing units 204, with the base impairment values ​​in the row dimension as input to the multiplicative adaptive processing units 204, and successive sample values ​​(which are downsampled to match the undersampled ADC 114) in the column dimension. The variable c is a residual coefficient vector that can be added to the current DPD coefficient vector to scale the magnitude of the impairment values ​​in the multiplicative adaptive processing units 204 to counteract the DAC channel 108 impairments, i.e., minimize the residual error.

[0037] This system of equations will generally be over-stated, so it is good to find a least-squares solution that minimizes the following equation:

[0038]

number

[0039] where e = the residual error vector of the waveform measured following the undersampled ADC output signal.

[0040] The least squares solution is given by the following equation (6).

[0041] c=-(U T U) -1 U T e (6)

[0042] This solution is U T If the U matrix is ​​not a singular matrix, i.e., |U T This is obtained under the condition that U|≠0.

[0043] The parallel LMS adaptation process that occurs at each cycle of the background calibration must converge to the solution of the above simultaneous equations for successive values ​​of U T Background calibration works well if the U matrix is ​​not singular or close to being singular. When an input waveform with good amplitude and spectral content diversity is applied to the TI DAC 108, the corresponding U T U will likely not be a singular or close to singular matrix.

[0044] If the corresponding U T If U is singular or close to being singular and an input signal is applied to TI DAC system 100, background calibration of the DPD coefficients may be stopped to prevent the state of the coefficients from straying from an appropriate model of hardware errors, and foreground calibration may be recommended when the input signal for TI DAC system 100 is chosen to allow particularly fast and accurate convergence of the DPD coefficients.

[0045] In some embodiments, the |U T A real-time digital signal processor (DSP) may be added to analyze the waveform data in the TI DAC system 100 before any correction is applied by the DPD unit 104 to estimate |U. The DSP can determine whether background adaptation should be allowed during that time span. The DSP can then perform background calibration for the TI DAC system 100 and estimate the corresponding |U T Disable for time spans where U| is close to zero, and T It can be enabled for time spans where |U| is not too close to zero. That is, an arbitrary threshold can be defined for the system, and if the corresponding |U TIf U| is greater than this threshold, background calibration is enabled and if the corresponding |U T If U| is less than this threshold, background calibration is disabled.

[0046] In an alternative embodiment, if the input waveform 102, x[n], is predetermined, for example by loading a known waveform into a pattern memory, then |U T In addition to pre-calculating the value of U|, a flag can be generated and stored in memory with the pre-calculated waveform that enables background calibration for periods of the input waveform where the DPD coefficients are likely to converge well and disables background calibration for periods of the input waveform where the DPD coefficients may not converge well.

[0047] As an alternative to the real-time calibration by the LMS described above, in some embodiments background and foreground calibration may be performed at a later time, offline, by capturing and processing packets of data.

[0048] To do so, a DT equivalent linear model of the DAC and ADC is estimated. This estimation may be performed using a low amplitude input waveform to minimize interference from the nonlinear portion of the channel 108. The data captured at the output of the ADC 114 may be collected into a row vector d. From the DPD input data x, an N / L×P matrix X (where N is the length of the TI DAC 108 input data pattern and P is the number of taps of the linear model) can be formed, where the p-th column of the matrix X contains p-1 zeros concatenated with the first N-p+1 data, followed by decimation by a factor L. Thus, the coefficients of the linear model FIR are obtained using the following equation (7):

[0049] c = (dX)(X'X) -1 (7)

[0050] Here, the name X' is used for the transpose of matrix X.

[0051] Once the linear model FIR coefficients c are estimated from equation (7), new TI DAC 108 data with full-scale amplitude may be captured and processed by the ADC 114. Using the same designation d (row vector) for the data packets captured at the output of the ADC 114, and the designations x, u (row vectors) for the data packets at the inputs of the DPD unit 104 and the MIMO block 810, the MIMO coefficients t (M×T matrix) can be obtained as follows:

[0052] The error vector is first convolved with the input data and the linear model filter coefficients, as shown in equation (8). mistake It can be calculated by

[0053] q = conv(x, c) (8)

[0054] Second, convolution Mino Down-sample the output by a factor L and subtract the data captured at the output of the ADC114.

[0055] e=downs(q,L)-d (9)

[0056] Then, a matrix B with T (M times S) columns and N / L rows (N is the data packet length) can be formed, where the t-th column contains t+1 zeros concatenated with the first N-t+1 data in the vector u at the input of the MIMO block 800, and is subsequently decimated by a factor L. The m-th phase of the vector e decimated by a factor M is e, as shown in equation (10). (m) It is specified by.

[0057] e (m) (k)=e(m+(k-1)M), k=1,2,…,N / M;m=1,…,M (10)

[0058] Similarly, B (m) may be a decimated matrix according to equation (11).

[0059] B (m)(k,:)=B(m+(k-1)M,:), k=1,2,…,N / M;m=1,…,M (11)

[0060] Therefore, equation (12) is obtained.

[0061] t (m) =(e (m) B (m) )(B (m) 'B (m) ) -1 (12)

[0062] where t (m) is a row vector with T (M times S) coefficients. Finally, the coefficients of the MIMO block 810 can be derived as shown in equation (13).

[0063] t (s) km =t m (k+(s-1)M), m,k=1,…,M;s=1,2,…,S (13)

[0064] FIG. 12 illustrates an alternative TI DAC system 1200 according to some embodiments of the present invention. Components similar to those of the TI DAC system 100 are given the same reference numerals and will not be described in further detail with respect to FIG. 12. In the TI DAC system 1200 of FIG. 12, a tunable radio frequency (RF) bandpass filter 1202, a local oscillator (LO) 1204, a mixer 1206, and an RF lowpass filter (LPF) 1208 may be used in combination to downconvert signal components of the TI DAC 108 output signal to a narrower bandwidth and sample rate associated with the TI DAC 108, and to a narrowband supported by the ADC 114. The tunable RF bandpass filter 1202 and the local oscillator 1204 are set by a frequency sweep control 1216. Although a tunable RF bandpass filter 1202 is shown, a bank of filters may be used instead in some embodiments. The frequency range covered by each narrowband capture of a given segment of error waveform data 122 is [f c:f c +BW ABC ] where f c is the LO frequency, BW ABC is the effective bandwidth captured by the ADC 114.

[0065] Then, after considering the DT linear model unit 106, [f c :f c +BW ABC In order to create a model of the ideal output signal content expected within a given frequency span covered by [100 MHz], the RF down conversion circuit is mirrored using a DSP: the output signal of the DT linear model unit 106 is sent to a tunable DSP bandpass filter 1210, which is mixed with a signal from a local oscillator 1214 by a mixer 1218. The tunable DSP bandpass filter 1210 and the local oscillator 1214 are set by a frequency sweep control 1216. The signal from the local oscillator 1214 is also sent to a phase aligner 1212 and used as a reference to ensure that the phase of the local oscillator 1214 and the local oscillator 1204 have a known phase relationship, thereby maintaining the phase of the segments captured by the ADC 114 coherently for the DT linear model unit 106 despite modifications by the tunable DSP bandpass filter 1210, mixer 1218, local oscillator 1214 and lowpass filter 1220, and allowing these waveforms to be subtracted to generate the error signal 122.

[0066] Segments of the error signal 122 can be captured over narrowband frequency spans. The segment size used to capture the error signal 122 determines the effective frequency resolution, which is the number of narrowband segments [f c :f c +BW ABC

[0046] The resulting segments may be subjected to a Discrete Fourier Transform (DFT) in DPD unit 104, as described below, to generate complex vectors of estimated error versus frequency, magnitude and phase components for the frequencies covered in each narrowband frequency span.

[0067] The frequency of the local oscillator 1204 is swept to cover the entire frequency range that is important for the calibration of the TI DAC 108. The estimated frequency domain error vectors obtained after DFT of the error signal 122 captured for each narrowband frequency span are then combined to generate a total complex frequency domain error vector e, as shown in equations (14)-(17).

[0068] f C =n BW ABC , n∈[0,…,N-1] (14)

[0069]

number

[0070]

number

[0071] e = E(f) (17)

[0072] Here, E n (f) is the narrowband error waveform segment f∈[0:BW ABC ) (within the bandwidth captured by narrowband ADC 114), E(f) is the total frequency domain error waveform, f is a vector of frequency values ​​used to solve for the adaptive DPD coefficients, and e is the total frequency domain error waveform vector used to solve for the adaptive DPD coefficients.

[0073] The DPD coefficients for the next iteration determined by the DPD unit 104 can be solved in the frequency domain. By performing successive DFTs on the input waveform to the parallel multiplicative adaptive processing block 208 in the DPD unit 104, a vector of frequency vs. input waveform impairments can be generated for each type of impairment modeled in the DPD unit 104 that is aligned with the frequencies covered by the frequency domain vector e. The input waveform to the parallel multiplicative adaptive processing block 208 can be captured in multiple segments that are aligned in time with the multiple segments captured by the narrowband ADC 114. By performing a DFT on each of these segments, a complex vector of frequency domain samples (including magnitude and phase components) can be extracted that are aligned with the frequency span covering the corresponding error signal 122 captured in a segment by the narrowband ADC 114 during a sequence of frequency sweep ranges. Then, by combining the frequency domain vectors captured for each segment in the frequency sweep sequence across all successive segments, a total vector e estimating the frequency domain error waveform is constructed covering the entire frequency range used in the calibration.

[0074] The estimated residual error can then be calculated in the frequency domain using equation (18).

[0075]

number

[0076] where ê is the vector of estimated total frequency domain residual error waveform after considering the effect of the current DPD correction coefficients, which is the sum of the errors due to each impairment type in the narrowband ADC 114 output signal, combined over the entire frequency range covered by the LO 1204 frequency sweep. W is the input waveform impairment matrix (in frequency domain form) before scaling by the parallel multiplicative adaptation block 208 in the DPD unit 104, with the row dimension containing the base impairment values ​​(as input to the multiplicative adaptation block 208) and the column dimension containing successive values ​​of frequency. The variable c is the residual coefficient vector that can be added to the current DPD coefficient vector to scale the magnitude of the impairment values ​​in the multiplicative adaptation block 208 to cancel the DAC 108 impairments, i.e., minimize the residual error.

[0077] Since equations (14)-(18) will typically be over-determined, it is convenient to find a least-squares solution that minimizes

[0078]

number

[0079] where e is the vector for the total frequency domain residual error waveform measured by capturing successive segments while sweeping across the frequency range, followed by a DFT.

[0080] Thus, the least squares solution is given by equation (19).

[0081] c=-(W T W) -1 W T e (19)

[0082] Equation (19) is W T The W matrix is ​​not singular (i.e., |W T W| ≠ 0).

[0083] The adaptation of the DPD coefficients for background calibration (which is performed in parallel with the generation of an arbitrary waveform for the DAC output signal) can be performed using equation (20).

[0084] d n =d n-1 +μc (20)

[0085] Here, n is the following vector of DPD coefficients, d n-1 is the current vector of DPD coefficients, μ is the adaptation rate, which may be dynamically adjusted, such as by a normalized LMS-type approach, and c is a coefficient whose solution is obtained from a frequency domain optimization process of the residual error in the current frequency sweep.

[0086] This approach can also be applied to foreground calibration. In such an embodiment, a set (group) of known input waveforms optimized for the calibration needs of the DAC may be used. The coefficients of the DPD unit 104 are then solved in the frequency domain according to equation (19).

[0087] FIG. 13 illustrates another alternative embodiment according to an embodiment of the present invention. The embodiment of FIG. 13 is similar to the embodiment described above in FIGS. 1 and 12, and thus similar components are given the same reference numerals and no additional description will be provided with respect to FIG. 13. In the TI DAC system 1300, the variable RF bandpass filter 1202 and the variable DSP bandpass filter 1210 are eliminated. This can simplify and reduce the cost of the system, given the complexity of the variable RF bandpass filter 1202. Removing the bandpass filters 1202 and 1210 allows the image components (ff c plus f+f c ) occurs.

[0088] The narrowband spectrum contains the image components of the input signals of both mixers (ff cplus f+f c ) can be mitigated by additional processing of the estimated residual complex frequency domain error frequency.

[0089] Each segment captured by the narrowband ADC and the resulting residual error waveform will contain signal components according to equations (21) and (22) below.

[0090] f C =n BW ABC , n∈[0,…,N-1] (21)

[0091]

number

[0092] Therefore, the desired residual error waveform is G of the segment as shown in equation (23). n It can be extracted repeatedly from (f).

[0093]

number

[0094] The segments can then be put together to produce the residual error waveform, as shown in equation (24).

[0095]

number

[0096] After the residual error waveform is obtained in the frequency domain, a process similar to that described above for the narrowband frequency sweep option that included a variable bandpass filter may be used to solve for the adaptive DPD coefficients.

[0097] Other variations of the narrowband ADC approach using down-conversion to adaptively process the DPD coefficients are possible, one such example being the adaptation of this approach to other RF down-conversion architectures, such as complex I / Q super-heterodyne receiver circuits.

[0098] 14 shows an example of a test and measurement instrument 1400 having a TI DAC system 1402. The TI DAC system 1402 may be any of the TI DAC systems 100, 1200 or 1300 described above. The test and measurement instrument 1400 may be, for example, an arbitrary waveform generator, an arbitrary function generator or any test and measurement instrument that provides a signal source.

[0099] The test and measurement instrument 1400 includes one or more ports 1404, which may be any electrical or fiber optic signal transmission medium. The ports 1404 may include receivers, transmitters, and / or transceivers. The ports 1404 are coupled to a TI DAC system 1402, which is connected to one or more processors 1406. Although only one processor 1406 is shown in FIG. 14 for simplicity, one skilled in the art will appreciate that multiple processors 1406 of various types may be used in combination rather than a single processor 1406.

[0100] The one or more processors 1406 may be configured to execute instructions from the memory 1408 and may perform any method or associated steps indicated in such instructions. The memory 1408 may be implemented as a processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, a hard disk drive, or other form of memory. The memory 1408 serves as a medium for storing data, computer program products, and other instructions. For example, the one or more processors 1406 may output digital signals to the TI DAC system 1402, which may be output as analog signals to the device under test through the port 1404, as described above.

[0101] A user input 1410 is coupled to the one or more processors 1406. The user input 1410 may include a keyboard, mouse, trackball, touch screen, or any other interface available to a user using a GUI on the display 1412. The display 1412 may be a digital screen, cathode ray tube-based display, or other monitor that displays waveforms, measurements, or other data to a user. Although the components of the test and measurement instrument 1400 are depicted as being integrated within the test and measurement instrument 1400, one skilled in the art will appreciate that any of these components may be external to the test and measurement instrument 1400 and may be coupled to the test and measurement instrument 1400 in any conventional manner (e.g., wired or wireless communication medium or mechanism). For example, in some embodiments, the display 1412 may be remote from the test and measurement instrument 1400.

[0102] Aspects of the invention can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The term "controller" or "processor" in this application contemplates microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the invention can be implemented in computer-available data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, and the like, which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. The computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, and the like. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. One or more aspects of the present invention may be more effectively implemented using certain data structures, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0103] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media that may be read and executed by one or more processors. Such instructions may be referred to as computer program products. A computer-readable medium as described herein means any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0104] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transitory forms of signal transmission.

[0105] A communication medium refers to any medium capable of communicating computer readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0106] Working Example In the following, examples useful for understanding the technology disclosed in the present application are presented. The embodiment of the technology may include one or more of the examples described below and any combination thereof.

[0107] Example 1 is a time-interleaved digital-to-analog converter system comprising: a digital pre-distortion unit configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal into an analog signal to correct mismatch between a plurality of time-interleaved channels of the time-interleaved digital-to-analog converter; and a calibration system, the calibration system comprising: an analog-to-digital converter having a second sample rate less than or equal to the first sample rate, the analog-to-digital converter configured to receive the analog signal and convert the analog signal into a down-sampled digital signal; a discrete-time linear model unit configured to receive the input digital signal and output a model signal; and a combiner configured to subtract the down-sampled digital signal from the model signal to generate the error signal.

[0108] Example 2 is the time-interleaved digital-to-analog converter system of Example 1, wherein the discrete-time linear model unit further receives the error signal and includes a finite impulse response filter having at least one adaptive tap and a fixed tap.

[0109] Example 3 is a time-interleaved digital-to-analog converter system of any of Examples 1 and 2, wherein the calibration system is enabled during pre-operation calibration with a known digital input signal.

[0110] Example 4 is the time interleaved digital-to-analog converter system of Example 3, further comprising a digital signal processor configured to, during operation with an unknown digital input signal, determine whether to disable the calibration system based on the digital input signal.

[0111] Example 5 is a time-interleaved digital-to-analog converter system according to any one of Examples 1 to 4, wherein the digital pre-distortion section has a plurality of delay lines having products of different orders, each of which receives the digital input signal.

[0112] Example 6 is the time interleaved digital-to-analog converter system of Example 5, wherein the digital pre-distortion unit includes a plurality of first demultiplexers, each of which is for a respective output signal of a plurality of the delay lines having a product of a different order, each of the first demultiplexers receiving the output signal of each of the delay lines and outputting a parallel stream of data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter, and a plurality of second demultiplexers, each of which is for a respective output signal of a plurality of the delay lines having a product of a different order, and a plurality of the second demultiplexers receiving the error signal and outputting a parallel stream of error data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter. the plurality of coefficient adaptation processors each configured to correlate a respective one of the parallel streams of data with the parallel stream of error data and output a number of variable coefficients equal to the number of channels of the time interleaved digital-to-analog converter; a plurality of first combiners each configured to combine a respective one of the variable coefficients with a parallel stream of data into a parallel stream of combined data; a plurality of multiplexers each configured to combine a respective one of the parallel streams of combined data into one signal; and a second combiner configured to combine each of the signals from the plurality of multiplexers into the distorted digital signal.

[0113] Example 7 is the time interleaved digital-to-analog converter system of Example 6, wherein the first combiner is a point-by-point multiplier that multiplies the parallel streams of data with the variable coefficients.

[0114] Example 8 is the time-interleaved digital-to-analog converter system of any of Examples 6 and 7, wherein the first combiner is a MIMO having a plurality of finite impulse response filters.

[0115] A ninth embodiment is the time-interleaved digital-to-analog converter system of the eighth embodiment, in which the coefficient adaptation processor is a MIMO type coefficient adaptation processor.

[0116] A tenth embodiment is a time-interleaved digital-to-analog converter system according to any one of the first to ninth embodiments, in which the calibration system operates in real time.

[0117] Example 11 is a test and measurement apparatus comprising the time-interleaved digital-to-analog converter system of any of Examples 1 to 10, and a port configured to receive the analog signal and output the analog signal to a device under test electrically or optically coupled to the device under test via fiber.

[0118] Example 12 is a method for calibrating a time-interleaved digital-to-analog converter, comprising the steps of: generating a distorted digital signal by distorting an input digital signal based on an error signal; converting the distorted digital signal to an analog signal by a time-interleaved digital-to-analog converter; converting the analog signal to a down-sampled digital signal; generating a model signal based on the input digital signal; and generating the error signal by subtracting the down-sampled digital signal from the model signal.

[0119] Example 13 is the method of example 12, wherein the process of generating the model signal includes a process of processing the digital input signal and the error signal with a finite impulse response filter having at least one adaptive tap and a fixed tap.

[0120] Example 14 is the method of any of examples 12 or 13, further comprising enabling the method during pre-operational calibration with a known digital input signal.

[0121] Example 15 is the method of any of examples 12-14, further comprising enabling the method during operation with an unknown digital input signal based on the digital input signal.

[0122] Example 16 is the method of any of Examples 12-15, further comprising delaying the digital input signal by a plurality of delay lines having different order products.

[0123] Example 17 is the method of example 16, further comprising the steps of: receiving output signals of each of the plurality of delay lines at a corresponding first demultiplexer and outputting a parallel stream of data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter from the corresponding first demultiplexer; receiving the error signal at each of a plurality of second demultiplexers and outputting a parallel stream of error data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter; the process further comprising: correlating each of the parallel streams of data with each of the parallel streams of error data in each of a plurality of coefficient adaptation processors to output a number of variable coefficients equal to the number of channels of the time interleaved digital-to-analog converter; combining each of the variable coefficients with each of the parallel streams of data into a respective parallel stream of combined data; multiplexing each of the combined data into a respective one signal in each of a plurality of multiplexers; and combining each of the signals into the distorted digital signal.

[0124] Example 18 is a method of any of Examples 12 to 17, further comprising the steps of: mixing the analog signal with a signal from a local oscillator to generate a mixed signal; and filtering the mixed signal with a low-pass filter before converting the analog signal into a down-sampled digital signal.

[0125] Example 19 is a method of any of Examples 12 to 18, further comprising the steps of: mixing the model signal with a signal from a local oscillator to generate a mixed signal; filtering the mixed signal with a low-pass filter; and down-sampling the filtered mixed signal before generating the error signal.

[0126] Example 20 is the method of example 19, further comprising filtering the model signal with a variable bandpass filter prior to mixing the model signal with the signal from the first local oscillator.

[0127] The above-described versions of the disclosed subject matter have many advantages that have been described or that will be apparent to those of skill in the art. Nevertheless, not all of these advantages or features are required in every version of a disclosed device, system or method.

[0128] In addition, the description of this application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of those specific features. When a particular feature is disclosed in the context of a particular aspect or embodiment, that feature can also be used in the context of other aspects and embodiments, to the extent possible.

[0129] Furthermore, when the application refers to a method having two or more defined steps or processes, those defined steps or processes may be performed in any order or simultaneously, unless the context precludes such a possibility.

[0130] For convenience of illustration, specific embodiments of the invention have been illustrated and described, but it will be understood that various changes can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims. [Explanation of symbols]

[0131] 100 TI DAC System 102 Digital Input Signal 104 Digital Pre-Distortion (DPD) Unit 106 DT Linear Model Units 108 TI DAC 109 TI DAC channels 110 Adder 112 Analog Signal 114 ADC 116 Down Sampler 118 Down Sampler 120 Combiner 122 Error Signal 200 First Order Delay Line 202 Second Order Delay Line 204 P extension line 206 Delay Block 208 Adaptive Processing Block 210 Combiner 500 Demultiplexer 502 Delayed Block 504 Down Sampler 506 Coefficient Adaptation Processing Block 508 Demultiplexer 510 Multiplier 512 Multiplexer 800 Adaptive Processing Blocks 802 Demultiplexer 804 Delay Block 806 MIMO Coefficient Adaptation Processing Block 808 Demultiplexer 810 MIMO Blocks 812 Multiplexer 1200 TI DAC System 1202 Variable RF Bandpass Filter 1204 Local Oscillator 1206 Mixer 1208 RF Low Pass Filter 1210 Variable DSP Bandpass Filter 1212 Phase Aligner 1214 Local Oscillator 1216 Frequency sweep control section 1218 Mixer 1220 Low Pass Filter 1300 TI DAC System 1400 Test and Measurement Equipment 1402 TI DAC System 1404 Port 1406 processor 1408 Memory 1410 User Input Section 1412 Display section

Claims

1. 1. A time-interleaved digital-to-analog converter system, comprising: a digital pre-distortion unit configured to receive an input digital signal and an error signal, and to output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal that compensates for mismatch between a plurality of time-interleaved channels of the time-interleaved digital-to-analog converter; an analog down-converter that down-converts the analog signal by a predetermined frequency and converts it into a narrow-band analog signal; an analog-to-digital converter having a second sample rate less than or equal to the first sample rate, the analog-to-digital converter configured to receive the narrowband analog signal and convert the narrowband analog signal to a down-sampled narrowband digital signal; a discrete-time linear model unit configured to receive the input digital signal and output a model signal; a digital down converter that down-converts the model signal by the predetermined frequency and converts it into a narrowband model signal having a narrow band; a frequency sweep control unit that controls the predetermined frequency to be swept over a predetermined frequency range based on a bandwidth of the analog signal; a combiner configured to subtract the down-sampled narrowband digital signal from the narrowband model signal to generate the error signal; A calibration system having A time-interleaved digital-to-analog converter system comprising:

2. 2. The time-interleaved digital-to-analog converter system of claim 1, wherein said discrete-time linear model unit further comprises a finite impulse response filter receiving said error signal and having at least one adaptive tap and a fixed tap.

3. 2. The time-interleaved digital-to-analog converter system of claim 1, wherein the calibration system is enabled during a pre-operational calibration using a known input digital signal.

4. 2. The time-interleaved digital-to-analog converter system of claim 1, wherein said digital pre-distortion section comprises a plurality of delay lines each receiving said input digital signal and having a multiplication order of different delay lines.

5. The digital pre-distortion section is a plurality of first demultiplexers, each for a respective output signal of a plurality of said delay lines having a product of a different order, each of said first demultiplexers receiving said output signal of each of said delay lines and outputting a parallel stream of data having a number of signals equal to the number of channels of said time-interleaved digital-to-analog converter; a plurality of second demultiplexers, each of which receives the error signal and outputs a parallel stream of error data having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of coefficient adaptation processors, each of which correlates a respective one of the parallel streams of data with the parallel stream of error data and outputs a number of variable coefficients equal to the number of channels of the time interleaved digital to analog converter; a plurality of first combiners, each of the first combiners configured to combine a respective one of the variable coefficients with a parallel stream of data into a parallel stream of combined data; a plurality of multiplexers, each multiplexer configured to combine each of the parallel streams of the combined data into one signal; a second combiner configured to combine each of the signals from a plurality of said multiplexers into said distorted digital signal; 5. The time interleaved digital to analog converter system of claim 4, further comprising:

6. generating a distorted digital signal by distorting the input digital signal based on the error signal; converting the distorted digital signal into an analog signal by a time-interleaved digital-to-analog converter; A process of down-converting the analog signal by a predetermined frequency and converting it into a narrow band analog signal; converting said narrowband analog signal into a down-sampled narrowband digital signal; generating a model signal based on the input digital signal; A process of down-converting the model signal by the predetermined frequency and converting it into a narrowband model signal having a narrow band; sweeping the predetermined frequency over a predetermined frequency range based on a bandwidth of the analog signal; subtracting the down-sampled narrowband digital signal from the narrowband model signal to generate the error signal; 23. A method for calibrating a time-interleaved digital-to-analog converter comprising:

7. 7. The method of calibrating a time-interleaved digital-to-analog converter of claim 6, wherein generating the model signal comprises processing the input digital signal and the error signal through a finite impulse response filter having at least one adaptive tap and a fixed tap.

8. 7. The method of claim 6, further comprising delaying the input digital signal by a plurality of delay lines having different order products.

9. receiving the output signals of each of the plurality of delay lines at a corresponding first demultiplexer and outputting from the corresponding first demultiplexer a parallel stream of data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter; receiving, at each of a plurality of second demultiplexers, the error signals and outputting a parallel stream of error data having a number of signals equal to the number of channels of the time interleaved digital-to-analog converter; correlating the parallel streams of data with the parallel streams of error data to output, in each of a plurality of coefficient adaptation units, a number of variable coefficients equal to the number of channels of the time-interleaved digital-to-analog converter; combining each of the variable coefficients and each of the parallel streams of data into respective parallel streams of combined data; multiplexing each of the combined data into a respective signal in a plurality of multiplexers; combining each of said signals into said distorted digital signal; 9. The method of calibrating a time interleaved digital-to-analog converter of claim 8, further comprising:

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