Semiconductor Device

Abstract

To provide a semiconductor device capable of preventing destruction of an output transistor due to secondary breakdown.SOLUTION: A detection transistor MNd flows a detection current IdN in a current path CP1n in a period where an output voltage Vo generated in a load terminal PNl is lower than a grounding voltage GND. A current mirror circuit CMp1 transfers a detection current IdN flowing in the current path CP1n to a current path CP2a. A detection resistor element Rd1 converts a mirror current I2a flowing in the current path CP2a to a detection voltage Vd1. A control transistor MNc1 is turned on in a period where the converted detection voltage Vd1 is higher than a prescribed value. An output transistor QO is controlled to become off in a period where the control transistor MNc1 is on.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device for power control. [Background technology]

[0002] In a semiconductor device for power control, when the current supply to an inductive load such as a solenoid or a motor is switched from on to off, a back electromotive force is generated by discharging the electromagnetic energy stored in the load. To prevent the output transistor from being destroyed by this back electromotive force, the semiconductor device may be equipped with a dynamic clamp circuit that clamps the back electromotive force to a predetermined clamp voltage.

[0003] A semiconductor device equipped with such a dynamic clamp circuit is shown in Patent Document 1 and Patent Document 2. In summary, the dynamic clamp circuit clamps the back electromotive voltage by increasing the gate voltage of the output transistor and turning the output transistor half-on when the drain-source voltage of the output transistor exceeds a predetermined value. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-208406 A [Patent Document 2] JP 2017-212522 A Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in the method of clamping the back electromotive force by half-on of the output transistor as shown in Patent Document 1 and Patent Document 2, the operating point of the output transistor at the half-on timing may not satisfy the safe operating area (SOA). In particular, in an output transistor in which the on-resistance is reduced by using a superjunction structure or the like, the SOA associated with the secondary breakdown may become narrow. In this case, it may become more difficult to satisfy the SOA.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a first and a second power supply terminal, a load terminal connected to a load, an output transistor, a driver, a first current path, a detection transistor, a current mirror circuit, a detection resistor element, and a control transistor. A first power supply voltage on the high potential side is applied to the first power supply terminal, and a second power supply voltage on the low potential side is applied to the second power supply terminal. The output transistor is connected to the first power supply terminal and the load terminal, and is controlled to be on / off based on a control voltage between a control node and the load terminal. The driver controls the control voltage of the output transistor based on a control input signal. The first current path is formed between the first power supply terminal and the load terminal. The detection transistor is inserted in the first current path, and flows a detection current in the first current path during a period when an output voltage generated at the load terminal is lower than the second power supply voltage. The current mirror circuit transfers the detection current flowing in the first current path to the second current path. The detection resistor element is inserted in the second current path and converts the current flowing through the second current path into a detection voltage. The control transistor is turned on during a period in which the detection voltage converted by the detection resistor element is higher than a predetermined value. The output transistor is controlled to be turned off during a period in which the control transistor is on. Effect of the Invention

[0008] According to the embodiment, it is possible to prevent the output transistor from being destroyed due to a secondary breakdown. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration example around a power control unit to which a semiconductor device according to a first embodiment is applied. [Diagram 2] FIG. 2 is a block diagram showing a schematic configuration example of a power control system to which the semiconductor device according to the first embodiment is applied. As shown in FIG. [Diagram 3] FIG. 3 is a plan view showing an example of the outer shape of the power device in FIG. 1 and FIG. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration example of the output transistor between A and A' in FIG. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration example of a main part of the power device shown in FIGS. [Figure 6] FIG. 6 is a waveform diagram showing an example of the operation of the power device shown in FIG. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a waveform diagram showing an example of the operation of the power device shown in FIG. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a waveform diagram showing an example of the operation of the power device shown in FIG. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to the fourth embodiment. [Figure 12] FIG. 12 is a waveform diagram showing an example of the operation of the power device shown in FIG. [Figure 13A] FIG. 13A is a waveform diagram showing an example of operation of a power device serving as a comparative example. [Figure 13B]FIG. 13B is a diagram showing the correspondence between the safe operating area (SOA) of the output transistor and the operation example of FIG. 13A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number.

[0011] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the same members are generally designated by the same reference numerals, and the repeated description will be omitted.

[0013] (Embodiment 1) <Outline of power control unit> Fig. 1 is a block diagram showing a schematic configuration example of a power control unit and its surroundings to which the semiconductor device according to the embodiment 1 is applied. Fig. 2 is a block diagram showing a schematic configuration example of a power control system to which the semiconductor device according to the embodiment 1 is applied. The power control units 10, 10a, 10b1, and 10b2 shown in Fig. 1 or 2 are, for example, engine control units (ECUs) for vehicles. The power control units 10, 10a, 10b1, and 10b2 have a function of controlling power supply from a battery 11 to a load 12.

[0014] The power control unit 10 shown in Fig. 1 includes a power device 20, which is a semiconductor device, and a microcomputer (referred to as MCU) 21. For example, each of the power device 20 and the MCU 21 is configured as a single semiconductor chip and mounted on a wiring board that configures the power control unit 10. The power device 20 includes, for example, a power semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In the embodiment, the power device 20 is configured as, for example, an intelligent power device (IPD) including a MOSFET and a control circuit including a driver for the MOSFET and various protection circuits.

[0015] The power device (semiconductor device) 20 includes a high-potential side power supply terminal PNv to which a high-potential side power supply voltage VCC is applied, a load terminal PNl connected to a load 12, and a control input terminal PNi to which a control input signal IN is input. The high-potential side power supply voltage VCC is generated by a battery 11 and has a voltage value of, for example, 12V to 15V. The load 12 is an inductive load, a resistive load, or a capacitive load. The inductive load is, for example, a solenoid, a motor, a coil, or the like. The load 12 operates by receiving the high-potential side power supply voltage from the load terminal PNl with respect to a low-potential side power supply voltage GND.

[0016] In this specification, the high-potential side power supply voltage VCC and the high-potential side power supply terminal PNv are simply referred to as the power supply voltage VCC and the power supply terminal PNv. Also, the low-potential side power supply voltage GND is assumed to have a value of 0V, and is referred to as the ground voltage GND.

[0017] The MCU 21 has a function of controlling the power device 20. The MCU 21 controls the power device 20, for example, by outputting a control input signal IN indicating on / off of power supply to the power device 20. The power device 20 switches on / off of the power supply from the battery 11 to the load 12, i.e., switches conduction / non-conduction between the power terminal PNv and the load terminal PNl, based on the control input signal IN. In this way, the power device 20 has a function as a power switch.

[0018] Moreover, the power device 20 outputs various monitor signals MNI to the MCU 21. Examples of the monitor signal MNI include an abnormality detection signal from various protection circuits (not shown) and a current sense signal from a current sense circuit (not shown). The various protection circuits are circuits that protect the power semiconductor elements from overvoltage, overcurrent, overtemperature, and the like. The current sense circuit is a circuit that senses the output current flowing from the power semiconductor elements to the load terminal PN1. Although not shown, the power control unit 10 may also be equipped with a DC-DC converter or the like that converts the power supply voltage VCC from the battery 11 and supplies it to the MCU 21.

[0019] Fig. 2 shows a power control system in which power control units as described in Fig. 1 are arranged in a hierarchical manner. The power control system includes a power control unit 10a as a higher-level unit and multiple (two in this example) power control units 10b1 and 10b2 as lower-level units. Each of the power control units 10a, 10b1, and 10b2 includes a power device 20 and an MCU 21, similar to the case of Fig. 1.

[0020] In the power device 20 in the power control unit 10a, which is the upper unit, a power supply voltage VCC from a battery 11 is applied to a power supply terminal PNv. Also, a load terminal PNl is connected to the power control units 10b1 and 10b2, which are lower units, via a wire harness WH or the like. That is, the upper unit operates with the lower units as loads.

[0021] On the other hand, in the power devices 20 in the power control units 10b1 and 10b2, which are the lower units, a power supply voltage Vcc from the battery 11 is commonly applied to a power supply terminal PNv via the power control unit 10a and a wire harness WH, etc. Also, the load terminals PNl in the power control units 10b1 and 10b2 are connected to the loads 12b1 and 12b2, respectively.

[0022] The power device 20 in the power control unit 10a controls ON / OFF of the power supply from the battery 11 to the multiple power control units 10b1, 10b2 based on a control input signal IN from the corresponding MCU 21. Meanwhile, the power devices 20 in the power control units 10b1, 10b2 control ON / OFF of the power supply from the power control unit 10a to the loads 12b1, 12b2 based on a control input signal IN from the corresponding MCU 21. In this example, for example, when a serious abnormality is detected based on a monitor signal MNI from the power device 20, the MCU 21 in the power control unit 10a causes an error display, not shown, to be displayed using an error signal ERR.

[0023] <Power device configuration> 3 is a plan view showing an example of the external shape of the power device in FIG. 1 and FIG. 2. The power device 20 is realized, for example, by a package in which a semiconductor chip CHP is sealed. In this example, the package has a shape called TO252-7pin. The semiconductor chip CHP is equipped with an output transistor QO and a control circuit CT that controls the output transistor QO. The control circuit CT includes a driver for the output transistor QO, various protection circuits, and the like.

[0024] The external terminals of the package, i.e., the leads, include the load terminal PNl, the control input terminal PNi, and the power supply terminal PNv described in Fig. 1, as well as a low-potential side power supply terminal PNg and monitor terminals PNm1 and PNm2. A ground voltage GND is applied to the low-potential side power supply terminal PNg. In this specification, the low-potential side power supply terminal PNg is referred to as the ground terminal PNg. The monitor terminals PNm1 and PNm2 are terminals for the monitor signal MNI described in Fig. 1.

[0025] The semiconductor chip CHP is mounted on a lead frame 25 that constitutes a package. The lead frame 25 is connected to a power supply terminal PNv. Here, a drain electrode DE of an output transistor QO is formed on the back surface of the semiconductor chip CHP. As a result, the power supply terminal PNv is connected to the drain electrode DE. The output transistor QO is composed of a plurality of unit cells UC. The plurality of unit cells UC are arranged side by side in the X-axis direction. Each of the plurality of unit cells UC is formed so as to extend in the Y-axis direction.

[0026] A source pad PDs, which is a part of the source electrode of the output transistor QO, is formed on the main surface side of the semiconductor chip CHP. The source pad PDs is connected to a load terminal PNl via a bonding wire BW. In this example, two load terminals PNl are provided to ensure a sufficient output current. Furthermore, a power supply pad PDp, a control input pad PDi, and monitor pads PDm1 and PDm2 are formed on the main surface side of the semiconductor chip CHP. The power supply pad PDp is connected to a ground terminal PNg via a bonding wire BW. The control input pad PDi and the monitor pads PDm1 and PDm2 are connected to a control input terminal PNi and monitor terminals PNm1 and PNm2, respectively, via bonding wires BW.

[0027] Fig. 4 is a cross-sectional view showing a configuration example of the output transistor between A-A' in Fig. 3. The output transistor QO shown in Fig. 4 is, for example, an n-channel MOSFET formed on a semiconductor substrate SUB. A unit cell UC constituting the output transistor QO has a drain region DA, a base region BA, a gate electrode GE, a backgate contact region BCT, a source region SA, and a column region CA formed on the semiconductor substrate SUB.

[0028] The drain region DA is, for example, an n-type region and is disposed on the back surface side of the semiconductor substrate SUB. A drain electrode DE is formed on the back surface of the drain region DA, i.e., the back surface of the semiconductor substrate SUB. The base region BA is, for example, a p-type region and is formed on the main surface of the drain region DA. The gate electrode GE is embedded in the semiconductor substrate SUB so as to reach the drain region DA from the main surface side of the base region BA. That is, the gate electrode GE has a trench gate structure. In addition, the gate electrode GE is covered with a gate oxide film GOX.

[0029] The back gate contact region BCT is, for example, p + The source region SA is an n-type region and is formed in the center between adjacent gate electrodes GE on the main surface side of the base region BA. + A source electrode SE is a type region and is formed between the back gate contact region BCT and the gate electrode GE. Furthermore, a source electrode SE is formed on the main surface of the semiconductor substrate SUB. The source electrode SE is in contact with the source region SA and the back gate contact region BCT. A protective film and the like (not shown) are formed on the source electrode SE. The source pad PDs shown in FIG. 3 corresponds to an opening in the protective film.

[0030] On the other hand, the column region CA is, for example, a p-type region, and is formed so as to extend from the rear surface of the base region BA to the rear surface side of the semiconductor substrate SUB. That is, the column region CA and the drain region DA are disposed so as to be adjacent to each other in the X-axis direction. In a typical MOSFET having a trench gate structure, the column region CA is not formed, and the drain region DA is, for example, an n-type region in order to ensure a high breakdown voltage. - On the other hand, in the configuration example of FIG. 4, the column region CA is formed, and the drain region DA is, for example, an n - The n-type region is more highly doped than the n-type region.

[0031] The configuration example shown in Figure 4 is called a superjunction structure. In the superjunction structure, when the output transistor QO is on, low on-resistance is achieved by flowing electrons through the drain region DA, which has a low resistivity. On the other hand, when the output transistor QO is off, high breakdown voltage is achieved by depleting the drain region DA and column region CA. In other words, by using the superjunction structure, it is possible to obtain high breakdown voltage and low on-resistance characteristics while maintaining the high-speed switching characteristics of the output transistor QO.

[0032] Unlike the output transistor QO, the control circuit CT shown in FIG. 3 includes a MOSFET, a capacitor, a diode, a resistor, and the like formed by a general CMOS (Complementary MOS) process. In this specification, the normal MOSFET mounted on the control circuit CT is called a MOS transistor to distinguish it from the output transistor QO, and an n-channel type is called an nMOS transistor, and a p-channel type is called a pMOS transistor. In addition, the output transistor QO is not necessarily limited to a superjunction structure, and may be a general trench gate structure or a planar gate structure, etc. Furthermore, the output transistor QO is not limited to a MOSFET, and may be an IGBT, etc.

[0033] <Circuit configuration of power device (first embodiment)> Fig. 5 is a circuit diagram showing a configuration example of the main part of the power device in Fig. 1 and Fig. 2. The power device 20a shown in Fig. 5 includes a power supply terminal PNv to which a power supply voltage VCC is applied, a control input terminal PNi to which a control input signal IN is input, a ground terminal PNg to which a ground voltage GND is applied, and a load terminal PNl connected to a load 12. The power device 20a also includes an output transistor QO, a driver 30, a current limiting element 31, and a protection circuit 32a.

[0034] In this example, the output transistor QO is an n-channel MOSFET. The drain (D) and source (S) of the output transistor QO are connected to the power supply terminal PNv and the load terminal PNl, respectively. The output transistor QO is controlled to be on / off based on the control voltage between the gate (G), which is the control node, and the source (S), which is connected to the load terminal PNl, that is, the gate-source voltage Vgs.

[0035] Here, as shown in Fig. 3, the power supply terminal PNv is also the drain electrode DE of the output transistor QO, and the load terminal PNl is also the source pad PDs of the output transistor QO. The control input terminal PNi is also the control input pad PDi, and the ground terminal PNg is also the power supply pad PDp. The load 12 is, for example, an inductive load, but may be a resistive load or the like in some cases. That is, for example, when the load 12 is viewed from the source pad PDs, even if the load 12 is a resistive load or the like, the inductance component of the bonding wire BW or the like may act as an inductive load.

[0036] The driver 30 controls the gate-source voltage Vgs of the output transistor QO based on a control input signal IN from a control input terminal PNi. For example, when the control input signal IN is at an “H” level, the driver 30 controls the gate-source voltage Vgs of the output transistor QO to an on level via the current limiting element 31. The on level is, for example, the level of the power supply voltage VCC.

[0037] As a result, the gate-source voltage Vgs of the output transistor QO becomes greater than the threshold voltage (Vth), and the output transistor QO turns on. When the output transistor QO turns on, an output current Io flows through the output transistor QO, and the output voltage Vo generated at the load terminal PNl rises to near the power supply voltage VCC. As a result, the power supply to the load 12 turns on.

[0038] On the other hand, when the control input signal IN is at the “L” level, the driver 30 controls the gate-source voltage Vgs of the output transistor QO to the off level via the current limiting element 31. The off level is, for example, the level of the ground voltage GND. As a result, the gate-source voltage Vgs of the output transistor QO becomes smaller than the threshold voltage (Vth), and the output transistor QO turns off. When the output transistor QO turns off, the output current Io does not flow, and the power supply to the load 12 is turned off. Then, the output voltage Vo generated at the load terminal PNl finally converges to the ground voltage GND.

[0039] Although not shown, the driver 30 is composed of, for example, a charge pump circuit that generates a gate voltage by adding the value of the power supply voltage VCC to the output voltage Vo generated at the load terminal PNl. The current limiting element 31 limits the charging / discharging current by the driver 30 using, for example, a resistor element so that the gate-source capacitance of the output transistor QO is not rapidly charged or discharged. This makes it possible to prevent rapid on / off transition of the output transistor QO and suppress noise. Details of the protection circuit 32a will be described later.

[0040] <Configuration and operation of power device (comparative example)> Fig. 13A is a waveform diagram showing an example of the operation of a power device as a comparative example. Unlike the configuration example of Fig. 5, the power device as a comparative example does not include a protection circuit 32a. Fig. 13A shows a load-on period T1, a load-off period T2, and a transient switching period T3. The load-on period T1 is a period during which the control input signal IN is at the "H" level and the output transistor QO is on.

[0041] When the control input signal IN transitions from the "L" level to the "H" level as a start condition for the load-on period T1, the output transistor QO switches from off to on in response to control from the driver 30. As a result, the output voltage Vo of the load terminal PNl rises from zero, i.e., the ground voltage GND, toward the vicinity of the power supply voltage VCC, and the output current Io increases at a gradient according to the inductance of the load 12, etc. During this period, electromagnetic energy is accumulated in the load 12.

[0042] The load-off period T2 is a period during which the control input signal IN is at the "L" level and the output transistor QO is off. When the control input signal IN transitions from the "H" level to the "L" level as a start condition for this period, the output transistor QO switches from on to off in response to control from the driver 30. As a result, the output voltage Vo of the load terminal PNl drops from near the power supply voltage VCC, and the output current Io decreases at a rate according to the inductance of the load 12, etc.

[0043] Here, when the output transistor QO switches from on to off, the electromagnetic energy stored in the load 12 is released, and a back electromotive force is generated at the load terminal PNl. This causes the output voltage Vo to drop to a value lower than 0V. Then, when the drain-source voltage Vds of the output transistor QO exceeds the avalanche breakdown voltage Vab, the output voltage Vo is clamped to a value near the clamp voltage Vclp that is determined based on the avalanche breakdown voltage Vab. After that, when the output current Io decreases to 0A, that is, when the release of the electromagnetic energy is completed, the output voltage Vo rises from a value near the clamp voltage Vclp to 0V.

[0044] The transient switching period T3 is a period after the control input signal IN transitions from the "L" level to the "H" level at any timing ton while the output voltage Vo is clamped near the clamp voltage Vclp. In response to this transition of the control input signal IN from the "L" level to the "H" level, the output transistor QO switches from off to on. As a result, the output voltage Vo rises from near the clamp voltage Vclp toward near the power supply voltage VCC. Here, at timing ton, the output transistor QO switches on while the drain-source voltage Vds is large, and flows the output current Io. As a result, a large amount of power is generated in the output transistor QO.

[0045] FIG. 13B is a diagram showing the correspondence between the safe operating area (SOA) of the output transistor and the operation example of FIG. 13A. In FIG. 13B, the horizontal axis represents the drain-source voltage Vds of the output transistor QO, and the vertical axis represents the output current Io flowing through the output transistor QO. As shown in FIG. 13B, the safe operating area (SOA) is determined by the Rds line, the current limit line, the thermal limit line, and the secondary breakdown line. Strictly speaking, each of these lines changes depending on the time width of each operation. However, for simplicity, it is assumed here that the time width of each operation, that is, the length of each period T1 to T3 shown in FIG. 13A, is equal.

[0046] As shown in Fig. 13B, each operating point during the load-on period T1 is within the range of the SOA. Also, with regard to each operating point during the load-off period T2, some operating points may be outside the range of the SOA because they exceed the secondary breakdown line due to the back electromotive force. However, during the load-off period T2, the output transistor QO is off. Therefore, the output transistor QO is not destroyed.

[0047] On the other hand, if the output transistor QO switches from off to on at any timing ton while the drain-source voltage Vds is clamped near the clamp voltage Vclp during the load-off period T2, various operating points are generated during the transient switching period T3. At some operating points 40 during the transient switching period T3, the output transistor QO is turned on beyond the secondary breakdown line, i.e., outside the range of the SOA.

[0048] As a result, the output transistor QO may be destroyed. In particular, as shown in FIG. 4, in the output transistor QO in which the on-resistance is reduced by using a superjunction structure or the like, the SOA associated with the secondary breakdown line may become narrow. In this case, it may become more difficult to satisfy the SOA. In addition, in the method shown in Patent Document 1 or Patent Document 2, the output transistor QO is half-on in a state in which a back electromotive force is applied. This half-on timing may be the timing ton shown in FIG. 13B. In this case, there is a risk that the destruction of the output transistor QO cannot be sufficiently prevented.

[0049] <Details of the protection circuit> 5, the power device 20a includes a protection circuit 32a. The protection circuit 32a includes two current paths CP1n and CP2a formed between a power supply terminal PNv and a load terminal PNl, a current mirror circuit CMp1, and a control transistor MNc1 which is an nMOS transistor. A detection transistor MNd which is an nMOS transistor, and an adjustment resistor element R11 are inserted into the current path CP1n.

[0050] The gate and source of the detection transistor MNd are connected to the ground terminal PNg and the load terminal PNl, respectively, so that the detection transistor MNd passes a detection current IdN through the current path CP1n during a period when the output voltage Vo generated at the load terminal PNl is lower than the ground voltage GND, specifically, during a period when the output voltage Vo falls by the width of a threshold voltage (Vth) or more.

[0051] The current mirror circuit CMp1 includes a pMOS transistor MP11 which is the mirror source and a pMOS transistor MP12 which is the mirror destination. The current mirror circuit CMp1 transfers the detection current IdN flowing through the current path CP1n to the current path CP2a. Specifically, the pMOS transistor MP11 inputs the detection current IdN to its drain, and the pMOS transistor MP12 outputs a mirror current I2a which is proportional to the detection current IdN from its drain. The sources of the pMOS transistors MP11 and MP12 are connected to the power supply terminal PNv. The adjustment resistor R11 is provided between the pMOS transistor MP11 and the detection transistor MNd, and adjusts the magnitude of the detection current IdN.

[0052] A resistor R12 and a detection resistor Rd1 are inserted into the current path CP2a. One end of the detection resistor Rd1 is connected to the load terminal PNl. The detection resistor Rd1 converts the mirror current I2a flowing through the current path CP2a into a detection voltage Vd1. The resistor R12 is provided between the detection resistor Rd1 and the pMOS transistor MP12. The resistor R12 and the detection resistor Rd1 configure a resistive voltage divider circuit to adjust the magnitude of the detection voltage Vd1.

[0053] The gate and source of the control transistor MNc1 are connected to both ends of the detection resistor Rd1, respectively. As a result, the control transistor MNc1 is turned on during a period in which the detection voltage Vd1 converted by the detection resistor Rd1 is higher than a predetermined value, i.e., a threshold voltage (Vth). The output transistor QO is controlled to be off during a period in which the control transistor MNc1 is on.

[0054] Specifically, the control transistor MNc1 has a drain connected to the control node of the output transistor QO, i.e., the gate (G), and shorts out the control node of the output transistor QO and the load terminal PNl during the on-period. The control transistor MNc1 also has a higher driving capability than the driver 30, and is capable of passing a discharge current larger than the charge current from the driver 30.

[0055] During the on-period, the control transistor MNc1 shorts the control node of the output transistor QO and the load terminal PNl regardless of the operation of the driver 30. In detail, for example, even during the period in which the driver 30 controls the gate-to-source voltage Vgs of the output transistor QO to the on level, the control transistor MNc1 can control the output transistor QO to be off due to the difference in driving capability described above.

[0056] <Circuit Operation of Power Device (Embodiment 1)> FIG. 6 is a waveform diagram showing an example of the operation of the power device shown in FIG. 5. FIG. 6 shows an example of the operation in a load-on period T1, a load-off period T2, and a transient switching period T3, similar to the case of FIG. 13A. The load-on period T1 is a period during which the control input signal IN is at the “H” level and the output transistor QO is on. The load-off period T2 is a period during which the control input signal IN is at the “L” level and the output transistor QO is off. The transient switching period T3 is a period after the control input signal IN transitions from the “L” level to the “H” level at any timing ton while the output voltage Vo is clamped near the clamp voltage Vclp.

[0057] Here, in Fig. 6, the operation in the load-off period T2 and the transient switching period T3 is different from that in Fig. 13A. In the load-off period T2, when the output voltage Vo falls below a predetermined value in response to the switching of the output transistor QO from on to off, the detection transistor MNd switches from off to on. The predetermined value is "-|Vth|" using the threshold voltage Vth of the detection transistor MNd. When the detection transistor MNd switches from off to on, a detection current IdN flows through the current path CP1n.

[0058] When the detection current IdN flows, the current mirror circuit CMp1 causes a mirror current I2a to flow in the current path CP2a. The detection resistor Rd1 converts the mirror current I2a into a detection voltage Vd1. When the detection voltage Vd1 becomes larger than the threshold voltage (Vth) of the control transistor MNc1, the control transistor MNc1 switches from off to on, shorting the gate (G) and source (S) of the output transistor QO. As a result, the output transistor QO is controlled to an off level by the driver 30 (for example, the gate-source voltage Vgs is 0 V), and is also controlled to an off level by the control transistor MNc1.

[0059] After that, the drain-source voltage Vds of the output transistor QO exceeds the avalanche breakdown voltage Vab, and the output voltage Vo is clamped near the clamp voltage Vclp. The output transistor QO then flows an output current Io associated with the avalanche breakdown, thereby consuming the electromagnetic energy released from the load 12. When the control input signal IN transitions from the "L" level to the "H" level at the timing ton while the output voltage Vo is clamped near the clamp voltage Vclp, the period switches to the transient switching period T3.

[0060] At timing ton, the driver 30 passes a charging current through the gate (G) of the output transistor QO to control the gate-source voltage Vgs of the output transistor QO to an on level, for example, the level of the power supply voltage VCC. Meanwhile, since the gate-source voltage of the detection transistor MNd is greater than the threshold voltage Vth, the detection transistor MNd remains on. Here, the discharge current by the detection transistor MNd is greater than the charging current by the driver 30. Therefore, the gate-source voltage Vgs of the output transistor QO does not exceed the threshold voltage Vth, and the output transistor QO remains off.

[0061] Thereafter, when the output current Io decreases to 0 A, that is, when the load 12 has completed discharging electromagnetic energy, the output voltage Vo rises from near the clamp voltage Vclp. Then, when the output voltage Vo becomes higher than the above-mentioned predetermined value "-|Vth|", the detection transistor MNd switches from on to off. As a result, the detection current IdN becomes zero, and the control transistor MNc1 switches from on to off. In response to this, the gate-source voltage Vgs of the output transistor QO rises toward the on level due to the charging current from the driver 30, and the output transistor QO switches from off to on.

[0062] <Major Effects of the First Embodiment> As described above, the semiconductor device of the first embodiment is provided with the protection circuit 32a. As a result, during the period when a back electromotive force is generated at the load terminal PNl, that is, during the period when a large drain-source voltage Vds is applied to the output transistor QO, the output transistor QO can be kept off even if the control input signal IN is at the "H" level. During the period when the output transistor QO is kept off, the electromagnetic energy of the load 12 can be consumed by the avalanche breakdown of the output transistor QO.

[0063] In this way, by keeping the output transistor QO off during the period when the back electromotive force is generated at the load terminal PNl, it is possible to prevent the output transistor QO from being destroyed due to secondary breakdown. That is, it is possible to prevent the output transistor QO from being turned on or half-on at the operating point 40 outside the SOA range as described in FIG. 13B. In addition, this makes it easier to apply a superjunction structure, etc., and makes it easier to reduce the on-resistance of the output transistor QO. As a result, this can contribute to the speedup, lower power consumption, and improved reliability of engine control units (ECUs), etc.

[0064] (Embodiment 2) <Circuit configuration of power device (second embodiment)> Fig. 7 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to embodiment 2. A power device (semiconductor device) 20b shown in Fig. 7 differs from the case of Fig. 5 in the configuration of a driver 30b and the configuration of a protection circuit 32b. The protection circuit 32b in Fig. 7 differs from the protection circuit 32a in Fig. 5 in the connection destination of a current path CP2b, which is a mirror destination of a current mirror circuit CMp1, and the connection destination of a control transistor MNc2.

[0065] Unlike the case of Fig. 5, the current path CP2b is formed between the power supply terminal PNv and the ground terminal PNg. Accordingly, the detection resistor element Rd2 inserted in the current path CP2b has one end connected to the ground terminal PNg and the other end connected to the gate of the control transistor MNc2. The detection resistor element Rd2 converts the mirror current I2b flowing through the current path CP2b into a detection voltage Vd2.

[0066] The control transistor MNc2 has a source connected to the ground terminal PNg and a drain connected to the driver 30b. As a result, the control transistor MNc2 applies the ground voltage GND applied to the ground terminal PNg to the driver 30b during an on-period based on the detection voltage Vd2. During the period in which the ground voltage GND is applied from the control transistor MNc2, the driver 30b controls the gate-source voltage Vgs of the output transistor QO to an off level regardless of the control input signal IN.

[0067] More specifically, the drain of the control transistor MNc2 is connected to the power supply terminal PNv via, for example, a high-resistance resistor element (not shown). In this case, the ground voltage GND is applied to the driver 30b while the control transistor MNc2 is on, and the power supply voltage VCC is applied to the driver 30b while the control transistor MNc2 is off. During the period when the power supply voltage VCC is being applied from the control transistor MNc2 side, the driver 30b controls the gate-source voltage Vgs of the output transistor QO to an on level or an off level based on the control input signal IN.

[0068] In this embodiment, the ground voltage GND is applied to one end of the detection resistor Rd2 and the source of the control transistor MNc2, but other voltages may be applied to them. In other words, any configuration may be used as long as it can notify the driver 30b of the on / off state of the control transistor MNc2.

[0069] <Circuit Operation of Power Device (Embodiment 2)> Fig. 8 is a waveform diagram showing an example of the operation of the power device shown in Fig. 7. In the example of operation of Fig. 6 described above, in a period T31 from the timing ton to the timing when the detection transistor MNd switches from on to off, the driver 30 supplies a charging current to the gate (G) of the output transistor QO. As a result, as shown in Fig. 6, in the period T31, the gate-source voltage Vgs of the output transistor QO may rise slightly from the off level, for example, the 0V level, within a range smaller than the threshold voltage Vth.

[0070] If the gate-source voltage Vgs of the output transistor QO rises slightly, for example, the output transistor QO may become half-on. Meanwhile, in the operation example of Fig. 7, unlike the case of Fig. 6, in period T31, the driver 30b does not supply a charging current to the gate (G) of the output transistor QO, and controls the gate-source voltage Vgs of the output transistor QO to the off level.

[0071] <Major Effects of the Second Embodiment> As described above, the use of the semiconductor device of the second embodiment also provides the same effects as those described in the first embodiment. Furthermore, the output transistor QO can be more reliably kept off during the period when a back electromotive force is generated at the load terminal PNl. This makes it possible to more reliably prevent the output transistor QO from being destroyed by a secondary breakdown.

[0072] (Embodiment 3) <Circuit configuration of power device (third embodiment)> Fig. 9 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to a third embodiment. A power device (semiconductor device) 20c shown in Fig. 9 has a different configuration of a protection circuit 32c compared to the case of Fig. 5. Unlike the case of Fig. 5, the protection circuit 32c has a clamp element inserted in a current path CP1z which is the mirror source of the current mirror circuit CMp1. In this example, the clamp element is formed of a Zener diode ZD with the load terminal PNl side as the anode and the power supply terminal PNv side as the cathode.

[0073] The Zener diode ZD is conductive during a period when a clamp voltage, i.e., a voltage exceeding the Zener voltage Vzd, is applied to the cathode with respect to the anode. The Zener voltage Vzd is set to a value greater than the power supply voltage VCC. For example, when the power supply voltage VCC is 13V, the Zener voltage Vzd is set to 18V or the like. In this case, even if a back electromotive force is generated at the load terminal PNl, if the drain-source voltage Vds of the output transistor QO is smaller than the Zener voltage Vzd, the detection current Iz does not flow through the current path CP1z. On the other hand, when the drain-source voltage Vds of the output transistor QO becomes larger than the Zener voltage Vzd due to the back electromotive force, the detection current Iz flows through the current path CP1z.

[0074] When the detection current Iz flows through the current path CP1z, the current mirror circuit CMp1 causes a mirror current I2c to flow through the mirrored current path CP2c by the current mirror circuit CMp1. Thereafter, as in the case of FIG. 5, the detection resistor element Rd3 converts the mirror current I2c into a detection voltage Vd3. The control transistor MNc3 is switched on / off by the detection voltage Vd3. During the on period, the control transistor MNc3 shorts the gate (G) and source (S) of the output transistor QO. Note that in FIG. 9, the connection order of the Zener diode ZD and the adjustment resistor element R11 can be interchanged. Also, a clamp element similar to that in FIG. 9 may be provided in the configuration example of FIG. 7.

[0075] <Circuit Operation of Power Device (Embodiment 3)> Fig. 10 is a waveform diagram showing an example of the operation of the power device shown in Fig. 9. In Fig. 10, the condition for switching the control transistor MNc3 on / off, and therefore the condition for controlling the output transistor QO to be turned off by the control transistor MNc3, are different from those in Fig. 6. That is, in the case of Fig. 6, the detection transistor MNd turns on, turning on the control transistor MNc1, but in the case of Fig. 10, the Zener diode ZD becomes conductive, causing the detection current Iz to flow and turning on the control transistor MNc3.

[0076] This makes it possible to prevent a situation in which the protection circuit 32c malfunctions due to the detection transistor MNd being turned on when a negative voltage occurs at the load terminal PNl due to a factor other than the back electromotive force and which is not the normal factor, specifically a situation in which the output transistor QO is controlled to be off. For example, the following first to third cases can be cited as cases in which the detection transistor MNd is turned on due to a factor other than the normal factor. If the first to third cases occur, a situation may arise in which the output transistor QO cannot be controlled to be on when necessary.

[0077] In the first case, noise called BCI (Bulk Current Injection) or DPI (Direct RF Power Injection) may be continuously input to the load terminal PNl. In this case, a negative voltage may always be generated at the load terminal PNl. In the second case, the output voltage Vo may fluctuate due to ringing when recovering from an avalanche breakdown. In this case, a positive voltage may be generated at the load terminal PNl once, and then a negative voltage may be generated again. In the third case, as shown in FIG. 9, a freewheeling diode RD may be connected to the load terminal PNl. In this case, a negative voltage may be generated at the load terminal PNl due to the forward voltage of the freewheeling diode RD or external noise during freewheeling.

[0078] 9, even if the detection transistor MNd is turned on due to the first to third cases, the control transistor MNc3 will not be turned on unless the negative voltage generated at the load terminal PNl is large enough to be considered as a back electromotive voltage. In other words, the control transistor MNc3 is turned on only when a back electromotive voltage is generated at the load terminal PNl, and the output transistor QO is controlled to be turned off. As a result, even if a negative voltage is generated at the load terminal PNl due to the first to third cases, the protection circuit 32c can be prevented from malfunctioning.

[0079] 9, the detection transistor MNd serves to prevent the protection circuit 32c from malfunctioning when the power supply voltage VCC is higher than normal. In other words, if the detection transistor MNd is not provided, a detection current Iz will flow when a power supply voltage VCC higher than the Zener voltage Vzd is applied by a battery or the like. If the detection transistor MNd is provided, such a detection current Iz will not flow.

[0080] <Major Effects of the Third Embodiment> As described above, by using the semiconductor device of the third embodiment, it is possible to obtain the same effects as those described in the first embodiment. Furthermore, it becomes possible to prevent the protection circuit 32c from malfunctioning when a negative voltage occurs at the load terminal PNl due to a factor other than the back electromotive force.

[0081] (Embodiment 4) <Circuit configuration of power device (fourth embodiment)> Fig. 11 is a circuit diagram showing a configuration example of a main part of a power device in a semiconductor device according to embodiment 4. The power devices shown in the above-mentioned embodiments 1 to 3 are connected to the high side of load 12, whereas a power device 20d shown in Fig. 11 is connected to the low side of load 12.

[0082] The power device (semiconductor device) 20d shown in Fig. 11 includes a power supply terminal PNv, a control input terminal PNi, a ground terminal PNg, and a load terminal PNl, similar to the case of Fig. 5. However, unlike the case of Fig. 5, a power supply voltage VCC is applied to one end of a load 12, and the other end of the load 12 is connected to the load terminal PNl. The power device 20d also includes an output transistor QO, a driver 30d, a current limiting element 31d, and a protection circuit 32d. The drain (D) and source (S) of the output transistor QO are connected to the load terminal PNl and the ground terminal PNg, respectively.

[0083] 5, the power supply terminal PNv is also a power supply pad PDp. The load terminal PNl is also a drain electrode DE of the output transistor QO, and the ground terminal PNg is also a source pad PDs of the output transistor QO. The control input terminal PNi is also a control input pad PDi, as in the case of FIG. 5.

[0084] The driver 30d controls the gate-source voltage Vgs of the output transistor QO via a current limiting element 31d based on a control input signal IN from a control input terminal PNi. Unlike the case of Fig. 5, the driver 30d does not need to include a charge pump circuit, and may be configured to output, for example, a power supply voltage VCC or a ground voltage GND. The current limiting element 31d limits the charging / discharging current by the driver 30 using, for example, a resistor element.

[0085] The protection circuit 32d includes a current path CP1p formed between the load terminal PNl and the ground terminal PNg, two current paths CP2d1 and CP2d2 formed between the power supply terminal PNv and the ground terminal PNg, two current mirror circuits CMn1 and CMp2, and a control transistor MNc4 which is an nMOS transistor. A detection transistor MPd which is a pMOS transistor and an adjustment resistor element R21 are inserted into the current path CP1p.

[0086] The gate and source of the detection transistor MPd are connected to the power supply terminal PNv and the load terminal PNl, respectively, so that the detection transistor MPd passes a detection current IdP through the current path CP1p while the output voltage Vo generated at the load terminal PNl is higher than the power supply voltage VCC, specifically, while the output voltage Vo rises to a value equal to or greater than the threshold voltage (Vth).

[0087] The current mirror circuit CMn1 includes an nMOS transistor MN11, which is the mirror source, and an nMOS transistor MN12, which is the mirror destination. The current mirror circuit CMn1 transfers the detection current IdP flowing through the current path CP1p to the current path CP2d1. Specifically, the nMOS transistor MN11 inputs the detection current IdP to its drain, and the nMOS transistor MN12 outputs a mirror current I2d1 proportional to the detection current IdP from its drain. The sources of the nMOS transistors MN11 and MN12 are connected to the ground terminal PNg. The adjustment resistor R21 is provided between the detection transistor MPd and the nMOS transistor MN11, and adjusts the magnitude of the detection current IdP.

[0088] The current mirror circuit CMp2 includes a pMOS transistor MP21 which is the mirror source, and a pMOS transistor MP22 which is the mirror destination. The current mirror circuit CMp2 transfers the mirror current I2d1 flowing through the current path CP2d1 to the current path CP2d2. Specifically, the pMOS transistor MP21 inputs the mirror current I2d1 to its drain, and the pMOS transistor MP22 outputs a mirror current I2d2 proportional to the mirror current I2d1 from its drain. The sources of the pMOS transistors MP21 and MP22 are connected to the power supply terminal PNv.

[0089] A detection resistor element Rd4 is inserted in the current path CP2d2. One end of the detection resistor element Rd4 is connected to the ground terminal PNg. The detection resistor element Rd4 converts the mirror current I2d2 flowing through the current path CP2d2 into a detection voltage Vd4. The gate and source of the control transistor MNc4 are connected to both ends of the detection resistor element Rd4, respectively. As a result, the control transistor MNc4 is turned on during a period in which the detection voltage Vd4 converted by the detection resistor element Rd4 is higher than a predetermined value, i.e., a threshold voltage (Vth). The output transistor QO is controlled to be turned off during a period in which the control transistor MNc4 is on.

[0090] Specifically, the control transistor MNc4 has a drain connected to the control node of the output transistor QO, i.e., the gate (G), and shorts out the control node of the output transistor QO and the ground terminal PNg during the on-period. The control transistor MNc4 also has a higher driving capability than the driver 30d, and is capable of passing a discharge current larger than the charge current from the driver 30d.

[0091] During the ON period, the control transistor MNc4 shorts the control node of the output transistor QO and the ground terminal PNg regardless of the operation of the driver 30d. In detail, for example, even during a period in which the driver 30d controls the gate-to-source voltage Vgs of the output transistor QO to an ON level, the control transistor MNc4 can control the output transistor QO to be OFF due to the difference in driving capability described above.

[0092] <Circuit Operation of Power Device (Fourth Embodiment)> Fig. 12 is a waveform diagram showing an example of the operation of the power device shown in Fig. 11. In Fig. 12, the polarity of the output voltage Vo is different from that in Fig. 5. That is, during the load-on period T1, the output voltage Vo is controlled to be near 0V, that is, near the ground voltage GND, via the output transistor QO that is on. Also, when the load-on period T1 switches to the load-off period T2 in response to the transition of the control input signal IN from the "H" level to the "L" level, a positive counter-electromotive voltage is generated at the load terminal PNl.

[0093] As a result, the output voltage Vo rises from near the ground voltage GND. When the output voltage Vo becomes higher than a predetermined value, the detection transistor MPd switches from off to on. The predetermined value is "VCC+|Vth|" using the power supply voltage VCC and the threshold voltage Vth of the detection transistor MPd. In addition, in the output transistor QO, an avalanche breakdown occurs due to the back electromotive force, and the output voltage Vo is clamped near the positive clamp voltage Vclp. The output transistor QO consumes the electromagnetic energy released from the load 12 by passing an output current Io associated with the avalanche breakdown.

[0094] Thereafter, at timing ton during which the output voltage Vo is clamped near the clamp voltage Vclp, the control input signal IN transitions from the "L" level to the "H" level, switching from the load-off period T2 to the transient switching period T3. However, at timing ton, the detection transistor MPd is on, so the output transistor QO remains off. Thereafter, when the discharge of electromagnetic energy from the load 12 is completed and the output voltage Vo falls below the aforementioned predetermined value "VCC+|Vth|", the detection transistor MPd switches from on to off. As a result, the output transistor QO is controlled to be on by the driver 30d.

[0095] The configuration example shown in FIG. 11 can be modified to the configuration example shown in FIG. 7. In this case, the drain of the control transistor MNc4 can be connected to the driver 30d. The configuration example shown in FIG. 11 can also be modified to the configuration example shown in FIG. 9. In this case, a clamp element can be inserted in the current path CP1p. Specifically, the clamp element can be, for example, a Zener diode ZD with the anode on the ground terminal PNg side and the cathode on the load terminal PNl side.

[0096] <Major Effects of the Fourth Embodiment> As described above, by using the semiconductor device of the fourth embodiment, the same effects as those described in the first embodiment can be obtained.

[0097] The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above-mentioned embodiments and can be modified in various ways without departing from the gist of the invention. For example, the above-mentioned embodiments have been described in detail to easily explain the present invention, and the present invention is not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0098] 12 Load 20, 20a to 20d Power devices (semiconductor devices) 30,30b,30d Driver CHP Semiconductor Chip CMp1, CMp2, CMn1 current mirror circuit CP1n, CP1z, CP1p, CP2a to CP2c, CP2d1, CP2d2 current path GND Ground voltage (low potential power supply voltage) IN Control input signal IdN, IdP, Iz detection current MNc1~MNc4 control transistors MNd,MPd Detection transistor PNg Ground terminal (low potential power supply terminal) PNl load terminal PNv power supply terminal (high potential power supply terminal) QO Output Transistor R11, R21 Adjustment resistor element Rd1~Rd4 Detector resistor elements VCC power supply voltage (high potential power supply voltage) Vd1~Vd4 detection voltage Vo output voltage ZD Zener diode

Claims

1. a first power supply terminal to which a first power supply voltage on a high potential side is applied; a second power supply terminal to which a second power supply voltage on a low potential side is applied; A load terminal connected to a load; an output transistor connected to the first power supply terminal and the load terminal, the output transistor being turned on / off based on a control voltage between a control node and the load terminal; a driver for controlling the control voltage of the output transistor based on a control input signal; a first current path formed between the first power supply terminal and the load terminal; a detection transistor that is inserted in the first current path and that passes a detection current through the first current path during a period in which an output voltage generated at the load terminal is lower than the second power supply voltage; a current mirror circuit that copies the detection current flowing through the first current path to a second current path; a detection resistor element that is inserted in the second current path and converts a current flowing through the second current path into a detection voltage; a control transistor that is turned on during a period in which the detection voltage converted by the detection resistor element is higher than a predetermined value; Equipped with the output transistor is controlled to be turned off during a period in which the control transistor is turned on; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the detection resistance element has one end connected to the load terminal and the other end connected to a control node of the control transistor, the control transistor shorts the control node of the output transistor and the load terminal during an on-period; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the control transistor has a driving capability higher than that of the driver, and shorts the control node of the output transistor and the load terminal during an on-period regardless of the operation of the driver; Semiconductor device.

4. 2. The semiconductor device according to claim 1, the detection resistor element has one end connected to the second power supply terminal and the other end connected to a control node of the control transistor, the control transistor applies the second power supply voltage, which is applied to the second power supply terminal, to the driver during an on-period; the driver controls the control voltage of the output transistor to an off level during a period in which the second power supply voltage is applied from the control transistor; Semiconductor device.

5. 2. The semiconductor device according to claim 1, an adjustment resistor element that is inserted in the first current path and adjusts the magnitude of the detection current; Semiconductor device.

6. 2. The semiconductor device according to claim 1, a clamp element that is inserted in the first current path and is conductive during a period when a voltage exceeding a clamp voltage is applied to both ends of the clamp element; the clamp voltage is set to a value greater than a difference voltage between the first power supply voltage and the second power supply voltage; Semiconductor device.

7. The semiconductor device according to any one of claims 1 to 6, The semiconductor device is composed of one semiconductor chip. Semiconductor device.

8. a first power supply terminal to which a first power supply voltage on a high potential side is applied; a second power supply terminal to which a second power supply voltage on a low potential side is applied; A load terminal connected to a load; an output transistor connected to the load terminal and the second power supply terminal, the output transistor being turned on / off based on a control voltage between a control node and the second power supply terminal; a driver for controlling the control voltage of the output transistor based on a control input signal; a first current path formed between the load terminal and the second power supply terminal; a detection transistor that is inserted in the first current path and that passes a detection current through the first current path during a period in which an output voltage generated at the load terminal is higher than the first power supply voltage; a current mirror circuit that copies the detection current flowing through the first current path to a second current path; a detection resistor element that is inserted in the second current path and converts a current flowing through the second current path into a detection voltage; a control transistor that is turned on during a period in which the detection voltage converted by the detection resistor element is higher than a predetermined value; Equipped with the output transistor is controlled to be turned off during a period in which the control transistor is turned on; Semiconductor device.

9. 9. The semiconductor device according to claim 8, the detection resistor element has one end connected to the second power supply terminal and the other end connected to a control node of the control transistor, the control transistor shorts the control node of the output transistor and the second power supply terminal during an on-period; Semiconductor device.

10. 10. The semiconductor device according to claim 9, the control transistor has a higher driving capability than the driver, and shorts the control node of the output transistor and the second power supply terminal during an on-period regardless of the operation of the driver; Semiconductor device.

11. 9. The semiconductor device according to claim 8, the detection resistor element has one end connected to the second power supply terminal and the other end connected to a control node of the control transistor, the control transistor applies the second power supply voltage, which is applied to the second power supply terminal, to the driver during an on-period; the driver controls the control voltage of the output transistor to an off level during a period in which the second power supply voltage is applied from the control transistor; Semiconductor device.

12. 9. The semiconductor device according to claim 8, an adjustment resistor element that is inserted in the first current path and adjusts the magnitude of the detection current; Semiconductor device.

13. 9. The semiconductor device according to claim 8, a clamp element that is inserted in the first current path and is conductive during a period when a voltage exceeding a clamp voltage is applied to both ends of the clamp element; the clamp voltage is set to a value greater than a difference voltage between the first power supply voltage and the second power supply voltage; Semiconductor device.

14. The semiconductor device according to any one of claims 1 to 13, The semiconductor device is composed of one semiconductor chip. Semiconductor device.

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