Method, apparatus, device and computer program for training a lithography mask generation model

Abstract

The embodiments of the present application provide a method, device, equipment, and storage medium for training a lithography mask generation model, which relates to the technical fields of chips and machine learning. The method includes: generating a predicted mask map corresponding to a chip layout by a lithography mask generation model (301); generating a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, where the wafer pattern generation model is a machine learning model constructed based on a neural network (302); determining a model accuracy evaluation index based on the predicted mask map, determining a mask quality evaluation index based on the predicted wafer pattern, determining a training loss based on the model accuracy evaluation index and the mask quality evaluation index (303); and adjusting parameters of the lithography mask generation model based on the training loss (304). The technical solution provided by the embodiments of the present application improves the training efficiency of the lithography mask generation model.

Description

[Technical field]

[0001] The embodiments of the present application relate to the technical fields of chips and machine learning, and in particular to a method, an apparatus, a device, and a storage medium for training a lithography mask generation model.

[0002] This application claims priority to a Chinese patent application bearing application number 202210673948.8, filed on June 14, 2022, and entitled "Method, apparatus, device, and storage medium for training a lithography mask generation model," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] During the chip production process, it is necessary to perform the lithography process exposure by obtaining a mask map corresponding to each chip layout.

[0004] In the related technology, a lithography mask generation model will generate a predicted mask map in a training process, and in the training process of the lithography mask generation model, a lithography physical model (Lithography Simulation, LS) needs to be adopted to generate a wafer pattern corresponding to the predicted mask map, thereby updating the lithography mask generation model.

[0005] In the above related art, the process of generating a wafer pattern using a lithography physical model is relatively complicated, and the generation speed is relatively slow, which affects the training efficiency of the lithography mask generation model. Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments of the present application provide a method, device, apparatus and storage medium for training a lithography mask generation model, which can improve the training efficiency of the lithography mask generation model.

[0007] According to one aspect of an embodiment of the present application, there is provided a method for training a lithography mask generation model, the method being executed by a computer device, the method comprising: generating a predicted mask map corresponding to a chip layout by a lithography mask generation model, the lithography mask generation model being a neural network model used to generate the predicted mask map; generating a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, the wafer pattern generation model being a machine learning model constructed based on a neural network; determining a model accuracy evaluation metric based on the predicted mask map and determining a mask quality evaluation metric based on the predicted wafer pattern, where the model accuracy evaluation metric is used to characterize a mask prediction accuracy of the lithography mask generation model and the mask quality evaluation metric is used to characterize a quality of the predicted mask map; determining a training loss based on the model accuracy evaluation metric and the mask quality evaluation metric; and adjusting parameters of the lithography mask generation model based on the training loss.

[0008] According to one aspect of an embodiment of the present application, there is provided an apparatus for training a lithography mask generation model, the apparatus comprising: A mask generation module is used for generating a predicted mask map corresponding to a chip layout according to a lithography mask generation model, the lithography mask generation model being a neural network model used for generating the predicted mask map; A pattern generation module is used to generate a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, the wafer pattern generation model being a machine learning model constructed based on a neural network; a loss determination module used for determining a model accuracy evaluation index based on the predicted mask map and for determining a mask quality evaluation index based on the predicted wafer pattern, wherein the model accuracy evaluation index is used to characterize a mask prediction accuracy of the lithography mask generation model, and the mask quality evaluation index is used to characterize a quality of the predicted mask map, and the loss determination module determines a training loss based on the model accuracy evaluation index and the mask quality evaluation index; and a parameter adjustment module adapted to adjust parameters of the lithography mask generation model based on the training loss.

[0009] According to one aspect of an embodiment of the present application, a computer device is provided, the computer device including a processor and a memory, a computer program is stored in the memory, and the computer program is loaded and executed by the processor to realize the training method of the lithography mask generation model.

[0010] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, and the computer program is loaded and executed by a processor to realize the training method for the lithography mask generation model.

[0011] According to one aspect of an embodiment of the present application, a computer program product is provided, the computer program product including a computer program, the computer program being stored in a computer readable storage medium, a processor of a computer device reads the computer program from the computer readable storage medium, and the processor executes the computer program to cause the computer device to perform the method for training the lithography mask generation model.

[0012] The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

[0013] In the process of training the lithography mask generation model, a machine learning model constructed based on the pre-trained neural network is adopted to generate a predicted wafer pattern, and a training loss is determined based on the generated predicted wafer pattern to update the parameters of the lithography mask generation model. By adopting the neural network model to generate the predicted wafer pattern, the required calculation amount is smaller and the calculation efficiency is higher than that of adopting a lithography physical model to generate the predicted wafer pattern, thus saving the time required for generating the predicted wafer pattern, and thereby improving the training efficiency of the lithography mask generation model. [Brief description of the drawings]

[0014] [Figure 1] 1 is a flowchart of a method for training a lithography mask generation model provided by one embodiment of the present application. [Diagram 2] FIG. 1 is a schematic diagram of a model training system provided by one embodiment of the present application. [Diagram 3] 4 is a flowchart of a method for training a lithography mask generation model provided by another embodiment of the present application. [Figure 4] 4 is a flowchart of a method for training a lithography mask generation model provided by another embodiment of the present application. [Diagram 5]4 is a flowchart of a method for training a lithography mask generation model provided by another embodiment of the present application. [Figure 6] 4 is a flowchart of a method for training a lithography mask generation model provided by another embodiment of the present application. [Figure 7] FIG. 1 is a schematic diagram showing a wafer pattern generation model and a complexity assessment model provided in one embodiment of the present application sharing a feature extraction network. [Figure 8] 1 is a block diagram of an apparatus for training a lithography mask generation model provided by one embodiment of the present application. [Figure 9] 1 is a block diagram of an apparatus for training a lithography mask generation model provided by one embodiment of the present application. [Figure 10] 1 is a block diagram of a computer device provided by one embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Artificial Intelligence (AI) is the theory, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, sense the environment, acquire knowledge, and use knowledge to obtain optimal results. In other words, AI is a comprehensive technology of computer science that aims to produce a new kind of intelligent machine that can grasp the essence of intelligence and react in a manner similar to human intelligence. AI is the study of the design principles and realization methods of various intelligent machines, and to give machines the functions of sensing, reasoning, and decision-making.

[0016] Artificial intelligence technology is a comprehensive discipline with a wide range of related fields, including hardware and software technologies. The basic technologies of artificial intelligence generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operating / interaction systems, mechatronics, etc. Artificial intelligence software technology mainly includes several major directions such as computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0017] Machine learning (ML) is a multidisciplinary field that involves multiple disciplines such as probability theory, statistics, approximation theory, convex analysis, and algorithmic complexity theory. It specializes in the study of how computers can acquire new knowledge or skills by simulating or realizing human learning behavior, and reorganize existing knowledge structures to continuously improve their own performance. Machine learning is the core of artificial intelligence and is the fundamental method of making computers intelligent, and its applications are widespread in each field of artificial intelligence. Machine learning and deep learning usually include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and imitation learning.

[0018] An embodiment of the present application employs machine learning techniques to train a lithography mask generation model, thereby enabling the lithography mask generation model to generate a predicted mask map with relatively high accuracy and provide a photomask for subsequent chip lithography processes.

[0019] The method provided by the embodiments of the present application can also be expanded and applied to other stages of integrated circuit design, such as chip logic circuit simulation, chip thermal transport simulation, chip performance detection, chip defect detection, light source-mask collaborative optimization, and other EDA (Electronic Design Automation) fields.

[0020] Fig. 1 of the present application provides a method for training a lithography mask generation model. As shown in Fig. 1, the method may include the following steps: pre-training a wafer pattern generation model 11 to obtain a pre-trained wafer pattern generation model 11; employing a lithography mask generation model 12 to perform mask prediction on a chip layout to generate a predicted mask map, and calculating a model accuracy evaluation index according to the difference between the predicted mask map and a standard mask map corresponding to the chip layout; employing the pre-trained wafer pattern generation model 11 to generate a predicted wafer pattern corresponding to the predicted mask map, and calculating a mask quality evaluation index according to the difference between the predicted wafer pattern and the chip layout; employing a lithography physical model to generate a plurality of wafer patterns corresponding to the predicted mask map according to a plurality of different process parameters; and determining a complexity evaluation index corresponding to the predicted mask map according to the difference between the plurality of wafer patterns; and training a lithography mask generation model 12 according to the model accuracy evaluation index, the mask quality evaluation index, and the complexity evaluation index.

[0021] Referring to FIG. 2, a schematic diagram of a model training system provided by one embodiment of the present application is shown. The model training system may be realized as a training system for a lithography mask generation model. The system 20 may include a model training device 13 and a model using device 14.

[0022] The model training device 13 may be an electronic device such as a personal computer, a server, an intelligent robot, or some other electronic device with relatively high computing power. The model training device 13 is used to train the lithography mask generation model 15. In the embodiment of the present application, the lithography mask generation model 15 is a neural network model used to generate a predicted mask map, and the model training device 13 adopts a machine learning method to train the lithography mask generation model 15, so that it has a relatively good performance.

[0023] The lithography mask generation model 15 that has completed the above-mentioned training can provide image processing results (i.e., automatic counting results) by being deployed and used in the model-using device 14. The model-using device 14 may be, for example, a terminal device such as a PC (Personal Computer), a tablet computer, a smartphone, a wearable device, an intelligent robot, a smart voice interaction device, a smart home appliance, an in-vehicle terminal, an aircraft, a medical device, or the like, or may be a server, and the present application is not limited thereto.

[0024] In some embodiments, as shown in FIG. 2, the lithography mask generation model 15 may include an encoding network 16 and a decoding network 17. In some embodiments, the encoding network 16 is an encoding network composed of a convolutional neural network. For example, the number of convolutional layers is 8, and after the chip layout is input, it passes through a multi-layered two-dimensional convolutional neural network. The eight convolutional layers include 8, 16, 32, 64, 128, 256, 512, and 1024 3×3 filters, respectively, and a batch normalization layer is established after each convolutional layer, and a corrected linear unit (ReLU) is used as the activation function. The final output (dimension (1,1,1024)) of the above eight layers of convolution is the input of the decoding network 17, and the decoding network 17 is composed of a multi-layered deconvolutional neural network. For example, the number of deconvolution layers is 8, the first 7 convolution layers respectively include 1024, 512, 256, 128, 64, 32, 16 3x3 filters, and a batch normalization layer is established after each deconvolution layer, and Leaky-ReLU is used as the activation function. Finally, a deconvolution layer consisting of one 3x3 filter and a sigmoid activation function provides a photomask with dimensions (256,256,1) and values ​​between 0 and 1, and then the photomask is binarized to obtain the final predicted photomask.

[0025] In some embodiments, the lithography mask generation model 15 is a U-shaped image division network U-Net, which includes an encoding network 16 and a decoding network 17, where the encoding network 16 is used to perform feature extraction (downsampling) on ​​the chip layout, and the decoding network 17 is used to perform upsampling and feature synthesis to obtain a predicted photomask. The computer device inputs the chip layout into the encoding network 16 and performs downsampling to obtain feature information corresponding to the chip layout. The computer device performs upsampling and feature synthesis on the feature information corresponding to the chip layout through the decoding network 17 to obtain a predicted mask map corresponding to the chip layout.

[0026] The embodiments of the present application can be applied to various scenarios, including but not limited to chip design, cloud technology, artificial intelligence, chip manufacturing, smart transportation, driving assistance, etc.

[0027] The technical solutions of the present application are introduced and described below through several embodiments.

[0028] Referring to Figure 3, it shows a flow chart of a training method for a lithography mask generation model provided by one embodiment of the present application. In this embodiment, the method is enumerated and described as being applied to the model training device introduced above. The method may include the following steps (301 to 304).

[0029] Step 301: Generate a predicted mask map corresponding to a chip layout by a lithography mask generation model.

[0030] The lithography mask generation model is a model that needs to be trained in embodiments of the present application. In some embodiments, a chip layout is input into the lithography mask generation model, and the lithography mask generation model generates a predicted mask map corresponding to the chip layout.

[0031] Here, the chip layout may be a labeled chip design layout, i.e., the chip layout may be a simulated layout. The labeled chip design layout refers to a chip layout for which a corresponding standard mask map has been generated.

[0032] A chip layout may be an integrated circuit layout, which is a description of the planar geometry in the physical context of a real integrated circuit. An integrated circuit layout is the result of physical design at the lowest level of integrated circuit design. The physical design converts the result of logic synthesis into a layout file by placement and wiring techniques. The file includes the shape, area, and position information of each hardware unit on the chip. In some embodiments, the type of chip layout may be classified according to the chip layer corresponding to the chip layout, such as a connecting layer, a metal wiring layer, etc. In some embodiments, the type of chip layout may be classified according to the application field, such as a quantum chip, a home appliance chip, a mobile phone chip, a personal computer chip, a wearable device chip, and an industrial robot chip.

[0033] The standard mask map refers to the mask map obtained by OPC (optical proximity correction) of the chip layout, and the standard mask map is the label of the labeled chip layout. Optical proximity correction refers to using a calculation method to correct the features on the photomask so that the features projected on the photoresist match the design requirements as much as possible, and is a kind of lithography resolution enhancement technology. In the lithography process, the features on the mask are projected onto the photoresist by the exposure system, but due to the imperfection of the optical system and the diffraction effect, the features on the photoresist and the features on the mask do not match perfectly. If these distortions are not corrected, they may change the electrical performance of the produced circuit to a relatively large extent. Optical proximity correction is a kind of technology that adjusts the topological structure of the features of the light-transmitting area on the lithography mask or adds auxiliary features below the fine resolution on the mask to make the imaging result in the photoresist as close as possible to the mask features. The OPC technology is also a kind of technology that further compensates for the deterioration of the imaging quality of the lithography system by changing the amplitude of the mask transmitted light. OPC is primarily used in the production process of semiconductor devices.

[0034] Step 302: Generate a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, where the wafer pattern generation model is a machine learning model constructed based on a neural network.

[0035] In some embodiments, for a pre-trained wafer pattern generation model, a corresponding predicted wafer pattern can be generated based on the mask map, i.e., when the predicted mask map is input to the pre-trained wafer pattern generation model, the pre-trained wafer pattern generation model can output a predicted wafer pattern corresponding to the predicted mask map.

[0036] The wafer pattern generation model is a neural network model used to generate a predicted wafer pattern, and the wafer pattern generation model can have relatively good performance by adopting a machine learning method to train the wafer pattern generation model.

[0037] In some embodiments, the wafer pattern generation model is a U-shaped image segmentation network U-Net. The U-Net includes an encoding network and a decoding network, where the encoding network is used to perform feature extraction (downsampling) on ​​the predicted mask map, and the decoding network is used to perform upsampling and feature synthesis to obtain a predicted wafer pattern. The computer device inputs the predicted mask map into the encoding network to perform downsampling to obtain feature information corresponding to the predicted mask map, and the computer device performs upsampling and feature synthesis on the feature information corresponding to the predicted mask map through the decoding network to obtain a predicted wafer pattern corresponding to the predicted mask map.

[0038] In some embodiments, the coding network in the wafer pattern generation model is a coding network composed of a convolutional neural network. For example, the number of convolutional layers is 8, and the predicted mask map is input and then passed through a multi-layered two-dimensional convolutional neural network. The eight convolutional layers include 8, 16, 32, 64, 128, 256, 512, and 1024 3×3 filters, respectively, and a batch normalization layer is established after each convolutional layer, and a corrected linear unit (ReLU) is used as the activation function. The final output (dimension (1,1,1024)) of the above eight layers of convolution is the input of the decoding network, and the decoding network is composed of a multi-layered deconvolutional neural network. Taking the number of deconvolution layers as an example, the first seven convolution layers contain 1024, 512, 256, 128, 64, 32, and 16 3×3 filters, respectively. A batch normalization layer is established after each deconvolution layer, and Leaky-ReLU is used as the activation function. Finally, a predicted wafer pattern corresponding to the predicted mask map is obtained.

[0039] Since the neural network model can very easily employ a processor (e.g., a CPU (Central Processing Unit)) to perform accelerated calculations, the time required for the calculations becomes shorter.

[0040] In some embodiments, a first data set is acquired, the first data set including at least one mask map sample and a standard wafer pattern corresponding to the mask map sample, and the first data set is employed to train a wafer pattern generation model to obtain a pre-trained wafer pattern generation model.

[0041] In some embodiments, the chip layout sample is subjected to OPC processing to obtain a mask map sample corresponding to the chip layout sample, and a second lithography physical model is used to obtain a standard wafer pattern corresponding to the mask map sample, the second lithography physical model being a mathematical physical simulation model based on optical principles, and a first data set is constructed based on the corresponding mask map sample and the standard wafer pattern, where the mask map sample refers to a mask map from which the corresponding standard wafer pattern is generated.

[0042] In some embodiments, the following loss function may be employed for training the wafer pattern generation model: L=|Wafer-Wafer pred | 2 (Wafer represents the wafer pattern obtained by the lithography physical model, and Wafer pred represents the wafer pattern predicted and obtained by the wafer pattern generation model, and L represents the loss function value.

[0043] In some embodiments, the lithography physics model (eg, the second lithography physics model) is a mathematical-physics simulation model based on optical principles.

[0044] Optionally, first input selected process parameters (e.g., standard process parameters) and a mask map into a lithography physics model, and the lithography physics model generates a light intensity distribution corresponding to the process parameters and the mask map, and then converts the light intensity distribution into a wafer pattern corresponding to the process parameters and the mask map by a sigmoid function.

[0045] In some embodiments, the lithography physics model is a Hopkins diffraction lithography physics model of a partially coherent imaging system. The light intensity distribution I imaged on the wafer obtained by the lithography physics model is obtained by convolving the mask map with a kernel function h of the lithography system, which is obtained by performing singular value decomposition on the cross transmission coefficients of the lithography system (e.g., a 193 nanometer annular source). In some embodiments, the lithography physics model is defined as follows:

[0046]

number

[0047] (where h k , and ω k are the k-th kernel function and corresponding weighting coefficient after singular value decomposition, respectively, (x, y) are data coordinates, M represents the mask, and I represents the light intensity distribution imaged on the lithography physical model. Optionally, the first 24 kernel functions and corresponding weighting coefficients after singular value decomposition can be adopted, i.e., K=24.

[0048] In some embodiments, the wafer pattern is obtained from the light intensity distribution imaged on the wafer by the following distribution function: Z(x,y)=1,I(x,y)≧I th Z(x,y)=0,I(x,y) th

[0049] In some embodiments, Z is the light intensity distribution imaged onto the wafer, and I th represents the intensity value, and I th is 0.225. Selectable, I th may take other values ​​in the interval [0,1], and the embodiment of the present application does not specifically limit it.

[0050] ​Step 303: determine a model accuracy evaluation index based on the predicted mask map, determine a mask quality evaluation index based on the predicted wafer pattern, and determine a training loss based on the model accuracy evaluation index and the mask quality evaluation index.

[0051] The model accuracy metric is used to characterize the mask prediction accuracy of the lithography mask generation model, and the mask quality metric is used to characterize the quality of the predicted mask map.

[0052] In some embodiments, for a chip layout, the mask prediction capability of the lithography mask generation model can be determined based on the predicted mask map and the predicted wafer pattern, and a training loss can be determined, where the training loss refers to a difference value between the predicted mask map and the predicted wafer pattern, and the training loss can be used to indicate the accuracy of the lithography mask generation model.

[0053] Step 304: Adjust parameters of the lithography mask generation model based on the training loss.

[0054] In some embodiments, the parameters of the lithography mask generation model are adjusted based on the training loss, and the lithography mask generation model is trained accordingly. When the training loss meets a training stopping condition, the training can be stopped and a trained lithography mask generation model can be obtained. In some embodiments, the training stopping condition includes at least one of the following: the number of model iterations reaches a set number, the gradient of the training loss is smaller than a threshold, the model accuracy evaluation index meets an accuracy threshold, the mask quality evaluation index meets a mask quality threshold, and the complexity evaluation index meets a complexity threshold.

[0055] In some embodiments, the disclosed lithography mask code dataset is used in the embodiments of the present application. For example, the lithography mask dataset is adopted from the datasets disclosed in the papers "GAN-OPC: Mask optimization with lithography-guided generative adversarial nets" and "Neural-ILT: Migrating ILT to neural networks for mask printability and complexity co-optimization". In these two datasets, there are a total of 10271 chip layouts and corresponding mask maps, and the chip layouts meet the 32 nanometer process node and certain design rules. Optionally, the mask maps in the above datasets are obtained by a reverse lithography mask optimization algorithm.

[0056] As described above, the technical solution provided by the embodiments of the present application, in the process of training a lithography mask generation model, employs a machine learning model constructed based on a pre-trained neural network to generate a predicted wafer pattern, and determines a training loss based on the generated predicted wafer pattern to update the parameters of the lithography mask generation model. Since the neural network model is employed to generate a predicted wafer pattern, the required calculation amount is smaller and the calculation efficiency is higher than that of employing a lithography physical model to generate a predicted wafer pattern, so the embodiments of the present application save the time required for generating a predicted wafer pattern, thereby improving the training efficiency of the lithography mask generation model.

[0057] As should be explained, on the one hand, the machine learning model based on the neural network adopted by the predicted wafer pattern is pre-trained, so the training process of the lithography mask generation model does not include the training process of the wafer pattern generation model, so that the time required for generating the predicted wafer pattern is saved, and the time required for training the lithography mask generation model is saved, so that the training efficiency of the lithography mask generation model is improved. On the other hand, the training of the wafer pattern generation model only requires the lithography physical model to generate standard wafer patterns corresponding to each of the mask map samples for a relatively small number of mask map samples, and then, in the process of adopting the pre-trained wafer pattern generation model to participate in the lithography mask generation model, the participation of the lithography physical model is not required. If the lithography physical model is adopted to generate the predicted wafer pattern, the predicted mask maps generated by the lithography mask generation model in each cycle are all different, so the lithography physical model needs to generate all of the wafer patterns corresponding to the predicted mask maps generated by the lithography physical model in each cycle. Under such circumstances, the number of wafer patterns that need to be generated based on the lithography physical model will be significantly increased, thereby increasing the time required for training the lithography mask generation model and reducing the training efficiency of the lithography mask generation model.

[0058] For example, the label data set used to train the lithography mask generation model includes 10,000 labeled chip layouts, and the training cycle of the lithography mask generation model is 100 (i.e., 100 times iterations). If the lithography physical model is used to generate a predicted wafer pattern, for each chip layout, one predicted mask map is generated according to the lithography mask generation model in each cycle, and each predicted mask map needs to generate one wafer pattern according to the lithography physical model. Therefore, the lithography physical model needs to be used to generate 10,000×100 wafer patterns. If the wafer pattern generation model is first pre-trained, and then the pre-trained wafer pattern generation model is used to generate a predicted wafer pattern corresponding to the predicted mask map, then in the training process of the wafer pattern generation model, there will also be 10,000 label data in the corresponding label data set. That is, the label data set adopted for training the wafer pattern generation model contains 10000 labeled mask maps, that is, only by adopting the lithography physical model to generate the wafer patterns corresponding to these 10000 mask maps at most, the pre-trained wafer pattern generation model can be obtained. Obviously, when the pre-trained wafer pattern generation model is adopted to generate the predicted wafer pattern corresponding to the predicted mask map, and the lithography mask generation model is trained based on this, the number of wafer patterns that need to be generated by the lithography physical generation model is much smaller than the number of wafer patterns that need to be generated by the lithography physical generation model in the method of adopting the lithography physical model to generate the predicted wafer pattern (i.e., 10000 is much smaller than 10000×100), which saves the time required for generating the predicted wafer pattern, and thereby improves the training efficiency of the lithography mask generation model.

[0059] In some possible implementations, as shown in FIG. 4, the above step 303 further includes the following steps (3031 to 3033).

[0060] Step 3031: Calculate a model accuracy evaluation index based on a difference between the predicted mask map and a standard mask map corresponding to the chip layout, where the model accuracy evaluation index is used to characterize the mask prediction accuracy of the lithography mask generation model.

[0061] In some embodiments, the model accuracy evaluation index is generated based on the absolute difference between the predicted mask map and the standard mask map belonging to the same group, or the model accuracy evaluation index is generated based on the absolute percentage difference between the predicted mask map and the standard mask map belonging to the same group, or the model accuracy evaluation index is generated based on the median absolute difference between the predicted mask map and the standard mask map belonging to the same group, but is not limited thereto, and the embodiments of the present application are not specifically limited thereto.

[0062] Absolute percentage difference refers to the absolute difference between the predicted mask map and the standard mask map as a percentage of the standard mask map.

[0063] The median absolute difference refers to the median value among multiple absolute differences between the predicted mask map and the standard mask map.

[0064] In some embodiments, for a chip layout input to the lithography mask generation model, the difference between the predicted mask map and a high-quality standard mask map can be calculated to determine the mask prediction accuracy of the lithography mask generation model, i.e., to determine the mask prediction ability of the lithography mask generation model. The smaller the difference between the predicted mask map and the standard mask map, the higher the mask prediction accuracy of the lithography mask generation model; conversely, the larger the difference between the predicted mask map and the standard mask map, the lower the mask prediction accuracy of the lithography mask generation model.

[0065] Step 3032: Calculate a mask quality evaluation index based on the difference between the predicted wafer pattern and the chip layout, where the mask quality evaluation index is used to characterize the quality of the predicted mask map.

[0066] In some embodiments, a smaller difference between the predicted wafer pattern and the corresponding chip layout indicates a higher quality of the corresponding predicted mask map, and conversely, a larger difference between the predicted wafer pattern and the corresponding chip layout indicates a lower quality of the corresponding predicted mask map.

[0067] In some embodiments, generating the mask quality metric includes generating a subjective rating and generating an objective rating.

[0068] Subjective evaluation refers to evaluating the difference between the predicted wafer pattern and the corresponding chip layout based on an observer's subjective perception.

[0069] Objective evaluation refers to making an objective comparison based on image features of the predicted wafer pattern and the chip layout, thereby obtaining the difference between the predicted wafer pattern and the corresponding chip layout.

[0070] Step 3033: Determine a training loss based on the model accuracy evaluation index and the mask quality evaluation index.

[0071] In some embodiments, the training loss is obtained by adding (e.g., weighting) the numerical values ​​corresponding to the model accuracy metric and the mask quality metric.

[0072] In some embodiments, as shown in FIG. 5, the method further includes the following steps (3034-3035).

[0073] Step 3034: Obtain a complexity evaluation metric corresponding to the predicted mask map, where the complexity evaluation metric is used to characterize the complexity of the predicted mask map.

[0074] By adding a complexity evaluation metric in the training loss, the lithography mask generation model tends to generate predicted mask maps with lower complexity, thereby reducing the complexity of the predicted mask maps generated by the lithography mask generation model and further improving the manufacturability of the predicted mask maps.

[0075] In some embodiments, if there are many easily exposed microstructures (e.g., holes, protrusions, sawtooth, etc.) on the wafer in the predicted mask map, the complexity of the predicted mask map is relatively high. If there are no or relatively few easily exposed microstructures (e.g., holes, protrusions, sawtooth, etc.) on the wafer in the predicted mask map, the complexity of the predicted mask map is relatively low.

[0076] In some embodiments, the method further comprises the following steps (1-2):

[0077] 1. A first lithography physical model is employed to generate a plurality of wafer patterns corresponding to a predicted mask map based on a plurality of different process parameters, where the first lithography physical model is a mathematical physical simulation model based on optical principles.

[0078] In some embodiments, a wafer pattern corresponding to a plurality of different process parameters of the predicted mask map is generated, and the process parameters include two or more types, such as exposure dose, defocus, etc. Optionally, the types of process parameters and the specific values ​​of the process parameters can be set by relevant technical personnel based on the actual situation, and the embodiments of the present application do not specifically limit the same.

[0079] In some embodiments, a first lithography physics model is employed to generate a first wafer pattern corresponding to a predicted mask map based on a first process parameter, and the first lithography physics model is employed to generate a second wafer pattern corresponding to the predicted mask map based on a second process parameter, where an exposure dose of the first process parameter is less than an exposure dose of the second process parameter and a defocus of the first process parameter is less than a defocus of the second process parameter.

[0080] 2. Determine a complexity metric corresponding to the predicted mask map based on the differences between the multiple wafer patterns.

[0081] The simpler the predicted mask map is (i.e., the lower the complexity), the smaller the difference between the wafer patterns acquired under different process parameter conditions. The more complex the predicted mask map is, the larger the difference between the wafer patterns acquired under different process parameter conditions is. Therefore, the smaller the difference between the wafer patterns is, the lower the complexity (i.e., the simpler) of the corresponding predicted mask map is, and the larger the difference between the wafer patterns is, the more complex the corresponding predicted mask map is. Therefore, the difference between the wafer patterns acquired under different process parameter conditions makes it possible to easily and intuitively determine the complexity of the predicted mask map. For each predicted mask map, it is necessary to generate a wafer pattern corresponding to one predicted mask map based on the process parameters of each group. The process parameters may have two groups (i.e., each predicted mask map corresponds to two wafer patterns), three groups (i.e., each predicted mask map corresponds to three wafer patterns), four groups (i.e., each predicted mask map corresponds to four wafer patterns), five groups (i.e., each predicted mask map corresponds to five wafer patterns), etc., and the embodiment of the present application is not specifically limited thereto.

[0082] In some embodiments, a complexity evaluation index corresponding to the predicted mask map is calculated based on the difference between the first wafer pattern and the second wafer pattern, i.e., for each predicted mask map, its complexity evaluation index can be calculated using only two wafer patterns corresponding to different process parameters, which reduces the amount of calculation and time required for calculating the complexity evaluation index compared with adopting three, four, five or more wafer patterns to calculate the complexity evaluation index, and further improves the training efficiency of the lithography mask generation model.

[0083] In some embodiments, the complexity evaluation index is generated by an average difference value of the pattern difference between any two wafer patterns, or the complexity evaluation index is generated by a percentage difference value of the pattern difference between any two wafer patterns, or the complexity evaluation index is generated by a median difference value of the pattern difference between any two wafer patterns, but is not limited thereto, and the embodiments of the present application are not specifically limited thereto.

[0084] The average difference value refers to the average value of the pattern difference value between any two wafer patterns.

[0085] The difference value percentage refers to the percentage of the pattern difference values ​​between any two wafer patterns that are greater than a threshold value.

[0086] The median difference value refers to the median value among multiple pattern difference values ​​between any two wafer patterns.

[0087] In some embodiments, as shown in Fig. 6, a complexity evaluation model 18 that has completed pre-training generates a complexity evaluation index corresponding to the predicted mask map. Here, the complexity evaluation model 18 is a machine learning model constructed based on a neural network. That is, after the mask map is input into the complexity evaluation model, the complexity evaluation model can output a complexity evaluation index corresponding to the mask map.

[0088] In some embodiments, a complexity evaluation index corresponding to a predicted mask map is obtained by directly outputting the complexity evaluation model. A specific method includes: obtaining a second data set, the second data set including at least one mask map sample and a standard complexity evaluation index corresponding to the mask map sample; and employing the second data set to train a complexity evaluation model to obtain a pre-trained complexity evaluation model.

[0089] Similarly to using the pre-trained wafer pattern generation model to generate a predicted wafer pattern, on the one hand, the complexity evaluation index corresponding to the predicted mask map is obtained by directly outputting the complexity evaluation model. In this way, there is no need to generate a mask map based on the lithography physical model in the training process of the lithography physical model, which saves computation resources and computation time, and further improves the training efficiency of the lithography mask generation model. On the other hand, if the lithography physical model is used to generate a predicted wafer pattern corresponding to the predicted mask map, and the complexity evaluation index of the predicted mask map is determined based on the predicted wafer pattern, the predicted mask maps generated by the lithography mask generation model in each cycle are all different, so the lithography physical model needs to generate all the corresponding wafer patterns for the predicted mask maps generated by the lithography physical model in each cycle. Under such circumstances, the number of wafer patterns that need to be generated based on the lithography physical model will be significantly increased, which will increase the time required for training the lithography mask generation model and reduce the training efficiency of the lithography mask generation model. To train the complexity evaluation model, it is only necessary to use the lithography physics model to generate standard wafer patterns corresponding to each of the relatively small number of mask map samples. Then, in the process of adopting the complexity evaluation model that has completed pre-training to involve the lithography mask generation model, the involvement of the lithography physics model is not required, which saves the time required for generating wafer patterns and improves the training efficiency of the lithography mask generation model.

[0090] In some embodiments, a plurality of wafer patterns (e.g., the first wafer pattern and the above-mentioned second wafer pattern) corresponding to the predicted mask map are generated under different process parameter conditions of the predicted mask map by the wafer pattern generation model, and then a complexity evaluation index corresponding to the predicted mask map is determined based on the difference between the plurality of wafer patterns. In this way, a lithography physical model is adopted to generate a plurality of wafer patterns corresponding to the predicted mask map, so that the time required for generating the wafer pattern can be saved compared with determining the complexity evaluation index of the predicted mask map based on the plurality of wafer patterns, and the training efficiency of the lithography mask generation model can also be improved. However, compared with adopting an end-to-end complexity index generation model to directly output the corresponding complexity evaluation index after inputting the predicted mask map, the wafer pattern still needs to be generated, so that the time required for determining the complexity evaluation index corresponding to the predicted mask map is increased.

[0091] In some embodiments, the wafer pattern generation model and the complexity assessment model are both machine learning models based on neural networks, the wafer pattern generation model and the complexity assessment model share the same feature extraction network, the wafer pattern generation model includes a feature extraction network and a wafer pattern prediction network, the complexity assessment model includes a feature extraction network and a complexity assessment network, in some embodiments, the complexity assessment network processes feature information corresponding to the predicted mask map obtained by the feature extraction network to obtain a complexity assessment index corresponding to the predicted mask map.

[0092] In some embodiments, the wafer pattern generation model and the complexity evaluation model may share the coding network, or may share a part of the coding network. The part of the coding network that is shared is the same feature extraction network. For the predicted mask map generated by the lithography mask generation model, the wafer pattern generation model and the complexity evaluation model first share the same feature extraction network to perform feature extraction, and obtain shared features. Then, the shared features are input into the wafer pattern prediction network and the complexity evaluation network, respectively, so that the wafer pattern prediction network outputs the predicted wafer pattern of the predicted mask map, and the complexity evaluation network outputs the complexity evaluation index corresponding to the predicted mask map.

[0093] In this way, the wafer pattern generation model and the complexity assessment model share the feature extraction network, thereby reducing the memory area occupied by the two models and saving the total processing resources and time required for the operation of the two models, and further improving the training efficiency of the lithography mask generation model.

[0094] 7 shows a schematic diagram in which the wafer pattern generation model and the complexity evaluation model share a feature extraction network. The wafer pattern generation model and the complexity evaluation model share an encoding network 702, and the encoding network 702 refers to the same feature extraction network in the wafer pattern generation model and the complexity evaluation model. The predicted mask map 701 is input to the encoding network 702 to perform feature extraction, and a shared feature 703 shared by the wafer pattern generation model and the complexity evaluation model is obtained. The shared feature 703 is input to a wafer pattern prediction network 704 to generate a wafer pattern, and a predicted wafer pattern 706 corresponding to the predicted mask map 701 is obtained. The shared feature 703 is input to a complexity evaluation network 705 to output a complexity evaluation index 707 corresponding to the predicted mask map 701.

[0095] Step 3035: Determine a training loss based on the model accuracy evaluation index, the mask quality evaluation index, and the complexity evaluation index.

[0096] In some embodiments, the model accuracy metric, the mask quality metric, and the complexity metric are added (e.g., weighted added) to obtain the training loss.

[0097] In some embodiments, matrices corresponding to the first wafer pattern and the second wafer pattern are differentiated to obtain a first difference value matrix, and a determinant corresponding to the first difference value matrix is ​​squared to obtain a complexity evaluation index corresponding to the predicted mask map.

[0098] In some embodiments, the calculation of the training loss may refer to the following equation:

[0099]

number

[0100] (Here, L represents the training loss, L fit represents the model accuracy evaluation index, and L target-wafer represents the mask quality evaluation index, and L complex represents a complexity metric corresponding to the predicted mask map, α and β are adjustable parameters, Mask represents a standard mask map, and Mask pred represents the predicted mask map, and Wafer pred represents the predicted wafer pattern, and Target represents the chip layout.)

[0101] Here, [Equation 3] represents a wafer pattern (e.g., a first wafer pattern) acquired under process conditions with low exposure dose and low defocus. In some embodiments, low exposure dose refers to 98% of the normal exposure dose, and low defocus refers to 25 nm defocus. [Equation 4] represents a wafer pattern (e.g., a second wafer pattern) acquired under process conditions with high exposure dose and no defocus. In some embodiments, high exposure dose refers to 102% of the normal exposure dose. Under process conditions with low exposure dose and low defocus, many microstructures (e.g., holes, protrusions, sawtooth, etc.) of the mask map are not exposed on the wafer, i.e., no or very few microstructures in the mask map are generated on the first wafer pattern. Under process conditions with high exposure dose and no defocus, if many microstructures exist in the mask map, these microstructures are exposed on the wafer, i.e., most or all of the microstructures in the mask map are displayed on the second wafer pattern. Therefore, the smaller the difference between [Equation 3] and [Equation 4], the less microstructures of the predicted mask map are generated, that is, the lower the complexity of the predicted mask map.

[0102]

number

number

[0103] In some implementations, the specific values ​​corresponding to the low exposure, low defocus, and high exposure are not limited to the above examples, and can be set by relevant technicians based on actual conditions, and the embodiments of the present application do not specifically limit the same.

[0104] In some embodiments, the training loss is minimized by a gradient descent algorithm, where the gradient of the training loss is defined as follows:

[0105]

number

[0106] (Here, L represents the training loss, L fit represents the model accuracy evaluation index, and L target-wafer represents the mask quality evaluation index, and L complex represents a complexity evaluation metric corresponding to the predicted mask map, α and β are adjustable parameters, and Mask pred represents the predicted mask map, Z is the light intensity distribution value imaged on the wafer, and Z min represents the light intensity distribution value under low exposure conditions, [Equation 6] represents the light intensity distribution value under low defocus process conditions, and Z max represents the light intensity distribution value under high exposure conditions, [Equation 7] represents the light intensity distribution value under high defocus process conditions, I represents the light intensity distribution imaged on the lithography physical model, sig represents the variance analysis, w represents the neuron weight in the lithography mask generation model, and θ z is a constant, which may have a value of 50, and I th The value of may be 0.225, [Equation 8] and ω k respectively represent the kernel function of the k-th defocus lithography system and the corresponding weighting coefficient. K can take on a value of 24. defocus * is the kernel function H of the defocus lithography system. defocus , and [Number 9] is H defocus is flipped by 180°, [Equation 10] represents a matrix convolution operation, [Equation 11] represents multiplication of corresponding elements of a matrix, M represents a mask code, [Equation 12], exp is an exponential function, where θ M is a constant, and θ M may be 4.)

[0107]

number

number

number

number

number

number

number

[0108] In the above implementation, a training loss is determined based on a model accuracy evaluation index and a mask quality evaluation index, and a lithography mask generation model is trained based on the determined training loss, thereby making it possible to improve the model accuracy of the lithography mask generation model and the quality of the generated predicted mask map.

[0109] In addition, by adding a complexity evaluation metric in the training loss, the lithography mask generation model tends to generate predicted mask maps with lower complexity, thereby reducing the complexity of the predicted mask maps generated by the lithography mask generation model and further improving the manufacturability of the predicted mask maps.

[0110] The following are apparatus embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not described in the apparatus embodiments of the present application, please refer to the method embodiments of the present application.

[0111] Referring to FIG. 8, a block diagram of a training device for a lithography mask generation model provided by an embodiment of the present application is shown. The device has a function of implementing the above-mentioned example of the training method for a lithography mask generation model, and the above-mentioned function can be implemented by hardware, or can be implemented by hardware executing corresponding software. The device can be the model training device introduced above, or can be installed on the model training device. The device 800 can include a mask generation module 810, a pattern generation module 820, a loss determination module 830, and a parameter adjustment module 840.

[0112] The mask generation module 810 is used to generate a predicted mask map corresponding to a chip layout through a lithography mask generation model, and the lithography mask generation model is a neural network model used to generate the predicted mask map.

[0113] The pattern generation module 820 is used to generate a predicted wafer pattern corresponding to the predicted mask map using a pre-trained wafer pattern generation model, which is a machine learning model constructed based on a neural network.

[0114] The loss determination module 830 determines a model accuracy evaluation index based on the predicted mask map and determines a mask quality evaluation index based on the predicted wafer pattern, where the model accuracy evaluation index is used to characterize a mask prediction accuracy of the lithography mask generation model, and the mask quality evaluation index is used to characterize a quality of the predicted mask map, and determines a training loss based on the model accuracy evaluation index and the mask quality evaluation index.

[0115] The parameter adjustment module 840 is used to adjust parameters of the lithography mask generation model based on the training loss.

[0116] In some embodiments, as shown in FIG. 9, the loss determination module 830 includes an index calculation sub-module 831 and a loss determination sub-module 832.

[0117] The index calculation sub-module 831 is used for calculating a model accuracy evaluation index based on the difference between the predicted mask map and a standard mask map corresponding to the chip layout.

[0118] The index calculation sub-module 831 is further used for calculating a mask quality evaluation index based on the difference between the predicted wafer pattern and the chip layout.

[0119] The loss determination sub-module 832 is used to determine the training loss according to the model accuracy evaluation index and the mask quality evaluation index.

[0120] In some embodiments, as shown in FIG. 9, the apparatus 800 further includes an index acquisition module 850 .

[0121] The metric obtaining module 850 is used to obtain a complexity metric corresponding to the predicted mask map, and the complexity metric is used to characterize the complexity of the predicted mask map.

[0122] The loss determination sub-module 832 is used for determining the training loss based on the model accuracy evaluation index, the mask quality evaluation index, and the complexity evaluation index.

[0123] In some embodiments, as shown in FIG. 9, the index acquisition module 850 includes a pattern generation sub-module 851 .

[0124] The pattern generation sub-module 851 is used to generate a plurality of wafer patterns corresponding to the predicted mask map based on a plurality of different process parameters by employing a first lithography physical model, where the first lithography physical model is a mathematical physical simulation model based on optical principles.

[0125] The index calculation sub-module 831 is used for determining a complexity evaluation index corresponding to the predicted mask map based on the differences between the plurality of wafer patterns.

[0126] In some embodiments, as shown in FIG. 9, the pattern generation submodule 851 includes: generating a first wafer pattern corresponding to the predicted mask map based on first process parameters employing the first lithography physics model; employing the first lithography physical model to generate a second wafer pattern corresponding to the predicted mask map based on a second process parameter, where an exposure dose of the first process parameter is smaller than an exposure dose of the second process parameter and a defocus of the first process parameter is smaller than a defocus of the second process parameter.

[0127] The index calculation sub-module 831 is further used for calculating a complexity evaluation index corresponding to the predicted mask map based on the difference between the first wafer pattern and the second wafer pattern.

[0128] In some embodiments, as shown in FIG. 9, the index calculation submodule 831 includes: obtaining a first difference value matrix by subtracting matrices corresponding to the first wafer pattern and the second wafer pattern; and squaring a determinant corresponding to the first difference matrix to obtain a complexity metric corresponding to the predicted mask map.

[0129] In some embodiments, as shown in FIG. 9 , the index acquisition module 850 is used to generate a complexity evaluation index corresponding to the predicted mask map through a pre-trained complexity evaluation model, where the complexity evaluation model is a machine learning model constructed based on a neural network.

[0130] In some embodiments, as shown in FIG. 9, the apparatus 800 further includes a dataset acquisition module 860 and a model training module 870.

[0131] The data set acquisition module 860 is used to acquire a second data set, where the second data set includes at least one mask map sample and a standard complexity metric corresponding to the mask map sample.

[0132] The model training module 870 is used for adopting the second data set to train the complexity assessment model to obtain the pre-trained complexity assessment model.

[0133] In some embodiments, the wafer pattern generation model and the complexity assessment model share the same feature extraction network, the wafer pattern generation model includes the feature extraction network and the wafer pattern prediction network, and the complexity assessment model includes the feature extraction network and the complexity assessment network. As shown in FIG. 9 , the index acquisition module 850 is used to process feature information corresponding to the predicted mask map obtained by the feature extraction network through the complexity assessment network to obtain a complexity assessment index corresponding to the predicted mask map.

[0134] In some embodiments, as shown in FIG. 9 , the dataset acquisition module 860 is further used to acquire a first dataset, where the first dataset includes at least one mask map sample and a standard wafer pattern corresponding to the mask map sample.

[0135] The model training module 870 is further used for adopting the first data set to train the wafer pattern generation model to obtain the pre-trained wafer pattern generation model.

[0136] In some embodiments, as shown in FIG. 9, the dataset acquisition module 860 includes: performing an optical proximity correction (OPC) process on the chip layout sample to obtain a mask map sample corresponding to the chip layout sample; Obtaining a standard wafer pattern corresponding to the mask map sample by a second lithography physics model, the second lithography physics model being a mathematical physics simulation model based on optical principles; and and constructing the first data set based on the corresponding mask map samples and the standard wafer pattern.

[0137] As described above, the technical solution provided by the embodiments of the present application, in the process of training the lithography mask generation model, adopts a machine learning model built based on a pre-trained neural network to generate a predicted wafer pattern, and determines a training loss based on the generated predicted wafer pattern to update the parameters of the lithography mask generation model, and adopts a neural network model to generate a predicted wafer pattern, so that the required calculation amount is smaller and the calculation efficiency is higher than that of adopting a lithography physical model to generate a predicted wafer pattern. Therefore, the embodiments of the present application save the time required for generating a predicted wafer pattern, thereby improving the training efficiency of the lithography mask generation model.

[0138] As is necessary to explain, the above embodiment provides an apparatus that only lists and describes the division of each of the above functional modules when implementing its functions, but in actual applications, the above functions can be assigned to different functional modules as needed to complete them, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the above-described functions. In addition, since the above embodiment provides an apparatus that belongs to the same technical idea as the method embodiment, the specific implementation process thereof can be referred to the method embodiment for details, and therefore a detailed description thereof will be omitted here.

[0139] Referring to Figure 10, a structural block diagram of a computer device provided in one embodiment of the present application is shown, which is used to implement the training method for a lithography mask generation model provided in the above embodiment. Specifically, it is as follows:

[0140] The computer device 1000 includes a CPU 1001, a system memory 1004 including a RAM (Random Access Memory) 1002 and a ROM (Read-Only Memory) 1003, and a system bus 1005 connecting the system memory 1004 and the central processing unit 1001. The computer device 1000 further includes a basic I / O (Input / Output) system 1006 that assists in transmitting information between each device in the computer, and a mass storage device 1007 used to store an operating system 1013, application programs 1014, and other program modules 1015.

[0141] The basic input / output system 1006 includes a display 1008 used to display information, and input devices 1009, such as a mouse, keyboard, etc., used by a user to input information. Here, the display 1008 and input devices 1009 are connected to the central processing unit 1001 via an input / output controller 1010 connected to the system bus 1005. The basic input / output system 1006 may further include an input / output controller 1010 used to receive and process input from a number of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 1010 may further provide output to a display screen, a printer, or other type of output device.

[0142] The mass storage device 1007 is connected to the central processing unit 1001 via a mass storage controller (not shown) that is connected to the system bus 1005. The mass storage device 1007 and its associated computer readable media provide non-volatile storage for the computing device 1000. That is, the mass storage device 1007 may include a computer readable medium (not shown), such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0143] Without loss of generality, the computer readable media may include computer storage media and communication media. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology used for storing information such as computer readable instructions, data structures, program modules, or other data. Computer storage media may include RAM, ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory or other solid state memory, CD-ROM, DVD (Digital Video Disc) or other optical storage, cassettes, magnetic tape, magnetic disk storage, or other magnetic storage devices. Of course, those skilled in the art will appreciate that the computer storage media is not limited to the above types. The system memory 1004 and mass storage device 1007 may be collectively referred to as memory.

[0144] According to various embodiments of the present application, the computer device 1000 may further operate as a remote computer connected over a network, such as the Internet, etc. That is, the computer device 1000 may be connected to a network 1012 via a network interface unit 1011 connected over the system bus 1005, or may use the network interface unit 1011 to connect to other types of networks or remote computer systems (not shown).

[0145] In an exemplary embodiment, a computer-readable storage medium is further provided, wherein at least one program is stored in the storage medium, and the at least one program, when executed by a processor, realizes the method for training the lithography mask generation model.

[0146] Optionally, the computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disks, etc. Here, the Random-Access Memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0147] In an exemplary embodiment, a computer program product or a computer program is further provided, the computer program product or the computer program including computer instructions stored in a computer readable storage medium, the computer instructions being read by a processor of a computer device from the computer readable storage medium, the processor executing the computer instructions to cause the computer device to perform the method for training a lithography mask generation model. [Explanation of symbols]

[0148] 11 Wafer pattern generation model 12 Lithography mask generation model 13 Model training equipment 14 Model equipment 15 Lithography mask generation model 16 Coding Network 17 Decoding Network 18 Complexity Assessment Model 20 Systems 701 Predictive Mask Map 702 Coding Network 704 Wafer Pattern Prediction Network 705 Complexity Evaluation Network 706 Predicted Wafer Pattern 707 Complexity Evaluation Index 800 equipment 810 Mask Generation Module 820 Pattern Generation Module 830 Loss Determination Module 831 Index Calculation Submodule 832 Loss Determination Submodule 840 Parameter Adjustment Module 850 Index Acquisition Module 851 Pattern Generation Submodule 860 Dataset Acquisition Module 870 Model Training Module 1000 Computer Equipment 1001 Central Processing Unit 1004 System Memory 1005 System Bus 1006 (Input / Output) System 1006 Output System 1007 Mass storage equipment 1008 Display 1009 Input Device 1010 Input Output Controller 1010 Input / Output Controller 1011 Network Interface Unit 1012 Network 1013 Operating Systems 1014 Application Program 1015 Program Module 1008 Display

Claims

1. 1. A method for training a lithography mask generation model, the method being performed by a computing device, the method comprising: generating a predicted mask map corresponding to a chip layout by a lithography mask generation model, the lithography mask generation model being a neural network model used to generate the predicted mask map; generating a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, the wafer pattern generation model being a machine learning model constructed based on a neural network; determining a model accuracy evaluation metric based on the predicted mask map and determining a mask quality evaluation metric based on the predicted wafer pattern, where the model accuracy evaluation metric is used to characterize a mask prediction accuracy of the lithography mask generation model and the mask quality evaluation metric is used to characterize a quality of the predicted mask map; determining a training loss based on the model accuracy evaluation metric and the mask quality evaluation metric; and adjusting parameters of the lithography mask generation model based on the training loss.

2. determining a model accuracy evaluation index based on the predicted mask map and determining a mask quality evaluation index based on the predicted wafer pattern, calculating a model accuracy evaluation index based on a difference between the predicted mask map and a standard mask map corresponding to the chip layout; and calculating a mask quality metric based on differences between the predicted wafer pattern and the chip layout.

3. The method comprises: obtaining a complexity metric corresponding to the predicted mask map, the complexity metric being used to characterize a complexity of the predicted mask map; The step of determining the training loss based on the model accuracy evaluation metric and the mask quality evaluation metric comprises: The method of claim 1 , comprising determining the training loss based on the model accuracy metric, the mask quality metric, and the complexity metric.

4. The step of obtaining a complexity metric corresponding to the predicted mask map further comprises: generating a plurality of wafer patterns corresponding to the predicted mask map based on a plurality of different process parameters employing a first lithography physics model, the first lithography physics model being a mathematical-physical simulation model based on optical principles; and determining a complexity metric corresponding to the predicted mask map based on differences between the plurality of wafer patterns.

5. generating a plurality of wafer patterns corresponding to the predicted mask map based on a plurality of different process parameters employing a first lithography physics model, generating a first wafer pattern corresponding to the predicted mask map based on first process parameters employing the first lithography physics model; employing the first lithography physics model to generate a second wafer pattern corresponding to the predicted mask map based on second process parameters, where a dose of the first process parameter is less than a dose of the second process parameter and a defocus of the first process parameter is less than a defocus of the second process parameter; determining a complexity metric corresponding to the predicted mask map based on differences between the plurality of wafer patterns, comprising:

5. The method of claim 4, further comprising calculating a complexity metric corresponding to the predicted mask map based on differences between the first wafer pattern and the second wafer pattern.

6. the step of calculating a complexity metric corresponding to the predicted mask map based on a difference between the first wafer pattern and the second wafer pattern, comprising: obtaining a first difference matrix by subtracting matrices corresponding to the first wafer pattern and the second wafer pattern; and squaring a determinant corresponding to the first difference matrix to obtain a complexity metric corresponding to the predicted mask map.

7. The step of obtaining a complexity metric corresponding to the predicted mask map further comprises: The method of claim 3, further comprising: generating a complexity evaluation index corresponding to the predicted mask map by a pre-trained complexity evaluation model, the complexity evaluation model being a machine learning model constructed based on a neural network.

8. The method comprises: obtaining a second data set, the second data set including at least one mask map sample and a standard complexity metric corresponding to the mask map sample; The method of claim 7 , further comprising: employing the second data set to train the complexity assessment model to obtain the pre-trained complexity assessment model.

9. the wafer pattern generation model and the complexity assessment model share the same feature extraction network, the wafer pattern generation model includes the feature extraction network and a wafer pattern prediction network, and the complexity assessment model includes the feature extraction network and a complexity assessment network; The step of generating a complexity evaluation index corresponding to the predicted mask map by a pre-trained complexity evaluation model includes:

8. The method of claim 7, further comprising: processing, by the complexity evaluation network, feature information corresponding to the predicted mask map obtained by the feature extraction network to obtain a complexity evaluation index corresponding to the predicted mask map.

10. The method comprises: acquiring a first data set, the first data set including at least one mask map sample and a standard wafer pattern corresponding to the mask map sample; 2. The method of claim 1, further comprising: employing the first data set to train the wafer pattern generation model to obtain the pre-trained wafer pattern generation model.

11. The step of acquiring a first data set comprises: performing an optical proximity correction (OPC) process on the chip layout sample to obtain a mask map sample corresponding to the chip layout sample; obtaining a standard wafer pattern corresponding to the mask map sample by a second lithography physics model, the second lithography physics model being a mathematical physics simulation model based on optical principles; 11. The method of claim 10, further comprising constructing the first data set based on the corresponding mask map samples and the standard wafer pattern.

12. 1. An apparatus for training a lithography mask generation model, the apparatus comprising: A mask generation module is used for generating a predicted mask map corresponding to a chip layout according to a lithography mask generation model, the lithography mask generation model being a neural network model used for generating the predicted mask map; A pattern generation module is used to generate a predicted wafer pattern corresponding to the predicted mask map by a pre-trained wafer pattern generation model, the wafer pattern generation model being a machine learning model constructed based on a neural network; a loss determination module used for determining a model accuracy evaluation index based on the predicted mask map and for determining a mask quality evaluation index based on the predicted wafer pattern, wherein the model accuracy evaluation index is used to characterize a mask prediction accuracy of the lithography mask generation model, and the mask quality evaluation index is used to characterize a quality of the predicted mask map, and the loss determination module determines a training loss based on the model accuracy evaluation index and the mask quality evaluation index; a parameter adjustment module used for adjusting parameters of the lithography mask generation model based on the training loss.

13. The loss determination module includes an index calculation sub-module and a loss determination sub-module; The index calculation submodule is used for calculating a model accuracy evaluation index based on a difference between the predicted mask map and a standard mask map corresponding to the chip layout; the index calculation submodule is used for calculating a mask quality evaluation index based on a difference between the predicted wafer pattern and the chip layout; The apparatus of claim 12 , wherein the loss determination submodule is used for determining the training loss based on the model accuracy evaluation metric and the mask quality evaluation metric.

14. The apparatus further includes an index acquisition module; The indicator obtaining module is used for obtaining a complexity evaluation indicator corresponding to the predicted mask map, the complexity evaluation indicator being used for characterizing a complexity of the predicted mask map; The apparatus of claim 13 , wherein the loss determination submodule is used for determining the training loss based on the model accuracy metric, the mask quality metric, and the complexity metric.

15. The index acquisition module includes a pattern generation sub-module; the pattern generation submodule is used for generating a plurality of wafer patterns corresponding to the predicted mask map based on a plurality of different process parameters by employing a first lithography physics model, the first lithography physics model being a mathematical physics simulation model based on optical principles; 15. The apparatus of claim 14, wherein the metric calculation submodule is adapted to determine a complexity metric corresponding to the predicted mask map based on differences between the plurality of wafer patterns.

16. the pattern generation submodule is configured to generate a first wafer pattern corresponding to the predicted mask map based on first process parameters employing the first lithography physics model; the pattern generation submodule is used for generating a second wafer pattern corresponding to the predicted mask map based on a second process parameter by employing the first lithography physical model, wherein an exposure amount of the first process parameter is smaller than an exposure amount of the second process parameter, and a defocus amount of the first process parameter is smaller than a defocus amount of the second process parameter; 16. The apparatus of claim 15, wherein the metric calculation submodule is configured to calculate a complexity metric corresponding to the predicted mask map based on a difference between the first wafer pattern and the second wafer pattern.

17. the index calculation submodule is used for obtaining a first difference value matrix by subtracting matrices corresponding to the first wafer pattern and the second wafer pattern; The apparatus of claim 16 , wherein the metric calculation submodule is configured to: square a determinant corresponding to the first difference matrix to obtain a complexity evaluation metric corresponding to the predicted mask map.

18. A computer device including a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to realize the method for training a lithography mask generation model according to any one of claims 1 to 11.

19. A computer program causing a computer to execute the method for training a lithography mask generation model according to any one of claims 1 to 11.

Images