Determination device and switch system equipped with same

Abstract

Provided are a determination device and a switch system capable of suppressing power loss of a semiconductor switch. A determination device (2) is used for a semiconductor switch (1). The semiconductor switch (1) includes a junction-type field-effect transistor (10) having a gate (10G) and a source (10S) corresponding to the gate (10G). The determination device (2) includes a resistor (Rg) and a determination circuit (3). The resistor (Rg) has a first end and a second end. The first end of the resistor (Rg) is connected to the gate (10G). Where a predetermined variation within a range smaller than a gate drive voltage (Vo) applied between the second end of the resistor (Rg) and the source (10S) is present with respect to a gate-source voltage (Vgs) of the junction-type field-effect transistor (10), the determination circuit (3) determines that an overcurrent (I1) is flowing through the semiconductor switch (1).

Description

[Technical field]

[0001] The present disclosure relates to a determination device used in a semiconductor switch and a switch system including the same, and more particularly to a determination device for detecting an overcurrent used in a semiconductor switch and a switch system including the same. [Background technology]

[0002] Patent Document 1 discloses a protection circuit for a power semiconductor element. The protection circuit for a power semiconductor element disclosed in Patent Document 1 includes a drive circuit for driving the power semiconductor element, a current detection unit including a first resistor and an inductor connected in parallel, and a detection unit for detecting a short-circuit state of the power semiconductor element. One end of the first resistor and one end of the inductor are connected to one terminal of the power semiconductor element. The detection unit detects a short-circuit state of the power semiconductor element by comparing the voltage of one terminal of the power semiconductor element, which changes according to the current flowing through the first resistor and the inductor, with a short-circuit detection voltage. A reference potential of the drive circuit is connected to the other end of the first resistor and the other end of the inductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 225121 Summary of the Invention

[0004] In a determination device for detecting an overcurrent used in a semiconductor switch, it is sometimes desirable to reduce power loss in a path through which a main current of the semiconductor switch flows.

[0005] An object of the present disclosure is to provide a determination device for detecting an overcurrent in a semiconductor switch that is capable of suppressing power loss, and a switch system including the same.

[0006] A determination device according to one aspect of the present disclosure is used in a semiconductor switch. The semiconductor switch includes a junction field effect transistor having a gate and a source corresponding to the gate. The determination device includes a resistor and a determination circuit. The resistor has a first end and a second end. The first end of the resistor is connected to the gate. The determination circuit determines that an overcurrent is flowing through the semiconductor switch when a predetermined change occurs in the gate-source voltage of the junction field effect transistor within a range smaller than a gate drive voltage applied between the second end of the resistor and the source.

[0007] A switch system according to another aspect of the present disclosure includes a determination device and a semiconductor switch.

[0008] The determination device and switch system of the present disclosure make it possible to reduce power loss. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a switch system including a determination device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating the operation of the switch system including the determination device. [Figure 3A] FIG. 3A is an explanatory diagram of the operation of the switch system including the determination device according to the embodiment, when the switch is on and in a normal state. [Figure 3B] FIG. 3B is an explanatory diagram of the operation of the switch system including the determination device of the above, when the switch is on and an overcurrent flows. [Figure 3C] FIG. 3C is an explanatory diagram of the operation of the switch system including the determination device according to the embodiment, when the switch is in an off and normal state. [Figure 4] FIG. 4 is a circuit diagram of a switch system including a determination device according to the second embodiment. [Figure 5A] FIG. 5A is a circuit diagram of a first determination circuit in the determination device. [Figure 5B]FIG. 5B is a circuit diagram of a second determination circuit in the determination device. [Figure 6A] FIG. 6A is a circuit diagram showing another configuration example of the first determination circuit in the determination device. [Figure 6B] FIG. 6B is a circuit diagram showing another configuration example of the second determination circuit in the determination device. [Figure 7] FIG. 7 is a diagram illustrating the operation of a switch system including a determination device according to the third embodiment. [Figure 8] FIG. 8 is a diagram illustrating the operation of the switch system including the determination device. [Figure 9] FIG. 9 is a circuit diagram of a switch system including a determination device according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram illustrating the operation of the switch system including the determination device. [Figure 11] FIG. 11 is a diagram illustrating the operation of the switch system including the determination device. [Figure 12] FIG. 12 is a circuit diagram of a switch system including a determination device according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram illustrating the operation of the switch system including the determination device. [Figure 14] FIG. 14 is a circuit diagram of the main part of the determination device. [Figure 15] FIG. 15 is a circuit diagram of a switch system including a determination device according to the sixth embodiment. [Figure 16] FIG. 16 is a circuit diagram of a control circuit in a determination device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] First Embodiment 1 is a circuit diagram of a switch system 8 including a determination device 2 according to a first embodiment. In the following, the determination device 2 according to the first embodiment and the switch system 8 including the same will be described with reference to FIGS. 1 and 2.

[0011] (1) Overview The determination device 2 is used in the semiconductor switch 1.

[0012] The semiconductor switch 1 includes a junction field effect transistor 10 having a gate 10G and a source 10S corresponding to the gate 10G. The junction field effect transistor 10 has a drain 10D corresponding to the gate 10G. The determination device 2 is used to determine whether or not an overcurrent is flowing between a pair of main terminals of the semiconductor switch 1.

[0013] The determination device 2 includes a resistor Rg and a determination circuit 3. The resistor Rg has a first end and a second end. The first end of the resistor Rg is connected to the gate 10G. The determination circuit 3 determines that an overcurrent is flowing through the semiconductor switch 1 when a predetermined change occurs in the gate-source voltage Vgs of the junction field effect transistor 10 within a range smaller than the gate drive voltage Vo applied between the second end of the resistor Rg and the source 10S.

[0014] The switch system 8 includes a determination device 2 and a semiconductor switch 1. The switch system 8 further includes a DC power supply 5 and a drive circuit 6. The drive circuit 6 supplies a gate drive voltage Vo to the junction field effect transistor 10 via a resistor Rg. The determination device 2 further includes a control circuit 4. The control circuit 4 controls the semiconductor switch 1 based on the determination result of the determination circuit 3. Here, the control circuit 4 controls the drive circuit 6 based on the determination result of the determination circuit 3, thereby controlling the semiconductor switch 1.

[0015] (2) Components of the switch system (2.1) Semiconductor Switch The semiconductor switch 1 includes a junction field effect transistor 10 (hereinafter also referred to as a JFET 10). The JFET 10 is, for example, a GaN-based GIT (Gate Injection Transistor). The JFET 10 does not include a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0016] The JFET 10 includes, for example, a substrate, a buffer layer, a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a gate electrode, a drain electrode, and a p-type layer. The buffer layer is formed on the substrate. The first nitride semiconductor layer is formed on the buffer layer. The second nitride semiconductor layer is formed on the first nitride semiconductor layer. The source electrode, the gate electrode, and the drain electrode are formed on the second nitride semiconductor layer. The p-type layer is interposed between the gate electrode and the second nitride semiconductor layer. In the JFET 10, the second nitride semiconductor layer and the p-type layer form a diode Dgu (see FIG. 2). The gate 10G in the JFET 10 includes a gate electrode and a p-type layer. The source 10S in the JFET 10 includes a source electrode. The drain 10D in the JFET 10 includes a drain electrode. The substrate is, for example, a silicon substrate. The buffer layer is, for example, an undoped GaN layer. The first nitride semiconductor layer is, for example, an undoped GaN layer. The second nitride semiconductor layer is, for example, an undoped AlGaN layer. The p-type layer is, for example, a p-type AlGaN layer. The buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer may each contain impurities such as Mg, H, Si, C, and O that are inevitably mixed in during growth by MOVPE (Metal Organic Vapor Phase Epitaxy) or the like.

[0017] (2.2) Drive circuit The drive circuit 6 is connected to the gate 10G of the JFET 10. In the switch system 8 according to the first embodiment, the drive circuit 6 is connected to the gate 10G of the JFET 10 via a resistor Rg.

[0018] The drive circuit 6 is a circuit that applies a gate voltage to the gate 10G of the JFET 10. The drive circuit 6 outputs a gate drive voltage Vo that corresponds to the DC voltage supplied from the DC power supply 5.

[0019] The drive circuit 6 has a power supply terminal and a ground terminal. The ground terminal of the drive circuit 6 is connected to the source 10S of the JFET 10.

[0020] A DC power supply 5 having a high potential output end and a low potential output end is connected between the power supply terminal and the ground terminal of the drive circuit 6. The high potential output end of the DC power supply 5 is connected to the power supply terminal of the drive circuit 6. The low potential output end of the DC power supply 5 is connected to the ground terminal of the drive circuit 6. The output voltage of the DC power supply 5 is, for example, 12 V. The DC power supply 5 is an insulated power supply. Note that the DC power supply 5 is not a component of the drive circuit 6.

[0021] The drive circuit 6 includes, for example, a driver IC (Integrated Circuit). The driver IC is, for example, a CMOS (Complementary Metal-Oxide Semiconductor) inverter, and includes an anti-series circuit of a p-channel MOSFET and an n-channel MOSFET. This anti-series circuit is connected between a high-potential output terminal and a low-potential output terminal of a DC power supply 5. In this anti-series circuit, the drains of the p-channel MOSFET and the n-channel MOSFET are connected to each other, the source of the p-channel MOSFET is connected to the high-potential output terminal of the DC power supply 5, and the source of the n-channel MOSFET is connected to the low-potential output terminal of the DC power supply 5.

[0022] (2.3) Judgment device The determination device 2 includes a resistor Rg and a determination circuit 3. The resistor Rg is an element for determining the gate-source voltage Vgs applied between the gate 10G and the source 10S of the semiconductor switch 1 in the steady-on state of the semiconductor switch 1. The resistance value of Rg is, for example, 800 Ω. In the determination device 2, the first end of the resistor Rg is connected to the gate 10G of the JFET 10. Also, in the determination device 2, the second end of the resistor Rg is connected to the drive circuit 6. In short, the determination device 2 includes a resistor Rg connected between the drive circuit 6 and the gate 10G of the JFET 10. The determination circuit 3 determines that an overcurrent is flowing through the semiconductor switch 1 when there is a predetermined change in the gate-source voltage Vgs of the JFET 10 within a range smaller than the gate drive voltage Vo applied between the second end of the resistor Rg and the source 10S.

[0023] The predetermined change in the gate-source voltage Vgs includes, for example, a change determined by a threshold value. In this case, the determination circuit 3 uses, for example, a reference voltage Vref smaller than the gate drive voltage Vo as a threshold value, and determines that an overcurrent is flowing through the semiconductor switch 1 when the gate-source voltage Vgs becomes larger than the reference voltage Vref (when the condition Vref < Vgs < Vo is satisfied). Here, the overcurrent is a current larger than the rated current of the main current I1 flowing between a pair of main terminals (drain 10D, source 10S) of the semiconductor switch 1, and is, for example, a short-circuit current. The determination circuit 3 includes, for example, a comparator that compares the gate-source voltage Vgs and the reference voltage Vref.

[0024] The predetermined change in the gate-source voltage Vgs is not limited to a change determined by a threshold value, and may include a change determined by the amount of change in the gate-source voltage Vgs. Also, the amount of change may be the rate of change (dVgs / dt) of the gate-source voltage Vgs.

[0025] The control circuit 4 controls the drive circuit 6 based on the determination result of the determination circuit 3. The executing entity of the control circuit 4 (control unit) includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and a memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the executing entity of the control circuit 4 (control unit) in the present disclosure. The program may be pre-recorded in the memory of the computer system, or may be provided through an electric communication line, or may be recorded and provided in a non-transitory recording medium such as a memory card, an optical disk, or a hard disk drive (magnetic disk) that can be read by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large scale integrated circuit (LSI). The multiple electronic circuits may be integrated in one chip, or may be distributed among multiple chips. The multiple chips may be integrated in one device, or may be distributed among multiple devices.

[0026] (3) Operation An operation example of the switch system 8 will be described with reference to Fig. 2 and Fig. 3A to Fig. 3C. Fig. 2 and Fig. 3A to Fig. 3C are diagrams illustrating the operation of the switch system 8 including the determination device 2.

[0027] Figure 2 shows, on a schematic equivalent circuit of JFET 10, the voltage Vgu applied to the diode Dgu, the channel resistance Rchgd between the gate and drain of JFET 10, the channel resistance Rchgs between the gate and source of JFET 10, the voltage drop Vchgs across the channel resistance Rchgs, and the main gate-source current I1.

[0028] Fig. 3A is an explanatory diagram of normal operation when semiconductor switch 1 is in the on state and no overcurrent flows through semiconductor switch 1. Fig. 3B is an explanatory diagram of operation when an overcurrent flows through semiconductor switch 1. Fig. 3C is an explanatory diagram of normal operation when semiconductor switch 1 is in the off state and no overcurrent flows through the semiconductor switch.

[0029] The switch system 8 is used by connecting a load circuit between the drain 10D and the source 10S of the semiconductor switch 1. In the switch system 8, in a state where a gate-source voltage Vgs is applied to the gate 10G of the JFET 10 at a predetermined voltage (4V) higher than the threshold voltage (e.g., 3.2V) of the JFET 10 (i.e., in a state where Vgs=4V), a charging current Icha flows through the gate 10G of the JFET 10 at a predetermined current value (e.g., 10mA) as shown in FIG. 3A. In the switch system 8, for example, the output voltage Vc of the DC power supply 5 is 12V, the gate drive voltage Vo is 12V, the threshold voltage of the JFET 10 is 3.2V, the predetermined voltage is 4V, the resistance value of the resistor Rg is 1kΩ, the predetermined current value is 10mA, and the reference voltage Vref is 4.5V, but is not limited to these values.

[0030] When the main current I1 flowing between the drain and source of the JFET 10 becomes an overcurrent, the voltage drop Vchgs at the channel resistance Rchgs increases. As a result, in the JFET 10, the voltage Vgu applied to the diode Dgu decreases. When the voltage Vgu decreases, the forward current flowing through the diode Dgu decreases, so that the charging current Icha decreases to 1 mA, as shown in FIG. 3B. If the decrease in the charging current Icha is ΔIcha, the gate-source voltage Vgs of the JFET becomes a value (5V) that is increased from the normal value (4V) by (the resistance value of the resistor Rg)×ΔIcha. Therefore, the determination circuit 3 can determine that an overcurrent is flowing when the gate-source voltage Vgs becomes larger than the reference voltage Vref (=4.5V). In the determination device 2, when the determination circuit 3 determines that an overcurrent is flowing, the control circuit 4 stops the drive circuit 6 and sets the gate drive voltage Vo to 0V, thereby controlling the semiconductor switch 1.

[0031] In the switch system 8, when the output voltage Vc of the DC power supply 5 is 0 V, if the semiconductor switch 1 is in a normal off state, as shown in FIG. 3C, the gate drive voltage Vo=0 V and the gate-source voltage Vgs=0 V.

[0032] (4) Advantages In the determination device 2 and switch system 8 according to the first embodiment, the determination circuit 3 determines that an overcurrent flows through the semiconductor switch 1 when the gate-source voltage Vgs of the junction field effect transistor 10 changes by a predetermined amount within a range smaller than the gate drive voltage Vo. Therefore, the determination device 2 and switch system 8 according to the first embodiment can suppress power loss. Here, the determination device 2 and switch system 8 according to the first embodiment can detect an overcurrent without connecting a shunt resistor for detecting an overcurrent to the source 10S of the junction field effect transistor 10, and can suppress power loss.

[0033] Furthermore, the determination device 2 according to the first embodiment includes the control circuit 4, and is therefore capable of controlling the semiconductor switch 1 when an overcurrent flows through the semiconductor switch 1.

[0034] Second Embodiment A determination device 2a according to a second embodiment and a switch system 8a including the same will be described below with reference to Fig. 4. Fig. 4 is a circuit diagram of the switch system 8a including the determination device 2a according to the second embodiment. The switch system 8a according to the second embodiment includes a semiconductor switch 1a and a determination device 2a instead of the semiconductor switch 1 and the determination device 2 of the switch system 8 according to the first embodiment. Regarding the determination device 2a and the switch system 8a according to the second embodiment, the same components as those of the determination device 2 and the switch system 8 according to the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0035] The semiconductor switch 1a is a bidirectional switch including two junction field effect transistors 10 (also referred to as JFETs 10). In the semiconductor switch 1a, the drains 10D of the two JFETs 10 are connected to each other. The two junction field effect transistors 10 include a first junction field effect transistor 11 and a second junction field effect transistor 12. Hereinafter, the first junction field effect transistor 11 will also be referred to as the first JFET 11. The second junction field effect transistor 12 will also be referred to as the second JFET.

[0036] Hereinafter, the gate 10G, source 10S, and drain 10D of the first JFET 11 are also referred to as the first gate 11G, the first source 11S, and the first drain 11D, respectively. The gate 10G, source 10S, and drain 10D of the second JFET 12 are also referred to as the second gate 12G, the second source 12S, and the second drain 12D, respectively. The gate-source voltage Vgs of the first JFET 11 is also referred to as the first gate-first source voltage Vgs1. The gate-source voltage Vgs of the second JFET 12 is also referred to as the second gate-second source voltage Vgs2. In the semiconductor switch 1a, the first source 11S of the first JFET 11 and the second source 12S of the second JFET 12 form a pair of main terminals. The switch system 8a is used by connecting a load circuit between the first source 11S and the second source 12S.

[0037] The determination device 2a includes two resistors Rg and two determination circuits 3. The two resistors Rg include a first resistor Rg1 corresponding to the first JFET 11 and a second resistor Rg2 corresponding to the second JFET 12. The resistance value of the second resistor Rg2 may be the same as or different from the resistance value of the first resistor Rg1.

[0038] The switch system 8a includes two drive circuits 6 and two DC power supplies 5. The two drive circuits 6 include a first drive circuit 61 and a second drive circuit 62. The two DC power supplies 5 include a first DC power supply 51 and a second DC power supply 52.

[0039] The first drive circuit 61 is connected to the first gate 11G of the first JFET 11 via a first resistor Rg1. The first drive circuit 61 is supplied with the output voltage of the first DC power supply 51 (hereinafter, the first output voltage). The first output voltage is, for example, 12 V. The high potential output terminal of the first DC power supply 51 is connected to the power supply terminal of the first drive circuit 61. The low potential output terminal of the first DC power supply 51 is connected to the first source 11S of the first JFET 11.

[0040] The second drive circuit 62 is connected to the second gate 12G of the second JFET 12 via a second resistor Rg2. The second drive circuit 62 is also supplied with the output voltage of the second DC power supply 52 (hereinafter, the second output voltage). The second output voltage is, for example, 12 V. The high potential output terminal of the second DC power supply 52 is connected to the power supply terminal of the second drive circuit 62. The low potential output terminal of the second DC power supply 52 is connected to the second source 12S of the second JFET 12.

[0041] Hereinafter, the gate drive voltage Vo output from the first drive circuit 61 will also be referred to as a first gate drive voltage Vo1, and the gate drive voltage Vo output from the second drive circuit 62 will also be referred to as a second gate drive voltage Vo2.

[0042] The two decision circuits 3 include a first decision circuit 31 corresponding to the first JFET 11 and a second decision circuit 32 corresponding to the second JFET 12 .

[0043] In the switch system 8a, when the semiconductor switch 1a is in an on state, a first gate-to-first source voltage Vgs1 is applied to the first gate 11G of the first JFET 11 at a first predetermined voltage (e.g., 4 V) higher than the first threshold voltage (e.g., 3.2 V) of the first JFET 11, and a first charging current Icha1 flows at a predetermined current value through the first gate 11G of the first JFET 11. Also, a second gate-to-second source voltage Vgs2 is applied to the second gate 12G of the second JFET 12 at a second predetermined voltage (e.g., 4 V) higher than the second threshold voltage (e.g., 3.2 V) of the second JFET 12, and a second charging current Icha2 flows at a predetermined current value through the second gate 12G of the second JFET 12.

[0044] In the switch system 8a, for example, when the main current I1 flows from the second source 12S to the first source 11S and becomes an overcurrent, the voltage drop Vgu at the diode Dgu (see FIG. 2) of the second gate 12G increases. This increases the second charging current Icha2, and the voltage between the second source 12S and the second gate 12G decreases. As a result, the second gate-to-second source voltage Vgs2 of the second JFET 12 decreases.

[0045] In the first JFET 11, when the main current I1 flows from the second source 12S to the first source 11S, if the main current I1 becomes an overcurrent, the first gate-to-first source voltage Vgs1 of the first JFET 11 increases.

[0046] In addition, in the switch system 8a, for example, when the main current I1 flows from the first source 11S to the second source 12S and becomes an overcurrent, the voltage drop Vgu at the diode Dgu (see FIG. 2) of the first gate 11G increases. This increases the first charging current Icha1, and the voltage between the first source 11S and the first gate 11G decreases. As a result, the first gate-to-first source voltage Vgs1 of the first JFET 11 decreases.

[0047] On the other hand, in the second JFET 12, if the main current I1 flows from the first source 11S to the second source 12S and becomes an overcurrent, the second gate-to-second source voltage Vgs2 of the second JFET 12 increases.

[0048] FIG. 5A is a circuit diagram of the first determination circuit 31 in the determination circuit 2a. The first determination circuit 31 includes, for example, a comparator Cp1 as shown in FIG. 5A. In the first determination circuit 31, in the comparator Cp1, the gate-source voltage Vgs1 of the first gate is compared with the first threshold value (reference voltage Vref1 + ΔV1). ΔV1 is a constant voltage. (Vref1 + ΔV1) < Vo1. In the first determination circuit 31, the gate-source voltage Vgs1 of the first gate is input to the non-inverting input terminal of the comparator Cp1, and the first threshold value (reference voltage Vref1 + ΔV1) is input to the inverting input terminal of the comparator Cp1. ΔV1 is not limited to a constant voltage and may be 0V.

[0049] FIG. 5B is a circuit diagram of the second determination circuit 32 in the determination circuit 2a. The second determination circuit 32 includes, for example, a comparator Cp2 as shown in FIG. 5B. In the second determination circuit 32, in the comparator Cp2, the gate-source voltage Vgs2 of the second gate is compared with the second threshold value (reference voltage Vref2 + ΔV2). In the second determination circuit 32, the gate-source voltage Vgs2 of the second gate is input to the non-inverting input terminal of the comparator Cp2, and the second threshold value (reference voltage Vref2 + ΔV2) is input to the inverting input terminal of the comparator Cp2. ΔV2 is not limited to a constant voltage and may be 0V.

[0050] In the determination device 2a and the switch system 8a according to the second embodiment, when there is a predetermined change in the gate-source voltage Vgs of the junction field effect transistor 10 within a range smaller than the gate drive voltage Vo, the determination circuit 3 determines that an overcurrent is flowing through the semiconductor switch 1. Therefore, in the determination device 2a and the switch system 8a according to the second embodiment, it is possible to suppress power loss.

[0051] Fig. 6A is a circuit diagram showing another example of the configuration of the first determination circuit 31 in the determination device 2a. For example, as shown in Fig. 6A, the first determination circuit 31 may have a first gate-to-first source voltage Vgs1 input to a non-inverting input terminal of a comparator Cp1, and a first gate voltage Vg1 in a steady state (normal state) of the first JFET 11 input to an inverting input terminal of the comparator Cp1. Here, the first gate voltage Vg1 in the steady state is, for example, a moving average value of the gate voltage (gate-to-source voltage Vgs) when the first JFET 11 is on.

[0052] Fig. 6B is a circuit diagram showing another example of the configuration of the second determination circuit 32 in the determination device 2a. For example, as shown in Fig. 6B, the second determination circuit 32 may have a second gate-to-second source voltage Vgs2 input to a non-inverting input terminal of a comparator Cp2, and a second gate voltage Vg2 in a steady state (normal state) of the second JFET 12 input to an inverting input terminal of the comparator Cp2. The second gate voltage Vg2 in a steady state is, for example, a moving average value of the gate voltage (gate-to-source voltage Vgs) when the second JFET 11 is on.

[0053] Third embodiment Fig. 7 is an explanatory diagram of the operation of a switch system 8b including a determination device 2b according to the third embodiment. Hereinafter, the determination device 2b according to the third embodiment and the switch system 8b including the same will be described with reference to Fig. 7. The switch system 8b according to the third embodiment includes a determination device 2b instead of the determination device 2a of the switch system 8a according to the second embodiment. Regarding the determination device 2b and the switch system 8b according to the third embodiment, the same components as those of the determination device 2a and the switch system 8a according to the second embodiment are denoted by the same reference numerals and will not be described.

[0054] The determination device 2b includes a third determination circuit 33 that determines whether or not the semiconductor switch 1a has an abnormality based on the determination result of the first determination circuit 31 and the determination result of the second determination circuit 32. The determination device 2b further includes a control circuit 4b that controls the semiconductor switch 1a based on the determination result of the third determination circuit 33.

[0055] The third judgment circuit 33 judges that there is an abnormality when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are different, as shown in Table 1 below, and judges that there is no abnormality when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are the same.

[0056] [Table 1]

[0057] In the switch system 8b, the first determination circuit 31 may be configured to set the logical value of the output signal to 1 when the first gate-first source voltage Vgs1 increases, and to set the logical value of the output signal to -1 when the first gate-first source voltage Vgs1 decreases. The second determination circuit 32 may be configured to set the logical value of the output signal to 1 when the second gate-second source voltage Vgs2 increases, and to set the logical value of the output signal to -1 when the second gate-second source voltage Vgs2 decreases. Therefore, the third determination circuit 33 may be configured to determine that there is an abnormality when the logical value of the determination result of the first determination circuit 31 and the logical value of the determination result of the second determination circuit 32 are different, as shown in Table 2 below, and to determine that there is no abnormality when the logical value of the determination result of the first determination circuit 31 and the logical value of the determination result of the second determination circuit 32 are the same.

[0058] [Table 2]

[0059] The control circuit 4b controls the first JFET 11 and the second JFET 12 based on the judgment result of the third judgment circuit 33. When the judgment result of the third judgment circuit 33 indicates that there is an abnormality, the control circuit 4b controls the first JFET 11 and the second JFET 12. More specifically, when the judgment result of the third judgment circuit 33 indicates that there is an abnormality, the control circuit 4b controls the first drive circuit 61 to set the first gate drive voltage Vo1 to 0 V, and controls the second drive circuit 62 to set the second gate drive voltage Vo2 to 0 V.

[0060] The determination device 2b and the switch system 8b according to the third embodiment can suppress power loss, similarly to the determination device 2a and the switch system 8a according to the second embodiment.

[0061] In the determination device 2b and the switch system 8b according to the third embodiment, the control circuit 4b is provided, so that when an overcurrent flows through the semiconductor switch 1a, the overcurrent can be quickly cut off.

[0062] The third judgment circuit 33 may be configured to determine the direction of an overcurrent when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are different, as shown in Table 3 below, and to determine that there is no abnormality when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are the same.

[0063] [Table 3]

[0064] Fig. 8 is an explanatory diagram of the operation of the switch system 8b including the determination device 2b. In the determination device 2b and the switch system 8b according to the third embodiment, when the main current I1 of the semiconductor switch 1a flows from the second source 12S to the first source 11S as shown in Fig. 7, the second JFET 12 operates in a diode mode as shown in Fig. 8. In this state, when the first gate-first source voltage Vgs1 of the first JFET 11 increases above the first reference voltage (Vref1 or Vref1+ΔV1) and the second gate-second source voltage Vgs2 of the second JFET 12 decreases below the second reference voltage (Vref2 or Vref2+ΔV2), the control circuit 4b turns off the first JFET 11 first among the first JFET 11 and the second JFET 12.

[0065] On the other hand, when the main current I1 of the semiconductor switch 1a flows from the first source 11S to the second source 12S, the first JFET 11 operates in the diode mode. In this state, when the first gate-to-first source voltage Vgs1 of the first JFET 11 falls below the first reference voltage and the second gate-to-second source voltage Vgs2 of the second JFET 12 rises above the second reference voltage, the control circuit 4b turns off the second JFET 12 first out of the first JFET 11 and the second JFET 12.

[0066] In the determination device 2b and switch system 8b of the third embodiment, by making the timing at which the control circuit 4b turns off the first JFET 11 and the timing at which it turns off the second JFET 12 different as described above, it is possible to suppress heat generation in the semiconductor switch 1a when the semiconductor switch 1a is turned off.

[0067] (Fourth embodiment) Fig. 9 is a circuit diagram of a switch system 8c including a determination device 2c according to the fourth embodiment. Hereinafter, the determination device 2c according to the fourth embodiment and the switch system 8c including the same will be described with reference to Fig. 9. The switch system 8c according to the fourth embodiment includes a semiconductor switch 1b and a determination device 2c instead of the semiconductor switch 1a and the determination device 2b of the switch system 8b according to the third embodiment. Regarding the determination device 2c and the switch system 8c according to the fourth embodiment, the same components as those of the determination device 2b and the switch system 8b according to the third embodiment are denoted by the same reference numerals and will not be described.

[0068] The semiconductor switch 1b is a dual-gate junction field effect transistor 10b (hereinafter also referred to as JFET 10b) having two gates 10G and two sources 10S, and can be used as a bidirectional switch. The two gates 10G and the two sources 10S correspond one-to-one. In the following, for convenience of explanation, one of the two gates 10G may be referred to as a first gate 11G, and the other may be referred to as a second gate 12G. In addition, of the two sources 10S, the source 10S corresponding to the first gate 11G may be referred to as a first source 11S, and the source 10S corresponding to the second gate 12G may be referred to as a second source 12S.

[0069] Below, the semiconductor switch 1b will be briefly described, and then the determination device 2c and the switch system 8c will be described.

[0070] The JFET 10b is a type of GaN-based GIT. The JFET 10b includes, for example, a substrate, a buffer layer, a first nitride semiconductor layer, a second nitride semiconductor layer, a first source electrode, a first gate electrode, a second gate electrode, a second source electrode, a first p-type layer, and a second p-type layer. The buffer layer is formed on the substrate. The first nitride semiconductor layer is formed on the buffer layer. The second nitride semiconductor layer is formed on the first nitride semiconductor layer. The first source electrode, the first gate electrode, the second gate electrode, and the second source electrode are formed on the second nitride semiconductor layer. The first p-type layer is interposed between the first gate electrode and the second nitride semiconductor layer. The second p-type layer is interposed between the second gate electrode and the second nitride semiconductor layer. In the JFET 10b, the first source 11S includes a first source electrode. The first gate 11G includes a first gate electrode and a first p-type layer. The second gate 12G includes a second gate electrode and a second p-type layer. The second source 12S includes a second source electrode. The substrate is, for example, a silicon substrate. The buffer layer is, for example, an undoped GaN layer. The first nitride semiconductor layer is, for example, an undoped GaN layer. The second nitride semiconductor layer is, for example, an undoped AlGaN layer. Each of the first p-type layer and the second p-type layer is, for example, a p-type AlGaN layer. Each of the buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer may contain impurities such as Mg, H, Si, C, and O that are inevitably mixed in during growth by MOVPE or the like.

[0071] In the JFET 10b, the second nitride semiconductor layer and the first nitride semiconductor layer form a heterojunction. In the first nitride semiconductor layer, two-dimensional electron gas is generated in the vicinity of the heterojunction. The region containing the two-dimensional electron gas (hereinafter, also referred to as the "two-dimensional electron gas layer") can function as an n-channel layer (electron conduction layer).

[0072] For convenience of explanation, the state in which a voltage equal to or greater than the first threshold voltage (e.g., 1.3V) is not applied between the first gate 11G and the first source 11S is also referred to as the off state of the first gate 11G. The state in which a voltage equal to or greater than the first threshold voltage is applied between the first gate 11G and the first source 11S with the first gate 11G serving as the high potential side is also referred to as the on state of the first gate 11G. The state in which a voltage equal to or greater than the second threshold voltage (e.g., 1.3V) is not applied between the second gate 12G and the second source 12S is also referred to as the off state of the second gate 12G. The state in which a voltage equal to or greater than the second threshold voltage is applied between the second gate 12G and the second source 12S with the second gate 12G serving as the high potential side is also referred to as the on state of the second gate 12G.

[0073] The JFET 10b includes the first p-type layer and the second p-type layer described above, thereby realizing a normally-off JFET.

[0074] The JFET 10b can switch between a bidirectional on state, a bidirectional off state, a first diode state, and a second diode state according to a combination of a first gate voltage and a second gate voltage applied to the first gate 11G and the second gate 12G, respectively. The first gate voltage is a voltage (first gate-first source voltage Vgs1) applied between the first gate 11G and the first source 11S. The second gate voltage is a voltage (second gate-second source voltage Vgs2) applied between the second gate 12G and the second source 12S. The bidirectional on state is a state in which a bidirectional current (a first direction and a second direction opposite to the first direction) passes. The bidirectional off state is a state in which a bidirectional current is blocked. The first diode state is a state in which a first directional current passes. The second diode state is a state in which a second directional current passes.

[0075] In the JFET 10b, a bidirectional ON state is achieved when the first gate 11G is ON and the second gate 12G is ON. In the JFET 10b, a bidirectional OFF state is achieved when the first gate 11G is OFF and the second gate 12G is OFF. In the JFET 10b, a first diode state is achieved when the first gate 11G is OFF and the second gate 12G is ON. In the JFET 10b, a second diode state is achieved when the first gate 11G is ON and the second gate 12G is OFF.

[0076] Next, the determination device 2c and the switch system 8c will be described.

[0077] The determination device 2c includes two resistors Rg and two determination circuits 3, similar to the determination device 2b according to the third embodiment. The two resistors Rg include a first resistor Rg1 connected to the first gate 11G and a second resistor Rg2 connected to the second gate 12G. The two determination circuits 3 include a first determination circuit 31 corresponding to the first gate 11G and the first source 11S, and a second determination circuit 32 corresponding to the second gate 12G and the second source 12S. The determination device 2c further includes a third determination circuit 33. The third determination circuit 33 determines the presence or absence of an abnormality in the semiconductor switch 1b based on the determination results of the first determination circuit 31 and the second determination circuit 32.

[0078] The operations of the determination device 2c and the switch system 8c are similar to those of the determination device 2b and the switch system 8b according to the third embodiment.

[0079] 10 and 11 are diagrams illustrating the operation of a switch system 8c including a determination device 2c. An example of the operation of the switch system 8c will be described with reference to FIGS.

[0080] In FIG. 10, the voltage Vgu1, the voltage Vgu2, the channel resistance Rchgs1, the channel resistance Rchgs2, the internal resistance Rchgg, and the main current I1 are indicated on a schematic equivalent circuit of the JFET 10b. The voltage Vgu1 is the voltage applied to the diode of the first gate 11G. The voltage Vgu2 is the voltage applied to the diode of the second gate 12G. The channel resistance Rchgs1 is the channel resistance between the first gate and the first source of the JFET 10b. The channel resistance Rchgs2 is the channel resistance between the second gate and the second source of the JFET 10b. The internal resistance Rchgg is the internal resistance between the channel resistance Rchgs1 and the channel resistance Rchgs2. The main current I1 is the current flowing from the second source 12S to the first source 11S.

[0081] In Fig. 11, the main current I1 flowing from the second source 12S to the first source 11S is Is2s1, the first gate-first source voltage is Vgs1, the second gate-second source voltage is Vgs2, the first charging current flowing through the first resistor Rg1 is Icha1, and the second charging current flowing through the second resistor Rg2 is Icha2, and the changes over time are shown. When the semiconductor switch 1b is in the on state and no overcurrent flows through the semiconductor switch 1b, the main current Is2s1, the first gate-first source voltage Vgs1, the second gate-second source voltage Vgs2, the first charging current Icha1, and the second charging current Icha2 are each approximately constant. In contrast, when the main current Is2s1 flowing from the second source 12S to the first source 11S increases, the first gate-first source voltage Vgs1 increases and the first charging current Icha1 decreases. Furthermore, when the main current Is2s1 flowing from the second source 12S to the first source 11S increases, the second gate-to-second source voltage Vgs2 decreases and the second charging current Icha2 increases.

[0082] The determination device 2c and the switch system 8c according to the fourth embodiment can suppress power loss, similarly to the determination device 2b and the switch system 8b according to the third embodiment.

[0083] The determination device 2c according to the fourth embodiment may include a control circuit similar to the control circuit 4b included in the determination device 2b according to the third embodiment.

[0084] Fifth embodiment 12 is a circuit diagram of a switch system 8d including a determination device 2d according to the fifth embodiment. Hereinafter, a determination device 2d according to the fifth embodiment and a switch system 8d including the same will be described with reference to FIG.

[0085] A switch system 8d according to the fifth embodiment includes a semiconductor switch 1c and a determination device 2d instead of the semiconductor switch 1a and the determination device 2a of the switch system 8a according to the second embodiment. Regarding the determination device 2d and the switch system 8d according to the fifth embodiment, the same components as those of the determination device 2a and the switch system 8a according to the second embodiment are denoted by the same reference numerals and will not be described.

[0086] In the semiconductor switch 1a, the first drain 11D of the first JFET 11 and the second drain 12D of the second JFET 12 are connected, whereas in the semiconductor switch 1c, the first source 11S of the first JFET 11 and the second source 12S of the second JFET 12 are connected.

[0087] In the switch system 8d, one DC power supply 5 is shared by the first drive circuit 61 and the second drive circuit 62, and the low-potential output terminal of the DC power supply 5 is connected to the node between the first source 11S of the first JFET 11 and the second source 12S of the second JFET 12.

[0088] In the semiconductor switch 1c, a pair of main terminals is formed by a first drain 11D of the first JFET 11 and a second drain 12D of the second JFET 12. In use, the switch system 8d is connected to a load circuit between the first drain 11D and the second drain 12D.

[0089] FIG. 13 is an explanatory diagram of the operation of the switch system 8d including the determination device 2d. In FIG. 13, the main current flowing from the second drain 12D to the first drain 11D is I1, the first gate-first source voltage is Vgs1, the second gate-second source voltage is Vgs2, the first discharge current flowing through the first resistor Rg1 is Idis1, and the second discharge current flowing through the second resistor Rg2 is Idis2, and the changes over time of these are shown. When the semiconductor switch 1c is in the on state and no overcurrent flows through the semiconductor switch 1c, the main current I1, the first gate-first source voltage Vgs1, the second gate-second source voltage Vgs2, the first discharge current Idis1, and the second discharge current Idis2 are each approximately constant. In contrast, when the main current I1 flowing from the second drain 12D to the first drain 11D increases, the first gate-first source voltage Vgs1 decreases and the first discharge current Idis1 decreases. Furthermore, when the main current I1 flowing from the second drain 12D to the first drain 11D increases, the second gate-to-second source voltage Vgs2 increases, and the second discharge current Idis2 increases.

[0090] The determination device 2d and the switch system 8d according to the fifth embodiment can suppress power loss, similarly to the determination device 2a and the switch system 8a according to the second embodiment.

[0091] In addition, in the determination device 2d according to the fifth embodiment, the reference potential of the first drive circuit 61 and the reference potential of the second drive circuit 62 can be made the same. Fig. 14 is a circuit diagram of a main part of the determination device 2a. As shown in Fig. 14, the first reference voltage Vref1 and the second reference voltage Vref2 can be made the same, and ΔV1 and ΔV2 can be made the same. This allows the determination device 2d to have a simplified circuit configuration and to be made smaller in size.

[0092] Furthermore, the determination device 2d according to the fifth embodiment may include a third determination circuit similar to the third determination circuit 33 included in the determination device 2b according to the third embodiment.

[0093] The third judgment circuit may be configured to determine the direction of an overcurrent when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are different, as shown in Table 4 below, and to determine that there is no abnormality when the level of the output signal of the first comparator Cp1 and the level of the output signal of the second comparator Cp2 are the same.

[0094] [Table 4]

[0095] (Sixth embodiment) 15 is a circuit diagram of a switch system 8e including a determination device 2e according to a sixth embodiment. Hereinafter, a determination device 2e according to the sixth embodiment and a switch system 8e including the same will be described with reference to FIG.

[0096] A determination device 2e and a switch system 8e according to the sixth embodiment differ from the determination device 2d and the switch system 8d according to the fifth embodiment in that the determination device 2e and the switch system 8e according to the sixth embodiment include a control circuit 4. Regarding the determination device 2e and the switch system 8e according to the sixth embodiment, components similar to those of the determination device 2d and the switch system 8d according to the fifth embodiment are denoted by the same reference numerals and will not be described.

[0097] The control circuit 4 controls the first JFET 11 and the second JFET 12 based on the judgment result of the third judgment circuit 33. The control circuit 4 controls the first JFET 11 and the second JFET 12 when the judgment result of the third judgment circuit 33 indicates an abnormality. More specifically, when the judgment result of the third judgment circuit 33 indicates an abnormality, the control circuit 4 controls the first drive circuit 61 to set the first gate drive voltage Vo1 to 0 V, and controls the second drive circuit 62 to set the second gate drive voltage Vo2 to 0 V.

[0098] The determination device 2e and the switch system 8e according to the sixth embodiment can suppress power loss, similarly to the determination device 2a and the switch system 8a according to the fifth embodiment.

[0099] In the determination device 2e and the switch system 8e according to the sixth embodiment, the control circuit 4 is provided, and therefore it is possible to quickly cut off an overcurrent when it flows through the semiconductor switch 1c.

[0100] The above-mentioned first to sixth embodiments are merely examples of various embodiments of the present disclosure. The above-mentioned first to sixth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0101] For example, with respect to the determination device 2 and switch system 8 according to the first embodiment, the above-mentioned determination circuit 3 may be configured with a Zener diode ZD, and the control circuit 4 may be configured to include a normally-off transistor Q1, as shown in Fig. 16. In the circuit of Fig. 16, the potential Vcont of the path between the drive circuit 6 and the resistor Rg is normally at an H (High) level (e.g., 12 V), and becomes an L (Low) level (e.g., 0 V) ​​when an overcurrent flows through the semiconductor switch 1 and the gate-source voltage Vgs increases, causing the drive circuit 6 to stop operating.

[0102] Furthermore, the determination circuit 3 determining that an overcurrent is flowing includes a case where the output of the determination circuit 3 differs between when an overcurrent is flowing and when it is not flowing.

[0103] The p-type layer in the semiconductor switches 1, 1a, and 1c is not limited to a p-type AlGaN layer, and may be, for example, a p-type GaN layer or a p-type metal oxide semiconductor layer. The p-type metal oxide semiconductor layer is, for example, a NiO layer. The NiO layer may contain, as an impurity, at least one alkali metal selected from the group consisting of lithium, sodium, potassium, rubidium, and cesium. The NiO layer may also contain, for example, a transition metal such as silver or copper that becomes monovalent when added as an impurity. The first p-type layer and the second p-type layer in the semiconductor switch 1b are similar to the p-type layers in the semiconductor switches 1, 1a, and 1c.

[0104] Each of the semiconductor switches 1, 1a to 1c may include one or more nitride semiconductor layers between the buffer layer and the first nitride semiconductor layer. The buffer layer is not limited to a single layer structure and may have, for example, a superlattice structure.

[0105] Furthermore, the substrate in each of the semiconductor switches 1, 1a to 1c is not limited to a silicon substrate, but may be, for example, a GaN substrate, a SiC substrate, a sapphire substrate, or the like.

[0106] The semiconductor switches 1 to 1c can be applied to electric devices such as circuit breakers, multilevel inverters, dimmers, and matrix converters that perform AC-AC power conversion.

[0107] (Aspect) From the above-described embodiments, the present specification discloses the following aspects.

[0108] A determination device (2; 2a; 2b; 2c; 2d; 2e) according to a first embodiment is used in a semiconductor switch (1). The semiconductor switch (1; 1a; 1b; 1c) includes a junction field effect transistor (10) having a gate (10G) and a source (10S) corresponding to the gate (10G). The determination device (2) includes a resistor (Rg) and a determination circuit (3). The resistor (Rg) has a first end and a second end. The first end of the resistor (Rg) is connected to the gate (10G). The determination circuit (3) determines that an overcurrent is flowing in the semiconductor switch (1; 1a; 1b; 1c) when a predetermined change occurs in the gate-source voltage (Vgs) of the junction field effect transistor (10) within a range smaller than the gate drive voltage (Vo) applied between the second end of the resistor (Rg) and the source (10S).

[0109] The determination device (2; 2a; 2b; 2c; 2d; 2e) according to the first aspect can suppress power loss.

[0110] In the determination device (2; 2a; 2b; 2c; 2d; 2e) according to the second aspect, in the first aspect, the predetermined change includes a change determined by a threshold value.

[0111] In the determination device (2; 2a; 2b; 2c; 2d) according to the second aspect, the determination circuit (3) can be configured using a comparator.

[0112] In the determination device (2; 2a; 2b; 2c; 2d) according to the third aspect, in the first aspect, the predetermined change includes a change determined by an amount of change.

[0113] In the determination device (2; 2a; 2b; 2c; 2d) according to the third aspect, it is possible to suppress erroneous detection of an overcurrent.

[0114] A determination device (2a) according to a fourth aspect is based on the first aspect. The semiconductor switch (1a) is a bidirectional switch including two junction field effect transistors (10). The two junction field effect transistors (10) include a first junction field effect transistor (11) and a second junction field effect transistor (12). The determination device (2a) includes two resistors (Rg) and two determination circuits (3). The two resistors (Rg) include a first resistor (Rg1) corresponding to the first junction field effect transistor (11) and a second resistor (Rg2) corresponding to the second junction field effect transistor (12). The two determination circuits (3) include a first determination circuit (31) corresponding to the first junction field effect transistor (11) and a second determination circuit (32) corresponding to the second junction field effect transistor (12).

[0115] The determination device (2a) according to the fourth aspect is capable of determining whether or not an overcurrent flows through a bidirectional switch.

[0116] In the determination device (2a) according to the fifth aspect, in the fourth aspect, the first determination circuit (31) compares the gate-source voltage (Vgs1) of the first junction field effect transistor (11) with a first threshold value (Vref1+ΔV1). The second determination circuit (32) compares the gate-source voltage (Vgs2) of the second junction field effect transistor (12) with a second threshold value (Vref2+ΔV2).

[0117] In the determination device (2a) according to the fifth aspect, the first determination circuit (31) can be configured using a comparator (Cp1), and the second determination circuit (32) can be configured using a comparator (Cp2).

[0118] In the determination device (2a) according to the sixth aspect, in the fourth aspect, the first determination circuit (31) compares the gate-source voltage (Vgs1) of the first junction field effect transistor (11) with the moving average value (Vg1) of the gate voltage when the first junction field effect transistor (11) is on. The second determination circuit (32) compares the gate-source voltage (Vgs2) of the second junction field effect transistor (12) with the moving average value (Vg2) of the gate voltage when the second junction field effect transistor (12) is on.

[0119] In the determination device (2a) according to the sixth aspect, the first determination circuit (31) can be configured using a comparator (Cp1), and the second determination circuit (32) can be configured using a comparator (Cp2).

[0120] The determination device (2b) according to the seventh aspect is any one of the fourth to sixth aspects, and further includes a third determination circuit (33) that determines the presence or absence of an abnormality in the semiconductor switch (1a) based on a determination result of the first determination circuit (31) and a determination result of the second determination circuit (32).

[0121] The determination device (2b) according to the seventh aspect can determine whether or not there is an abnormality in the semiconductor switch (1a).

[0122] In a determination device (2b) according to an eighth aspect, in the seventh aspect, the third determination circuit (33) determines the direction in which the overcurrent flows.

[0123] The determination device (2b) according to the eighth aspect can determine the direction in which an overcurrent flows.

[0124] In the determination device (2b) according to the ninth aspect, in the eighth aspect, the determination device (2b) further includes a control circuit (4b). The control circuit (4b) controls the first junction field effect transistor (11) and the second junction field effect transistor (12) based on the determination result of the third determination circuit (33). When the gate-source voltage (Vgs1) of the first junction field effect transistor (11) increases above the first reference voltage and the gate-source voltage (Vgs2) of the second junction field effect transistor (12) decreases below the second reference voltage, the control circuit (4b) turns off the first junction field effect transistor (11) first out of the first junction field effect transistor (11) and the second junction field effect transistor (12). When the gate-source voltage (Vgs1) of the first junction field effect transistor (11) falls below a first reference voltage and the gate-source voltage (Vgs2) of the second junction field effect transistor (12) increases above a second reference voltage, the control circuit 4 turns off the second junction field effect transistor (12) first, out of the first junction field effect transistor (11) and the second junction field effect transistor (12).

[0125] The determination device (2b) according to the ninth aspect can suppress a temperature rise of the semiconductor switches (1; 1a; 1c) when an overcurrent flows through the semiconductor switches (1; 1a; 1c) and the semiconductor switches (1; 1a; 1c) are turned off.

[0126] In the determination device (2c) according to the tenth aspect, in the first aspect, the semiconductor switch (1b) is a dual-gate junction field effect transistor having two gates (10G) and two sources (10S). The two gates (10G) include a first gate (11G) and a second gate (12G). The two sources (10S) include a first source (11S) corresponding to the first gate (11G) and a second source (12S) corresponding to the second gate (12G). The determination device (2c) includes two resistors (Rg) and two determination circuits (3). The two resistors (Rg) include a first resistor (Rg1) connected to the first gate (11G) and a second resistor (Rg2) connected to the second gate (12G). The two determination circuits (3) include a first determination circuit (31) corresponding to the first gate (11G) and the first source (11S) and a second determination circuit (32) corresponding to the second gate (12G) and the second source (12S). The determination device (2c) further includes a third determination circuit (33). The third determination circuit (33) determines the presence or absence of an abnormality in the semiconductor switch (1b) based on the determination results of the first determination circuit (31) and the second determination circuit (32).

[0127] The determination device (2) according to the tenth aspect can determine whether or not there is an abnormality in the semiconductor switch (1b).

[0128] The determination device (2e) according to the eleventh aspect is based on the seventh aspect. In the semiconductor switch (1c), the gate (10G) and the source (10S) of the first junction field effect transistor (11) are the first gate (11G) and the first source (11S), respectively. The gate (10G) and the source (10S) of the second junction field effect transistor (12) are the second gate (12G) and the second source (12S), respectively. The first source (11S) of the first junction field effect transistor (11) and the second source (12S) of the second junction field effect transistor (12) are connected. The determination device (2e) further includes a control circuit (4). The control circuit (4) controls the first junction field effect transistor (11) and the second junction field effect transistor (12) based on the determination result of the third determination circuit (33). The third determination circuit (33) determines that the semiconductor switch (c) is abnormal when the voltage between the second gate (12G) and the second source (12S) increases above the first reference voltage and the voltage between the first gate (11G) and the first source (11S) decreases.

[0129] The determination device (2e) according to the eleventh aspect can determine the presence or absence of an abnormality in the semiconductor switch (1c).

[0130] A determination device (2) according to a twelfth aspect is based on the fifth aspect. In the semiconductor switch (1), the gate (10G) and source (10S) of the first junction field effect transistor (11) are the first gate (11G) and the first source (11S), respectively. The gate (10G) and source (10S) of the second junction field effect transistor (12) are the second gate (12G) and the second source (12S), respectively. The first source (11S) of the first junction field effect transistor (11) and the second source (12S) of the second junction field effect transistor (12) are connected. The first threshold (Vref1+ΔV1) and the second threshold (Vref2+ΔV2) are the same.

[0131] In the determination device (2a) according to the twelfth aspect, the circuit configuration can be simplified and made smaller.

[0132] A switch system (8; 8a; 8b; 8c; 8d; 8e) according to a thirteenth aspect includes a determination device (2; 2a; 2b; 2c; 2d; 2e) according to any one of the first to twelfth aspects, and a semiconductor switch (1; 1a; 1b; 1c).

[0133] The switch system (8; 8a; 8b; 8c; 8d; 8e) according to the thirteenth aspect can suppress power loss. [Industrial Applicability]

[0134] The determination device and the switch system including the same according to the present disclosure are capable of suppressing power loss, and therefore the determination device and the switch system including the same according to the present disclosure lead to power saving in semiconductor devices and electronic devices using the same, and are industrially useful. [Explanation of symbols]

[0135] 1, 1a, 1b, 1c Semiconductor switches 2, 2a, 2b, 2c, 2d, 2e judgment device 3 Judgment circuit 31 First judgment circuit 32 Second judgment circuit 33 Third judgment circuit 4 Control circuit 5 DC power supply 51 1st DC power supply 52 2nd DC power supply 6 Drive circuit 61 First drive circuit 62 Second drive circuit 8, 8a, 8b, 8c, 8d, 8e Switch Systems 10, 10b Junction field effect transistor 10D Drain 10G Gate 10S Source 11 First junction field-effect transistor 11G 1st Gate 11S First Source 11D First Drain 12 Second junction field effect transistor 12G 2nd Gate 12S Second Source 12D Second Drain I1, Is2s1 Main current Icha charging current Icha1 1st charging current Icha2 2nd charging current Vg1 First gate voltage Vg2 Second gate voltage Vgs Gate-source voltage Vgs1 First gate-first source voltage Vgs2 Second gate-second source voltage Vo Gate drive voltage Vo1 Gate drive voltage Vo2 Gate drive voltage

Claims

1. A determination device for use in a semiconductor switch including a junction field effect transistor having a gate and a source corresponding to the gate, a resistor having a first end and a second end, the first end being connected to the gate; a determination circuit that determines that an overcurrent is flowing through the semiconductor switch when a predetermined change occurs in a range smaller than a gate drive voltage applied between the second end of the resistor and the source of the junction field effect transistor; the semiconductor switch is a bidirectional switch including two of the junction field effect transistors, the two junction field effect transistors include a first junction field effect transistor and a second junction field effect transistor; the determination device includes two of the resistors and two of the determination circuits; The two resistors are: a first resistor corresponding to the first junction field effect transistor; a second resistor corresponding to the second junction field effect transistor; The two determination circuits are a first determination circuit corresponding to the first junction field effect transistor; a second determination circuit corresponding to the second junction field effect transistor; the determination device further includes a third determination circuit that determines whether or not an abnormality exists in the semiconductor switch based on a determination result of the first determination circuit and a determination result of the second determination circuit, The third determination circuit determines a direction in which the overcurrent flows, The determination device includes: a control circuit that controls the first junction field effect transistor and the second junction field effect transistor based on a determination result of the third determination circuit, The control circuit includes: when the gate-source voltage of the first junction field effect transistor increases above a first reference voltage and the gate-source voltage of the second junction field effect transistor decreases below a second reference voltage, the first junction field effect transistor is turned off first out of the first junction field effect transistor and the second junction field effect transistor; when the gate-source voltage of the first junction field effect transistor falls below a first reference voltage and the gate-source voltage of the second junction field effect transistor increases above a second reference voltage, the second junction field effect transistor out of the first junction field effect transistor and the second junction field effect transistor is turned off first; Judgment device.

2. A determination device for use in a semiconductor switch including a junction field effect transistor having a gate and a source corresponding to the gate, a resistor having a first end and a second end, the first end being connected to the gate; a determination circuit that determines that an overcurrent is flowing through the semiconductor switch when a predetermined change occurs in a range smaller than a gate drive voltage applied between the second end of the resistor and the source of the junction field effect transistor; the semiconductor switch is a bidirectional switch including two of the junction field effect transistors, the two junction field effect transistors include a first junction field effect transistor and a second junction field effect transistor; the determination device includes two of the resistors and two of the determination circuits; The two resistors are: a first resistor corresponding to the first junction field effect transistor; a second resistor corresponding to the second junction field effect transistor; The two determination circuits are a first determination circuit corresponding to the first junction field effect transistor; a second determination circuit corresponding to the second junction field effect transistor; the determination device further includes a third determination circuit that determines whether or not an abnormality exists in the semiconductor switch based on a determination result of the first determination circuit and a determination result of the second determination circuit, In the semiconductor switch, the gate and the source of the first junction field effect transistor are a first gate and a first source, respectively; the gate and the source of the second junction field effect transistor are a second gate and a second source, respectively; the first source of the first junction field effect transistor and the second source of the second junction field effect transistor are connected; The determination device includes: a control circuit that controls the first junction field effect transistor and the second junction field effect transistor based on a determination result of the third determination circuit, The third determination circuit is determining that the semiconductor switch is abnormal when the voltage between the second gate and the second source increases above a first reference voltage and the voltage between the first gate and the first source decreases; Judgment device.

3. The first determination circuit compares the gate-source voltage of the first junction field effect transistor with a first threshold value; the second determination circuit compares the gate-source voltage of the second junction field effect transistor with a second threshold value; The determination device according to claim 1 or 2.

4. The first determination circuit compares the gate-source voltage of the first junction field effect transistor with a moving average value of the gate voltage when the first junction field effect transistor is on, the second determination circuit compares the gate-source voltage of the second junction field effect transistor with a moving average value of the gate voltage when the second junction field effect transistor is on; The determination device according to claim 1 or 2.

5. A determination device according to any one of claims 1 to 4, The semiconductor switch, Switch system.

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