Systems and methods for SOC power-up sequencing

Abstract

The apparatus and related method relate to an integrated power-on reset system (PORS) at the system-on-chip (SoC) level. In an illustrative example, an integrated circuit (215) may include a first power domain (300a) and a second power domain (300b). A level shifter circuit (300c) may be coupled to move data from the first power domain to the second power domain. A PORS (270) including a voltage detection circuit (410, 470a, 470b), a glitch filter circuit (415, 475a, 475b), and logic gates (420a, 420b) may be configured to generate an isolation signal (310, 320) between the first power domain (300a) and the second power domain (300b). The level shifter circuit (300c) may be enabled in response to the generated isolation signal. By using isolated signals, multiple power domains on the IC (215) can be comprehensively managed when powered on, and unstable operation can be avoided.

Description

[Technical field]

[0001] Various embodiments relate generally to integrated circuit devices, and more particularly to devices that include power management circuitry capable of managing multiple power sources supplied to a System-on-Chip (SoC) upon power-up. [Background technology]

[0002] A programmable integrated circuit (IC) is a type of IC that contains programmable circuits. One example of a programmable IC is the Field Programmable Gate Array (FPGA). The characteristic of an FPGA is that it contains programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, Input / Output Blocks (IOBs), Configurable Logic Blocks (CLBs), Dedicated Random Access Memory blocks (BRAMs), Digital Signal Processing Blocks (DSPs), Processors, Clock Managers, and Delay Lock Loops (DLLs).

[0003] A circuit design may be physically embodied within the programmable circuitry of a programmable IC by loading configuration data, sometimes referred to as a configuration bitstream, into the device. The configuration data may be loaded into the device's internal configuration memory cells. The collective state of the individual configuration memory cells determines the function of the programmable IC. For example, the specific operations performed by the various programmable circuit blocks, and the connectivity between the programmable circuit blocks of a programmable IC, are defined by the collective state of the configuration memory cells at the time the configuration data is loaded. Summary of the Invention

[0004] The apparatus and related method relate to an integrated Power-On-Reset System (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power domain. A level shifter circuit may be coupled to move data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and a logic gate may be configured to generate an isolation signal between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signal. The isolation signal may be used to comprehensively manage multiple power domains on an IC during power-up to avoid unstable operation.

[0005] Various embodiments may achieve one or more advantages. For example, at power-up, power supplies with different ramp rates may be controlled, which may significantly reduce or eliminate competing currents in the chip and / or noise coupling between various power domains. In some embodiments, chip damage at power-up due to multiple voltage cross-domain shortages and huge current surges may be significantly reduced or eliminated. In some embodiments, the isolation signal may reach the High-availability Seamless Redundancy protocol (HSR) before the Programmable Logic (PL) gets a Power-On-Reset (POR) signal. In the event of an unintended POR / reset event, delaying the POR signal beyond the isolation signal may prevent IO glitches. In some embodiments, the isolation signal between the PL and the power supplies of the Network-on-Chip (NoC) block may be delayed (e.g., 100 ns) by the PL power off, which may significantly reduce noise coupling to the NoC block. Some embodiments may provide power aware support to the POR voltage detector model for enhanced Register-Transfer Level (RTL) verification. Some embodiments may reduce total power-up time while other embodiments may improve performance of the PL fabric with on-chip voltage generation. Some embodiments may also provide a PMC deep sleep mode that can reduce power consumption at the system level. Some embodiments may provide a PMC deep sleep mode that can reduce power consumption at the system level by deriving all PL supplies (V ccint , V ccint_ram , V ccauxA firmware (FM) dependent skip_por_cnt that can skip the counter for 26 ms after the ) is seen to have come up can be used to generate the por_pl_b signal to minimize the total power-up time. Some embodiments can provide a smooth boundary scan chain that crosses multiple power domains.

[0006] In an exemplary embodiment, an integrated circuit (IC) includes a first region provided by a first power domain and a second region provided by a second power domain. A first level shifting circuit is coupled to move first data from the first power domain to the second power domain, and a second level shifting circuit is coupled to move second data from the second power domain to the first power domain. The IC also includes a power-on reset system (PORS). The PORS includes a voltage detection circuit configured to detect voltages of the first power domain and the second power domain. A control circuit is coupled to the first level shifting circuit and the second level shifting circuit and configured to generate a first isolation signal for controlling the first level shifting circuit and a second isolation signal for controlling the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain.

[0007] In some embodiments, the PORS may also include a glitch filter circuit coupled to the voltage detection circuit and indicative of a voltage change in the second power domain. When the voltage change in the second power domain exceeds a predetermined period of time, the control circuit may be configured to disable the first level shifting circuit and then disable the second level shifting circuit a first predetermined delay later. In some embodiments, the control circuit may be further configured to emit a power-on reset signal that resets the second power domain a second predetermined delay later after disabling the second level shifting circuit.

[0008] In some embodiments, the control circuitry may be configured to emit a power-on reset signal that resets the second power domain after a second predetermined delay after disabling the second level shifting circuitry. The second domain may be provided in a portion of the IC that does not overlap with the first domain. The first domain may include a platform management controller (PMC) configured to act as a master power supply and provide power management for the IC. The second domain may include a programmable logic (PL) block. The second domain may include a processor system (PS). In some embodiments, the integrated circuit may also include a third domain provided by a third power domain. The third level shifting circuitry may be coupled to move third data from the second power domain to the third power domain, and the fourth level shifting circuitry may be coupled to move fourth data from the third power domain to the second power domain. The voltage detection circuitry may be further configured to detect voltages of the first power domain, the second power domain, and the third power domain. The control circuit may further be coupled to the third level shifting circuit and the fourth level shifting circuit and configured to generate a third isolation signal to control the third level shifting circuit and a fourth isolation signal to control the fourth level shifting circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain. In some embodiments, the third domain may include a data processing engine (DPE) array.

[0009] In another exemplary aspect, a method includes a first power domain providing a first region and a second power domain providing a second region. A first level shifting circuit is coupled to move first data from the first power domain to the second power domain and a second level shifting circuit is coupled to move second data from the second power domain to the first power domain. The method also includes detecting voltages of the first power domain and the second power domain and generating a first isolation signal to control the first level shifting circuit and a second isolation signal to control the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain.

[0010] In some embodiments, when the voltage change in the second power domain exceeds a predetermined period of time, the method may include disabling the first level shifting circuit using a first isolation signal, disabling the second level shifting circuit using a second isolation signal a first predetermined delay after disabling the first level shifting circuit, and emitting a power-on reset signal to reset the second power domain a second predetermined delay after disabling the second level shifting circuit.

[0011] In some embodiments, the second region may be located in a portion of the IC that does not overlap with the first region. The first region may include a platform management controller (PMC) configured to act as a master power supply and provide power management for the IC. In some embodiments, the second region may include a processor system. In some embodiments, the second region may include an extended performance I / O block (XPIO). The second region may include a programmable logic (PL) block.

[0012] In some embodiments, the method may also include: (1) providing a third region, where a third power domain is provided, where a third level shifting circuit is coupled to move third data from the second power domain to the third power domain, and a fourth level shifting circuit is coupled to move fourth data from the third power domain to the second power domain; (2) detecting voltages of the first power domain, the second power domain, and the third power domain; and (3) generating a third isolation signal to control the third level shifting circuit and a fourth isolation signal to control the fourth level shifting circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain.

[0013] In some embodiments, when the voltage change in the third power domain exceeds a predetermined period of time, the method may also include: (4) disabling the third level shifting circuit using a third isolation signal; (5) disabling the fourth level shifting circuit using a fourth isolation signal a third predetermined delay after disabling the third level shifting circuit; and (6) emitting a power-on reset signal to reset the third power domain a fourth predetermined delay after disabling the fourth level shifting circuit. In some embodiments, the third domain may include a data processing engine (DPE) array.

[0014] The details of various embodiments are set forth in the accompanying drawings and description below. Other features and advantages will become apparent from the description and drawings, and from the claims. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 illustrates an example programmable integrated circuit (IC) in which the circuits and processes of the present disclosure may be embodied. [Diagram 2] FIG. 1 illustrates an example integrated circuit having a system-on-chip (SoC) level power-on reset system (PORS). [Figure 3A] 1 is an example schematic diagram of various power domains on an IC. [Figure 3B] FIG. 1 illustrates an example interface architecture between an interconnect block power domain and an XPIO power domain in the programming logic (PL). [Figure 4] FIG. 1 illustrates an example architecture of a power-on reset system on an IC. [Diagram 5] FIG. 1 illustrates a data sheet relating to an exemplary isolated signal generated by a PORS. [Figure 6] 1 is a flowchart of an example method for coordinating power transitions between power domains in an IC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Like symbols in the various drawings indicate like elements.

[0017] To aid in understanding, the present specification is organized as follows. First, an exemplary platform (e.g., FPGA) suitable for comprehensively managing signal isolation across power domains during power-up transients is briefly introduced with reference to FIG. 1. Second, the discussion moves to introduce how an exemplary power-on reset system (PORS) can be used to generate isolation signals between various power domains with reference to FIG. 2-4. Next, with reference to FIG. 5, the discussion discloses an exemplary isolation signal generated by the power-on reset system (PORS). Finally, with reference to FIG. 6, the discussion discloses an exemplary method of coordinating power transitions between power domains in an IC. Using a power-on reset system (PORS), multiple power supplies of a system-on-chip (SoC) can be managed at power-up such that contention currents in the chip can be virtually reduced or eliminated.

[0018] 1 illustrates an exemplary programmable integrated circuit (IC) in which the circuits and processes of the present disclosure may be embodied. The programmable IC 100 may include an FPGA logic circuit. The programmable IC 100 may be embodied with a variety of programmable resources and may be referred to as a system on a chip (SoC). Various examples of FPGA logic circuits may include an arrangement of several different types of programmable logic blocks.

[0019] For example, Figure 1 illustrates an example programmable IC 100 that includes a number of different programmable tiles, including a Multi-Gigabit Transceiver (MGT) 101, a Configurable Logic Block (CLB) 102, a Block of Random Access Memory (BRAM) 103, an Input / Output Block (IOB) 104, a Configuration and Clocking Logic (CONFIG / CLOCKS) 105, a Digital Signal Processing (DSP) 106, specialized Input / Output Blocks (I / O) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include an internal reconfiguration port and an external reconfiguration port (not shown).

[0020] In various examples, the MGT 101 can be used to embody a serializer / deserializer. The MGT 101 can include various data serializers and deserializers. The data serializer can include various multiplexer implementations. The data deserializer can include various demultiplexer implementations.

[0021] In some examples of FPGA logic circuits, each programmable tile includes a programmable interconnect element (INT) 111 having normalized interconnects 124 between corresponding interconnect elements in each adjacent tile. The programmable interconnect elements taken together thereby embody a programmable interconnect structure for the illustrated FPGA logic circuit. The programmable interconnect element INT 111 includes intra connections 120 between programmable logic elements within the same tile as shown as an example included in FIG. 1. The programmable interconnect element INT 111 includes inter-INT- connections 122 between programmable interconnect elements INT 111 within the same tile as shown as an example included in FIG.

[0022] For example, the CLB 102 may include one programmable interconnect element INT 111 in addition to configurable logic elements (CLEs) 112 that may be programmed to embody user logic. The BRAM 103 may include a BRAM Logic element (BRL) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a tile may be determined by the height of the tile. In the illustrated implementation, the height of the BRAM tile is the same as five CLBs, although other numbers (e.g., four) may be used. The DSP tile 106 may include a DSP logic element (DSPL) 114 and one or more programmable interconnect elements. The IOB 104 may include, for example, two instances of an Input / Output Logic element (IOL) 115 and one instance of a programmable interconnect element INT 111. For example, the actual I / O bond pads connected to I / O logic element 115 may be fabricated using metal laminated onto the various illustrated logic blocks and may not be confined to the area of ​​the input / output logic element 115.

[0023] In the illustrated implementation, a columnar area near the center of the die (shown as shaded in FIG. 1) is used for configuration, clocks, and other control logic. A horizontal area 109 extending from this column distributes clock and configuration signals across the width of the programmable IC 100. Note that the terms "columnar" and "horizontal" are relative to the vertical direction of the drawing.

[0024] Some programmable ICs utilizing the architecture shown in Figure 1 may include additional logic blocks that break the normal columnar structure that constitutes most programmable ICs. The additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC 110 shown in Figure 1 spans several columns of CLBs 102 and BRAMs 103.

[0025] 1 is illustrative of the architecture of an exemplary programmable IC. The number of logic blocks in a column, the relative width of the columns, the number and order of the columns, the types of logic blocks contained in the columns, the relative sizes of the logic blocks, and the interconnect / logic implementation are presented as examples only. For example, an actual programmable IC may include multiple adjacent columns of CLBs 102 wherever CLBs 102 appear to facilitate efficient instantiation of user logic.

[0026] Programmable logic (PL) and processor system (PS) may be integrated in a single chip to provide comprehensive functionality. The single chip may be embodied in, for example, communication systems, medical devices, and vision applications. The single chip may include multiple power domains. Different ramp rates of any / all power supplies may lead to, for example, coupling noise and competing currents. A power-on reset system (PORS) may be used to manage signaling between the various power domains that the single chip's multiple power supplies provide to be effective upon power-up.

[0027] FIG. 2 shows an example integrated circuit with a system-on-chip (SoC) level power-on reset system (PORS). In this illustrated example, a communication system 200 includes a base station 205. The base station 205 may be used to transmit and receive analog signals from a cell phone. The base station 205 includes an integrated circuit (IC) 215 that communicates data between the base station 205 and the cell phone 210. The IC 215 may also be used to perform data processing using separate circuits provided by multiple power domains. In various embodiments, the multiple power domains may be provided by separate and independent voltage regulators, for example. In various embodiments, the separate domains may be provided by a common regulator through independent electrical paths, and the separate domains may have separate inductive or capacitive filtering, for example.

[0028] In this illustrated example, IC 215 is embodied as a system-on-chip (SoC) type device. Typically, an SoC is an IC that includes two or more subsystems that can interact with each other. As an example, an SoC may include a processor that executes program code and one or more other circuits. The other circuits may be embodied as hardwired circuits, programmable circuits, other subsystems, and / or any combination thereof. The circuits may work in cooperation with each other and / or with the processor. In this illustrated example, the SoC includes a data processing engine (DPE) arrangement 220. The DPE arrangement 220 may include one or more DPEs. The DPE may include, for example, a math engine (ME).

[0029] For illustrative purposes, IC 215 includes programmable logic (PL) 230. PL 230 is a circuit that can be programmed to perform a particular function. As an example, PL 230 may be embodied as a field programmable gate array (FPGA) circuit. PL 230 may include a programmable circuit block arrangement. Examples of programmable circuit blocks in PL 230 include, but are not limited to, interconnect block 231, PL interface block 232, configurable logic block (CLB), dedicated random access memory block (BRAM), digital signal processing block (DSP), clock manager, and / or delay lock loop (DLL). In the example of FIG. 2, PL 230 is shown in two separate sections. In another example, PL 230 may be embodied as a unified region of programmable circuitry. In yet another example, PL 230 may be embodied as three or more distinct regions of programmable circuitry. The particular organization of PL 230 is not intended to be limiting. In some embodiments, PL 230 may include several programmable circuit blocks. Each programmable circuit block in PL 230 may include both programmable interconnect circuitry (e.g., interconnect block 231) and programmable logic circuitry. The programmable interconnect circuitry may include multiple interconnect wires of various lengths interconnected by programmable interconnect points (PIPs). The interconnect wires may be configured (e.g., wire-by-wire) to provide bit-wise connectivity (e.g., each wire carries one bit of information). The programmable logic circuitry embodies the logic of the user design using programmable elements, which may include, for example, look-up tables, registers, arithmetic logic, and the like. The programmable interconnect (e.g., interconnect block 231) and programmable logic circuitry may be programmed by loading configuration data into internal configuration memory cells that defines how the programmable elements are configured and operate.

[0030] In some embodiments, multiple power supplies may be required to power the various PL resources in IC 215. Different resources may operate at different voltage levels to improve performance or signal strength while maintaining improved immunity to noise and parasitic effects. For example, interconnect block 231 may operate at V ccint The PL interface 232 may be used to interface between the various voltage domains. An example of a PL interface architecture is described in more detail with reference to FIG. 3B.

[0031] The IC 215 also includes a processor system (PS) 235 embodied as a hardwired circuit fabricated as part of the IC 215. The PS 235 may be embodied as or include any of a variety of different processor types. For example, the PS 235 may be embodied as a separate processor, e.g., one core capable of executing program code. In another example, the PS 235 may be embodied as a multi-core processor. In yet another example, the PS 235 may include one or more cores, modules, co-processors, interfaces, and / or other resources. The PS 235 may be embodied using any of a variety of different types of architectures. Example architectures that may be used to embody the PS 235 may include, but are not limited to, an ARM processor architecture, an x86 processor architecture, a RISC architecture, a GPU architecture, a mobile processor architecture, a DSP architecture, or any other suitable architecture capable of executing computer-readable instructions or program code. In some embodiments, the PS 235 may include both a low power domain (LPD) and a full power domain (FPD).

[0032] The IC 215 also includes subsystems such as a network-on-chip (NoC) 225 and / or any of the hardwired circuit blocks 240, 245, 250, 255, and / or 260. Through the NoC 225, one or more DPEs in the DPE array 220 may be able to communicate with the PS and / or the hardwired circuit blocks 255 and 260. In some embodiments, the hardwired circuit blocks 255 and 260 may include, for example, I / O (e.g., an extended performance I / O (XPIO) 256) or a memory controller (MC). In some embodiments, one or more DPEs of the DPE array 220 may be able to communicate with the hardwired circuit blocks 240, 245, 250 via a system-on-chip (SoC) interface block and the PL 230. In some embodiments, the SoC interface block may be directly coupled to one or more subsystems of the IC 215. For example, the SoC interface block may be directly connected to the PS 235 and / or other hardwired circuit blocks. In certain embodiments, the hardwired circuit blocks 240-260 may be considered examples of ASICs.

[0033] In this illustrated example, PS 235 also includes a platform management controller (PMC) 265. PMC 265 is designed as a master power supply that handles power management (e.g., power up / down, reset, isolation, IRO clocking). In some embodiments, PMC 265 may be a natural power domain that should be able to be brought up and used to initiate IC 215 and all other functions in IC 215. Other power domains may also be configured as slave power domains to the PMC power domain. For example, the power supplies of PL 230 (e.g., the power domain of interconnect block 231) may be designed as a subset of the PMC 265 power supplies. In some embodiments, PL 230 may operate at a different reference voltage and clock speed than DPE array 220 and / or PS 235, for example.

[0034] The PMC 265 also includes a power-on reset system (PORS) 270. The PORS 270 is configured to generate a number of isolation signals for power domain crossings. The PORS is also configured to generate a power-on reset (POR) signal after detecting all power supplies, and power supply status signals for the various power supplies. The power supply status signals for the various power supplies can indicate the stability of the various power domains (e.g., PL power domain, PMC power domain). An example in which the PORS controls the sequencing between the power domains in the IC during ramp-up and / or ramp-down is described in further detail with reference to FIG. 3A.

[0035] In this illustrated example, PORS 270 is located in PMC 265, although in various embodiments, PORS 270 may be embodied in a different location (eg, in the programmable logic PL).

[0036] In some embodiments, the PORS 270 may be embodied as a hard-blocked circuit. For example, an application specific integrated circuit (ASIC) may provide the PORS 270 that generates the isolation and POR signals.

[0037] In some embodiments, some or all of the functionality of PORS 270 may be embodied in a processor (e.g., PS 235) configured to execute a set of instructions stored in a data store that controls generation of the isolation and / or POR signals. The processor (e.g., PS 235) and data store may be located on the same integrated circuit 215 as PL 230. In some embodiments, the processor (e.g., PS 235) and data store may be embodied in a programmable logic block (e.g., PL 230) of a system on chip (SoC) or in a hard block using fixed circuitry of the SoC.

[0038] 3A shows an example schematic diagram of various power domains on an IC. Various functional blocks on IC 215 can operate at various voltages. Thus, IC 215 may include several power domains. For example, PS 235 may include a low power domain (LPD) and / or a full power domain (FPD), NoC 225 may have a different power domain, and DPE array 220 may have another different power domain. In this illustrated example, PMC 265 is a natural power domain that should be able to be powered up and used to power IC 216 and all other functions in IC 215.

[0039] In this illustrated example, IC 215 includes a first power domain 300a (provided by a first voltage) and a second power domain 300b (provided by a second voltage). The first domain 300a and the second power domain 300b may provide one or more functional blocks. For example, in some embodiments, DPE array 220 may be provided by first power domain 300a. In some embodiments, PS 235 may be provided by first power domain 300a. In some embodiments, PL 230 may be provided by first power domain 300a. In some embodiments, XPIO 256 may be provided by first power domain 300a. In some embodiments, NoC 225 may be provided by second power domain 300b. In some embodiments, DPE array 220 may be provided by second power domain 300b. The IC 215 also includes an interface circuit 300c (e.g., PL interface 232) that interfaces with the PMC power domain 300 and the first power domain 300a. In this illustrated example, the interface circuit 300c (e.g., PL interface 232) is also used to interface with the first power domain 300a and the second power domain 300b. In some embodiments, other interface circuits may be used to interface with the first power domain 300a and the second power domain 300b. In some embodiments, the IC 215 may include several interface blocks that interface between the corresponding various power domains. For example, the DPE array 220 in FIG. 2 may include a first interface block that communicates with the NoC 225 and a second interface block that communicates with the interconnect block 231. In other examples, the IC 215 may include many different power domains (e.g., six or more power domains).

[0040] In controlling the sequencing between the various power domains, the power status (e.g., voltage) of the various power domains may be received by the PORS and processed by the PORS 270 to generate an isolation signal to apply to the interface block and / or generate a power-on reset signal to reset one or more of the various power domains. For example, the PORS 270 receives the power status (e.g., voltage) 301 of the PMC power domain 300 and the first power status 302 of the first power domain 300a. The received power status may be processed by the PORS 270 to generate an isolation signal 304a. The isolation signal 304a enables or disables the interface circuit 300c to initiate data transfer between the two power domains 300 and 300a. The interface circuit 300c may include several level shifter circuits that may be enabled or disabled by the isolation signal 304a to move data from the PMC power domain 300 to the first power domain 300a and from the first power domain 300a to the PMC power domain 300. For example, when the isolation signal is high (e.g., digital 1), the interface circuit 300c between the PMC power domain 300 and the first power domain 300a may be enabled. When the isolation signal is low (e.g., digital 0), the interface circuit 300c between the two power domains 300 and 300a may be disabled. By controlling the delays between the various isolation signals, the power-up and / or power-down sequence of the various power domains may be controlled. Thereby, the competing currents and / or noise coupling between the various power domains may be advantageously reduced. In this illustrated example, PORS 270 also receives a power status (e.g., voltage) 301 of the PMC power domains 300, a first power status 302 of the first power domain 300a, and a second power status 303 of the second power domain 300b. The received power status may be processed by PORS 270 to generate an isolation signal 304b.The isolation signal 304b allows or prevents the interface circuit 300c from initiating data transfer between the two power domains 300a and 300b. For example, when the isolation signal is at a high level (e.g., digital 1), the interface circuit 300c between the two power domains 300a and 300b may be enabled. When the isolation signal is at a low level (e.g., digital 0), the interface circuit 300c between the two power domains 300a and 300b may be disabled. By controlling the delays between the various isolation signals, the power-up and / or power-down sequence of the various power domains may be controlled. Thereby, the competing currents and / or noise coupling between the various power domains may be advantageously reduced. An example of a PORS architecture is described in further detail with reference to FIG. 4.

[0041] FIG. 3B illustrates an example interface architecture between an interconnect block power domain and an XPIO power domain in the programming logic (PL). More specifically, in this illustrated example, the PL interface 232 interfaces with two different power domains (e.g., ccint Domain and V ccint_soc In this case, the PL interface 232 can provide an interface between the interconnect block 231 and the operating voltage V ccint and the operating voltage V of other circuits in IC215 (e.g., NoC225 and / or XPIO256). ccint_socThe PL interface 232 may provide an interface that transitions between the SoC and the PL power domain. Other circuits may include, for example, a NoC, a math engine (ME), functional blocks in a low power domain (LPD), and / or functional blocks in a full power domain (FPD). In this illustrated example, the PL interface 232 includes a first level shifter 305 configured to move signals from the SoC power domain (e.g., the power domain of the NoC and XPIO) to the PL power domain and enable compatibility between the SoC power domain and the PL power domain. The first level shifter 305 is controlled by an isolation signal iso_soc_pl_b 310. For example, the first level shifter 305 may be enabled or disabled based on whether the isolation signal iso_soc_pl_b 310 is a digital one or a digital zero.

[0042] The PL interface 232 includes a second level shifter 315 configured to move signals from the PL power domain to the SoC power domain and enable compatibility between the PL and SoC power domains. The second level shifter 315 is controlled by an isolation signal iso_pl_soc_b 320. The isolation signals iso_soc_pl_b 310 and iso_pl_soc_b 320 are used as gating signals in the level shifters 305 / 315 across the PL and SoC power domains on the chip. These isolation signals may be generated by the PORS 270. An example of a PORS is described in more detail with reference to FIG. 4. In some embodiments, the connection between the PL interface 232 and the PL 230 may be programmable (e.g., configurable) in width. For example, the connection between the PL interface 232 and the PL 230 may be configured to be 32 bits, 64 bits, or 128 bits in width. In this illustrated example, the PORS 270 increases or decreases the V ccint It also generates a POR signal por_pl_b that resets the domain (for example, V ccintThe domain has a voltage change (e.g., a glitch) that is, for example, 40 ns or longer. PORS 270 also generates a POR signal, por_int_b, that resets interconnect block 231. In some embodiments, POR signal por_int_b can be generated later (e.g., about 3 us) than POR signal por_pl_b to keep data in interconnect block 231 long enough to be received by other functional blocks.

[0043] An example architecture of a power-on reset system on an IC is shown in Figure 4. In this illustrated example, PORS 207 includes a first circuit 405 configured to generate power-on reset signals (e.g., a first power-on reset signal por_int_b to interconnect blocks in PL 230, a second power-on reset signal por_pl_pmc_b to PL-related logic circuits in PMC 265, and a third power-on reset signal por_pl_b to PL 230).

[0044] The first circuit 405 includes a first voltage detection circuit 410. The first voltage detection circuit 410 includes a power-on detection device that detects the power supplies of the PL 230, the PS 235, and the PMC 265. In this illustrated example, the first voltage detection circuit 410 detects the internal core supply voltage V ccint , the supply voltage of the block BRAM V cc_ram , PL auxiliary supply voltage V ccaux , PMC265 internal core supply voltage V ccint_pmc , and the auxiliary supply voltage V of the PMC auxiliary logic circuit ccaux_pmcThe detected voltage is then filtered by a first glitch filter circuit 415 to filter out any power down supply glitches, approximately, for example, at 40 ns or less. The filtered voltage is then processed by a first logic circuit 420a to generate power on reset signals por_int_b, por_pl_pmc_b, and por_pl_b. The POR signal por_int_b can be used to reset the interconnect block 231, and the POR signal por_pl_b can be used to reset the interconnect block 231, and the POR signal por_pl_b can be used to reset the interconnect block 231, and the POR signal por_pl_b can be used to reset the interconnect block 231, and the POR signal por_pl_b can be used to reset the interconnect block 231, and the POR signal por_int ... ccint Can be used to reset the entire domain.

[0045] In this illustrated example, the first logic circuit 420a includes a first AND logic circuit 425. All of the filtered voltages are received by the first AND logic circuit 425 to generate a first AND signal POR_1. The first AND signal POR_1 is delayed by 26 ms or 1 us. A selection circuit (e.g., a two-input multiplexer) 430 is used to receive the 26 ms delayed signal and the 1 us delayed signal. A selection signal skip_por_cnt is used to output the 26 ms delayed signal or the 1 us delayed signal. A user can select between the two delayed signals using the selection signal skip_por_cnt, whereby the output signal generating the first intermediate signal por_pl_pmc_b_src is delayed by 2 ms. The 2 ms delay is V gg is stable, i.e., V ggmay be a regulated power supply for the configuration memory cells of the interconnect block 231. The first intermediate signal por_pl_pmc_b_src and the hardware dependent signal pl_ipor_b are received by a two-input AND gate 435 to generate the por_pl_pmc_b_buf_int signal. The hardware dependent signal pl_ipor_b is a function of the external signal Ext_por_b and the external test (e.g., joint test action group (JTAG) mode). The signal pl_ipor_b signal may be gated by boundary scan, and the boundary scan chain may span many power domains. In some embodiments, isolation control for many power domains may be controlled by software, and the PL power domain and the SoC power domain may be stitched together by the por_pl_b signal. The por_ipor_b signal may control the por_pl_b signal to JTAG requirements.

[0046] Thereby, the por_pl_pmc_b_buf_int signal is processed to generate the power-on reset signals por_int_b, por_pl_pmc_b, and por_pl_b. More specifically, the por_pl_pmc_b_buf_int signal is received by a first buffer 440. The first buffered por_pl_pmc_b_buf_int signal is delayed by 3us during power ramp down. The first buffered por_pl_pmc_b_buf_int signal and the 3us delayed por_pl_pmc_b_src signal are received by a first two-input OR gate 445 to generate the first power-on reset signal por_int_b. The por_pl_pmc_b_buf_int signal is received by a second buffer 450. The second buffered por_pl_pmc_b_buf_int signal is delayed by, for example, about 200ns during power ramp down. The second buffered por_pl_pmc_b_buf_int signal and the 200 ns delayed por_pl_pmc_b_buf_int signal are received by a second two-input OR gate 455 to generate a second power-on reset signal, por_pl_pmc_b. The second power-on reset signal, por_pl_pmc_b, is an internal POR signal used in the PMC power domain 300. The second power-on reset signal, por_pl_pmc_b, is buffered by a third buffer 460 to generate a third power-on reset signal, por_pl_b. The third power-on reset signal, por_pl_b, is an internal POR that is released after all internal PMC and internal PL detection devices are powered and the interconnects and configuration memory cells are ready to be configured. The third power-on reset signal, por_pl_b, also supplies the regulated power supply (V gg) can rise and stabilize. The first power-on reset signal, por_int_b, is a delayed version of por_pl_b and can be used to avoid contention in the interconnect when powering down. The second power-on reset signal, por_pl_pmc_b, can have the same function as the third power-on reset signal, por_pl_b.

[0047] In this illustrated example, the PORS 270 also includes a second circuit 465 configured to generate an isolated signal that can be used by the PL interface 232. The second circuit 465 includes a second voltage detection circuit 470a. The second voltage detection circuit 470a detects the internal core supply voltage V ccint_pmc , and the auxiliary supply voltage V of the PMC auxiliary logic circuit ccaux_pmc The second detection voltage is then filtered by a second glitch filter circuit 475a. The filtered second voltage is then processed by a second two-input AND gate 480a to generate a second AND signal POR_2. The second AND signal POR_2 is a V ccaux_pmcThe second AND signal POR_1 and the external power-on reset signal Ext_por_b are then received by a third two-input AND gate 480b, which generates a third AND signal pmc_raw_por_n. The third AND signal pmc_raw_por_n can act as a master power-on reset signal for the entire IC 215. When the PMC power is ramped up, the external power-on reset signal Ext_por_b is released by the user. User confirmation may be required before releasing the actual internal POR signal. In some embodiments, the first AND signal POR_1 and the second AND signal POR_2 may be monitored by a watchdog circuit. When the first voltage detection circuit 410 and / or the second voltage detection circuit 470a fail, the watchdog circuit may detect the failure and cause the first AND signal POR_1 and the second AND signal POR_2 to externally bypass the first voltage detection circuit 410 and / or the second voltage detection circuit 470a, thereby ensuring that the generation of the first AND signal POR_1 and the second AND signal POR_2 as isolation signals may be a fail-safe option.

[0048] The second circuit 465 also includes a third voltage detection circuit 470b. The third voltage detection circuit 470b detects the power status of all power domains in the IC 215 except for the PMC power domain 300. In this illustrated example, the third voltage detection circuit 470b detects the internal core supply voltage V ccint_soc , PS235's low power domain V cc_psintlp , PS235 full power domain V cc_psintfp , PL230 internal core supply voltage V ccint , the internal core supply voltage of the block BRAM, V ccint_ram , and the auxiliary supply voltage V of the PL auxiliary logic circuitry ccauxThe third voltage detection circuit 470b may also detect the power status of the DPE array 220, for example. In this illustrated example, the voltage detected by the third voltage detection circuit 470b is filtered by a third glitch filter circuit 475b. All of the filtered third detected voltages are output as a power status signal. The filtered third detected voltage, the third AND signal pmc_raw_por_n, the first control signal ctrl_iso_pmc_pl, the second control signal ctrl_iso_pl_soc, and the first intermediate signal por_pl_pmc_b_src are processed by the second logic circuit 420b to generate isolation signals between the various power domains. The first control signal ctrl_iso_pmc_pl and the second control signal ctrl_iso_pl_soc may be stored in an on-chip control register. For example, the first control signal ctrl_iso_pmc_pl is connected to the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ) can be a resistor-based control signal that releases or isolates a signal to the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ) can be isolated. When the control signal ctrl_iso_pmc_pl is low (e.g., digital 0), the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ) A second control signal, ctrl_iso_pl_soc, can also be emitted to the PL power domain (V ccint ) to the NoC / XPIO power domain (V ccint_soc ) can be resistor-based control signals that emit or isolate signals. * 4. Similarly, .function..times ...

[0049] In this illustrated example, a three-input AND gate 480c receives the filtered V ccint, a third AND signal pmc_raw_por_n, and an inverted first control signal ctrl_iso_pmc_pl to generate a fourth AND signal. The fourth AND signal is an isolation signal iso_pl_pmc_b. This isolation signal iso_pl_pmc_b can be used to enable a level shifter that moves data from the PL 230 to the PMC 265. This isolation signal iso_pl_pmc_b is also coupled to the first V ccint Level shifter 485b receives and generates an isolation signal iso_pmc_pl_b that can be used to enable a level shifter that moves data from PMC 265 to PL 230. A four-input AND gate 480d receives the filtered V ccint , filtered V ccint_soc , and the inverted second control signal ctrl_iso_pl_soc to generate a fifth AND signal. ccint A level shifter 485c receives the fifth AND signal and generates an isolation signal iso_soc_pl_b, which can be used to enable a level shifter that moves data from the SoC 215 to the PL 230. The fifth AND signal is also delayed, for example, by 100 ns during power ramp down, to V ccint_soc The second logic circuit is processed by level shifter 485d and by OR gate 490 to generate isolation signal iso_pl_soc_b, which may be used to enable the level shifter to move data from PL 230 to SoC 215. An example datasheet of an isolation signal that may be generated by the second logic circuit is described with reference to FIG.

[0050] For example, in one mode, the total voltage across the PMC domain (e.g., V ccint_pmc , V ccaux_pmc ) and V of PL ccintcan be at a high level. By controlling the ctrl_iso_pmc_pl signal, the isolation signals iso_pmc_pl_b and iso_pl_pmc_b can be generated at a high level (e.g., digital 1). This can enable the corresponding level shifters located between the PMC and the PL and controlled by the isolation signals. In another mode, the full voltage in the PMC domain (e.g., V ccint_pmc , V ccaux_pmc ) may be high, and the voltage in the PL domain V ccint , the voltage in the NoC / XPIO domain V ccint_soc is high, the isolation signals iso_soc_pl_b310 and iso_pl_soc_b320 may be generated at a high level (e.g., digital 1) by controlling the ctrl_iso_pl_soc signal, which may enable the corresponding level shifters controlled by the isolation signals.

[0051] In some embodiments, the first glitch filter circuit 415, the second glitch filter circuit 475a, and / or the third glitch filter circuit 475b may be configured to keep valid an isolation signal generated in response to a disturbance (e.g., a power-down glitch) in either the PMC power domain or the SoC power domain that is shorter than, for example, about 40 ns. The disturbance may be a voltage below a predetermined minimum operating voltage for less than a predetermined time threshold. ccint_ram , V ccint , V ccaux ) is powered down, the isolation signal iso_pl_soc_b320 may be generated later than the isolation signal iso_soc_pl_b310. For example, the isolation signal iso_pl_soc_b320 may be generated about 100 ns after the isolation signal iso_soc_pl_b310. This may cause the second level shifter 315 to be enabled about 100 ns after the first level shifter 305. This may cause the PORS 270 to be enabled about 200 ns after the isolation signal iso_soc_pl_b310. ccintThis generates the por_pl_b signal that resets the domain. This way of sequencing the isolation signals can avoid noise or glitch propagation to the XPIO256 during power down. The level shifter (e.g., second level shifter 315) from the interconnect (PL domain) to the XPIO (SoC domain) can be locked 100 ns before powering down the PL domain by asserting por_pl_b low (with iso_pl_soc_b=0). This resets the V gg To avoid any interconnect contention due to memory cells, the interconnect block 232 can be reset within 3us by the por_int_b signal after por_pl_b.

[0052] FIG. 5 illustrates an example datasheet related to example isolated signals generated by the power-on reset system. The datasheet includes isolated signals between various power domains. For example, the datasheet includes isolated signals iso_soc_pmc_b and iso_pl_pmc_b. The datasheet also includes isolated signals between the math engine and the PL (e.g., iso_1_me_pl, iso_1_pl_me, iso_2_me_pl, etc.) and between the math engine and the SoC (e.g., iso_1_me_soc, iso_1_soc_me, iso_2_me_soc, etc.). A separate portion of the POR corresponding to the math engine (ME) can effectively reduce or eliminate buffering / loading requirements.

[0053] 6 illustrates a flow chart of an exemplary method for coordinating power transitions between power domains in an IC. Power transitions may include powering up and / or powering down power domains in an IC 215. In method 600, at 605, a controller (e.g., PS 235) detects whether a PMC power domain 300 (e.g., master power supply) is powered on. If a PNC power domain 300 is not powered on (e.g., V ccint_pmc and V ccaux_pmcis low), the controller continues to monitor the status of the PMC power domain 300. If the PMC power domain 300 is powered on (e.g., V ccint_pmc and V ccaux_pmc is high), in this illustrated example, at 610, the controller instructs the voltage detection circuit to detect the power status S0 (e.g., voltage) of the PMC power domain 300, the power status S1 (e.g., voltage) of the first power domain (e.g., 300a) (e.g., slave power supply), and the power status S2 of the second power domain (e.g., 300b) (e.g., slave power supply). For example, the voltage detection circuit detects the power status V ccint_soc and the power supply V of the interconnect domain ccint In some embodiments, the first power domain and the second power domain may be any power domain of IC 215 other than the PMC power domain (e.g., PL, PS, NoC, XPIO, or ME). In some embodiments, the controller may instruct the voltage detection circuit to detect the power status S0 (e.g., voltage) of the PMC power domain 300 and the power status S1 (e.g., voltage) of the first power domain (e.g., 300a) and generate an isolation signal and / or a POR signal to the PMC power domain and / or the first power domain, as appropriate.

[0054] At 615, the controller determines whether the PMC power domain, the first power domain, and / or the second power domain have a glitch of greater than or equal to a predetermined threshold (e.g., 40 ns). For example, in an embodiment of this understanding, the controller determines whether the second power domain has a glitch of greater than or equal to 40 ns.

[0055] If the glitch is less than 40 ns, then at 620 the controller commands the PORS 270 to generate a first isolation signal (e.g., 310) that allows a first level shifter (e.g., level shifter circuit 305) to move data from a first power domain (e.g., first power domain 300a) to a second power domain (e.g., second power domain 300b), and at 625 the controller commands the PORS 270 to generate a second isolation signal (e.g., second isolation signal 320) that allows a second level shifter (e.g., level shifter circuit 315) to move data from the second power domain to the first power domain. The method then loops back to 615 where the second power domain continues to monitor for a glitch of 40 ns or more.

[0056] If the glitch is greater than 40 ns (e.g., if the glitch is between 40 ns and 80 ns), at 630, the controller commands PORS 270 to generate a first isolation signal that disables a first level shifter that moves data from the first power domain to the second power domain, and at 635 and 640, the controller commands PORS 270 to generate a second isolation signal that disables a second level shifter that moves data from the first power domain to the second power domain after a first predetermined delay (e.g., 100 ns) from the generation of the first isolation signal. At 645 and 650, the controller commands PORS 270 to generate a POR signal that resets the second power domain after a second predetermined delay (e.g., 200 ns after the generation of the first isolation signal or 100 ns after the generation of the second isolation signal).

[0057] In some embodiments, if there is a long glitch in the first power domain or the PMC power domain (eg, a voltage disturbance of more than 40 ns), PORS 270 may generate a POR signal that resets the first power domain or the PMC power domain.

[0058] Different subsystems (e.g., PL (interconnect), NoC (SoC), XPIO, ME, and / or PS) may be controlled in response to different isolation signals. By generating the isolation and POR signals after various predefined delays (e.g., about 100ns delay, 3us delay, 200ns delay), smooth power sequencing may be controlled to avoid contention during power-up and / or power-down of various power supplies. For example, sequencing of isolation signals between PL and SoC may be controlled to avoid glitch propagation to XPIO when one of the PL power supplies ramps down. A sequence of events to avoid glitches may include first isolating XPIO / SoC to PL using iso_soc_pl_b, then isolating PL to SoC using iso_pl_soc_b signal with about 100ns delay at power-down, and releasing por_pl_b signal with about 200ns delay from isolation from XPIO / SoC to PL at power-down. Thus, the level shifters from the interconnect blocks in the PL domain to the SoC domain of the XPIOs can be frozen before powering down the PL domain by asserting por_pl_b low.

[0059] Although various embodiments have been described with reference to the figures, other embodiments are possible. For example, mini PORS can be used when a new power domain is added. In some embodiments, the PL interface 232 (e.g., level shifters 305, 320) can be located in the PS 235 or the PL 230.

[0060] In some embodiments, some or all of the voltage detection circuits 410, 470a, 470b may be located in the PS 235 or the PL 230. In another embodiment, some or all of the logic gates (e.g., AND gates, OR gates) in the first circuit 405 and the second circuit 465 may be located in the PS 235 or the PL 230.

[0061] Various examples of modules including various electronic hardware may be embodied using circuits. By way of example and not limitation, hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other modules. In various examples, modules may include analog and / or digital logic circuits, discrete components, trace circuits, and / or memory circuits fabricated on silicon substrates, including various integrated circuits (e.g., FPGAs, ASICs). In some embodiments, modules may involve the execution of pre-programmed instructions and / or software executed by a processor. For example, various modules may involve both hardware and software.

[0062] In various implementations, the communication system can communicate using suitable communication methods, equipment, and techniques. For example, the system can communicate with compatible devices (e.g., devices that can move data to and / or from the system) using point-to-point communication, where messages are conveyed directly from a source to a recipient via a dedicated physical link (e.g., fiber optic link, infrared link, ultrasonic link, point-to-point wiring, daisy-chain). The components of the system can exchange information, including packet-based messages, over the communication network by analog or digital data communication of any form or medium. Examples of communication networks include, for example, LANs (local area networks), WANs (wide area networks), MANs (metropolitan area networks), wireless and / or optical networks, and the computers and networks that make up the Internet. In other implementations, messages can be conveyed by broadcasting to all or nearly all devices connected together by the communication network, for example, by using omnidirectional radio frequency (RF) signals. In still other embodiments, messages may be carried that are characterized by high directionality, such as RF signals transmitted using directional (i.e., narrow beam) antennas, or infrared signals that may possibly be used with focusing optics. Still other implementations may be envisioned using corresponding interfaces and protocols, such as, by way of example and not by way of limitation, USB2.0, FireWire, ATA / IDE, RS-232, RS-422, RS-485, 802.11a / b / g / n, Wi-Fi, WiFi-Direct, Li-Fi, BlueTooth, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), Token-Ring networks, or frequency, time, or code division based multiplexing techniques.Depending on the implementation, features such as Error Checking and Correction (ECC) may be incorporated for data integrity, or security measures such as encryption (eg, WEP) and password protection.

[0063] Several implementations have been described. Nevertheless, it will be appreciated that various modifications may be made. For example, beneficial results may be obtained if the steps of the disclosed techniques were performed in a different order, or if the components of the disclosed systems were combined in various ways, or if the components were supplemented with other components. Accordingly, other implementations are within the scope of the following claims.

Claims

1. a first area provided by a first power domain; a second area provided by a second power domain; and a programmable interface disposed directly between the first power domain and the second power domain; a first level shifting circuit disposed within the programmable interface and configured to move first data from the first power domain to the second power domain; a second level shifting circuit disposed within the programmable interface and configured to move second data from the second power domain to the first power domain; A power-on reset system (PORS) is provided. The PORS is a voltage detection circuit configured to detect a voltage of the first power domain and the second power domain; a control circuit coupled to the first level shifting circuit and the second level shifting circuit, configured to generate a first isolation signal for controlling the first level shifting circuit and a second isolation signal for controlling the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain, control a delay between the first isolation signal and the second isolation signal, and control noise coupling between the first power domain and the second power domain.

2. 2. The integrated circuit of claim 1, further comprising a glitch filter circuit coupled to the voltage detection circuit, the PORS being indicative of a voltage change in the second power domain.

3. 3. The integrated circuit of claim 2, wherein the control circuit is further configured to disable the first level shifting circuit and then disable the second level shifting circuit a first predetermined delay after the voltage change in the second power domain exceeds a predetermined period of time.

4. 4. The integrated circuit of claim 3, wherein the control circuitry is further configured to emit a power-on reset signal that resets the second power domain a second predetermined delay after disabling the second level shifting circuit.

5. 2. The integrated circuit of claim 1, wherein the second region is disposed in a portion of the IC that does not overlap the first region.

6. 2. The integrated circuit of claim 1, wherein the first domain comprises a platform management controller (PMC) configured to act as a master power supply and provide power management for the IC.

7. The integrated circuit of claim 6 , wherein the second region comprises a processor system (PS) or a programmable logic (PL) block.

8. a third region provided by a third power domain; and a third level shifting circuit coupled to move third data from the second power domain to the third power domain; a fourth level shifting circuit coupled to move a fourth data from the third power domain to the second power domain; 8. The integrated circuit of claim 7, wherein the voltage detection circuit is further configured to detect voltages of the first power domain, the second power domain, and the third power domain, and the control circuit is further configured to couple to the third level shifting circuit and the fourth level shifting circuit and generate a third isolation signal for controlling the third level shifting circuit and a fourth isolation signal for controlling the fourth level shifting circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain.

9. A method for coordinating power transitions between power domains, comprising: a first power domain providing a first region; a second power domain providing a second region; disposing a programmable interface directly between the first power domain and the second power domain; disposing a first level shifting circuit within the programmable interface to move first data from the first power domain to the second power domain; disposing a second level shifting circuit within the programmable interface to move second data from the second power domain to the first power domain; detecting a voltage of the first power domain and the second power domain; generating, by a control circuit, a first isolation signal that controls the first level shifting circuit and a second isolation signal that controls the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain, and controlling, by the control circuit, a delay between the first isolation signal and the second isolation signal and noise coupling between the first power domain and the second power domain.

10. when the voltage change of the second power domain exceeds a predetermined period of time; disabling the first level shifting circuit using the first isolation signal; disabling the second level shifting circuit using the second isolation signal a first predetermined delay after disabling the first level shifting circuit; 10. The method of claim 9, further comprising: disabling the second level shifting circuit and resetting the second power domain a second predetermined delay after releasing a power-on reset signal.

11. 11. The method of claim 10, wherein the second region is located in a portion of an IC that does not overlap with the first region.

12. 12. The method of claim 11, wherein the first domain comprises a platform management controller (PMC) configured to act as a master power supply and provide power management for the IC.

13. 13. The method of claim 12, wherein the second region comprises a processor system (PS), an extended performance I / O block (XPIO), or a programmable logic (PL) block.

14. a third power domain providing a third region; moving third data from the second power domain to the third power domain; moving a fourth data from the third power domain to the second power domain; detecting a voltage of the first power domain, the second power domain, and the third power domain; 14. The method of claim 13, further comprising: controlling the third level shifting circuit using a third isolated signal and controlling the fourth level shifting circuit using a fourth isolated signal in response to the detected voltages of the first power domain, the second power domain, and the third power domain.

15. when the voltage change of the third power domain exceeds a predetermined period of time; disabling the third level shifting circuit using the third isolation signal; and disabling the fourth level shifting circuit using the fourth isolation signal a third predetermined delay after disabling the third level shifting circuit; 15. The method of claim 14, further comprising: disabling the fourth level shifting circuit and resetting the third power domain a fourth predetermined delay after releasing a power-on reset signal.

Images