Integrated circuit including vertical electrical connections connecting plurality of semiconductor dies and electronic device including same

Abstract

A processing chip assembly according to one embodiment includes: a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; and an interconnection layer, wherein the interconnection layer is arranged between the first bare chip and the second bare chip. The interconnect layer may include a first through silicon via (TSV), the first TSV connecting the first SERDES circuit and the second SERDES circuit, and the second TSV connecting the first SERDES circuit and the second SERDES circuit. The second circuit is coupled to the third circuit so as to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit comprising a vertical electrical connection connecting multiple semiconductor dies and an electronic device including the integrated circuit. Background Technology

[0002] A system-on-a-chip (SoC) is an electronic component that integrates circuitry that performs various functions. As the number of functions supported by electronic devices, including SoCs, increases, the complexity of the circuitry integrated within the SoC also increases.

[0003] To aid in understanding this disclosure, the information described above may be provided as related technology. Nothing described above is to be claimed to be prior art relating to this disclosure, or that it should not be used in decisions relating to prior art. Summary of the Invention

[0004] Technical solution According to an embodiment, a processing chip assembly may include a first die, the first die including a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first circuit and the second circuit. The processing chip assembly may include a second die, the second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip assembly may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through-silicon via (TSV), the first TSV being configured to connect between the first SERDES circuit and the second SERDES circuit and providing a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

[0005] According to an embodiment, a processing chip assembly may include a first die, the first die including a first circuit and a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit. The processing chip assembly may include a second die, the second die including a third circuit and a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip assembly may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through-silicon via (TSV), the first TSV being configured to directly connect the first circuit to the third circuit and being configured to transmit a first type of signal from the first circuit to the third circuit. The interconnect layer may include a second TSV, the second TSV being configured to connect the first SERDES circuit to the second SERDES circuit and being configured to serialize and transmit a second type of signal based on the first SERDES circuit. The second type of signal transmitted through the second TSV may include a sequence of at least one bit provided by the first circuit and at least one bit provided by the second circuit.

[0006] According to an embodiment, an electronic device may include a memory and a processor. The processor may include a first die comprising a plurality of circuits and a first serializer-deserializer (SERDES) circuit, the plurality of circuits including a central processing unit (CPU), the first SERDES circuit being coupled to each of the plurality of circuits. The processor may include a second die comprising a memory interface circuit and a second SERDES circuit for communicating with the memory. The processor may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the CPU of the first die to the memory interface circuit. The interconnect layer may include a second TSV configured to connect the first SERDES circuit to the second SERDES circuit. The CPU may be configured to transmit data signals, including data to be stored in the memory, to the memory interface circuit via the first TSV. The CPU may be configured to send control signals to the first SERDES circuit for controlling the memory interface circuit, such that the data is sent to the memory.

[0007] According to an embodiment, a three-dimensional integrated circuit may include: a substrate; a first integrated circuit layer disposed above the substrate and including a plurality of first circuit elements; a second integrated circuit layer disposed above the first integrated circuit layer and including a plurality of second circuit elements; and an interconnect layer disposed between the first integrated circuit layer and the second integrated circuit layer and including a plurality of through-silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first control signal pins and at least one first data signal terminal. The plurality of first control signal pins may be connected to a first TSV among the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of second control signal pins corresponding to the plurality of first control signal pins and at least one second data signal pin corresponding to the at least one first data signal pin. The first TSV may be connected to the plurality of second control signal pins via a second SERDES circuit.

[0008] According to an embodiment, an electronic device may include: a display; an antenna; a printed circuit board; a first integrated circuit disposed on the printed circuit board; and a second integrated circuit disposed on the printed circuit board and electrically connected to the first integrated circuit. The second integrated circuit may include: a first circuit layer including a plurality of first circuit elements; a second circuit layer disposed above the first circuit layer and including a plurality of second circuit elements; and a connection layer disposed between the first circuit layer and the second circuit layer and including a plurality of through-silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first control signal pins and at least one first data signal pin. The plurality of first control signal pins may be connected to a first TSV among the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of second control signal pins corresponding to the plurality of first control signal pins and at least one second data signal pin corresponding to the at least one first data signal pin. The first TSV may be connected to the plurality of second control signal pins via a second SERDES circuit.

[0009] According to an embodiment, an integrated circuit may include a first integrated circuit layer, the first integrated circuit layer including a plurality of first circuit elements corresponding to a first minimum circuit linewidth. The integrated circuit may include a second integrated circuit layer disposed above the first integrated circuit layer and including a plurality of second circuit elements corresponding to a second minimum circuit linewidth smaller than the first minimum circuit linewidth. The integrated circuit may include a plurality of paths electrically connecting the first integrated circuit layer and the second integrated circuit layer. The first integrated circuit layer may include a first serializer-deserializer (SERDES) circuit connecting the plurality of first circuit elements to a first path that is a specific path among the plurality of paths. The second integrated circuit layer may include a second SERDES circuit connecting the first path to the plurality of second circuit elements.

[0010] According to an embodiment, an application processor (AP) may include: a first circuit layer including a first serializer-deserializer (SERDES) electronic component connected to each of a first electronic component, at least one second electronic component, and a third electronic component including the first electronic component and the at least one second electronic component; a second circuit layer including a fourth electronic component and a second SERDES electronic component connected to the fourth electronic component; and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a through-silicon via (TSV), the TSV including a first through-silicon via (TSV) connecting the first electronic component to the fourth electronic component and a second TSV connecting the first SERDES electronic component to the second SERDES electronic component. The first electronic component may transmit a first type of signal to the fourth electronic component via the first TSV in the interconnect layer. The first electronic component may transmit a second type of signal to the first SERDES electronic component to transmit the second type of signal to the fourth electronic component. The first SERDES electronic component may serialize the second type of signal together with at least one signal transmitted from the at least one second electronic component. The first SERDES electronic component can transmit a signal obtained based on the serialization to the second SERDES electronic component via the second TSV. The second SERDES electronic component can be configured to obtain a signal of the second type to be transmitted to the fourth electronic component based on demodulation and / or deserialization of the signal transmitted via the second TSV.

[0011] According to an embodiment, an application processor (AP) may include: a first circuit layer including a first electronic component, a plurality of second electronic components including the first electronic component, and a first serializer-deserializer (SERDES) electronic component connected to each of the plurality of second electronic components; a second circuit layer including a third electronic component and a second SERDES electronic component connected to the third electronic component; and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the first electronic component to the third electronic component and configured to send a first type of signal from the first electronic component to the third electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component to the second SERDES electronic component and configured to transmit a second type of signal based on the serialization of the first SERDES electronic component. The second type of signal transmitted via the second TSV may include a sequence of bits based on the serialized plurality of second electronic components, including at least one bit provided by the first electronic component.

[0012] According to an embodiment, an electronic device may include a memory and an application processor (AP). The AP may include: a first circuit layer including a plurality of electronic components and a first serializer-deserializer (SERDES) electronic component, the plurality of electronic components including a central processing unit (CPU), the first SERDES electronic component being connected to each of the plurality of electronic components; a second circuit layer including a memory interface electronic component and a second SERDES electronic component for communicating with the memory; and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the CPU of the first circuit layer and the memory interface electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component and the second SERDES electronic component. The CPU may be configured to send data signals, including data to be stored in the memory, to the memory interface electronic component via the first TSV. The CPU, as the first SERDES electronic component, may be configured to send control signals to control the memory interface electronic component, causing the data to be sent to the memory. Attached Figure Description

[0013] Figure 1An exemplary hardware configuration of an electronic device including an application processor (AP) according to an embodiment is shown.

[0014] Figure 2 An exemplary structure of the interconnect layer included in the AP according to an embodiment is shown.

[0015] Figure 3a , Figure 3b and Figure 3c An embodiment of an AP comprising multiple circuit layers connected via interconnect layers is shown.

[0016] Figure 4 An exemplary structure of the interconnect layer included in the AP according to an embodiment is shown.

[0017] Figure 5 An exemplary structure for an interconnect layer that supports multiple wired communication protocols is shown.

[0018] Figure 6 This is an exemplary timing diagram of electrical signals transmitted from the interconnect layer based on the biphase mark coding (BMC) scheme.

[0019] Figure 7 This is a block diagram of an electronic device in a network environment according to various embodiments. Detailed Implementation

[0020] In the following description, various embodiments of this document will be described with reference to the accompanying drawings.

[0021] Figure 1 An exemplary hardware configuration of an electronic device 101 including an application processor (AP) 110 according to an embodiment is shown.

[0022] Reference Figure 1 Electronic device 101 can be one of various types of electronic devices, such as a laptop personal computer (PC) 190, a smartphone 191 with various form factors (e.g., a candybar smartphone 191-1, a foldable smartphone 191-2, or a sliding (or rollable) smartphone 191-3), a tablet PC 192, a head-mounted display (HMD) device 193, a watch 194, a cellular phone (not shown), and other similar computing devices (not shown). Electronic device 101 can be referred to as a mobile device, user equipment (UE) (or user terminal), multi-functional device, portable device, or server. The form factor of electronic device 101 is not limited to... Figure 1The exemplary shape factor is shown. For example, electronic device 101 may be included as an electronic control unit (ECU) in a vehicle (e.g., an electric vehicle (EV)). For example, electronic device 101 may have a shape factor that is wearable by a user, such as earplugs (or wireless headphones) and / or a ring, or may have a shape factor that can be implanted in a part of a user's body.

[0023] Figure 1 The components, their relationships, and their functions shown are illustrative only and do not limit the implementations described or claimed in this document. See also... Figure 1 According to an embodiment, electronic device 101 may include components such as a processor (e.g., an application processor (AP), a communication processor (CP) 110), a memory (e.g., volatile memory 121 and / or non-volatile memory 122), a display 123, communication circuitry 124, an image sensor 125, and / or a sensor 126. For example, the processor may be implemented as a three-dimensional integrated circuit (3D-IC) including multiple circuit layers.

[0024] Reference Figure 1 The illustration shows an embodiment in which processor 110, volatile memory 121, non-volatile memory 122, and / or communication circuitry 124 are disposed above or on a printed circuit board (PCB) 105, but the embodiment is not limited thereto. On the PCB 105, processor 110 may be electrically coupled and / or operatively coupled to volatile memory 121, non-volatile memory 122, and / or communication circuitry 124. In the following, operative coupling of components may mean a direct or indirect connection between components established via wired or wireless means, such that a second component is controlled by a first component.

[0025] The components included in the electronic device 101 are not limited to Figure 1 In some embodiments, electronic device 101 may include other components (e.g., power management integrated circuit (PMIC), audio processing circuitry, antenna, rechargeable battery, or input / output interface). For example, some components may be omitted from electronic device 101. For example, several components may be integrated into one component.

[0026] Reference Figure 1The volatile memory 121 and / or non-volatile memory 122 can be configured to store data and / or instructions based on an address space managed by the processor 110. The display 123 can display images and / or video provided by the processor 110 on a surface (e.g., a flat surface and / or a curved surface) of the housing of the electronic device 101. The communication circuitry 124 can be configured to support wired and / or wireless communication between the electronic device 101, including the processor 110, and external electronic devices. The image sensor 125 can be configured to provide an electrical signal representing external light to the processor 110 and / or memory (e.g., volatile memory 121 and / or non-volatile memory 122). The sensor 126 can be configured to provide an electrical signal to the processor 110 and / or memory (e.g., volatile memory 121 and / or non-volatile memory 122) at least based on the external environment. Figure 1 The volatile memory 121, non-volatile memory 122, display 123, communication circuit 124, image sensor 125, and sensor 126 can each correspond to Figure 7 The volatile memory 732, non-volatile memory 734, display module 760, communication module 790, camera module 780, and sensor module 776 shown are also included.

[0027] According to an embodiment, electronic device 101 may include a processor 110 for processing data. Processor 110 may include circuit elements comprising passive components, transistors, diodes, or combinations thereof. In processor 110, logic circuitry for processing data may be interconnected. Processor 110 may be referred to as an integrated circuit (IC) and / or a system-on-a-chip (SoC). The circuitry included in processor 110 may be divided into units, modules, and / or electronic components according to function. For example, processor 110 may include electronic components such as a central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), image signal processor (ISP), display controller, memory controller, storage controller, application processor (AP), communication processor (CP), and / or sensor interface. Hereinafter, units, modules, and / or electronic components are collections of circuitry included in processor 110 and may refer to at least a portion of processor 110 designed to perform a particular function. Figure 1 The processor 110 can correspond to Figure 7 The processor is 120.

[0028] According to an embodiment, processor 110 may have a three-dimensional integrated circuit (3D-IC) structure in which multiple dies are stacked. A die may be referred to as a circuit layer and / or integrated circuit layer (IC layer) in relation to including one or more circuit elements. The yield of the die (e.g., the defect rate of the die) may decrease as the area of ​​the die decreases (e.g., random failures). Because processor 110, designed to include multiple dies, comprises dies with a smaller area compared to a case designed to include a single die, it can be manufactured with an improved yield compared to a case with a single die. Hereinafter, "layer" may be used to distinguish layers in processor 110 along a reference direction (in... Figure 1 In the embodiments, the term "layer" refers to the stacked dies and / or substrates (in the z-axis direction). For example, "layer" can be replaced with terms such as "substrate," "layer hierarchy," "semiconductor die," and / or "die." Processor 110 may include multiple dies based on silicon wafers. Embodiments are not limited thereto, and processor 110 may include dies based on silicon carbide (SiC) wafers, gallium nitride (GaN) wafers, gallium arsenide (GaAs) wafers, and / or any other suitable wafers.

[0029] According to an embodiment, a first circuit layer 130 and a second circuit layer 150 are shown in processor 110. In processor 110, the first circuit layer 130 may be disposed (or positioned) above the second circuit layer 150. (See also...) Figure 1 An exemplary structure is shown for a second circuit layer 150 included in a processor 110 and a first circuit layer 130 disposed above the second circuit layer 150 along the z-axis direction (e.g., vertical direction). The first circuit layer 130 and the second circuit layer 150 may be arranged parallel to the xy plane in the processor 110. Based on the first circuit layer 130 and / or the second circuit layer 150 disposed along the z-axis direction, circuit elements may have different three-dimensional positions in the processor 110. In terms of including circuit elements with three-dimensional positions, the processor 110 may be referred to as a three-dimensional integrated circuit (3D-IC), a 3D package, a 3D stacked IC (SIC), a processing chip assembly, and a monolithic 3DIC.

[0030] According to an embodiment, the processor 110 may include at least one interconnect layer (or connection layer) 140 disposed between the first circuit layer 130 and the second circuit layer 150. The interconnect layer may be referred to as an interposer (or interposer). The interconnect layer may be formed based on materials such as silicon, glass, and / or organic compounds.

[0031] In an embodiment, the processor 110 may further include Figure 1 Other components not shown in the figure and Figure 1The first circuit layer 130, the second circuit layer 150, and the interconnect layer 140 are exemplarily shown. For example, the processor 110 may include a substrate, a redistribution layer (RDL), and / or at least one solder ball. The substrate and / or RDL may be disposed below the second circuit layer 150, for example, along the -z-axis direction. The processor 110 may include a package structure surrounding the components described above.

[0032] In an embodiment, the interconnect layer 140 formed between the first circuit layer 130 and the second circuit layer 150 may include a component for supporting an electrical connection between the first circuit layer 130 and the second circuit layer 150. This component may include a through-silicon via (TSV). A TSV may be referred to as a through-chip via and / or a through-hole. This component is not limited to a TSV and may include another component (e.g., a bonding wiring) for electrical connection along the z-axis. The interconnect layer 140 may be formed in various forms. For example, the interconnect layer 140 may be formed with substantially the same width, height, thickness, area, shape, and / or size as the first circuit layer 130 and / or the second circuit layer 150, but is not limited thereto, and may be formed with various widths, heights, thicknesses, areas, shapes, and / or sizes. According to an embodiment, the interconnect layer 140 may include at least one connection member (e.g., wiring, solder bumps, metal bumps, and other conductive adhesives) based on an access technology different from that of a TSV. The first circuit layer 130 and the second circuit layer 150 may be electrically connected via the connection member included in the interconnect layer 140.

[0033] Reference Figure 1 An example of an interconnect layer 140 including at least one TSV (e.g., a first TSV 141 and / or a second TSV 142) is shown. Multiple TSVs included in the interconnect layer 140 can be formed based on a front-pass process formed prior to the front-end (FEOL) and / or back-end (BEOL) processes of the first circuit layer 130 and / or the second circuit layer 150. In the front-pass process, the multiple TSVs may be degraded or distorted due to heat transferred to the interconnect layer 140 during the FEOL and / or BEOL processes. The embodiments are not limited thereto, and multiple TSVs included in the interconnect layer 140 can also be formed based on a back-pass process formed after the FEOL and / or BEOL processes. With the back-pass process, multiple TSVs can be formed independently of the heat generated in the FEOL and / or BEOL processes. While multiple TSVs are formed via the back-pass process (e.g., an etching process), circuit elements included in the first circuit layer 130 and / or the second circuit layer 140 may be damaged. For example, as the number of TSVs included in the interconnect layer 140 is reduced, the yield of the processor 110 can be improved.

[0034] According to an embodiment, processor 110 may include structures for reducing the number of TSVs included in interconnect layer 140. For example, TSV 141 for transmitting combinations (or bundles) of signals and / or information generated from each of the electronic components and / or circuits included in first circuit layer 130 may be formed in interconnect layer 130. To generate combinations, processor 110 may include a first serializer-deserializer (SERDES) circuit 131 connected to each electronic component (e.g., a first circuit element) included in first circuit layer 130. The first SERDES circuit 131 may be electrically connected to the end of TSV 141 adjacent to first circuit layer 130.

[0035] In an embodiment, processor 110 may include a second SERDES circuit 151 configured to receive signal or combined information transmitted from a first SERDES via TSV 141. The second SERDES circuit 151 may be electrically connected to the other end of TSV 141 adjacent to the second circuit layer 150. The second SERDES circuit 151 may be configured to obtain signals and / or information to be transmitted to at least one circuit included in the second circuit layer 150 from the signal or combination (i.e., combined information) transmitted from the first SERDES via TSV 141. The second SERDES circuit 151 may be included in the second circuit layer 150. The second SERDES circuit 151 may be connected to each circuit included in the second circuit layer 150. An embodiment in which a combination of signals and / or information generated in the first circuit layer 130 is transmitted to the second circuit layer 150 via TSV 141 has been described; however, the embodiment is not limited thereto, and combinations of signals and / or information generated in each circuit of the second circuit layer 150 may be transmitted to the first circuit layer 130 via TSV 141. That is, the first SERDES circuit 131, the second SERDES circuit 151, and the TSV 141 enable bidirectional communication between the circuits in the first circuit layer 130 and the circuits in the second circuit layer 150. (Refer to...) Figures 2 to 5 An exemplary structure of a first SERDES circuit 131 and a second SERDES circuit 151 connected to the two ends of TSV 141 is described.

[0036] In reference Figure 1In the processor 110 described, which includes TSV 141, first SERDES circuit 131, and second SERDES circuit 151, TSV 141 can be configured to transmit information between circuits disposed in each different circuit layer (e.g., first circuit layer 130 and / or second circuit layer 150). Because at least one circuit in the first circuit layer 130 is electrically connected to TSV 141 via the first SERDES circuit 131, and at least one circuit in the second circuit layer 150 is electrically connected to TSV 141 via the second SERDES circuit 151, a particular circuit in the first circuit layer 130 can be designed to communicate with another circuit disposed in the second circuit layer 150 without an additional TSV. For example, the TSV for connecting at least one circuit in the first circuit layer 130 to a circuit in the second circuit layer 150 may not be configured separately for each circuit, but may be integrated into TSV 141. In an embodiment, interconnect layer 140 may further include a TSV 141 connecting the first SERDES circuit 131 and the second SERDES circuit 151, and another TSV dedicated to communication between circuits located in different circuit layers. Figure 1 In one embodiment, processor 110 may include a TSV 142 configured to electrically connect circuit 132 of the first integrated circuit layer 130 and circuit 152 of the second circuit layer 150. Circuit 132 can directly transmit a first type of signal (e.g., a signal including data) to circuit 152 via TSV 142. To transmit a second type of signal (e.g., a signal for controlling circuit 152) via TSV 141, circuit 132 can send the second type of signal to the first SERDES circuit 131. For example, either TSV 141 or 142 can be selected for signal transmission depending on the type of signal, data rate, and / or protocol. (See reference...) Figures 3a to 3c This describes exemplary operation of processor 110 and / or circuitry using TSVs 141 and 142 for communication within processor 110. Reference will be made to... Figure 6 An example of the communication protocol used by the first SERDES circuit 131 and the second SERDES circuit 151 to transmit signals in the TSV 141 is described.

[0037] As described above, according to an embodiment, the processor 110 included in the electronic device 101 may have a structure in which multiple signal paths (or signal pins) connected between circuits are integrated into a number of signal paths less than the number of signal paths (e.g., forming a single signal path TSV 141). By using an interface structure based on TSV 141, first SERDES circuit 131, and second SERDES circuit 151, the processor 110 can support communication between circuit 132 disposed in the first circuit layer 130 and circuit 152 disposed in the second circuit layer 150. Because the processor 110 is designed and / or manufactured to have a relatively small number of TSVs based on the interface structure, the yield of the processor 110 can be improved.

[0038] For example, processor 110 (or processing chip assembly) includes: a first die including a first circuit, a second circuit (e.g., a first circuit layer 130), and a first SERDES circuit 131 connected to the first and second circuits; a second die including a third circuit, a fourth circuit (e.g., a second circuit layer 150), and a second SERDES circuit 151 connected to the third and fourth circuits; and an interconnect layer 140 disposed between the first die and the second die, wherein the interconnect layer 140 includes a first TSV 141 configured to connect the first SERDES circuit 131 and the second SERDES circuit 151. For example, the first TSV 141 can provide a first signal path between the first and third circuits, a second signal path between the first and fourth circuits, a third signal path between the second and third circuits, and a fourth signal path between the second and fourth circuits. As described above, the first TSV 141 can provide a single signal path through each of the first, second, third, and fourth signal paths.

[0039] The first SERDES circuit 131 can be configured to serialize signals transmitted from the first circuit and signals transmitted from the second circuit, and transmit the serialized signal to the second SERDES circuit 151 via the first TSV 141. The second SERDES circuit 151 can be configured to obtain a signal to be transmitted to at least one of the third and fourth circuits based on the deserialization of the signal transmitted via the first TSV 141. The second SERDES circuit 151 can also be configured to serialize signals transmitted from the second circuit and signals transmitted from the fourth circuit, and transmit the serialized signal to the first SERDES circuit 131 via the first TSV 141. The first SERDES circuit 131 can also be configured to obtain a signal to be transmitted to at least one of the first and second circuits based on the deserialization of the signal transmitted via the first TSV 141.

[0040] The first SERDES circuit 131 and the second SERDES circuit 151 can be configured to obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path based on the number of bits of each of the plurality of bits in the signal transmitted through the first TSV, according to the deserialization.

[0041] Interconnect layer 141 may further include a second TSV 142 connecting the first circuit to the third circuit. The second TSV 142 may provide a fifth signal path between the first circuit and the third circuit, wherein the fifth signal path does not include the first SERDES circuit 131 and does not include the second SERDES circuit 151.

[0042] In the example, the first circuit can be configured to transmit a first type of signal to the third circuit via a second TSV 142 in interconnect layer 140, and to transmit a second type of signal to the first SERDES circuit 131 to transmit the second type of signal to the third circuit via the first TSV. For example, the first and third circuits, which are directly (i.e., via TSV 142) and indirectly (i.e. via the first SERDES circuit 131, TSV 141, and the second SERDES circuit 151), can selectively use direct or indirect connections based on the purpose, data rate, and / or content of the signal.

[0043] For example, the first type of signal may include data signals to be input to the third circuit, and the second type of signal may include control signals corresponding to the third circuit.

[0044] The following example is about Figure 2 , Figures 3a to 3c , Figure 4 and Figure 5 Description and can be included Figure 1 Other features related to the first TSV 141 and the second TSV 142 in the processor 110.

[0045] In the example, the first SERDES circuit 131 may include a buffer for storing bits received from the first and second circuits, wherein each bit corresponds to at least one of a first signal path, a second signal path, a third signal path, or a fourth signal path. The first SERDES circuit 131 may include a controller configured to generate a sequence of bits by performing serialization on the bits stored in the buffer, the sequence of bits to be included in a signal to be transmitted to the second die via a first TSV.

[0046] In the example, the second SERDES circuit 151 may include a buffer for storing bits received from the third and fourth circuits, wherein each bit corresponds to at least one of the first, second, third, or fourth signal paths. The second SERDES circuit 151 may include a controller configured to generate a sequence of bits by performing serialization on the bits stored in the buffer, the sequence to be included in a signal to be transmitted to the first die via the first TSV 141.

[0047] The first SERDES circuit can be configured to: store bits obtained from the first circuit and the second circuit within a preset time interval into a buffer; and perform serialization of the bits stored in the buffer based on the expiration of the preset time interval.

[0048] The second SERDES circuit can be configured to: store bits obtained from the third and fourth circuits into a buffer within a preset time period; and serialize the bits stored in the buffer based on the expiration of the preset time period.

[0049] The following example is about Figure 2 , Figures 3a to 3c , Figure 4 and Figure 5 Description and can be included Figure 1 Other features related to the SERDES circuitry (e.g., buffers and controllers) in the processor 110.

[0050] The circuitry included in the first die (e.g., the first and second circuits) and the second die (e.g., the third and fourth circuits) may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a serial communication interface (SCI) / last-level cache (LLC), an input / output interface (I / F) and a high-speed synchronous serial interface (HSI), a memory management (M / M), a neural processing unit (NPU), low-power dynamic random access memory (LP-DDR), a physical interface (PHY), an on-chip network (NOC), a display controller, an image signal processor (ISP), and / or a modem. However, these are merely examples, and the circuitry may include any other suitable components.

[0051] In the example, the first circuit may include a CPU circuit and the second circuit may include a GPU circuit.

[0052] In one example, the third circuit may include an ISP circuit and the fourth circuit may include a display control circuit. In another example, the third circuit may include a memory interface circuit for communicating with a memory connected to the processing chip assembly; and the fourth circuit may include an NPU circuit.

[0053] In an example where the first circuit includes a CPU circuit, the second circuit includes a GPU circuit, the third circuit includes an ISP circuit, and the fourth circuit includes a display control circuit, the CPU circuit may include a first signal pin connected to the first SERDES circuit 131, and the second TSV 142 may be connected to a second signal pin of the CPU circuit. The ISP circuit may include a third signal pin electrically connected to the second TSV 142. The CPU circuit may be configured to transmit control signals for requesting data from the ISP circuit to the first SERDES circuit 131 via the first signal pin, and to receive data corresponding to the control signals from the ISP circuit via the second signal pin connected to the second TSV 142.

[0054] The following example is about Figure 2 , Figures 3a to 3c , Figure 4 and Figure 5 Description and can be included Figure 1 Other features related to the signal pins in processor 110.

[0055] In an example where the first circuit includes a CPU, the second SERDES circuit 151 can be configured to receive from the third circuit a signal for informing the first circuit of at least one of the status of the third circuit or an interrupt (e.g., a software interrupt) associated with the third circuit.

[0056] In the example, the first die may be configured to include circuit elements with dimensions smaller than the minimum dimension of the circuit elements included in the second die. For example, the first die may include circuitry manufactured using a process capable of implementing circuit elements based on a first minimum linewidth (e.g., a 3nm process and / or a 2nm process), and the second die may include circuitry manufactured using a process capable of implementing circuit elements based on a second minimum linewidth greater than the first minimum linewidth.

[0057] In the example, the first SERDES circuit 131 can be configured to transmit a signal obtained based on serialization and encoded based on a biphasic marker coding (BMC) scheme to the second SERDES circuit 151 via the first TSV 141. The following example relates to... Figure 6 Description and can be included Figure 1 Other features related to the BMC scheme in processor 110.

[0058] In the example, the power state of at least one of the first SERDES circuit 131 and the second SERDES circuit 151 can be controlled independently of the power state of the CPU included in the processing chip assembly. The following example relates to... Figures 3a to 3c Description and can be included Figure 1Other features related to the state of the SERDES circuit in processor 110.

[0059] In the example, interconnect layer 140 may include an auxiliary TSV configured to connect between the first SERDES circuit 131 and the second SERDES circuit 151, and to provide an auxiliary first signal path between the first circuit and the third circuit, an auxiliary second signal path between the first circuit and the fourth circuit, an auxiliary third signal path between the second circuit and the third circuit, and an auxiliary fourth signal path between the second circuit and the fourth circuit.

[0060] The first die may include a first switching circuit and the second die may include a second switching circuit. The first and second switching circuits may be configured to control the connection between the first SERDES circuit 131 and the second SERDES circuit 151 by switching the connection between the first TSV and the auxiliary TSV.

[0061] The following example is about Figure 4 Description and can be included Figure 1 Other features related to auxiliary TSVs in processor 110.

[0062] In the example, the interconnect layer includes multiple TSVs; wherein the first SERDES circuit includes: a first protocol circuit configured to support a first communication protocol; a second protocol circuit configured to support a second communication protocol; and a first multiplexer switching circuit configured to connect the multiple TSVs to the first protocol circuit and the second protocol circuit; wherein the second SERDES circuit includes: a third protocol circuit configured to support the first communication protocol; a fourth protocol circuit configured to support the second communication protocol; and a second multiplexer switching circuit configured to connect the multiple TSVs to the third protocol circuit and the fourth protocol circuit; and wherein the first multiplexer switching circuit and the second multiplexer switching circuit are configured to: select a communication protocol, establish a connection between the first protocol circuit and the third protocol circuit via the multiple TSVs when the first communication protocol is selected, and establish a connection between the second protocol circuit and the fourth protocol circuit via the multiple TSVs when the second communication protocol is selected.

[0063] The following example is about Figure 5 Description and can be included Figure 1 Other features related to the protocol circuitry in the processor 110.

[0064] In the following text, reference will be made to Figure 2 An exemplary structure for inter-layer circuit connections between circuit layers formed by the first SERDES circuit 131, the second SERDES circuit 151, and the TSV 141 is described.

[0065] Figure 2 An exemplary structure of the interconnect layer 140 included in the processor 110 according to an embodiment is shown. Figure 2 At least a portion of the processor 110 shown can correspond to Figure 1 At least a portion of the processor 110 shown, and even though not shown or specifically described below, in Figure 2 The processor 110 may also include the above-mentioned... Figure 1 The features described in the processor 110.

[0066] Reference Figure 2 The diagram illustrates a second circuit layer 150, an interconnect layer 140, and a first circuit layer 130 stacked sequentially along the z-axis in a processor 110. In the interconnect layer 140, a TSV 141 may be formed for the overall transmission of signals (e.g., signals based on general purpose input / output (GPIO)) transmitted between the first circuit layer 130 and the second circuit layer 150. To transmit signals overall through a single signal path such as the TSV 141, a first SERDES circuit 131 and a second SERDES circuit 151 may be positioned at opposite ends of the TSV 141. For example, when the first SERDES circuit 131 transmits signals for the circuits of the first circuit layer 130 overall, the second SERDES circuit 151 may distribute integrated signals to each circuit of the second circuit layer 150. Conversely, when the second SERDES circuit 151 transmits signals for the circuits of the second circuit layer 150 overall, the first SERDES circuit 131 may distribute integrated signals to each circuit of the first circuit layer 130.

[0067] According to an embodiment, the SERDES circuit (e.g., the first SERDES circuit 131 and / or the second SERDES circuit 151) may include pins (or signal pins) for electrical connection to other circuits (e.g., circuits included in a circuit layer on which the SERDES circuit is disposed (e.g., the first integrated circuit layer 130 and / or the second integrated circuit layer 150)). See also... Figure 2 Exemplary examples illustrate a first SERDES circuit 131 comprising k pins (e.g., p11, p12, ..., p1k) and a second SERDES circuit 151 comprising k pins (e.g., p21, p22, ..., p2k), but the number of pins extending from the SERDES circuits is not limited thereto. The k pins of the first SERDES circuit 131 may be electrically connected to different circuits disposed in the first circuit layer 130. Similarly, the k pins of the second SERDES circuit 151 may be electrically connected to different circuits disposed in the second circuit layer 150.

[0068] In embodiments, SERDES circuits (e.g., first SERDES circuit 131 and / or second SERDES circuit 151) can receive electrical signals comprising one or more bits from another circuit via at least one pin. For example, one or more bits may indicate a value corresponding to the state of the other circuit. For example, one or more bits may indicate an interrupt (e.g., a software interrupt) generated in the other circuit. The one or more bits indicating the interrupt may indicate the type of interrupt and / or uniquely assign a value to the interrupt. For example, a circuit disposed on a particular circuit layer may transmit electrical signals to a SERDES circuit connected to the circuit to notify a circuit disposed on another circuit layer of at least one of the circuit's state and / or an interrupt associated with the circuit.

[0069] In an embodiment, the SERDES circuit may include a buffer for storing signals and / or bits included in signals received independently via different pins. (See also...) Figure 2 The first SERDES circuit 131 may include a buffer 212 for storing bits received through k pins. The second SERDES circuit 151 may include a buffer 222 for at least partially storing signals received through k pins. In each of the buffers 212 and 222, bits indicating the state of the circuits included in each of the first circuit layer 130 and the second circuit layer 150 and / or interrupts generated in the circuits may be stored.

[0070] In an embodiment, the SERDES circuitry may include a controller for performing serialization of bits stored in a buffer or for performing deserialization of bits included in a signal received via TSV 141. See also... Figure 2 The diagram exemplarily illustrates a controller 211 included in a first SERDES circuit 131 and a controller 221 included in a second SERDES circuit 151. The controller 211 of the first SERDES circuit 131 can obtain multiple bits to be included in the signal to be transmitted via TSV 141 to the second circuit layer 150 and / or the second SERDES circuit 151 by combining bits stored in buffer 212. Similarly, the controller 221 of the second SERDES circuit 151 can obtain a sequence of bits to be transmitted via TSV 141 to the first circuit layer 130 and / or the first SERDES circuit 131 by combining bits stored in buffer 222.

[0071] In an embodiment, the first SERDES circuit 131 or the second SERDES circuit 151 may be implemented by including a parallel input serial output (PISO) function block, a serial input parallel output (SIPO) function block, or a clock circuit, etc., without a controller.

[0072] In embodiments, the combination of bits performed by controller 211 of the first SERDES circuit 131 and / or controller 221 of the second SERDES circuit 151 may include serialization. Serialization may include the operation of obtaining a sequence (e.g., a bit stream) of bits to be transmitted sequentially through a single signal path (or channel) such as TSV 141. For example, controller 211 may generate or obtain the sequence of bits by concatenating bits stored in buffer 212 and / or bits received via pins (p11 to p1k). The position of each bit in the sequence may be determined based on the pin where the received bit is located. For example, Table 1 exemplarily shows bits received via four pins (p11 to p14).

[0073] [Table 1]

[0074] The controller 211 of the first SERDES circuit 131, which receives the bits shown in Table 1, can generate a bit sequence 1011 by sequentially combining bit 1 received through pin p11, bit 0 received through pin p12, bit 1 received through pin p13, and bit 1 received through pin p14. Based on the operation described above, the controller 211 can generate a sequence of k bits received from k pins. The controller 211 can transmit a signal indicating the sequence via TSV 141.

[0075] In an embodiment where the first SERDES circuit 131 is connected to each of k different circuits via k pins, the timing of the signals transmitted from the k circuits to the first SERDES circuit 131 can be different from each other. In an exemplary case of receiving bits from Table 1, the timing of receiving bit 0 via pin p12 and the timing of receiving bit 1 via pin p11 can be the same or different. According to an embodiment, the controller 211 can accumulate or store in buffer 212 bits included in signals transmitted from different circuits during a preset time interval (e.g., approximately 5 ms). For example, within a time interval divided based on a preset period, the controller 211 can receive at least one bit to be included in the signal to be transmitted to TSV 141.

[0076] Based on the expiration of a time segment (or at the expiration date), controller 211 may perform serialization of the bits stored in buffer 212. If a particular circuit does not transmit any signal during the time segment, controller 211 may perform serialization based on bits transmitted from the particular circuit before the time segment (e.g., stored in buffer 212 before the time segment).

[0077] In an embodiment, whenever a signal appears on any of the k pins (e.g., p11, p12, ..., p1k), the first SERDES circuit 131 can transmit the corresponding signal to the second SERDES circuit 151 via TSV 141. In an embodiment, the first SERDES circuit 131 can transmit the corresponding signal to the second SERDES circuit 151 by identifying a pin or signal with a preset name or format among the k pins (e.g., p11, p12, ..., p1k), regardless of the transmission period. In an embodiment, when a signal is generated from a pin with a preset name or format, the first SERDES circuit 131 can perform serialization of the signals that have appeared up to that point, even if the transmission period has not yet been reached. The first SERDES circuit 131 can then transmit the signal generated and / or obtained through serialization to the second SERDES circuit 151.

[0078] Referring to Table 1, an embodiment of a first SERDES circuit 131 connected to k different circuits via k pins has been described, but the embodiment is not limited thereto. For example, at least two of the k pins can be configured to connect the first SERDES circuit 131 to a single circuit. For example, a circuit connected to the first SERDES circuit 131 via two pins can transmit a signal comprising two bits. By using this signal, the circuit can inform a circuit selected from up to four states of its current state.

[0079] According to an embodiment, the first SERDES circuit 131 can transmit a signal (e.g., a signal comprising a sequence of bits) obtained based on the operations described above (e.g., serialization) to the second SERDES circuit 151 via TSV 141. The controller 221 of the second SERDES circuit 151, upon receiving the signal, can obtain at least one bit to be provided to at least one circuit of the second circuit layer 150 by performing deserialization or reserialization on the received signal. For example, the controller 221 can obtain or generate the signal to be transmitted to the circuit of the second circuit layer 150 based on deserialization.

[0080] For example, controller 221, which receives a sequence of bits received via TSV 141, can assign multiple bits to different pins based on the position of each of the multiple bits in the sequence. Second SERDES circuit 151, which receives a signal comprising a sequence of k bits via TSV 141, can assign bits positioned at different positions in the sequence to k pins (e.g., p21, p22, ..., p2k). For example, second SERDES circuit 151, which receives a sequence of bits 1011 via TSV 141, can assign bits 2...1...1...101k ... 3 The digital bit 1 is output to pin p21, which will convert 2 bits to 1. 2The digit 0 is output to pin p22, which will convert 2 to 1. 1 The digital bit 1 is output to pin p23, and 2 is output to pin p23. 0 The digital bit 1 is output to pin p24. When the second SERDES circuit 151 is connected to the circuit of the second circuit layer 150 through different pins, different bits in the sequence can be transmitted to the circuit through the pins.

[0081] As described above, based on the serialization in the first SERDES circuit 131 and the deserialization in the second SERDES circuit 151, bits input to a specific pin of the first SERDES circuit 131 can be output through a pin corresponding to a specific pin in the second SERDES circuit 151. For example, the pins of the first SERDES circuit 131 can be matched one-to-one with the pins of the second SERDES circuit 151. Based on the one-to-one correspondence between the pins of the first SERDES circuit 131 and the pins of the second SERDES circuit 151, an exclusive connection between a specific circuit in the first circuit layer 130 and another circuit in the second circuit layer 150 can be established via TSV 141. Figure 2 In this embodiment, up to k exclusive connections can be established based on the first SERDES circuit 131, the second SERDES circuit 151, and the TSV 141. In other words, because the k exclusive connections are integrated into a single TSV 141, the processor 110 can be designed and manufactured using a relatively small number of TSVs. Because the processor 110 has a relatively small number of TSVs, the yield of the processor 110 can be improved.

[0082] Reference Figure 2 An embodiment for transmitting a signal from the first SERDES circuit 131 to the second SERDES circuit 151 has been described, but the embodiment is not limited thereto. For example, the controller 221 of the second SERDES circuit 151 can perform serialization of the signal and / or bits stored in the buffer 222 within a preset time interval. Based on serialization, bits received through different pins (p21, p22, ..., p2k) within the preset time interval can be integrated into a bit stream. The controller 221 can transmit the signal including the bit stream to the first circuit layer 130 and / or the first SERDES circuit 131 via TSV 141. The first SERDES circuit 131 and / or the controller 211, which receive the signal through TSV 141, can divide the bits included in the bit stream based on deserialization. The bits divided based on their position in the bit stream can be output by the controller 211 through different pins (p11, p12, ..., p1k) of the first SERDES circuit 131. When the pins are connected to different circuits in the first circuit layer 130, the bits output through the pins (p11, p12, ..., p1k) can be transmitted to the circuit.

[0083] As described above, based on the first SERDES circuit 131, TSV 141, and second SERDES circuit 151 included in the processor 110, signals from different circuits can be transmitted holistically via TSV 141. In terms of integrated signals, the SERDES circuits (such as the first SERDES circuit 131 and / or the second SERDES circuit 151) can be referred to as signal coupling circuits and / or signal modulators. The signal transmitted via TSV 141 can be divided into one or more signals to be transmitted by the SERDES circuits to different circuits. In terms of signal division, the SERDES circuits (such as the first SERDES circuit 131 and / or the second SERDES circuit 151) can be referred to as signal division circuits and / or signal demodulators.

[0084] The following description will include references Figure 2 An exemplary structure of the processor 110 described is shown for the first SERDES circuit 131, TSV 141, and the second SERDES circuit 151.

[0085] Figure 3a , Figure 3b and Figure 3c An embodiment of a processor 110 is shown, comprising multiple circuit layers (e.g., a first circuit layer 130 and / or a second circuit layer 150) connected via an interconnect layer 140. Figures 3a to 3c At least a portion of the processor 110 shown can correspond to Figure 1 and / or Figure 2 At least a portion of the processor 110, and even though not shown or specifically described below, in Figures 3a to 3c The processor 110 may also include the above-mentioned... Figure 1 and / or Figure 2 The features described in the processor 110.

[0086] Reference Figure 3a For ease of illustration, the circuitry included in processor 110 is shown in block form in each of the first circuit layer 130 and the second circuit layer 150. Examples of the circuitry included in processor 110 include a central processing unit (CPU) 310, a graphics processing unit (GPU) 312, a serial communication interface (SCI) / last-level cache (LLC), an input / output interface (I / F) and a high-speed synchronous serial interface (HSI), a memory management (M / M) unit, a neural processing unit (NPU), low-power dynamic random access memory (LP-DDR), a physical interface (PHY) 320, a network on-chip (NOC), a display controller 322, an image signal processor (ISP) 324, and / or a modem. The circuitry included in processor 110 is not limited to... Figure 3aThe embodiment, and the processor 110 may also include Figure 3a The circuit not shown in the diagram may be excluded from processor 110. Figure 3a Some circuits.

[0087] Reference Figure 3a An embodiment is shown in which the CPU 310 and / or GPU 312 are disposed in the first circuit layer 130 and the NPU and / or MODEM are disposed in the second circuit layer 150, but the embodiment is not limited thereto. For example, circuits shown as different blocks in each of the first circuit layer 130 and the second circuit layer 150 may be disposed in... Figure 3a Different locations and / or die sites in different embodiments. For example, based on the heat dissipation structure in processor 110, the location of the circuit can be determined as a first circuit layer 130 and / or a second circuit layer 150.

[0088] For example, CPU 310 may include circuitry configured to process data based on at least one instruction input to CPU 310. GPU 312 may include circuitry configured to perform parallel operations of graphics (e.g., rendering). NPU (or neural engine) may include circuitry configured to perform operations of an artificial intelligence model (e.g., convolution calculation). SCI / LLC may include circuitry configured to at least temporarily store data to be processed by CPU 310, GPU 312, and / or NPU. Signal I / F may include circuitry configured to control the transmission of signals in circuit layers (e.g., first circuit layer 130 and / or second circuit layer 150). HSI may include circuitry configured to transmit signals between circuits in circuit layers (e.g., first circuit layer 130 and / or second circuit layer 150) at a relatively high speed. M / M may include translation between virtual and physical addresses to access memory stored connected to processor 110 (e.g., ...). Figure 1 The LP-DDR PHY 320 may include circuitry for storing data in volatile memory 121 and / or non-volatile memory 122 connected to the processor 110. Figure 1The volatile memory 121) directly transmits and / or receives data between the CPU 310 and the processor 110. The NOC may include circuitry configured to control the transmission and reception of signals between circuitry within the processor 110. The display controller 322 may include circuitry for controlling a display electrically connected to the processor 110 using data (e.g., rendered images and / or video) provided from the CPU 310 and / or GPU 312. The image signal processor (ISP) 324 may include circuitry for controlling a camera electrically connected to the processor 110 and / or receiving data from the camera (e.g., images, video, and / or image frames acquired by the camera). The MODEM may include communication circuitry configured to control communication circuitry connected to the processor 110 (e.g., ...). Figure 1 The communication circuit 124).

[0089] The circuitry described above can be disposed on either the first circuit layer 130 or the second circuit layer 150 in the processor 110, manufactured using different processes. For example, the minimum size of the first circuit element included in the first circuit layer 130 can be smaller than the minimum size of the second circuit element included in the second circuit layer 150. The first circuit layer 130 can be manufactured using a first process (e.g., a 3nm process and / or a 2nm process) capable of implementing circuit elements (e.g., transistors with a gate-all-around (GAA) structure) based on a minimum linewidth (or line pitch) of 3nm. The second circuit layer 150 can be manufactured using a second process that supports the production of circuit elements with a minimum linewidth greater than 3nm (e.g., transistors with a FinFET structure). The processes corresponding to the first circuit layer 130 and the second circuit layer 150 are not limited to the first and second processes described above.

[0090] In embodiments, circuitry described as integrated within processor 110 (e.g., CPU, ISP, MODEM, NPU, and / or GPU) can be implemented or fabricated as a standalone integrated circuit. In embodiments, an integrated circuit comprising at least one of the CPU, ISP, MODEM, NPU, and / or GPU described above can be implemented as a 3D-IC comprising stacked circuit layers (e.g., semiconductor die layers) and serial interconnect wiring (e.g., TSV) connecting the stacked circuit layers.

[0091] In embodiments, the performance, power consumption, and / or yield of the circuit layer (e.g., performance measured by parameters such as instructions per cycle (IPC) and / or floating-point operations per second (FLOPS)) may be related to the process used in the production of the circuit layer. The circuitry included in processor 110 may be configured in a first integrated circuit layer 130 or a second integrated circuit layer 150 based on the required performance, power consumption, and / or yield. (Refer to...) Figure 3a The example illustrates a processor 110 including a first circuit layer 130 and a second circuit layer 150. The first circuit layer 130 includes a CPU 310, a GPU 312, and an SCI / LLC, and the second circuit layer 150 includes an NPU, an HIS, an LP-DDR PHY 320, a MODEM, an M / M, and an NOC. However, the embodiments are not limited thereto.

[0092] Reference Figure 3a The first circuit layer 130 of processor 110 may include a first SERDES circuit 131 connected to each of a plurality of circuits (e.g., first circuit elements) of the first integrated circuit layer 130 (including CPU 310). The second circuit layer 150 of processor 110 may include a plurality of circuits connected to the second circuit layer 150 (including circuits for use with memory (e.g., ...). Figure 2 The processor 110 may include a memory interface circuit 151 for communicating with each of the volatile memory 121, such as the second SERDES circuit 151 of the LP-DDR PHY 320. The processor 110 may include an interconnect layer 140 disposed between the first circuit layer 130 and the second circuit layer 150.

[0093] In an embodiment, interconnect layer 140 may include one or more signal paths for electrically connecting and / or operatively connecting the circuitry of the first circuit layer 130 and the circuitry of the second circuit layer 150. The signal paths may be established by TSVs. (See also...) Figure 3a As an example of a signal path, a TSV 141 configured to connect a first SERDES circuit 131 and a second SERDES circuit 151 is shown. Through the TSV 141, signals for informing the first SERDES circuit 131 of the status and / or interruption of the other circuit can be transmitted between the first SERDES circuit 131 and the second SERDES circuit 151. Signals can be transmitted at relatively slow data rates (e.g., including data rates in the range of 300 kbps to 5 Mbps, or at data rates less than or equal to this range). In terms of supporting relatively slow speeds, the interface established based on the TSV 141 can be referred to as low-speed input / output (IO). To transmit signals through a single TSV 141, the first SERDES circuit 131 and / or the second SERDES circuit 151 can transmit signals based on a single-wire protocol such as a biphasic marker coding (BMC) method.

[0094] In an embodiment, based on the first SERDES circuit 131 and the second SERDES circuit 151 connected to both ends of the TSV 141, signal paths that can be used by all circuits included in the first circuit layer 130 and the second circuit layer 150 can be established. The embodiment is not limited thereto, and the interconnect layer 140 of the processor 110 may include one or more signal paths dedicated to a pair of circuits disposed in each of the first circuit layer 130 and the second circuit layer 150.

[0095] Reference Figure 3a A TSV 330 for electrical connection between CPU 310 and LP-DDR PHY 320 can be formed in interconnect layer 140. For high-speed communication between CPU 310 and LP-DDR PHY 320, multiple TSVs including TSV 330 can be formed. High-speed communication may include high-speed peripheral component interconnect bus (PCIe), universal serial bus (USB), mobile industrial processor interface (MIPI), Marconi, universal flash memory (UFS), memory interface (MIF), inter-integrated circuit (I2C), and / or improved inter-integrated circuit (I3C). For high-speed communication, differential interfaces based on multiple TSVs (or signal paths) can be formed between circuits. For high-speed communication, any one of the multiple TSVs can be used for clock signal transmission.

[0096] Reference Figure 3a The signal path between the first circuit (e.g., CPU 310) of the first circuit layer 130 and the second circuit (e.g., LP-DDR PHY 320) of the second circuit layer 150 can be divided into a first signal path that directly connects the first and second circuits and a second signal path that indirectly connects the first and second circuits based on SERDES circuitry. TSV 330 may correspond to at least a portion of the first signal path. TSV 141, the first SERDES circuit 131, and / or the second SERDES circuit 151 may correspond to at least a portion of the second signal path.

[0097] In embodiments, circuitry directly and indirectly connected via a first signal path and a second signal path can selectively use either signal path based on the purpose, data rate, and / or content of the signal. For example, the first signal path, including TSV 330, can be used to transmit data signals (e.g., signals including data to be transferred to volatile memory via LP-DDR PHY 320). The second signal path, including TSV 141, can be used to transmit control signals (e.g., signals generated by CPU 310 to adjust the state of LP-DDR PHY 320).

[0098] Reference Figure 3b An exemplary block diagram is shown to describe the first and second signal paths formed by TSVs 141 and 330. For transmitting data signals based on TSV 330, data signal pins included in CPU 310 and / or LP-DDR PHY 320 can be directly connected via TSV 330. For transmitting control signals based on TSV 141, one or more control signal pins of CPU 310 used to transmit control signals to be transmitted to LP-DDR PHY 320 can be connected to one or more pins P11 and P12 of the first SERDES circuit 131. For example, one or more control signal pins can be connected to TSV 141 via the first SERDES circuit 131. For example, a first control signal pin used to transmit interrupt-related signals can be connected to pin P11 of the first SERDES circuit 131. For example, a second control signal pin used to transmit signals for controlling the state of LP-DDRPHY 320 (such as reset) can be connected to pin P12 of the first SERDES circuit 131. Embodiments are not limited thereto.

[0099] exist Figure 3b In this embodiment, CPU 310 can transmit a first type of signal via TSV 330 to transmit data to LP-DDR PHY 320. For example, data signals including data to be stored in a memory connected to processor 110 can be transmitted from CPU 310 to LP-DDR PHY 320 via TSV 330. In the TSV 330 that proprietaryly connects CPU 310 and LP-DDR PHY 320, the first type of signal can be transmitted at a speed within a first data rate range.

[0100] exist Figure 3b In this embodiment, the CPU 310 can transmit a second type of signal for controlling the controller of the LP-DDR PHY 320 to the first SERDES circuit 131 via either pin P11 or P12. For example, control signals adjusting the state of the LP-DDR PHY 320 or controlling the execution of specific functions (e.g., the function of transferring data to memory included in the first type of signal) and / or the operation (or calculation) of the LP-DDR PHY 320 can be transmitted from the CPU 310 to the first SERDES circuit 131. For example, control signals for transferring data provided to the LP-DDR PHY 320 to memory via the TSV 330 can be transmitted from the CPU 310 to the first SERDES circuit 131.

[0101] exist Figure 3bIn some embodiments, CPU 310 may include multiple sub-circuits. Each of the multiple sub-circuits may correspond to different pins P11 and P12 and / or different TSVs 141 and 330. For example, the multiple sub-circuits of CPU 310 may include a first sub-circuit connected to the first SERDES circuit 131 to transmit a second type of signal to TSV 141 via the first SERDES circuit 131. The first sub-circuit of CPU 310 may be connected to the first SERDES circuit 131 via at least one of pins P11 and P12. The first sub-circuit of CPU 310 may include a memory address register (MAR) and / or control circuitry in CPU 310 to transmit control signals corresponding to the LP-DDR PHY 320. The multiple sub-circuits of CPU 310 may include a second sub-circuit connected to TSV 330 to transmit a first type of signal. The second sub-circuit of CPU 310 is a sub-circuit for transmitting data signals to be input to LP-DDR PHY 320, and may include a memory buffer register (MBR) and / or cache memory (e.g., L1, L2 and / or L3 cache memory).

[0102] In embodiments, similar to a CPU 310 including sub-circuits configured to be directly and / or indirectly connected to different TSVs (e.g., via indirect connections through first SERDES circuitry 131 and / or second SERDES circuitry 151), each circuit included in processor 110 (e.g., GPU 312, SCI / LLC, signal I / F, HSI, M / M, NPU, LP-DDR PHY 320, NOC, display controller, ISP 324, and / or MODEM) may include a sub-circuit corresponding to at least one TSV such as TSV 141 in interconnect layer 140. For example, GPU 312 may include a sub-circuit corresponding to each of a plurality of TSVs (including TSV 141) directly and / or indirectly connected to GPU 312. The circuits in processor 110 may include a sub-circuit corresponding to each TSV used by the circuit. Embodiments are not limited thereto, and the number of sub-circuits included in the circuits in processor 110 may be greater than or less than the number of TSVs used by the circuit.

[0103] As shown above (refer to the reference) Figure 2Described, the first SERDES circuit 131 can perform modulation and / or serialization of signals transmitted from a circuit including a first circuit layer 130 of CPU 310. For example, by performing serialization of control signals transmitted from the circuit, the first SERDES circuit 131 can obtain a signal including a sequence of bits included in the control signals. The first SERDES circuit 131 can transmit the obtained signal via TSV 141. In embodiments where control signals are transmitted independently of the circuit, the first SERDES circuit 131 can transmit control signals sent at different timings to the second SERDES circuit 151 based on a preset period. In TSV 141, signals generated based on serialization of the first SERDES circuit 131 or the second SERDES circuit 151 can be transmitted at a second data rate range less than or equal to the first data rate range.

[0104] exist Figure 3b In this embodiment, the second SERDES circuit 151, which receives the signal serialized by the TSV 141 based on the first SERDES circuit 131, can divide the multiple bits included in the signal by performing deserialization. The second SERDES circuit 151 can allocate the multiple bits to the pins of the second SERDES circuit 151 based on the relationship between the pins of the first SERDES circuit 131 and the pins of the second SERDES circuit 151. For example, the control signal pins of the LP-DDR PHY 320, which are the targets of control signals transmitted to pins P11 and P12, can be connected to pins P21 and P22 corresponding to pins P11 and P12 of the first SERDES circuit 131, respectively. The LP-DDR PHY 320 can receive one or more bits transmitted from the CPU 310 to pins P11 and P12 via pins P21 and P22. The LP-DDR PHY 320 can perform operations indicated by one or more bits received via pins P21 and P22 (e.g., transferring data received via TSV 330 to volatile memory connected to processor 110).

[0105] As described above, the signal transmitted from the first SERDES circuit 131 via TSV 141 may include one or more bits provided by the circuitry of the first circuit layer 130 including CPU 310. For example, the signal may include a sequence of one or more serialized bits.

[0106] Reference Figure 3bAn embodiment in which data signals and / or control signals are transmitted from CPU 310 to LP-DDR PHY 320 has been described, but the embodiment is not limited thereto. For example, LP-DDR PHY 320 can transmit data transferred from memory to CPU 310 via TSV 330. LP-DDR PHY 320 can transmit signals to second SERDES circuit 151 via pins P21 and P22 to notify LP-DDR PHY 320 of its status and / or interrupts generated in LP-DDR PHY 320. Second SERDES circuit 151 can obtain or generate a signal to be transmitted to first SERDES circuit 131 via TSV 141 by combining (e.g., serializing) this signal with another signal transmitted from other circuits of second circuit layer 150. First SERDES circuit 131, which receives the signal generated by second SERDES circuit 151 via TSV 141, can obtain at least one bit of the bits included in the signal to be transmitted to CPU 310 via pins P11 and P12 based on deserialization.

[0107] Reference Figure 3c An exemplary block diagram is shown to describe multiple signal paths formed by TSVs 141, 332, and 334. A first circuit layer 130 (or first die) including circuitry such as CPU 310 and / or GPU 312 may include first SERDES circuitry 131 connected to CPU 310 and GPU 312. A second circuit layer 150 (or second die) including circuitry such as display controller 322 and / or ISP 324 may include second SERDES circuitry 151 connected to display controller 322 and ISP 324.

[0108] Reference Figure 3cIn the first circuit layer 130, the CPU 310 can be connected to the first SERDES circuit 131 via signal pins P11 and P12, and the GPU 312 can be connected to the second SERDES circuit 151 via signal pins P13 and P14. In the second circuit layer 150, the display controller 322 can be connected to the second SERDES circuit 151 via signal pins P21 and P22, and the ISP 324 can be connected to the second SERDES circuit 151 via signal pins P23 and P24. Based on the serialization and / or deserialization (or modulation and / or demodulation) of the first SERDES circuit 131 and / or the second SERDES circuit 151, multiple signal paths can be integrated in the TSV 141. The multiple signal paths may include a first signal path between the CPU 310 and the display controller 322, a second signal path between the CPU 310 and the ISP 324, a third signal path between the GPU 312 and the display controller 322, and a fourth signal path between the GPU 312 and the ISP 324. The first signal path may include signal pins P11 and P21. The second signal path may include signal pins P12 and P22. The third signal path may include signal pins P13 and P23. The fourth signal path may include signal pins P14 and P24.

[0109] Reference Figure 3c The interconnect layer 140 may further include other TSVs (e.g., TSVs 332 and 334) for directly connecting the circuitry of the first circuit layer 130 and the circuitry of the second circuit layer 150, and a TSV 141 for providing a first signal path to a fourth signal path. For example, the interconnect layer 140 may include a TSV 332 for connecting the CPU 310 and the display controller 322. The interconnect layer 140 may include a TSV 334 for connecting the GPU 312 and the ISP 324. Embodiments are not limited thereto, and additional TSVs connecting the CPU 310 and the ISP 324 and / or connecting the GPU 312 and the display controller 322 may be formed in the interconnect layer 140.

[0110] In an embodiment, the CPU 310 may include a first sub-circuit corresponding to TSV 141 and / or the first SERDES circuit 131 (e.g., a first sub-circuit connected to at least one of pins P11 and P12) and / or a second sub-circuit connected to TSV 332 to communicate with the display controller 322. The GPU 312 may include a third sub-circuit corresponding to TSV 141 and / or the first SERDES circuit 131 (e.g., a third sub-circuit connected to at least one of pins P13 and P14) and / or a fourth sub-circuit connected to TSV 334 to communicate with the ISP 324. The display controller 322 may include a fifth sub-circuit corresponding to TSV 141 and / or the second SERDES circuit 151 (e.g., a fifth sub-circuit connected to the second SERDES circuit 151 via pins P21 and P22) and / or a sixth sub-circuit connected to TSV 332 to communicate with the CPU 310. ISP 324 may include a seventh sub-circuit corresponding to TSV 141 and / or the second SERDES circuit 151 (e.g., a seventh sub-circuit connected to the second SERDES circuit 151 via at least one of pins P23 and P24) and / or an eighth sub-circuit connected to TSV 334 to communicate with GPU 312.

[0111] In this embodiment, the first to fourth signal paths can be used to transmit control signals for the function and / or operation of the control circuit, status signals for notifying the status of the circuit, and / or interrupt signals for notifying interrupts. The CPU 310 can transmit a first type of signal, including control signals, status signals, and / or interrupt signals, to the display controller 322 and / or the ISP 324 via TSV 141. For example, the CPU 310 can transmit a first signal of the first type associated with the display controller 322 to the first SERDES circuit 131 via signal pin P11. The CPU 310 can transmit a second signal of the first type associated with the ISP 324 to the first SERDES circuit 131 via signal pin P12. In the above example, the first SERDES circuit 131 can generate a third signal to be transmitted to the second SERDES circuit 151 via TSV 141 based on the serialization of the first and second signals. The first SERDES circuit 131 can then transmit the third signal to TSV 141.

[0112] In an embodiment where the third signal is transmitted via TSV 141, the second SERDES circuit 151 can obtain the first and second signals based on the deserialization of the third signal received via TSV 141. The second SERDES circuit 151 can transmit the obtained first signal to the display controller 322 via signal pin P21. The second SERDES circuit 151 can transmit the obtained second signal to the ISP 324 via signal terminal P22. Similarly, the GPU 312 can transmit a first type of signal to the display controller 322 via signal pin P13, and can transmit a second type of signal to the ISP 324 via signal pin P14.

[0113] In embodiments, TSVs 332 and 334, different from TSV 141 in which the first signal path to the third signal path is integrated, can be used to transmit data and / or information between circuits. For example, CPU 310 can transmit information including images and / or video to be displayed on a monitor to display controller 322 via TSV 332. In the above example, CPU 310 can transmit a first type of signal requesting information to be output to the display to display controller 322 using TSV 141. GPU 312 can receive information including images and / or video (e.g., images and / or video obtained by a camera) from ISP 324 via TSV 334. In the above example, GPU 312 can transmit a first type of signal requesting information to be transmitted from ISP 324 to ISP 324 using TSV 141.

[0114] An embodiment in which the circuitry of the first circuit layer 130 transmits signals to the circuitry of the second circuit layer 150 has been described, but the embodiment is not limited thereto. For example, the display controller 322 may transmit a first-type signal to the CPU 310 and / or GPU 312 using each of signal pins P21 and P22 to notify the display controller 322 of its status and / or interrupts generated by the display controller 322. Similarly, the ISP 324 may transmit a first-type signal to the CPU 310 and / or GPU 312 using signal pins P23 and P24 to notify the ISP 324 of its status and / or interrupts generated by the ISP 324. Signals received via signal pins P21 and P22 may be modulated or serialized by the second SERDES circuitry 151. Signals serialized by the second SERDES circuitry 151 may be transmitted to the first SERDES circuitry 131 via TSV 141. The first SERDES circuit 131 can obtain or generate signals to be output to the CPU 310 and GPU 312 through each of the signal pins P11, P12, P13 and P14 based on the deserialization of the signal received through TSV 141.

[0115] An embodiment of processor 110, including CPU 310, GPU 312, display controller 322, and ISP 324, has been described, but the embodiments are not limited thereto. For example, another circuitry of the second circuit layer 150, such as LP-DDR PHY 320 and / or NPU, may also be connected to the second SERDES circuitry 151 to use a TSV 141-based signal path. For example, another circuitry of the first circuit layer 130, different from CPU 310 and / or GPU 312, may also be connected to the first SERDES circuitry 131 to use a TSV 141-based signal path.

[0116] As shown above (refer to the reference) Figures 3a to 3c The different circuits in the processor 110, including CPU 310 and / or LP-DDR PHY 320, described herein, can use an interface structure formed by a first SERDES circuit 131, a TSV 141, and a second SERDES circuit 151. Through this interface structure, the state of the circuits in the first circuit layer 130 can be transferred to the circuits in the second circuit layer 150. Through this interface structure, the state of the circuits in the second circuit layer 150 can be transferred and / or broadcast to the circuits in the first circuit layer 130.

[0117] In this embodiment, to manage power consumption, the state of the circuitry in the processor 110 can be adaptively controlled. For example, the CPU 310 can adjust the state of the circuitry, including the state of the CPU 310, based on instruction execution. For instance, the power state of the circuitry may include a sleep state (or low voltage state, low power state, disabled or deactivated state) receiving a power signal that is less than a preset voltage (e.g., a voltage within the range of 0V). The state of the circuitry may include a wake-up state (or enabled or activated state) receiving a power signal that is greater than or equal to a preset voltage.

[0118] In embodiments, to support signal transmission between circuits independent of the state of CPU 310 (e.g., sleep state and / or wake-up state), the states of the first SERDES circuit 131 and / or the second SERDES circuit 151 can be switched or maintained independently of the state of CPU 310. For example, the power state of at least one of the first SERDES circuit 131 and the second SERDES circuit 151 can be controlled independently of the power state of CPU 310. For example, when the state of CPU 310 corresponds to a low power state, the states of the first SERDES circuit 131 and / or the second SERDES circuit 151 can be maintained in a wake-up state. Based on the wake-up state, the first SERDES circuit 131 and / or the second SERDES circuit 151 can perform signal transmission and / or reception based on TSV 141. When the state of CPU 310 corresponds to a low power state, the first SERDES circuit 131 and the second SERDES circuit 151 can perform or control communication based on TSV 141 independently of CPU 310.

[0119] In an embodiment, communication based on TSV 141 can be controlled by a controller (e.g., controllers 211 and 221) of CPU 310 and / or SERDES circuitry. CPU 310 can control communication in TSV 141 when its state corresponds to a wake-up state. For example, a first timing sequence for transmitting signals from the first SERDES circuitry 131 to the second SERDES circuitry 151 and a second timing sequence for transmitting signals from the second SERDES circuitry 151 to the first SERDES circuitry 131 can be separated in the time domain by CPU 310 in a wake-up state. The embodiment is not limited thereto, and either controller 211 or 221 can operate as a master for controlling the first and second timing sequences. For example, either controller 211 or 221 can operate as a master after CPU 310 switches to a sleep state. In an embodiment, communication in TSV 141 can be controlled by CPU 310 and / or controllers 211 and 221 operating based on Link Training and State Machine (LTSSM).

[0120] In an embodiment where the state of the circuit is periodically transmitted via TSV 141, the state of the first SERDES circuit 131 and the state of the second SERDES circuit 151 can be periodically switched between a wake-up state and a sleep state. For example, controllers 211 and 221 can be periodically switched between a wake-up state and a sleep state based on a preset period (e.g., approximately 5 ms).

[0121] As described above, for example, to improve the yield of processor 110, signal paths for specific purposes (e.g., signal paths for transmitting status and / or interrupts) can be integrated into a single TSV 141. For example, based on the interface structure of TSV 141, first circuit 131, and second circuit 151, the number of TSVs required to form the signal paths can be reduced. Because the number of TSVs is reduced, the difficulty and / or complexity of the process used to form the TSVs can be reduced, and the yield of processor 110 can be improved.

[0122] According to an embodiment, the processor 110 can be designed with the yield of the TSV 141 used to connect the first SERDES circuit 131 and the second SERDES circuit 151 in mind. Hereinafter, reference is made to... Figure 4 An exemplary structure of interconnect layer 140 is described in relation to the yield of a single TSV 141 formed between the first SERDES circuit 131 and the second SERDES circuit 151.

[0123] Figure 4 An exemplary structure of the interconnect layer 140 included in the processor 110 according to an embodiment is shown. Figure 4 At least a portion of the processor 110 shown can correspond to Figure 1 , Figure 2 and / or Figures 3a to 3c At least a portion of the processor 110 shown, and even though not shown or specifically described below, in Figure 4 The processor 110 may also include the above-mentioned... Figure 1 , Figure 2 and / or Figures 3a to 3c The features described in the processor 110.

[0124] Reference Figure 4 The diagram illustrates a second circuit layer 150, an interconnect layer 140, and a first circuit layer 130 stacked sequentially along the z-axis in processor 110. A TSV 141 based on a serial communication protocol such as the BMC scheme can be formed between the first SERDES circuit 131 and the second SERDES circuit 151. In embodiments, processor 110 may include an interface structure robust to defects in the TSV.

[0125] Reference Figure 4 Interconnect layer 140 may include at least two TSVs 141 and 410 disposed between the first SERDES circuit 131 and the second SERDES circuit 151. TSVs 141 and 410 may be designed to have substantially the same characteristics (e.g., size, material, and / or process of the filled TSVs). In embodiments where two TSVs 141 and 410 are formed between the first SERDES circuit 131 and the second SERDES circuit 151, the first circuit layer 130 may include a first switching circuit 421 for connecting either TSV 141 or 410 to the first SERDES circuit 131. In the above embodiments, the second circuit layer 150 may include a second switching circuit 422 for connecting either TSV 141 or 410 to the second SERDES circuit 151. Either TSV 141 or 410 may be electrically isolated from the first SERDES circuit 131 and the second SERDES circuit 151 via the first switching circuit 421 and / or the second switching circuit 422.

[0126] exist Figure 4 In this embodiment, one end of TSV 141 can be connected to the first SERDES circuit 131 via the first switching circuit 421, and the other end of TSV 141 can be connected to the second SERDES circuit 151 via the second switching circuit 422. Because TSV 141 is electrically connected to the first SERDES circuit 131 and the second SERDES circuit 151 via the first switching circuit 421 and the second switching circuit 422, TSV 410 can be electrically isolated from the first SERDES circuit 131 and the second SERDES circuit 151. During the manufacturing process of processor 110, TSV 410, which is determined to be defective, can be disconnected from the first SERDES circuit 131 and the second SERDES circuit 151.

[0127] exist Figure 4 In this embodiment, the TSV 141 electrically connected to the first SERDES circuit 131 and the second SERDES circuit 151 can be referred to as the main TSV, normal TSV, and / or default TSV. Figure 4 In some embodiments, TSV 410, which is electrically disconnected from the first SERDES circuit 131 and the second SERDES circuit 151, may be referred to as a sub-TSV, redundant TSV, auxiliary TSV, and / or replacement (reserved or substitute) TSV. Embodiments are not limited thereto, and TSV 410 may be formed in interconnect layer 140 to establish electrical connections based on deficiencies in the main TSV (e.g., TSV 141).

[0128] In an embodiment, the connection of TSVs 141 and 410 via the first switching circuit 421 and the second switching circuit 422 can be dynamically changed according to the characteristics of each of TSVs 141 and 410. For example, if TSV 141, which is connected to the first SERDES circuit 131 and the second SERDES circuit 151, is damaged, TSV 410 can be connected to the first SERDES circuit 131 and the second SERDES circuit 151 instead of TSV 141. For example, either TSV 141 or 410 can be connected to the first SERDES circuit 131 and the second SERDES circuit 151 based on the characteristics of the protocol used between the first SERDES circuit 131 and the second SERDES circuit 151 (e.g., type and / or speed) and / or the characteristics of the signals transmitted between the first SERDES circuit 131 and the second SERDES circuit 151. For example, the TSVs connected to the first SERDES circuit 131 and the second SERDES circuit 151 when transmitting signals based on the BMC scheme and the TSVs connected to the first SERDES circuit 131 and the second SERDES circuit 151 when transmitting signals based on a faster protocol than the BMC scheme (e.g., the MIPI protocol) can be different. In the example, either TSV 141 or 410 can be selected based on different characteristics of TSV 141 and 410 (e.g., interference characteristics and / or high-frequency characteristics).

[0129] The connection between TSVs 141 and 410 shown above and the SERDES circuit can be controlled by a first switching circuit 421 and a second switching circuit 422. The first switching circuit 421 and / or the second switching circuit 422 may include a controller for controlling the connection. Embodiments are not limited thereto, and the first switching circuit 421 and / or the second switching circuit 422 may be controlled by controllers 211 and 221 and / or a CPU (e.g., Figure 3a CPU 310) control.

[0130] In embodiments including multiple TSVs 141 and 410, the first SERDES circuit 131 and the second SERDES circuit 151 can transmit a single signal using all of the multiple TSVs 141 and 410. For example, a signal transmitted from the first SERDES circuit 131 can propagate substantially simultaneously in the multiple TSVs 141 and 410. The second SERDES circuit 151 can eliminate errors occurring in either TSV 141 or 410 by comparing or combining the signals received simultaneously through the TSVs 141 and 410.

[0131] In embodiments including multiple TSVs 141 and 410, the first SERDES circuit 131 and the second SERDES circuit 151 may use at least one first TSV 141 of the multiple TSVs 141 and 410 to transmit signals from the first SERDES circuit to the second SERDES circuit, and may use a second TSV 410 to transmit signals from the second SERDES circuit to the first SERDES circuit. According to embodiments, signal transmission and reception may be performed substantially simultaneously in the TSVs 141 and 410.

[0132] As described above, according to the embodiments, the processor 110 may have an interface structure that is robust to the yield of TSVs and / or errors occurring in TSVs.

[0133] In this embodiment, the first SERDES circuit 131 and the second SERDES circuit 151 can support communication based on multiple protocols, including the BMC scheme. Referring below... Figure 5 The description includes an exemplary structure of a processor 110 that includes an interface structure supporting communication based on multiple protocols.

[0134] Figure 5 An exemplary structure for an interconnect layer 140 to support multiple wired communication protocols is shown. Figure 5 At least a portion of the processor 110 shown can correspond to Figure 1 , Figure 2 , Figures 3a to 3c and / or Figure 4 At least a portion of the processor 110 shown, and even though not shown or specifically described below, in Figure 5 The processor 110 may also include the above-mentioned... Figure 2 , Figures 3a to 3c and / or Figure 4 The features described in the processor 110.

[0135] Reference Figure 5 The diagram illustrates at least a portion of a second circuit layer 150, an interconnect layer 140, and a first circuit layer 130, sequentially stacked along the z-axis in a processor 110. A first SERDES circuit 131 of the first circuit layer 130 may include pins (p11, p12, p13, p14, ..., p1k) for connection to circuitry included in the first integrated circuit layer 130. A second SERDES circuit 151 of the second circuit layer 150 may include pins (p21, p22, p23, p24, ..., p2k) for connection to circuitry included in the second circuit layer 150. To transmit bits obtained through these pins, one or more TSVs may be formed between the first SERDES circuit 131 and the second SERDES circuit 151.

[0136] Reference Figure 5 In embodiments including multiple TSVs 531, 532, 533, and 534 formed in interconnect layer 140, signal transmission based on multiple protocols (e.g., serial communication protocols) can be supported between the first SERDES circuit 131 and the second SERDES circuit 151. For example, high-speed communication protocols (e.g., USB including PCIe, MIPI, and / or USB 3.2) requiring a dedicated signal path for transmitting clock signals can be supported by the multiple TSVs 531, 532, 533, and 534 and the first SERDES circuit 131 and the second SERDES circuit 151 connected to the multiple TSVs 531, 532, 533, and 534. (Refer to...) Figure 5 An interface structure based on four TSVs 531, 532, 533 and 534 is illustrated, but the embodiments are not limited thereto.

[0137] In an embodiment, the first SERDES circuit 131 may include circuitry for supporting different high-speed communication protocols. For example, the first SERDES circuit 131 may include a PCIe circuit 511 for transmitting and / or receiving PCIe-based signals, a MIPI circuit 512 for transmitting and / or receiving MIPI-based signals, and a USB circuit 513 for transmitting and / or receiving USB-based signals. To support high-speed communication protocols, the second SERDES circuit 132 may also include a PCIe circuit 521, a MIPI circuit 522, and a USB circuit 523. An exemplary illustration shows a first SERDES circuit 131 and / or a second SERDES circuit 151 including circuitry for supporting three high-speed communication protocols (e.g., PCIe, MIPI, and / or USB), but the embodiments are not limited thereto.

[0138] In an embodiment, the first SERDES circuit 131 may include a first multiplexer switching circuit 514 for selecting a protocol. Similarly, the second SERDES circuit 151 may also include a second multiplexer switching circuit 524 for selecting a protocol. During a first time segment for transmitting USB-based signals, in the first SERDES circuit 131, pins of the USB circuit 513 and multiple TSVs 531, 532, 533, and 534 can be connected via the first multiplexer switching circuit 514. During the first time segment, in the second SERDES circuit 151, pins of the USB circuit 523 and multiple TSVs 531, 532, 533, and 534 can be connected via the second multiplexer switching circuit 524.

[0139] In this embodiment, during a second time segment for transmitting PCIe-based signals, in the first SERDES circuit 131, the pins of the PCIe circuit 511 and multiple TSVs 531, 532, 533, and 534 can be connected via a first multiplexer switching circuit 514. During the second time segment, in the second SERDES circuit 151, the pins of the PCIe circuit 521 and multiple TSVs 531, 532, 533, and 534 can be connected via a second multiplexer switching circuit 524. During the second time segment, multiple TSVs 531, 532, 533, and 534 can be matched with each signal path defined by PCIe.

[0140] Similarly, during the third time segment of transmitting MIPI-based signals, an electrical connection between MIPI circuits 512 and 522 based on multiple TSVs 531, 532, 533, and 534 can be established via the first multiplexer switching circuit 514 and the second multiplexer switching circuit 524. The protocol corresponding to the signal to be transmitted via the multiple TSVs 531, 532, 533, and 534 can be determined based on the required transmission speed (e.g., data rate), the information included in the signal, and / or the size of the data. The determination of the protocol can be made by the controllers of the first SERDES circuit 131 and / or the second SERDES circuit 151 (e.g., Figure 2 The controllers 211 and 221) and / or another circuit in the processor 110 (e.g., Figure 3a The CPU 310) executes the command.

[0141] As described above, according to the embodiments, the processor 110 may include an interface structure for supporting multiple communication protocols (e.g., an interface structure including a first SERDES circuit 131, a second SERDES circuit 151, and TSVs (e.g., TSVs 531, 532, 533, and 534)). Based on the interface structure, the processor 110 can select a suitable interface protocol.

[0142] In the following text, reference will be made to Figure 6 This describes an exemplary operation of a processor 110 that supports single TSV communication based on a BMC scheme.

[0143] Figure 6 This is an exemplary timing diagram 600 of electrical signals transmitted from the interconnect layer based on a biphase mark coding (BMC) scheme. (Refer to...) Figure 6 The described BMC scheme can be used in Figures 1 to 5 The interconnect layer in the interface structure (e.g., the interface structure including the first SERDES circuit 131, the second SERDES circuit 151, and the TSV 141) included in the processor 110 (e.g., Figures 1 to 5 Signals are transmitted in the interconnect layer 140.

[0144] In an embodiment, the first circuit layer (e.g., Figures 1 to 5 The first SERDES circuit of the first circuit layer 130 can encode the serialized signal based on the BMC scheme. The first SERDES circuit can transmit the encoded signal to the second circuit layer (e.g., via TSV) Figures 1 to 5 The second SERDES circuit of the second circuit layer 150).

[0145] In an embodiment, the BMC scheme can be used for communication (e.g., Power over a single wire (PD) communication) at the Configuration Channel (CC) pin of the USB Type-C port. The BMC scheme can be referred to as the Differential Manchester Encoding scheme. At the CC pin, ID and / or power configuration information can be sent or received based on the BMC scheme. See reference... Figure 6 The BMC scheme demonstrates the connection with TSVs (e.g., via the interconnect layer) based on the interconnect layer. Figures 1 to 4 An exemplary timing diagram 600 related to the electrical signals transmitted by the TSV 141.

[0146] Reference Figure 6 In timing diagram 600, curves 610, 620, and 630 are shown along the equivalent time domain. Curve 610 shows the clock signal associated with the electrical signal to be transmitted via TSV. Curve 620 shows multiple bits to be included in the electrical signal to be transmitted via TSV. These multiple bits can be serialized by the SERDES circuitry. For example, multiple bits can be provided from different circuits connected to the SERDES circuitry to notify status and / or interrupts. (See reference...) Figure 6 As shown in graph 620, in an embodiment where transmission begins from the most significant bit (MSB) of the serialized bit sequence, the sequence of bits serialized by the SERDES circuit may include 10011010010 (2) Graph 630 can indicate the final sequence of bits included in the signal sent to the TSV by the SERDES circuit.

[0147] According to an embodiment, the SERDES circuit can be based on a BMC scheme through a single signal path (e.g., Figures 1 to 4The TSV (141) transmits all clock signals and data (e.g., a sequence of bits). Based on the BMC scheme, at each of the rising and falling edges of the clock signal indicated by curve 610, the bits to be included in the final sequence can be determined or changed based on the bits indicated by curve 620. Based on the BMC scheme, the voltage level of the signal sent to the TSV can be changed during the time segments (e.g., t1, t4, t5, t7, and / or t10) when bits 1 in the sequence are encoded. During the visual guidance (e.g., t2, t3, t6, t8, and / or t9) when bits 0 in the sequence are encoded, the voltage level of the signal sent to the TSV can be maintained.

[0148] In an embodiment, a SERDES circuit that receives a signal with a voltage level such as curve 630 via TSV can obtain the clock and bit sequence from the signal based on the characteristics of the BMC scheme. For example, during the time intervals when the voltage level changes (t1, t4, t5, t7, and / or t10), the SERDES circuit can determine that bit 1 is encoded. For example, during the time intervals when the voltage level is maintained (t2, t3, t6, t8, and / or t9), the SERDES circuit determines that bit 0 has been received. A SERDES circuit that identifies the bit sequence indicated by curve 620 from the signal based on curve 630 can obtain the bits to be output to each of the multiple pins of the SERDES circuit based on deserialization bit division.

[0149] Exemplary operation of a SERDES circuit for analyzing signals transmitted over a single TSV based on a BMC scheme has been described, but the embodiments are not limited thereto. (Refer to the above...) Figures 1 to 5 As described, SERDES circuitry can transmit or analyze signals based on protocols with data rates exceeding those supported by the BMC scheme, such as I2C, I3C, USB (e.g., USB 3.2), PCIe, MIPI (D-PHY, C-PHY, M-PHY), DP (Display Port), LPDDR4-6, and / or UFS. To support high-speed protocols, multiple TSVs can be formed between SERDES circuitry located in different circuit layers.

[0150] As described above, an electronic device including an access point (AP) is provided, the AP having a structure in which multiple circuit layers are stacked. In this AP, an interconnect layer comprising signal paths (e.g., TSV-based signal paths) between the multiple circuit layers can be formed. To reduce the number of TSVs included in the interconnect layer, an integrated signal transmission interface based on SERDES circuits can be formed in each circuit layer disposed above and below the interconnect layer. Each SERDES circuit can perform serialization of bits (e.g., bits indicating values ​​to notify the state and / or interruption of the circuit) included in the corresponding circuit layer. Serialized signals can be transmitted from one circuit layer to another via at least one TSV of the interconnect layer. In response to a signal received via a TSV, each SERDES circuit can perform deserialization of the bits included in the signal. The signals and / or bits obtained based on the deserialization can be assigned to other circuits connected to the SERDES circuit performing the deserialization.

[0151] In the following text, reference will be made to Figure 7 Description Reference Figures 1 to 6 Examples of the described AP and / or electronic devices.

[0152] Figure 7 This is a block diagram illustrating an electronic device 701 in a network environment 700 according to various embodiments. (Refer to...) Figure 7 In network environment 700, electronic device 701 can communicate with electronic device 702 via a first network 798 (e.g., a short-range wireless communication network), or with at least one of electronic device 704 or server 708 via a second network 799 (e.g., a long-range wireless communication network). According to an embodiment, electronic device 701 can communicate with electronic device 704 via server 708. According to an embodiment, electronic device 701 may include a processor 720, memory 730, input module 750, sound output module 755, display module 760, audio module 770, sensor module 776, interface 777, connection terminal 778, haptic module 779, camera module 780, power management module 788, battery 789, communication module 790, user identification module (SIM) 796, or antenna module 797. In some embodiments, at least one of the above components (e.g., connection terminal 778) may be omitted from electronic device 701, or one or more other components may be added to electronic device 701. In some embodiments, some of the components described above (e.g., sensor module 776, camera module 780, or antenna module 797) may be implemented as a single component (e.g., display module 760).

[0153] Processor 720 may run software (e.g., program 740) to control at least one other component (e.g., hardware or software component) coupled to electronic device 701, and may perform various data processing or calculations. According to embodiments, as at least part of the data processing or calculation, processor 720 may store commands or data received from another component (e.g., sensor module 776 or communication module 790) in volatile memory 732, process the commands or data stored in volatile memory 732, and store the resulting data in non-volatile memory 734. According to embodiments, processor 720 may include a main processor 721 (e.g., central processing unit (CPU) or application processor (AP)) or an auxiliary processor 723 (e.g., graphics processing unit (GPU), neural processing unit (NPU), image signal processor (ISP), sensor central processor, or communication processor (CP)) that is operationally independent of or combined with the main processor 721. For example, when the electronic device 701 includes a main processor 721 and an auxiliary processor 723, the auxiliary processor 723 can be adapted to consume less power than the main processor 721, or adapted to be dedicated to a specific function. The auxiliary processor 723 can be implemented separately from the main processor 721, or implemented as part of the main processor 721.

[0154] When the main processor 721 is inactive (e.g., in sleep mode), the auxiliary processor 723 (rather than the main processor 721) can control at least some of the functions or states associated with at least one component of the electronic device 701 (e.g., display module 760, sensor module 776, or communication module 790), or when the main processor 721 is active (e.g., running an application), the auxiliary processor 723 can work with the main processor 721 to control at least some of the functions or states associated with at least one component of the electronic device 701 (e.g., display module 760, sensor module 776, or communication module 790). According to embodiments, the auxiliary processor 723 (e.g., an image signal processor or a communication processor) can be implemented as part of another component (e.g., camera module 780 or communication module 790) functionally associated with the auxiliary processor 723. According to embodiments, the auxiliary processor 723 (e.g., a neural processing unit) can include hardware architectures dedicated to artificial intelligence model processing. Artificial intelligence models can be generated through machine learning. For example, such learning can be performed via electronic device 701 where the artificial intelligence model is executed or via a separate server (e.g., server 708). The learning algorithm can include, but is not limited to, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The artificial intelligence model can include multiple layers of artificial neural networks. The artificial neural network can be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), or a deep Q-network, or a combination of two or more thereof, but is not limited thereto. Additionally or optionally, the artificial intelligence model can include software structures in addition to hardware structures.

[0155] The memory 730 may store various data used by at least one component of the electronic device 701 (e.g., processor 720 or sensor module 776). The various data may include, for example, software (e.g., program 740) and input or output data for commands associated with it. The memory 730 may include volatile memory 732 or non-volatile memory 734.

[0156] The program 740 can be stored as software in the memory 730, and the program 740 may include, for example, an operating system (OS) 742, middleware 744, or application 746.

[0157] The input module 750 can receive commands or data from outside the electronic device 701 (e.g., from a user) that will be used by another component of the electronic device 701 (e.g., the processor 720). The input module 750 may include, for example, a microphone, a mouse, a keyboard, keys (e.g., buttons), or a digital pen (e.g., a stylus).

[0158] The sound output module 755 can output sound signals to the outside of the electronic device 701. The sound output module 755 may include, for example, a speaker or a receiver. The speaker can be used for general purposes such as playing multimedia or playing records. The receiver can be used to receive incoming calls. According to embodiments, the receiver can be implemented separately from the speaker, or as part of the speaker.

[0159] Display module 760 can visually provide information to the outside of electronic device 701 (e.g., to a user). Display module 760 may include, for example, a display, a holographic device, or a projector, and control circuitry for controlling a corresponding one of the display, holographic device, and projector. According to an embodiment, display module 760 may include a touch sensor adapted to detect touch or a pressure sensor adapted to measure the intensity of the force caused by touch.

[0160] The audio module 770 can convert sound into electrical signals and vice versa. According to an embodiment, the audio module 770 can obtain sound via the input module 750, or output sound via the sound output module 755 or headphones of an external electronic device (e.g., electronic device 702) that is directly (e.g., wired) coupled to the electronic device 701 or wirelessly coupled to it.

[0161] Sensor module 776 can detect the operating state of electronic device 701 (e.g., power or temperature) or the environmental state outside electronic device 701 (e.g., user state), and then generate an electrical signal or data value corresponding to the detected state. According to embodiments, sensor module 776 may include, for example, a gesture sensor, gyroscope sensor, atmospheric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0162] Interface 777 may support one or more specific protocols used to couple (e.g., wired) or wirelessly to electronic device 701 with external electronic device (e.g., electronic device 702). According to embodiments, interface 777 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface.

[0163] Connection 778 may include a connector through which electronic device 701 can be physically connected to an external electronic device (e.g., electronic device 702). According to embodiments, connection 778 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0164] The haptic module 779 can convert electrical signals into mechanical stimuli (e.g., vibration or motion) or electrical stimuli that can be recognized by a user through their touch or kinesthesia. According to embodiments, the haptic module 779 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0165] Camera module 780 can capture still or moving images. According to embodiments, camera module 780 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0166] The power management module 788 can manage the power supply to the electronic device 701. According to an embodiment, the power management module 788 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0167] Battery 789 can power at least one component of electronic device 701. According to embodiments, battery 789 may include, for example, a non-rechargeable primary battery, a rechargeable rechargeable battery, or a fuel cell.

[0168] Communication module 790 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 701 and external electronic devices (e.g., electronic device 702, electronic device 704, or server 708), and perform communication via the established communication channel. Communication module 790 may include one or more communication processors capable of operating independently of processor 720 (e.g., application processor (AP)) and support direct (e.g., wired) or wireless communication. According to embodiments, communication module 790 may include wireless communication module 792 (e.g., cellular communication module, short-range wireless communication module, or Global Navigation Satellite System (GNSS) communication module) or wired communication module 794 (e.g., local area network (LAN) communication module or power line communication (PLC) module). A corresponding one of these communication modules can communicate via a first network 798 (e.g., a short-range communication network, such as Bluetooth). TM The communication module 792 can communicate with external electronic devices via a Wi-Fi Direct or Infrared Data Association (IrDA) network or a second network 799 (e.g., a long-range communication network, such as a traditional cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). These various types of communication modules can be implemented as a single component (e.g., a single chip) or as multiple components that are separate from each other (e.g., multiple chips). The wireless communication module 792 can use user information (e.g., the International Mobile Subscriber Identity (IMSI)) stored in the user identification module 796 to identify and verify the electronic device 701 in the communication network (such as the first network 798 or the second network 799).

[0169] Wireless communication module 792 can support 5G networks following 4G networks and next-generation communication technologies (such as new radio (NR) access technologies). NR access technologies can support enhanced mobile broadband (eMBB), massive machine-type communication (mMTC), or ultra-reliable low-latency communication (URLLC). Wireless communication module 792 can support high-frequency bands (e.g., millimeter-wave bands) to achieve, for example, high data transmission rates. Wireless communication module 792 can support various technologies used to ensure performance in high-frequency bands, such as, for example, beamforming, massive MIMO, full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, or massive antennas. Wireless communication module 792 can support various requirements specified in electronic device 701, external electronic device (e.g., electronic device 704), or network system (e.g., second network 799). According to an embodiment, the wireless communication module 792 may support peak data rates (e.g., 20 Gbps or greater) for implementing eMBB, lost coverage (e.g., 164 dB or less) for implementing mMTC, or U-plane latency (e.g., 0.5 ms or less for each of the downlink (DL) and uplink (UL), or 1 ms or less round trip) for implementing URLLC.

[0170] Antenna module 797 can transmit or receive signals or power to or from the outside of electronic device 701 (e.g., external electronic device). According to an embodiment, antenna module 797 may include an antenna comprising a radiating element formed of conductive material or conductive patterns formed in or on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, antenna module 797 may include multiple antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication scheme used in a communication network (such as a first network 798 or a second network 799) can be selected from the multiple antennas by, for example, communication module 790 (e.g., wireless communication module 792). Signals or power can then be transmitted or received between communication module 790 and external electronic device via the selected at least one antenna. According to an embodiment, another component besides the radiating element (e.g., a radio frequency integrated circuit (RFIC)) may be additionally incorporated into antenna module 797.

[0171] According to various embodiments, antenna module 797 can form a millimeter-wave antenna module. According to embodiments, the millimeter-wave antenna module may include a printed circuit board, an RFIC, and multiple antennas (e.g., an array antenna), wherein the RFIC is disposed on or adjacent to a first surface (e.g., a bottom surface) of the printed circuit board and is capable of supporting a specified high-frequency band (e.g., a millimeter-wave band), and the multiple antennas are disposed on or adjacent to a second surface (e.g., a top or side surface) of the printed circuit board and are capable of transmitting or receiving signals in the specified high-frequency band.

[0172] At least some of the aforementioned components can be coupled to each other and transmit signals (e.g., commands or data) between them via an inter-peripheral communication scheme (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), or mobile industrial processor interface (MIPI)).

[0173] According to an embodiment, commands or data can be sent or received between electronic device 701 and external electronic device 704 via server 708 coupled to a second network 799. Each of electronic device 702 or electronic device 704 can be a device of the same type as electronic device 701, or a device of a different type. According to an embodiment, all or some operations to be performed on electronic device 701 can be performed on one or more of external electronic devices 702, external electronic devices 704, or server 708. For example, if electronic device 701 is required to automatically perform a function or service, or is required to perform a function or service in response to a request from a user or another device, electronic device 701 may request one or more external electronic devices to perform at least a portion of the function or service, instead of running the function or service, or electronic device 701 may request one or more external electronic devices to perform at least a portion of the function or service in addition to running the function or service. Upon receiving the request, one or more external electronic devices may perform at least a portion of the requested function or service, or perform additional functions or services related to the request, and transmit the result of the execution to electronic device 701. Electronic device 701 can provide the result as at least a partial response to the request, with or without further processing of the result. For this purpose, technologies such as cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing can be used. Electronic device 701 can use, for example, distributed computing or mobile edge computing to provide ultra-low latency services. In another embodiment, external electronic device 704 may include an Internet of Things (IoT) device. Server 708 may be an intelligent server using machine learning and / or neural networks. According to embodiments, external electronic device 704 or server 708 may be included in a second network 799. Electronic device 701 can be applied to intelligent services (e.g., smart homes, smart cities, smart cars, or healthcare) based on 5G communication technology or IoT-related technologies.

[0174] The electronic device according to various embodiments can be one of a variety of types of electronic devices. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. According to embodiments of this disclosure, the electronic device is not limited to those described above.

[0175] It should be understood that the various embodiments of this disclosure and the terminology used therein are not intended to limit the technical features set forth herein to the specific embodiments, but rather to include various changes, equivalents, or substitutions to the respective embodiments. In the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It will be understood that the singular form of a noun corresponding to an item may include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may include any one or all possible combinations of the items enumerated together with the corresponding phrase among the plurality of phrases. As used herein, terms such as “first” and “second” or “first” and “second” may be used to simply distinguish one component from another and do not limit the components in other respects (e.g., importance or order). It will be understood that, whether the terms “operably” or “communically” are used or not, if an element (e.g., a first element) is referred to as being “coupled” or “connected” to another element (e.g., a second element), it means that the element can be directly (e.g., wiredly) coupled to the other element, wirelessly connected to the other element, or coupled to the other element via a third element.

[0176] As used in connection with various embodiments of this disclosure, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic," "logic block," "part," or "circuit." A module may be a single integrated component adapted to perform one or more functions, or the smallest unit or part of such a single integrated component. For example, according to embodiments, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0177] The various embodiments set forth herein can be implemented as software (e.g., program 740) containing one or more instructions readable by a machine (e.g., electronic device 701) stored in a storage medium (e.g., internal memory 736 or external memory 738). For example, under the control of a processor (e.g., processor 720) of the machine (e.g., electronic device 701), the processor can invoke and execute at least one instruction from one or more instructions stored in the storage medium, with or without the use of one or more other components. This enables the machine to operate to perform at least one function according to the invoked at least one instruction. The one or more instructions may include code generated by a compiler or code that can be run by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" means only that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but this term does not distinguish between cases where data is stored semi-permanently in the storage medium and cases where data is temporarily stored in the storage medium.

[0178] According to embodiments, methods according to various embodiments of this disclosure may be included and provided in a computer program product. The computer program product can be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disk read-only memory (CD-ROM)) or via an app store (e.g., the Play Store). TM The computer program product may be distributed online (e.g., downloaded or uploaded), or may be distributed directly between two user devices (e.g., smartphones) (e.g., downloaded or uploaded). If it is distributed online, at least a portion of the computer program product may be temporarily generated, or at least a portion of the computer program product may be temporarily stored in a machine-readable storage medium (such as the memory of a manufacturer's server, an app store's server, or a forwarding server).

[0179] According to various embodiments, each of the above components (e.g., a module or program) may include a single entity or multiple entities, and some of the multiple entities may be separately disposed in different components. According to various embodiments, one or more of the above components may be omitted, or one or more other components may be added. Optionally or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, according to various embodiments, the integrated component may still perform one or more functions of each of the multiple components in the same or similar manner as the corresponding component of the multiple components performed one or more functions before integration. According to various embodiments, the operations performed by a module, program, or other component may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more operations may be run in a different order or omitted, or one or more other operations may be added.

[0180] In an embodiment, a method for integrating a signal path established within the AP may be required. In an embodiment, a method for improving the yield of the AP included in an electronic device may be required. In an embodiment, a method for stably producing an AP including stacked circuit layers may be required. As mentioned above, according to embodiments, three-dimensional integrated circuits (3D-ICs) (e.g., Figure 1 The processor 110 may include a substrate, a first integrated circuit layer disposed above the substrate and including a plurality of first circuit elements (e.g., Figure 1 The second circuit layer 150), disposed above the first integrated circuit layer and including a plurality of second circuit elements (e.g., Figure 1 The first circuit layer 130) and the through silicon via (TSV) disposed between the first integrated circuit layer and the second integrated circuit layer (e.g., Figure 1 The interconnect layers of TSV 141 and 142 (e.g., Figure 1 Interconnect layer 140). The plurality of first circuit elements may include a plurality of first signal pins corresponding to a first signal type and at least one second signal pin corresponding to a second signal type. The plurality of first signal pins may be accessible via a first serializer-deserializer (SERDES) circuit (e.g., Figure 1 The second SERDES circuit 151) is connected to the first TSV among a plurality of TSVs (e.g., Figure 1 The TSV 141). The plurality of second circuit elements may include a plurality of third signal pins corresponding to a plurality of first signal pins and at least one fourth signal pin corresponding to at least one second signal pin. The first TSV may be accessible via a second SERDES circuit (e.g., Figure 1The first SERDES circuit 131) is connected to multiple third signal pins. In an embodiment, signal paths established within the AP can be integrated. In an embodiment, the yield of the AP included in the electronic device can be improved. In an embodiment, APs including stacked circuit layers can be manufactured stably.

[0181] For example, multiple TSVs may include alternative TSVs connected between the first SERDES circuit and the second SERDES circuit and configured to have the characteristics of the first TSV (e.g., Figure 4 TSV 410).

[0182] For example, an alternative TSV can be configured to operate based on the connection state of the first TSV.

[0183] For example, the first signal type can correspond to a control signal, and the second signal type can correspond to a data signal.

[0184] For example, the first TSV and the alternative TSV can be switched via a first switching circuit (e.g., Figure 4 The second switching circuit 422) is connected to the first SERDES circuit. The first TSV and the alternative TSV can be configured to be connected via the second switching circuit (e.g., Figure 4 The first switching circuit 421) is connected to the second SERDES circuit.

[0185] For example, at least one first data signal pin and at least one second data signal pin can be configured to be directly connected via a second TSV among a plurality of TSVs.

[0186] For example, multiple first signal pins can be configured to include interrupt-related signal pins and reset-related signal pins.

[0187] For example, multiple control signals corresponding to multiple first signal pins can be generated at different timings. The first SERDES circuit can be configured to send multiple control signals to the second SERDES circuit based on a specified period.

[0188] For example, multiple first circuit elements can be configured to include a modem. Multiple second circuit elements can be configured to include a central processing unit (CPU) (e.g., Figures 3a to 3c CPU 310).

[0189] For example, the minimum linewidth of the first integrated circuit layer can be greater than the minimum linewidth of the second integrated circuit layer.

[0190] For example, the first SERDES circuit and the second SERDES circuit can be configured to communicate via a first TSV using serial communication of less than 5 Mbps.

[0191] For example, the first SERDES circuit and the second SERDES circuit can be configured to communicate based on a specified serial communication protocol for each of the plurality of first signals among a plurality of serial communication protocols.

[0192] For example, the first TSV can be configured to be selected from multiple TSVs based on a specified serial communication protocol.

[0193] For example, the first SERDES circuit can be configured to maintain a wake-up state when a low-voltage power signal is supplied to the first circuit element.

[0194] For example, the first SERDES circuit may include a controller (e.g., Figure 2 The controller 211. The controller can be configured to control the communication between the first SERDES circuit and the second SERDES circuit based on whether the first circuit element receives a low-voltage power signal.

[0195] As described above, according to an embodiment, an electronic device (e.g., Figure 1 The electronic device 101 may include a display (e.g., Figure 1 Displays 123), antennas, printed circuit boards (e.g., Figure 1 The PCB 105 comprises a first integrated circuit disposed on the printed circuit board and a second integrated circuit disposed on the printed circuit board and electrically connected to the first integrated circuit. The second integrated circuit may include: a first circuit layer including a plurality of first circuit elements; a second circuit layer disposed above the first circuit layer and including a plurality of second circuit elements; and an interconnect layer disposed between the first and second circuit layers and including a plurality of through-silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first signal pins corresponding to a first signal type and at least one second signal pin corresponding to a second signal type. The plurality of first control signal pins may be connected to a first TSV among the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of third control signal pins corresponding to the plurality of first control signal pins and at least one fourth signal pin corresponding to at least one second signal pin. The first TSV may be connected to the plurality of third control signal pins via a second SERDES circuit.

[0196] For example, a plurality of TSVs may include a second TSV connected between a first SERDES circuit and a second SERDES circuit and transmitting substantially the same signal as the first TSV.

[0197] For example, at least one second signal pin and at least one fourth signal pin can be directly connected through a third TSV among a plurality of TSVs.

[0198] As described above, according to an embodiment, an integrated circuit may include: a first integrated circuit layer including a plurality of first circuit elements corresponding to a first minimum circuit linewidth; a second integrated circuit layer disposed above the first integrated circuit layer and including a plurality of second circuit elements corresponding to a second minimum circuit linewidth smaller than the first minimum circuit linewidth; and a plurality of pathways electrically connecting the first integrated circuit layer and the second integrated circuit layer. The first integrated circuit layer may include a first serializer-deserializer (SERDES) circuit that connects the plurality of first circuit elements to a first pathway that is a specific pathway among the plurality of pathways. The second integrated circuit layer may include a second SERDES circuit that connects the first pathway to the plurality of second circuit elements.

[0199] For example, the multiple first circuit elements may include multiple control signal pins. The multiple control signals corresponding to the multiple control signal pins can be configured to be transmitted through a first path based on a serial communication protocol.

[0200] For example, the integrated circuit may include a second path configured to transmit substantially the same signal as the first path. The second path may be configured to be located between the first SERDES circuit and the second SERDES circuit.

[0201] As described above, according to an embodiment, an application processor (AP) (e.g., Figures 1 to 5 The processor 110 may include: a first circuit layer (e.g., Figure 1 The first circuit layer 130 includes a first serializer-deserializer (SERDES) electronic assembly (e.g., Figure 1 The first SERDES circuit 131), the first SERDES electronics is connected to the first electronic component (e.g., Figure 1 The circuit 132), at least one second electronic component, and each of a third electronic component comprising a first electronic component and at least one second electronic component; a second circuit layer (e.g., Figure 1 The second circuit layer 150 includes a fourth electronic component (e.g., Figure 1 The second circuit 152) and the second SERDES electronic component connected to the fourth electronic component (e.g., Figure 1 The second SERDES circuit 151); and the interconnect layer (e.g., Figure 1 An interconnect layer 140 is disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a TSV, which includes a first through-silicon via (TSV) connecting the first electronic component to the fourth electronic component (e.g., ...). Figure 1 TSV 142) and a second TSV (e.g., connecting the first SERDES electronic component to the second SERDES electronic component) Figure 1(TSV 141). The first electronic component can transmit a first type of signal to the fourth electronic component via the first TSV in the interconnect layer. The first electronic component can transmit a second type of signal to the first SERDES electronic component in order to transmit the second type of signal to the fourth electronic component. The first SERDES electronic component can perform serialization on the second type of signal together with at least one signal transmitted from at least one second electronic component. The first SERDES electronic component can transmit a signal obtained based on serialization to the second SERDES electronic component via the second TSV. The second SERDES electronic component can be configured to obtain the second type of signal to be transmitted to the fourth electronic component based on the deserialization of the signal transmitted via the second TSV.

[0202] For example, the first SERDES electronic component may include a buffer (e.g., Figure 2 The buffer 212 is configured to store one or more bits included in a second type of signal that indicate the state of the first electronic component.

[0203] For example, the first SERDES electronic component can be configured to generate a sequence of multiple bits by performing serialization of the one or more bits and at least one bit included in at least one signal transmitted from at least one second electronic component. The first SERDES electronic component can be configured to transmit the signal including the sequence to the second SERDES electronic component via a second TSV.

[0204] For example, the first SERDES electronic component can be configured to store at least one bit obtained from the third electronic component in a buffer within a preset time interval. The first SERDES electronic component can be configured to perform serialization of the at least one bit stored in the buffer based on the expiration of the preset time interval.

[0205] For example, the second SERDES electronic component can be configured to generate a signal to be transmitted to the first SERDES electronic component via the second TSV based on a second type of signal sent from the fourth electronic component.

[0206] For example, the second SERDES electronic component can be connected to each of the fifth electronic components, including the fourth electronic component, included in the second circuit layer. The second SERDES electronic component can be configured to generate a signal to be sent to the first SERDES electronic component based on the serialization of a second type of signal transmitted from the fifth electronic component.

[0207] For example, the second SERDES electronic component can be configured to receive from the fourth electronic component for use as a central processing unit (CPU) (e.g., Figures 3a to 3cThe first electronic component of the CPU 310 signals at least one of the status of the fourth electronic component or an interrupt related to the fourth electronic component.

[0208] For example, the second SERDES electronic component can be configured to send multiple bits to each of the fifth electronic components on the second circuit layer, including the fourth electronic component, based on deserialization according to the number of bits of each of the multiple bits in the signal transmitted through the second TSV.

[0209] For example, the first circuit layer can be configured to include circuit elements whose size is smaller than the smallest size of the circuit elements included in the second circuit layer.

[0210] For example, the first SERDES electronic component can be configured to send a signal obtained based on serialization and encoded based on a biphase mark decoding (BMC) scheme to the second SERDES electronic component via the second TSV.

[0211] For example, a second TSV can be configured to transmit signals within a first data rate range including 300 kbps. A first TSV can be configured to transmit a first type of signal within a second data rate range exceeding the first data rate range.

[0212] For example, the interconnect layer can be configured to include a third TSV (e.g., Figure 4 The TSV 410), configured to connect one end of the second TSV or the third TSV to the first switching electronics assembly (e.g., Figure 4 The first switching circuit 421) and the second switching electronics (e.g., configured to connect the other end of the second TSV, either the second TSV or the third TSV, to the second SERDES electronics) are also included. Figure 4 The second switching circuit 422).

[0213] For example, the first electronic component can be configured to send a first type of signal, including data, to the fourth electronic component via a first TSV. The first electronic component can also be configured to send a second type of signal to the first SERDES electronic component for controlling a controller included in the fourth electronic component.

[0214] For example, the fourth electronic component can be configured to send data to a volatile memory connected to the application processor based on a signal of the first type.

[0215] For example, the controller of the fourth electronic component can be configured to receive a second type of signal based on general purpose input / output (GPIO).

[0216] As described above, according to an embodiment, an application processor (AP) may include: a first circuit layer including a first electronic component, a plurality of second electronic components including the first electronic component, and a first serializer-deserializer (SERDES) electronic component connected to each of the plurality of second electronic components; a second circuit layer including a third electronic component and second SERDES electronic components connected to the third electronic component; and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the first electronic component to the third electronic component and configured to transmit a first type of signal from the first electronic component to the third electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component to the second SERDES electronic component and configured to transmit a second type of signal based on the serialization of the first SERDES electronic component. The second type of signal transmitted via the second TSV may include a sequence of bits based on the serialized plurality of second electronic components, the sequence including at least one bit provided by the first electronic component.

[0217] For example, the first SERDES electronic component may include a buffer configured to store bits transmitted from each of a plurality of second electronic components. The first SERDES electronic component may be configured to obtain a plurality of bits to be included in a second type of signal to be transmitted to the second SERDES electronic component via a second TSV, based on the serialization of the bits stored in the buffer during a preset time interval.

[0218] For example, the first SERDES electronic component can be configured to, in response to receiving a second type of signal from the second SERDES electronic component via the second TSV, obtain at least one bit to be provided to each of the plurality of second electronic components by performing deserialization of the received second type of signal.

[0219] For example, the first electronic component, which serves as a central processing unit (CPU), can be configured to send a first type of signal, including data, to the third electronic component via a first TSV. The first electronic component can also be configured to send a second type of signal to the first SERDES electronic component for controlling a controller of the third electronic component.

[0220] As described above, according to an embodiment, an electronic device may include a memory and an application processor (AP). The AP may include: a first circuit layer including a plurality of electronic components and a first serializer-deserializer (SERDES) electronic component, the plurality of electronic components including a central processing unit (CPU), the first SERDES electronic component being connected to each of the plurality of electronic components; a second circuit layer including a memory interface electronic component and a second SERDES electronic component for communicating with the memory; and an interconnect layer disposed between the first and second circuit layers. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the CPU of the first circuit layer and the memory interface electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component and the second SERDES electronic component. The CPU may be configured to send data signals, including data to be stored in the memory, to the memory interface electronic component via the first TSV. The CPU, as the first SERDES electronic component, may be configured to send control signals for controlling the memory interface electronic component, causing data to be sent to the memory.

[0221] For example, the first SERDES electronic component can be configured to obtain a signal including a sequence of bits included in the control signals by performing serialization of control signals obtained from multiple electronic components. The first SERDES electronic component can be configured to transmit the signal including the sequence to a second SERDES electronic component via a second TSV.

[0222] For example, the first SERDES electronic component can be configured to transmit signals including sequences based on a biphase marker coding (BMC) scheme.

[0223] For example, the first SERDES electronic component can be configured to obtain at least one bit to be sent to the CPU based on the deserialization of bits included in the received signal, based on the signal received from the second SERDES electronic component via the second TSV.

[0224] For example, a data signal can be configured to be transmitted in a first TSV based on a first data rate exceeding the second data rate supported by the second TSV.

[0225] For example, multiple electronic components can be configured to include circuit elements whose size is smaller than the smallest size of the circuit elements included in the memory interface electronic components of the second circuit layer.

[0226] As described above, according to an embodiment, a processing chip assembly may include a first die including a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first and second circuits. The processing chip assembly may include a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third and fourth circuits. The processing chip assembly may include an interconnect layer disposed between the first and second dies. The interconnect layer may include a first through-silicon via (TSV) configured to connect between the first and second SERDES circuits and provide a first signal path between the first and third circuits, a second signal path between the first and fourth circuits, a third signal path between the second and third circuits, and a fourth signal path between the second and fourth circuits.

[0227] For example, the interconnect layer may include a second TSV connecting the first circuit to the third circuit. The first circuit may be configured to transmit a first type of signal to the third circuit via the second TSV in the interconnect layer. The first circuit may be configured to send a second type of signal to a first SERDES circuit to transmit the second type of signal to the third circuit. The first SERDES circuit may be configured to perform serialization on the second type of signal together with the signal sent from the second circuit. The first SERDES circuit may be configured to transmit the signal obtained based on serialization to the second SERDES circuit via the first TSV. The second SERDES circuit may be configured to obtain the second type of signal to be transmitted to the third circuit based on the deserialization of the signal transmitted via the first TSV.

[0228] For example, the first type of signal may include data signals to be input to the third circuit. The second type of signal may include control signals corresponding to the third circuit.

[0229] For example, the first SERDES circuit may include a buffer for storing bits received from the first and second circuits, wherein the bits correspond to each of the first, second, third, and fourth signal paths. The first SERDES circuit may include a controller configured to generate a sequence of bits to be included in a signal to be transmitted to the second die via the first TSV by performing serialization on the bits stored in the buffer.

[0230] For example, the first SERDES circuit can be configured to store bits obtained from the first and second circuits into a buffer within a preset time interval. The first SERDES circuit can be configured to perform serialization of the bits stored in the buffer based on the expiration of the preset time interval.

[0231] For example, the first circuit may correspond to a central processing unit (CPU) circuit, and the second circuit may correspond to a graphics processing unit (GPU) circuit.

[0232] For example, the third circuit can correspond to an image signal processor (ISP) circuit. The fourth circuit can correspond to a display control circuit.

[0233] For example, the interconnect layer may include a second TSV connected to a second signal pin of a CPU circuit, wherein the CPU circuit includes a first signal pin connected to a first SERDES circuit. The ISP circuit may include a third signal pin electrically connected to the second TSV.

[0234] For example, the CPU circuit can be configured to send a control signal to the first SERDES circuit via a first signal pin for requesting data from the ISP circuit. The CPU circuit can be configured to receive data corresponding to the control signal from the ISP circuit via a second signal pin connected to the second TSV.

[0235] For example, the third circuit may correspond to a memory interface circuit for communicating with a memory connected to the processing chip assembly. The fourth circuit may correspond to a neural processing unit (NPU) circuit.

[0236] For example, the second SERDES circuit can be configured to generate a signal to be transmitted to the first SERDES circuit via the first TSV based on the serialization of signals sent from the third and fourth circuits.

[0237] For example, the second SERDES circuit can be configured to receive from the third circuit a signal for informing the first circuit, which is a central processing unit (CPU), of at least one of the states of the third circuit or an interrupt associated with the third circuit.

[0238] For example, the second SERDES electronic component can be configured to obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path based on the number of bits of each of the multiple bits in the signal transmitted through the first TSV, according to the deserialization.

[0239] For example, the first die can be configured to include circuit elements with dimensions smaller than the minimum dimension of the circuit elements included in the second die.

[0240] For example, the first SERDES circuit can be configured to transmit signals obtained based on serialization and encoded based on the biphase mark decoding (BMC) scheme to the second SERDES circuit via the first TSV.

[0241] For example, a first TSV can be configured to transmit signals within a first data rate range including 300 kbps. The interconnect layer can include a second TSV configured to transmit signals within a second data rate range exceeding the first data rate range.

[0242] For example, the interconnect layer may include redundant TSVs. The interconnect layer may include a first switching circuit configured to connect one end of a first TSV or a redundant TSV to a first SERDES circuit. The interconnect layer may be configured to include a second switching circuit configured to connect the other end of a first TSV or a redundant TSV to a second SERDES circuit.

[0243] For example, the first circuit can be configured to transmit a first type of signal, including data, to the third circuit via a second TSV included in the interconnect layer. The first circuit can also be configured to transmit a second type of signal to a first SERDES circuit for controlling a controller included in the third circuit, thereby transmitting the second type of signal via a third signal path.

[0244] For example, the first SERDES circuit can be configured to transmit signals based on general purpose input / output (GPIO) to the second SERDES circuit via the first TSV.

[0245] As described above, according to an embodiment, a processing chip assembly may include a first die including a first circuit and a second circuit, and a first SERDES circuit connected to the first and second circuits. The processing chip assembly may include a second die including a third circuit and a fourth circuit, and a second SERDES circuit connected to the third and fourth circuits. The processing chip assembly may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the first circuit to the third circuit and configured to transmit a first type of signal from the first circuit to the third circuit. The interconnect layer may include a second TSV configured to connect the first SERDES circuit to the second SERDES circuit and configured to serialize and transmit a second type of signal based on the first SERDES circuit. The second type of signal transmitted via the second TSV may include a sequence of at least one bit provided by the first circuit and at least one bit provided by the second circuit.

[0246] As described above, according to an embodiment, an electronic device may include a memory and a processor. The processor may include a first die comprising a plurality of circuits and a first serializer-deserializer (SERDES) circuit, the plurality of circuits including a central processing unit (CPU), the first SERDES circuit being coupled to each of the plurality of circuits. The processor may include a second die comprising memory interface circuitry for communicating with the memory and a second SERDES circuitry. The processor may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through-silicon via (TSV) configured to directly connect the CPU of the first die to the memory interface circuitry. The interconnect layer may include a second TSV configured to connect the first SERDES circuitry to the second SERDES circuitry. The CPU may be configured to send data signals, including data to be stored in the memory, to the memory interface circuitry via the first TSV. The CPU may be configured to send control signals to the first SERDES circuitry for controlling the memory interface circuitry, such that data is sent to the memory.

[0247] In a first example, a processing chip assembly is provided, comprising: a first die including a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first and second circuits; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third and fourth circuits; and an interconnect layer disposed between the first die and the second die, wherein the interconnect layer includes a first through-silicon via (TSV) configured to connect between the first and second SERDES circuits and provide: a first signal path between the first and third circuits, a second signal path between the first and fourth circuits, a third signal path between the second and third circuits, and a fourth signal path between the second and fourth circuits.

[0248] In the second example, a processing chip component of the first example is provided, wherein a first SERDES circuit is configured to: perform serialization on a signal transmitted from a first circuit together with a signal transmitted from a second circuit, and transmit the signal obtained based on the serialization to a second SERDES circuit via a first TSV; and wherein the second SERDES circuit is configured to obtain a signal to be transmitted to at least one of a third circuit and a fourth circuit based on the deserialization of the signal transmitted via the first TSV.

[0249] In the third example, a processing chip assembly of the first or second example is provided, wherein the interconnect layer further includes a second TSV connecting the first circuit to the third circuit; wherein the first circuit is configured to: send a first type of signal to the third circuit via the second TSV in the interconnect layer, and send a second type of signal to the first SERDES circuit via the first TSV to send the second type of signal to the third circuit.

[0250] In the fourth example, a processing chip assembly of the third example is provided, wherein the second TSV provides a fifth signal path between the first circuit and the third circuit, and wherein the fifth signal path does not include the first SERDES circuit and does not include the second SERDES circuit.

[0251] In the fifth example, a processing chip component of the third or fourth example is provided, wherein the first type of signal includes a data signal to be input to the third circuit, and wherein the second type of signal includes a control signal corresponding to the third circuit.

[0252] In the sixth example, a processing chip component of any of the second to fifth examples is provided, wherein the first SERDES circuitry includes: a buffer for storing bits received from the first and second circuits, wherein each bit corresponds to at least one of a first signal path, a second signal path, a third signal path, or a fourth signal path; and a controller configured to generate a sequence of bits to be included in a signal to be transmitted to the second die via the first TSV by performing serialization on the bits stored in the buffer.

[0253] In the seventh example, a processing chip component of the sixth example is provided, wherein the first SERDES circuit is configured to: store bits obtained from the first circuit and the second circuit into a buffer within a preset time interval; and perform serialization of the bits stored in the buffer based on the expiration of the preset time interval.

[0254] In the eighth example, a processing chip component of any one of the first to seventh examples is provided, wherein the first circuitry includes a central processing unit (CPU) circuitry; and wherein the second circuitry includes a graphics processing unit (GPU) circuitry.

[0255] In the ninth example, a processing chip assembly of the eighth example is provided, wherein the third circuitry includes an image signal processor (ISP) circuitry; and wherein the fourth circuitry includes a display control circuitry.

[0256] In the tenth example, a processing chip assembly of the ninth example is provided, wherein the interconnect layer includes: a second TSV, a second signal pin connected to a CPU circuit, wherein the CPU circuit includes a first signal pin connected to a first SERDES circuit; and wherein the ISP circuit includes a third signal pin electrically connected to the second TSV.

[0257] In the eleventh example, a processing chip assembly of the tenth example is provided, wherein the CPU circuit is configured to: send a control signal to a first SERDES circuit via a first signal pin for requesting data from an ISP circuit, and receive data corresponding to the control signal from the ISP circuit via a second signal pin connected to a second TSV.

[0258] In the twelfth example, a processing chip assembly of the eighth example is provided, wherein the third circuitry includes a memory interface circuitry for communicating with a memory connected to the processing chip assembly; and wherein the fourth circuitry includes a neural processing unit (NPU) circuitry.

[0259] In the thirteenth example, a processing chip component of any one of the first to twelfth examples is provided, wherein the second SERDES circuit is configured to generate a signal to be transmitted to the first SERDES circuit via the first TSV based on the serialization of signals sent from the third and fourth circuits.

[0260] In the fourteenth example, a processing chip assembly of the thirteenth example is provided, wherein the first circuitry includes a central processing unit (CPU); and wherein the second SERDES circuitry is configured to receive from the third circuitry a signal for informing the first circuitry of at least one of the status of the third circuitry or an interrupt associated with the third circuitry.

[0261] In the fifteenth example, a processing chip assembly according to any one of the first to fourteenth examples is provided, wherein the second SERDES circuit is configured to: obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path based on the number of bits of each of the plurality of bits in the signal transmitted through the first TSV, according to the deserialization.

[0262] In the sixteenth example, a processing chip assembly of any of the first to fifteenth examples is provided, wherein the first die is configured to include circuit elements with a size smaller than the smallest size of the circuit elements included in the second die.

[0263] In the seventeenth example, a processing chip assembly of any one of the first to sixteenth examples is provided, wherein the first die includes circuitry manufactured by a process capable of implementing circuitry elements based on a first minimum linewidth; wherein the second die includes circuitry manufactured by a process capable of implementing circuitry elements based on a second minimum linewidth; and wherein the second minimum linewidth is greater than the first minimum linewidth.

[0264] In the eighteenth example, a processing chip component of any one of the first to seventeenth examples is provided, wherein the first SERDES circuit is configured to transmit a signal obtained based on serialization and encoded based on a biphasic marker coding (BMC) scheme to the second SERDES circuit via a first TSV.

[0265] In the nineteenth example, a processing chip assembly of any one of the first to eighteenth examples is provided, wherein the power state of at least one of the first SERDES circuit and the second SERDES circuit is controlled independently of the power state of the CPU included in the processing chip assembly.

[0266] In the twentieth example, a processing chip assembly of any one of the first to nineteenth examples is provided, wherein the interconnect layer includes an auxiliary TSV configured to connect between the first SERDES circuit and the second SERDES circuit, and configured to provide: an auxiliary first signal path between the first circuit and the third circuit, an auxiliary second signal path between the first circuit and the fourth circuit, an auxiliary third signal path between the second circuit and the third circuit, and an auxiliary fourth signal path between the second circuit and the fourth circuit.

[0267] In the twenty-first example, a processing chip assembly of the twenty-first example is provided, wherein a first die includes a first switching circuit; wherein a second die includes a second switching circuit; and wherein the first switching circuit and the second switching circuit are configured to control the connection between a first SERDES circuit and a second SERDES circuit by switching the connection between a first TSV and an auxiliary TSV.

[0268] In the twenty-second example, a processing chip component of any one of the first to twenty-first examples is provided, wherein the interconnect layer includes a plurality of TSVs; wherein the first SERDES circuit example includes: a first protocol circuit configured to support a first communication protocol; a second protocol circuit configured to support a second communication protocol; and a first multiplexer switching circuit configured to connect the plurality of TSVs to the first protocol circuit and the second protocol circuit; wherein the second SERDES circuit includes: a third protocol circuit configured to support the first communication protocol; a fourth protocol circuit configured to support the second communication protocol; and a second multiplexer switching circuit configured to connect the plurality of TSVs to the third protocol circuit and the fourth protocol circuit; and wherein the first multiplexer switching circuit and the second multiplexer switching circuit are configured to: select a communication protocol, establish a connection between the first protocol circuit and the third protocol circuit via the plurality of TSVs when the first communication protocol is selected, and establish a connection between the second protocol circuit and the fourth protocol circuit via the plurality of TSVs when the second communication protocol is selected.

[0269] The apparatus described above can be implemented using hardware components, software components, and / or combinations of hardware and software components. For example, the apparatus and components described in the embodiments can be implemented using one or more general-purpose or special-purpose computers, such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of executing and responding to instructions. The processing apparatus can execute an operating system (OS) and one or more software applications executing on the operating system. Additionally, the processing apparatus can access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, only one processing apparatus is described as being used; however, those skilled in the art will recognize that a processing apparatus can include multiple processing elements and / or various types of processing elements. For example, a processing apparatus can include multiple processors or one processor and one controller. Furthermore, another processing configuration, such as a parallel processor, is also possible.

[0270] Software may include computer programs, code, instructions, or combinations thereof, and may configure a processing device to operate as needed or to independently or jointly command the processing device. Software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or apparatus to be interpreted by the processing device or to provide commands or data to the processing device. Software may be distributed across network-connected computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0271] The method according to the embodiments can be implemented in the form of program instructions that can be executed by various computer means and recorded on a computer-readable medium. In this case, the medium can continuously store a computer-executable program or can temporarily store the program for execution or download. Furthermore, the medium can be various recording or storage means in the form of a single piece of hardware or a combination of several pieces of hardware, but is not limited to a medium directly connected to a computer system, and can be distributed over a network. Examples of the medium may include media that can be configured to store program instructions, including magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floppy disks; and ROM, RAM, flash memory, etc. Additionally, other examples of the medium may include recording or storage media managed by application stores that distribute applications, sites that provide or distribute various software, servers, etc.

[0272] As described above, although embodiments have been described with limited examples and figures, those skilled in the art can make various modifications and variations based on the above description. For example, suitable results can be achieved even if the described techniques are performed in a different order than the described methods, and / or the components of the described systems, structures, devices, circuits, etc. are coupled or combined in a different form than the described methods, or are replaced or substituted by other components or equivalent forms.

[0273] Therefore, other implementations, other embodiments, and those embodiments equivalent to the scope of the claims are within the scope of the claims described later.

Claims

1. A processing chip assembly, the processing chip assembly comprising: The first die includes a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first circuit and the second circuit. The second die includes a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; as well as An interconnect layer is disposed between the first die and the second die. The interconnect layer includes a first through-silicon via (TSV), which is configured to connect between the first SERDES circuit and the second SERDES circuit and provides: The first signal path between the first circuit and the third circuit. The second signal path between the first circuit and the fourth circuit The third signal path between the second circuit and the third circuit, and The fourth signal path between the second circuit and the fourth circuit.

2. The processing chip assembly according to claim 1, wherein, The interconnect layer also includes a second TSV that connects the first circuit to the third circuit. The first circuit is configured as follows: The first type of signal is transmitted to the third circuit via the second TSV in the interconnect layer. The second type of signal is transmitted to the first SERDES circuit in order to transmit the second type of signal to the third circuit. The first SERDES circuit is configured as follows: Serialization is performed on the second type of signal and the signal transmitted from the second circuit. The first TSV transmits the serialized signal to the second SERDES circuit. The second SERDES circuit is configured to obtain the second type of signal to be transmitted to the third circuit based on the deserialization of the signal transmitted through the first TSV.

3. The processing chip assembly according to claim 2, wherein, The first type of signal includes the data signal to be input to the third circuit. The second type of signal includes control signals corresponding to the third circuit.

4. The processing chip assembly according to claim 2, wherein, The first SERDES circuit includes: A buffer for storing bits received from the first circuit and the second circuit, wherein the bits correspond to each of the first signal path, the second signal path, the third signal path, and the fourth signal path; and A controller configured to generate a sequence of bits by performing serialization on the bits stored in the buffer, the sequence being included in a signal to be transmitted to the second die via the first TSV.

5. The processing chip assembly according to claim 4, wherein, The first SERDES circuit is configured as follows: The bits obtained from the first circuit and the second circuit are stored in the buffer within a preset time interval; The serialization of the bits stored in the buffer is performed upon the expiration of the preset time period.

6. The processing chip assembly according to claim 1, in, The first circuit corresponds to the central processing unit (CPU) circuit. The second circuit corresponds to the graphics processing unit (GPU) circuit.

7. The processing chip assembly according to claim 6, in, The third circuit corresponds to an image signal processor (ISP) circuit. The fourth circuit corresponds to the display control circuit, and The interconnection layer includes: A second TSV is connected to a second signal pin of the CPU circuit, wherein the CPU circuit includes a first signal pin connected to the first SERDES circuit. The ISP circuit includes a third signal pin electrically connected to the second TSV; and the CPU circuit is configured to: A control signal for requesting data from the ISP circuit is sent to the first SERDES circuit via the first signal pin. Data corresponding to the control signal is received from the ISP circuit via the second signal pin connected to the second TSV.

8. The processing chip assembly according to claim 6, in, The third circuit corresponds to a memory interface circuit for communicating with a memory connected to the processing chip assembly. The fourth circuit corresponds to the neural processing unit (NPU) circuit.

9. The processing chip assembly according to any one of the preceding claims, wherein, The second SERDES circuit is configured as follows: The signal to be transmitted to the first SERDES circuit via the first TSV is generated based on the serialization of the signals transmitted from the third circuit and the fourth circuit.

10. The processing chip assembly according to claim 9, wherein, The second SERDES circuit is configured as follows: The first circuit receives a signal from the third circuit for notifying the first circuit of at least one of the status of the third circuit or an interrupt associated with the third circuit, wherein the first circuit is a central processing unit (CPU).

11. The processing chip assembly according to any one of the preceding claims, wherein, The second SERDES circuit is configured as follows: Based on deserialization, at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path is obtained according to the number of bits of each of the multiple bits in the signal transmitted through the first TSV.

12. The processing chip assembly according to any one of the preceding claims, wherein, The first die is configured to include circuit elements whose dimensions are smaller than the smallest dimension of the circuit elements included in the second die.

13. The processing chip assembly according to any one of the preceding claims, wherein, The first SERDES circuit is configured as follows: The first TSV transmits a signal to the second SERDES circuit, which is obtained based on serialization and encoded based on the biphasic mark coding (BMC) scheme.

14. The processing chip assembly according to any one of the preceding claims, wherein, The interconnect layer includes an auxiliary TSV configured to connect between the first SERDES circuit and the second SERDES circuit, and configured to provide: An auxiliary first signal path between the first circuit and the third circuit. An auxiliary second signal path between the first circuit and the fourth circuit. An auxiliary third signal path between the second circuit and the third circuit, and An auxiliary fourth signal path between the second circuit and the fourth circuit; The first die includes a first switching circuit; The second die includes a second switching circuit; and The first switching circuit and the second switching circuit are configured to control the connection between the first SERDES circuit and the second SERDES circuit by switching the connection between the first TSV and the auxiliary TSV.

15. The processing chip assembly according to any one of the preceding claims, wherein, The interconnection layer includes multiple TSVs. The first SERDES circuit includes: A first protocol circuit, configured to support a first communication protocol. A second protocol circuit, configured to support a second communication protocol, and A first multiplexer switching circuit is configured to connect the plurality of TSVs to the first protocol circuit and the second protocol circuit. The second SERDES circuit includes: A third protocol circuit, configured to support the first communication protocol. A fourth protocol circuit, configured to support the second communication protocol, and A second multiplexer switching circuit is configured to connect the plurality of TSVs to the third protocol circuit and the fourth protocol circuit; and The first multiplexer switching circuit and the second multiplexer switching circuit are configured as follows: Select the communication protocol. When the first communication protocol is selected, a connection is established between the first protocol circuit and the third protocol circuit via the plurality of TSVs, and When the second communication protocol is selected, a connection is established between the second protocol circuit and the fourth protocol circuit via the plurality of TSVs.

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