IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD AND PROGRAM FOR IMAGE PROCESSING APPARATUS

Abstract

To generate a plurality of seed values in a short time such that respective pseudo-random number sequences for image processing of a plurality of blocks obtained by dividing an image do not collide with each other on the basis of one seed value.SOLUTION: An image processing device comprises: seed value generation means 105 which generates a plurality of seed values for a plurality of blocks obtained by dividing an image on the basis of one seed value; pseudo-random number generation means 102 which generates a pseudo-random number sequence of each of the plurality of blocks on the basis of the plurality of seed values for the plurality of blocks; and image processing means 101 which performs image processing on each of the plurality of blocks obtained by dividing the image by using the pseudo-random number sequence of each of the plurality of blocks. The seed value generation means generates the plurality of pseudo-random numbers skipping by a prescribed number in the pseudo-random number sequence generated on the basis of the one seed value by the pseudo-random number generation means as the plurality of seed values.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an image processing device, an image processing method for the image processing device, and a program. [Background technology]

[0002] Random numbers are sometimes required when performing image processing using computers or logic circuits. There are two main types of random numbers: true random numbers, which are generated by observing physical phenomena, and pseudorandom numbers, which use a specific algorithm to output values ​​that appear random.

[0003] Although pseudorandom numbers are not truly random, their algorithm is fixed, so it is easier to check the quality of the random numbers than true random numbers. For example, the quality of random numbers can be checked using statistical random number testing methods, such as NIST SP800-22. Therefore, if you can confirm that the quality is suitable for your purpose, there is no problem in using pseudorandom numbers instead of true random numbers.

[0004] Another advantage of pseudorandom numbers is that they are reproducible. Reproducibility is the ability to generate the same pseudorandom number sequence again. Therefore, if you need to use the same random number sequence multiple times, you would need to store the entire sequence in the case of true random numbers, whereas with pseudorandom numbers you only need to regenerate them.

[0005] There are two main types of pseudorandom numbers: those that can be used for encryption, and those that are general purpose. Pseudorandom numbers that can be used for encryption have high quality random numbers, but the speed at which they are generated is usually slow. Since image processing does not require high quality random numbers, pseudorandom numbers for encryption purposes are not usually used in image processing, and general, simple pseudorandom numbers are used instead.

[0006] One of the simple pseudorandom number algorithms is the linear feedback shift register. The linear feedback shift register does not have the quality to be used for encryption as it is, but it can be used alone for general random number applications such as image processing. Another example of the pseudorandom number algorithm is the Xorshift (for example, see Non-Patent Document 1).

[0007] For example, Patent Document 1 describes a method for enlarging an image by adding pixels to an input image and using pseudo-random numbers to scatter the added locations, thereby making the points at which the image pattern changes due to the added pixels less noticeable.

[0008] Patent Document 2 describes a method of preventing a plurality of pseudo-random number generating circuits from generating the same random numbers by setting different seed values ​​(initial values) for the plurality of pseudo-random number generating circuits.

[0009] Patent Document 3 describes a method of setting the same initial value to multiple pseudo-random number generating circuits, but generating different pseudo-random numbers by changing the position from which the pseudo-random numbers are extracted from the pseudo-random number sequence for each pseudo-random number generating circuit.

[0010] Patent Documents 4 and 5 disclose methods for calculating the value of a linear feedback shift register when the phase of the shift register is arbitrarily advanced. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Patent No. 6066955 [Patent Document 2] Japanese Patent Application Publication No. 5-206793 [Patent Document 3] JP 2009-151429 A [Patent Document 4] JP 2003-345246 A [Patent Document 5] Japanese Patent Application Publication No. 11-4144 [Non-patent literature]

[0012] [Non-Patent Document 1] Marsaglia, "Xorshift RNGs" (2003) Summary of the Invention [Problem to be solved by the invention]

[0013] However, in the method of Patent Document 3, when dividing an image into a plurality of blocks and generating pseudo-random numbers for each block, it is necessary to generate a large number of pseudo-random numbers in a pseudo-random number sequence. In addition, Patent Documents 4 and 5 describe a method of advancing a phase, but do not disclose a circuit configuration required for image processing in which an image is divided into a plurality of blocks, such as how to hold a plurality of seed values ​​or the timing of generating the seed values.

[0014] The object of the present invention is to make it possible to generate multiple seed values ​​in a short period of time based on a single seed value, such that the pseudo-random number sequences for image processing of each of the multiple blocks into which an image is divided do not collide. [Means for solving the problem]

[0015] An image processing device of the present invention has a seed value generation means for generating a plurality of seed values ​​for a plurality of blocks obtained by dividing an image based on one seed value, a pseudo-random number generation means for generating a pseudo-random number sequence for each of the plurality of blocks based on the plurality of seed values ​​for the plurality of blocks, and an image processing means for image processing each of the plurality of blocks obtained by dividing the image using the pseudo-random number sequence for each of the plurality of blocks, and the seed value generation means generates a plurality of pseudo-random numbers, which are skipped by a predetermined number from the pseudo-random number sequence generated by the pseudo-random number generation means based on the one seed value, as the plurality of seed values. and changing the predetermined number by changing some bits of one of the plurality of seed values ​​to other bits. do. Effect of the Invention

[0016] According to the present invention, multiple seed values ​​can be generated in a short time based on one seed value, so that the pseudo-random number sequences for image processing of each of the multiple blocks into which an image is divided do not collide. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 illustrates an example of the configuration of an image processing device. [Diagram 2] FIG. 2 illustrates an example of the configuration of a pseudo-random number generating unit; [Diagram 3] FIG. 13 is a diagram showing the transition of values ​​in a shift register. [Figure 4] FIG. 13 is a diagram illustrating the process contents of a seed value generating unit. [Diagram 5] 13 is a diagram for explaining the processing content of a pseudo-random number sequence skip unit. FIG. [Figure 6] FIG. 13 is a diagram illustrating an example of the configuration of a pseudo-random number sequence skip unit. [Figure 7] FIG. 2 illustrates an example of the configuration of a pseudo-random number generating unit; [Figure 8] 13 is a diagram for explaining the processing content of a pseudo-random number sequence skip unit. FIG. [Figure 9] 1 is a flowchart illustrating a pseudorandom number generation method of Xorshift. [Figure 10] FIG. 2 illustrates an example of the configuration of a pseudo-random number generating unit; [Figure 11] FIG. 1 is a diagram illustrating an example of the configuration of a linear feedback shift register. [Figure 12] FIG. 13 is a diagram illustrating an example of dividing an input image into a plurality of blocks. [Figure 13] FIG. 13 is a diagram showing pixel insertion positions. [Figure 14] FIG. 13 is a diagram showing pixel insertion positions. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 11 is a circuit diagram showing an example of the configuration of a linear feedback shift register that generates pseudorandom numbers. Each register of the shift register 1101 holds one bit, so that it can hold five bits in total. When one bit is input from the left, the bit held by the shift register is shifted by one. An exclusive-OR calculator 1102 inputs several bits of the shift register 1101, and outputs one bit of the result of the exclusive-OR of the input bits. Each time the shift register 1101 shifts once, one bit of the pseudorandom number is output.

[0019] The period of the pseudorandom numbers generated by the linear feedback shift register is configured to be maximum. The period of the pseudorandom numbers depends on the number of bits that the shift register 1101 can hold and the bits input to the exclusive OR calculator 1102. If the number of bits in the shift register 1101 is N, the number of bit states that the shift register 1101 can express is 2 N However, if all the bits of the shift register 1101 are 0, the bits of the shift register 1101 always become 0. Therefore, excluding this one pattern, the number of bit states that the shift register 1101 can express is 2 N -1. Therefore, 2 N The input to the exclusive OR operator 1102 is a bit state represented by the shift register 1101 with a period of 2 N -1. This also ensures that the pseudorandom number period is 2 N It will be -1.

[0020] Pseudo-random numbers can be used in image processing. Pseudo-random numbers can be used in image processing to make moire and changes in image patterns that occur due to enlargement / reduction processing or halftone processing performed on image data less noticeable. For example, pixels are added to an input image in order to perform image enlargement processing. Normally, when pixels are added, the image pattern changes at the location where the pixels are added. Therefore, if the pixel addition points are fixed at all times, the points of change in the image pattern that occur at the locations where the pixels are added will be concentrated in one place and will stand out. Therefore, by using pseudo-random numbers to spread out the addition points, the points of change in the image pattern due to the addition of pixels can be made less noticeable.

[0021] Fig. 12 is a diagram showing an example of dividing an input image into multiple blocks. By performing image processing for each block, it is possible to process multiple blocks in parallel and change the magnification ratio for each block. However, in order to perform image processing for each block, it is also necessary to generate pseudo-random numbers for each block.

[0022] Fig. 13 is a diagram showing an example of pixel insertion positions when pixels are inserted using the same pseudo-random numbers for each block in Fig. 12. If the same seed value (initial value) is used for each block and the same pseudo-random number sequence is generated for each block, pixels will be inserted at the same positions in all blocks. Since pixels are inserted at the same positions in all blocks, changes in the image pattern occur periodically, which may be recognized as a pattern.

[0023] For this reason, it is better to use a different pseudo-random number sequence for each block. By setting different seed values ​​(initial values) for multiple pseudo-random number generators, it is possible to prevent the multiple pseudo-random number generators from generating the same random numbers. However, even if a different seed value is set for each block, the pseudo-random number sequences of multiple blocks may partially collide, because the period of the pseudo-random number sequence is finite.

[0024] Fig. 14 is a diagram showing an example of pixel insertion positions when pseudo-random number sequences of multiple blocks partially collide. Since the pseudo-random number sequences of multiple blocks partially collide, the pixel insertion positions of the multiple blocks partially overlap. Therefore, the same pattern occurs at the overlapping points of the multiple blocks. This causes the image pattern to change periodically, which may be recognized as a pattern.

[0025] In order to reliably avoid partial collisions of pseudo-random number sequences as described above, for example, the same initial value is set in multiple pseudo-random number generating circuits, but the position from which the pseudo-random numbers are extracted from the pseudo-random number sequence is changed for each pseudo-random number generating circuit, thereby avoiding collisions of pseudo-random numbers.

[0026] However, when there are many blocks, the amount of calculation required to generate pseudorandom numbers increases. For example, if there are 1,000 blocks, it is necessary to generate 1,000 pseudorandom numbers of the pseudorandom number sequence to extract one pseudorandom number from the pseudorandom number sequence. In image processing, a pseudorandom number may be required for each pixel, so it is necessary to generate pseudorandom numbers with a small amount of calculation while preventing collisions between pseudorandom numbers between blocks.

[0027] Another method for avoiding collisions is to store multiple seed values ​​that do not collide in advance and generate a pseudorandom number sequence using the stored seed values ​​before the start of image processing. However, if all the seed values ​​that do not collide are generated in advance and stored externally, the number of circuits required to store the seed values ​​externally will increase, and it will take time to write the seed values ​​stored externally to the image processing circuit. For example, if there are 1,000 seeds, 1,000 external storage circuits will be required, and if it takes 100 cycles to write each seed value to the image processing circuit, it will take 100,000 cycles to write all the seed values.

[0028] In order to solve the above problem, an embodiment is described below in which pseudo-random number generation during image processing of each block can be performed in a short time without the need to set seed values ​​for each of multiple blocks from the outside.

[0029] (First embodiment) 1 is a diagram showing an example of the configuration of an image processing device 100 according to the first embodiment. The image processing device 100 includes an image processing circuit 101, a pseudo-random number generating unit 102, a plurality of seed value holding units 103, a seed value setting unit 104, a seed value generating unit 105, and a pseudo-random number sequence skip unit 106. An image processing method of the image processing device 100 will be described below.

[0030] The image processing circuit 101 performs image processing that requires pseudo-random numbers, such as image enlargement / reduction processing. The image processing circuit 101 receives an input image, divides the input image into a plurality of blocks, performs image processing on each block, and outputs an output image.

[0031] The pseudo-random number generator 102 has a linear feedback shift register and generates a pseudo-random number sequence. The seed value holders 103 each hold a seed value of a pseudo-random number sequence required for image processing of a plurality of blocks of an input image. For example, when the image processing circuit 101 divides an input image into a maximum of 1024 blocks, the seed value holders 103 are configured with 1024 units.

[0032] The seed value setting unit 104 sets a seed value in any one of the multiple seed value holding units 103. This seed value is a seed value required for one of the multiple blocks. When the seed value generation unit 105 confirms that the seed value setting unit 104 has written a seed value in any one of the multiple seed value holding units 103, the seed value generation unit 105 generates seed values ​​required for other blocks based on the seed value, and writes the seed values ​​in the other seed value holding units 103. The pseudo-random number sequence skip unit 106 is used by the seed value generation unit 105 to generate a seed value.

[0033] Fig. 2 is a diagram showing an example of the configuration of the pseudorandom number generating unit 102 in Fig. 1. The pseudorandom number generating unit 102 is configured, for example, with a Fibonacci linear feedback shift register. The pseudorandom number generating unit 102 has a shift register 201 and an exclusive OR operator 202.

[0034] Shift register 201 is composed of a 31-bit register, and when one bit is input from the left, the bits in all registers are shifted one bit to the right, and the bit that overflows from the right is output as a pseudo-random number. Exclusive-OR calculator 202 inputs the output bit of shift register 201 and bits of some of the 31-bit registers of shift register 201. Exclusive-OR calculator 202 then outputs one bit to the first-stage register of shift register 201 as the result of the exclusive-OR of the input bits. In this way, pseudo-random number generator 102 can generate 31-bit pseudo-random numbers.

[0035] 3 is a diagram showing the transition of the bit value of the shift register 201 when the Fibonacci linear feedback shift register implemented in the pseudo-random number generator 102 is operated. The seed value 301 represents the initial value of the shift register 201. The transition value 302 represents the transition of the bit value of the shift register 201 when the random number is generated once, twice, three times, ..., twice. 31 The transition value 303 is a value that is a 2-bit value, and the transition value 304 is a value that is a 1-bit value. 31 -1st transition value, but 2 31 The transition value 304 is the same as the seed value 301 for the first time at the -1st iteration. 31 The shift register 201 generates a periodic value, and the seed value 301 and the transition value 302 represent the second and subsequent transition values. 31 Generate a sequence of numbers with one period consisting of -1 value repeatedly.

[0036] Since the shift register 201 is a 31-bit register, the number of numbers that the shift register 201 can represent is 2 31However, if all bits are 0, the bit value does not change, so it cannot be used to generate random numbers, and the actual upper limit is 2 31 In addition, the length of one period of the bit value transition of the shift register 201 is also 2 31 In other words, Fig. 3 shows the number of 31 The shift register 201 can take two values ​​before reaching the −1st transition value 303. 31 This represents going through all the -1 values ​​and then returning to the first value.

[0037] From the above, we can see the following: No matter what seed value 301 is selected, the shift register 201 will have either the seed value 301 or the transition value 302, so the random number sequence will only be generated in the order shown in FIG.

[0038] That is, the following can be seen regarding the seed value 301. First, if the two seed values ​​are the same, the same transition will result, and the same pseudo-random number sequence will be generated. Also, even if the two seed values ​​are different, if two close values ​​are used as seed values ​​in the sequence represented by the seed value 301 and the transition value 302, the pseudo-random number sequences generated will partially match. Note that using two close values ​​as seed values ​​means that the distance between the seed values ​​is shorter than the number of pseudo-random numbers required for image processing of each block.

[0039] In image processing, if such a collision of pseudo-random number sequences occurs, the image processing results of each block may partially match, which may be recognized as a pattern.

[0040] In order to avoid this, the present embodiment aims to prevent collisions between the pseudo-random number sequences of each block by setting the intervals between the seed values ​​of each block to values ​​that are sufficiently separated on the sequence indicated by the seed value 301 and the transition value 302. Setting the intervals between the seed values ​​of each block to values ​​that are sufficiently separated means setting values ​​that are spaced apart wider than the maximum number of pseudo-random numbers required for image processing of each block. For example, if a maximum of 1 million pseudo-random numbers are required for each block, collisions can be prevented by setting the intervals between the seed values ​​of each block to 2 million.

[0041] Fig. 4 is a flowchart showing a processing method of the seed value generation unit 105 in Fig. 1. In step S401, the seed value setting unit 104 writes a 31-bit seed value into any one of the multiple seed value holding units 103. The seed value generation unit 105 waits until the seed value setting unit 104 finishes writing the 31-bit seed value, and proceeds to step S402 when the process is finished.

[0042] In step S402, the seed value generation unit 105 reads the 31-bit seed value written in step S401 in the seed value holding unit 103. Next, in step S403, the seed value generation unit 105 instructs the pseudo-random number sequence skip unit 106 to execute processing, and obtains a seed value for the next block. Next, in step S404, the seed value generation unit 105 writes the seed value obtained in step S403 into another one of the multiple seed value holding units 103.

[0043] Next, in step S405, the seed value generation unit 105 determines whether or not all necessary seed values ​​have been written to all seed value holding units 103. If all seed values ​​have not been written, the seed value generation unit 105 returns to step S403 and repeats the processing of seed values ​​of other blocks, and if all seed values ​​have been written, ends the processing of the flowchart in Fig. 4. In this way, the seed value generation unit 105 can cause multiple seed values ​​corresponding to multiple blocks of the input image to be held in multiple seed value holding units 103.

[0044] FIG. 5 is a diagram for explaining the processing method of the pseudo-random number sequence skip unit 106 in FIG. 1. FIG. 5 shows the processing contents calculated by the pseudo-random number sequence skip unit 106. The pseudo-random number sequence skip unit 106 is a circuit that outputs a value obtained by shifting the bit value of the linear feedback shift register of the pseudo-random number generation unit 102 shown in FIG. 2 a predetermined number of times. For example, the pseudo-random number sequence skip unit 106 is implemented to output a value after shifting 2 million times. An input value 501 is an initial 31-bit value of the linear feedback shift register of the pseudo-random number sequence skip unit 106. An exclusive OR calculator 502 performs the same processing as the exclusive OR calculator 202 in FIG. 2. A transition value 503 represents the same value as the result of shifting the bits of the shift register 201 of the pseudo-random number generation unit 102 shown in FIG. 2. The output value 504 is the bit value after the bit value of the linear feedback shift register of the pseudo-random number sequence skip unit 106 has been shifted and the transition value 503 has been generated 2 million times.

[0045] 5, it can be seen that the only operation between the input value 501 and the output value 504 is the exclusive OR operator 502. In other words, the equation expressing each bit value of the output value 504 can be expressed only by each bit of the input value 501 and the operation of the exclusive OR operator 502.

[0046] An equation consisting only of the operation of the exclusive OR calculator 502 can be transformed into a simpler equation by modifying the equation. The operation of the exclusive OR calculator 502 is commutative and associative, so the order of calculations can be changed as desired. Furthermore, when an even number of identical values ​​are collected and an exclusive OR is calculated, the result is 0. And, since the exclusive OR of a certain value and 0 does not change the value, 0 can be ignored. In other words, all bit values ​​that appear an even number of times in the equation can be ignored. Similarly, all bit values ​​that appear an odd number of times in the equation can be ignored except for one. In other words, the equation for calculating each bit value of the output value 504 can be reduced to an equation that only requires the exclusive OR of several selected bit values ​​of the input value 501 without duplication.

[0047] Fig. 6 is a diagram showing an example of the configuration of the pseudo-random number sequence skip unit 106 in Fig. 1. The pseudo-random number sequence skip unit 106 has 31 1-bit calculation units 601. Each of the 31 1-bit calculation units 601 has an exclusive OR operator 604.

[0048] The 1-bit calculation section 601 receives a 31-bit input value 602 and outputs a 1-bit output value 605. The 31 1-bit calculation sections 601 each calculate the 31 1-bit output values ​​605.

[0049] Input value 602 is a 31-bit input value. Mask 603 selects only some bits from the 31-bit input value 602, outputs the selected bits to exclusive-or calculator 604, and sets the other bits to 0 and outputs them to exclusive-or calculator 604. Exclusive-or calculator 604 calculates the exclusive-or of the bit values ​​output by mask 603, and outputs the calculation result as 1-bit output value 605.

[0050] When the bits selected by the mask 603 are fixed, the mask 603 may simply be a connection, and the exclusive-OR calculator 604 may calculate the exclusive-OR of only the bits connected by the mask 603. As another example of the configuration of the mask 603, the bits selected by the mask 603 may be changed from the outside, so that the interval between each seed value can be changed.

[0051] As another example of the configuration of the mask 603, the mask 603 and the exclusive OR calculator 604 can be configured to process one bit at a time, and 31 cycles can be taken to calculate a one-bit output value 605. In this case, the number of cycles required for the calculation by the pseudo-random number sequence skip unit 106 increases, but the circuit scale can be further reduced.

[0052] 6, the pseudo-random number sequence skip unit 106 is configured with 31 1-bit calculation units 601, but as another configuration example, it may be configured with only one 1-bit calculation unit 601. In this configuration, the process of the 1-bit calculation unit 601 is repeatedly executed 31 times, whereby a 31-bit output value 605, which is the same result as in FIG. 6, can be calculated.

[0053] As described above, the seed value setting unit 104 writes the 31-bit seed value of the first block to the first seed value holding unit 103 among the multiple seed value holding units 103. After that, the seed value generation unit 105 reads the 31-bit seed value of the first block from the first seed value holding unit 103. Then, the seed value generation unit 105 outputs the 31-bit seed value of the first block to the pseudo-random number sequence skip unit 106, and instructs it to calculate the 31-bit seed value of the second block. As shown in FIG. 5, the pseudo-random number sequence skip unit 106 inputs the 31-bit seed value of the first block as an input value 501, and after 2 million bit shifts, outputs the seed value of the second block to the seed value generation unit 105 as an output value 504. The seed value generation unit 105 writes the seed value of the second block to the second seed value holding unit 103. The interval between the seed value of the first block and the seed value of the second block is 2 million times.

[0054] Next, the seed value generation unit 105 outputs the 31-bit seed value of the second block to the pseudo-random number sequence skip unit 106, and instructs it to calculate the 31-bit seed value of the third block. As shown in FIG. 5, the pseudo-random number sequence skip unit 106 inputs the 31-bit seed value of the second block as an input value 501, and after 2 million bit shifts, outputs the seed value of the third block to the seed value generation unit 105 as an output value 504. The seed value generation unit 105 writes the seed value of the third block to the third seed value holding unit 103. The interval between the seed value of the second block and the third seed value is 2 million times.

[0055] Similarly, the seed value generation unit 105 uses the pseudo-random number sequence skip unit 106 to write the 31-bit seed values ​​of all blocks to all seed value holding units 103. The interval between seed values ​​of adjacent blocks is 2 million times.

[0056] For the first block of the input image, the image processing circuit 101 reads out the seed value of the first block from the first seed value holding unit 103, outputs the seed value of the first block to the pseudo-random number generating unit 102, and instructs the pseudo-random number generation. Then, as shown in Fig. 3, the pseudo-random number generating unit 102 sets the seed value of the first block as the seed value 301 in the shift register 201, generates, for example, one million pseudo-random numbers, and outputs, for example, the one million pseudo-random numbers to the image processing circuit 101. The image processing circuit 101 performs image processing, such as image enlargement / reduction processing, on the first block of the input image using, for example, the one million pseudo-random numbers, and generates and stores an output image of the first block.

[0057] Next, for the second block of the input image, the image processing circuit 101 reads out the seed value of the second block from the second seed value holding unit 103, outputs the seed value of the second block to the pseudo-random number generating unit 102, and instructs the pseudo-random number generation. Then, as shown in Fig. 3, the pseudo-random number generating unit 102 sets the seed value of the second block as the seed value 301 in the shift register 201, generates, for example, one million pseudo-random numbers, and outputs, for example, the one million pseudo-random numbers to the image processing circuit 101. The image processing circuit 101 performs image processing, such as image enlargement / reduction processing, on the second block of the input image using, for example, the one million pseudo-random numbers, and generates and stores an output image of the second block.

[0058] Similarly, the image processing circuit 101 performs image processing using pseudo-random numbers on the third to the last blocks of the input image, and generates and stores output images of the third to the last blocks.Then, the image processing circuit 101 integrates the output images of all the blocks and outputs the integrated output image.

[0059] The pseudo-random number generator 102 can prevent collisions between pseudo-random number sequences in each block of the input image because the interval between seed values ​​of adjacent blocks is 2 million times. The image processing circuit 101 can, for example, prevent overlapping of pixel insertion positions in each block of the input image, and prevent the occurrence of patterns due to periodic changes in the image pattern.

[0060] As described above, the seed value setting unit 104 sets one seed value for one seed value holding unit 103. The seed value generating unit 105 uses the pseudo-random number sequence skip unit 106 to generate multiple seed values ​​for multiple blocks into which the input image is divided, based on the single seed value set by the seed value setting unit 104. The pseudo-random number generating unit 102 is a pseudo-random number generating unit, and generates a pseudo-random number sequence for each of the multiple blocks, based on the multiple seed values ​​for the multiple blocks. The image processing circuit 101 is an image processing unit, and performs image processing on each of the multiple blocks into which the input image is divided, using the pseudo-random number sequence for each of the multiple blocks.

[0061] The seed value generating unit 105 generates a plurality of pseudo-random numbers by skipping a predetermined number from the pseudo-random number sequence generated based on the one seed value by the pseudo-random number generating unit 102. The predetermined number is a number larger than the maximum number of pseudo-random numbers used by the image processing circuit 101 for image processing of each block.

[0062] The plurality of seed values ​​includes the one seed value. The seed value setting unit 104 writes the one seed value into one seed value holding unit 103. The seed value generating unit 105 writes the seed values ​​other than the one seed value out of the plurality of seed values ​​into the other seed value holding units 103.

[0063] The pseudo-random number generator 102 generates pseudo-random numbers by performing an exclusive-OR operation based on a seed value as shown in Fig. 2. The seed value generator 105 uses the pseudo-random number sequence skip unit 106 to perform an exclusive-OR operation on some bits of one of the multiple seed values ​​as shown in Fig. 6, thereby generating another of the multiple seed values.

[0064] The pseudo-random number sequence skip unit 106 has a plurality of 1-bit calculation units 601. Each of the plurality of 1-bit calculation units 601 is a bit operation unit, and performs an exclusive OR operation on some bits of one of the plurality of seed values ​​to generate one bit of another of the plurality of seed values.

[0065] The pseudo-random number sequence skip unit 106 may repeat the process of generating one bit of another of the plurality of seed values ​​by performing an exclusive OR operation on some bits of one of the plurality of seed values. Also, the pseudo-random number sequence skip unit 106 can change the predetermined number by changing some bits of one of the plurality of seed values ​​to other bits.

[0066] In this manner, in this embodiment, the seed value generation unit 105 can adjust the interval between seed values ​​held in the seed value holding unit 103. The maximum number of pseudo-random numbers that need to be generated for each seed value can be estimated based on the size of each block, etc., so by making the interval between seed values ​​wider than the maximum number, it is possible to prevent collisions between pseudo-random number sequences used in each block.

[0067] When the seed value setting unit 104 sets an initial seed value, the seed value generation unit 105 can automatically generate multiple seed values ​​that do not collide with each other in pseudo-random number sequences, using the pseudo-random number sequence skip unit 106. This eliminates the need to externally set seed values ​​for each of the multiple blocks into which the input image is divided, and allows pseudo-random numbers for image processing of each block to be generated in a short time.

[0068] Second Embodiment The image processing device 100 according to the second embodiment has the same configuration as that of the first embodiment shown in Fig. 1, but the pseudo-random number generating unit 102 is configured with a Galois linear feedback shift register. Even in the case of the Galois linear feedback shift register, the pseudo-random number sequence skip unit 106 can be realized with the configuration shown in Fig. 6 of the first embodiment.

[0069] FIG. 7 is a diagram showing an example of the configuration of the pseudorandom number generating unit 102 according to the second embodiment. The pseudorandom number generating unit 102 has a plurality of exclusive OR operators 701 and a shift register 702. The exclusive OR operator 701 inputs 2 bits and outputs a 1-bit result of the exclusive OR of the 2 input bits. The shift register 702 has 31 registers, each of which holds 1 bit, and the entire register holds a 31-bit value. However, several exclusive OR operators 701 are inserted between the 31-bit registers of the shift register 702. The exclusive OR operator 701 takes the exclusive OR of 1 bit input from the previous register and 1 bit output from the output end (right end) of the shift register 702, and outputs 1 bit to the next register. In this way, the pseudorandom number generating unit 102 can generate a 31-bit pseudorandom number.

[0070] Fig. 8 corresponds to Fig. 5 of the first embodiment and is a diagram for explaining the processing method of the pseudo-random number sequence skip unit 106. However, Fig. 8 only shows one stage of Fig. 5. An input value 801 is the initial 31-bit value of the Galois linear feedback shift register of the pseudo-random number sequence skip unit 106. An exclusive-OR calculator 802 performs the same processing as the exclusive-OR calculator 701 in Fig. 7. A transition value 803 represents the same value as the result of shifting the bits of the shift register 702 in Fig. 7.

[0071] 8, it can be seen that the operation of the pseudo-random number sequence skip unit 106 of this embodiment is performed only by the exclusive-OR operator 802. That is, similar to the result considered in FIG. 5 of the first embodiment, the pseudo-random number sequence skip unit 106 of this embodiment can also be implemented with the configuration of FIG. 6.

[0072] (Third embodiment) The image processing device 100 according to the third embodiment has the same configuration as that of the first embodiment shown in Fig. 1, but the pseudo-random number generation unit 102 is configured with Xorshift. Even in the case of Xorshift, the pseudo-random number sequence skip unit 106 can be realized with the configuration shown in Fig. 6 of the first embodiment.

[0073] 9 is a flowchart showing an example of the Xorshift pseudo-random number generation process of the pseudo-random number generator 102. Here, the variable y is a 32-bit unsigned integer. The variable y represents one value in the pseudo-random number sequence. By the process of FIG. 9, the value of the variable y is updated to the value of the next pseudo-random number.

[0074] In step S901, the pseudo-random number generation unit 102 performs an exclusive OR operation on the value of the variable y and the value of the variable y shifted 13 bits to the left, and assigns the result to the variable y. In step S902, the pseudo-random number generation unit 102 performs an exclusive OR operation on the value of the variable y and the value of the variable y shifted 17 bits to the right, and assigns the result to the variable y. In step S903, the pseudo-random number generation unit 102 performs an exclusive OR operation on the value of the variable y and the value of the variable y shifted 5 bits to the left, and assigns the result to the variable y. In this manner, the variable y is generated as a pseudo-random number. Note that in the process of FIG. 9, bits that fall outside the 32-bit range as a result of the left or right shift are ignored.

[0075] Fig. 10 is a diagram showing the pseudo-random number generation process of Xorshift shown in Fig. 9 by an exclusive-OR calculator 1002. Fig. 10 is also a diagram showing an example of the configuration of the pseudo-random number generator 102 according to this embodiment.

[0076] Pseudo-random number value 1001 represents the current 32-bit pseudo-random number value. The pseudo-random number generator 102 uses the circuit in Fig. 10 to find the next pseudo-random number value 1005 based on the current pseudo-random number value 1001. The exclusive-OR calculator 1002 performs an exclusive-OR calculation. The variable 1003 represents the variable y resulting from the calculation in step S901. The variable 1004 represents the variable y resulting from the calculation in step S902. The pseudo-random number value 1005 represents the variable y resulting from the calculation in step S903.

[0077] The processing contents of the pseudo-random number sequence skip unit 106 according to this embodiment can be realized by repeating the processing of Fig. 10 as in Fig. 5. Looking at Fig. 10, it can be seen that the calculation of the pseudo-random number sequence skip unit 106 of this embodiment is only performed by the exclusive OR calculator 1002. That is, like the first embodiment, the pseudo-random number sequence skip unit 106 of this embodiment can also be implemented with the configuration of Fig. 6.

[0078] (Other embodiments) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) for implementing one or more of the functions.

[0079] It should be noted that the above-mentioned embodiments are merely illustrative of specific examples of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be embodied in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0080] 100 Image processing device, 101 Image processing circuit, 102 Pseudo-random number generation unit, 103 Seed value holding unit, 104 Seed value setting unit, 105 Seed value generation unit, 106 Pseudo-random number sequence skip unit

Claims

1. a seed value generating means for generating a plurality of seed values ​​for a plurality of blocks obtained by dividing an image based on one seed value; a pseudo-random number generating means for generating a pseudo-random number sequence for each of the plurality of blocks based on a plurality of seed values ​​for the plurality of blocks; an image processing means for performing image processing on each of a plurality of blocks obtained by dividing the image, using a pseudo-random number sequence for each of the plurality of blocks; The image processing device is characterized in that the seed value generation means generates a plurality of pseudo-random numbers, which are generated by skipping a predetermined number from a pseudo-random number sequence generated by the pseudo-random number generation means based on the one seed value, as the plurality of seed values, and changes the predetermined number by changing some bits of one of the plurality of seed values ​​to other bits.

2. 2. The image processing apparatus according to claim 1, wherein the predetermined number is a number larger than a maximum number of pseudo-random numbers used by the image processing means for image processing of each block.

3. 3. The image processing apparatus according to claim 1, further comprising a seed value setting unit for setting the one seed value.

4. the plurality of seed values ​​includes the one seed value, The seed value setting means writes the one seed value, 4. The image processing apparatus according to claim 3, wherein the seed value generating means writes a seed value other than the one seed value among the plurality of seed values.

5. The pseudo-random number generating means generates pseudo-random numbers by performing an exclusive OR operation based on the seed value; The image processing device according to any one of claims 1 to 4, characterized in that the seed value generation means generates another of the plurality of seed values ​​by performing an exclusive-OR operation on some bits of one of the plurality of seed values.

6. The seed value generating means includes a plurality of bit operation means, 6. The image processing device according to claim 5, wherein each of the plurality of bit operation means generates one bit of another of the plurality of seed values ​​by performing an exclusive OR operation on some bits of one of the plurality of seed values.

7. 6. The image processing device according to claim 5, wherein the seed value generating means repeats a process of generating one bit of another of the plurality of seed values ​​by performing an exclusive OR operation on some bits of one of the plurality of seed values ​​a plurality of times.

8. 8. The image processing device according to claim 1, wherein the pseudo-random number generating means generates the pseudo-random numbers using a Fibonacci linear feedback shift register.

9. 8. The image processing apparatus according to claim 1, wherein the pseudo-random number generating means generates the pseudo-random numbers using a Galois linear feedback shift register.

10. 8. The image processing device according to claim 1, wherein the pseudo-random number generating means generates Xorshift pseudo-random numbers.

11. a seed value generating step of generating a plurality of seed values ​​for a plurality of blocks obtained by dividing the image based on one seed value; a pseudorandom number generating step of generating a pseudorandom number sequence for each of the plurality of blocks based on a plurality of seed values ​​for the plurality of blocks; and an image processing step of performing image processing on each of a plurality of blocks obtained by dividing the image, using a pseudo-random number sequence for each of the plurality of blocks; an image processing method for an image processing device, characterized in that in the seed value generation step, a plurality of pseudo-random numbers are generated as the plurality of seed values ​​by skipping a predetermined number from the pseudo-random number sequence generated based on the one seed value in the pseudo-random number generation step, and the predetermined number is changed by changing some bits of one of the plurality of seed values ​​to other bits.

12. A program for causing a computer to function as each of the means of the image processing device according to any one of claims 1 to 10.

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