How to manufacture a gate

Abstract

A method for fabricating semiconductor-superconductor nanowires is provided, the method comprising: forming a first amorphous mask having first openings over trenches in a substrate; forming a single-crystalline conductive material in the first openings by selective area growth; forming gates for the nanowires in the trenches in the substrate; forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of the second openings; forming an insulating crystalline buffer in the second openings; and forming a crystalline semiconductor material on the buffer in the second openings by selective area growth to form cores of the nanowires, the gates intersecting the cores in the plane of the substrate; and forming a coating of superconductor material over at least a portion of each of the cores.

Description

[Background technology]

[0001] Topological quantum computing is based on the phenomenon that non-abelian anyons in the form of “Majorana zero modes” (MZMs) can form in regions where semiconductors are coupled to superconductors. Non-abelian anyons are a type of quasiparticle, meaning excitations in an electron liquid that are not exactly particles but behave at least partially like particles. MZMs are specific bound states of such quasiparticles. Under certain conditions, these states can be formed near the semiconductor-superconductor interface in a nanowire made of a length of semiconductor coated with a superconductor. When MZMs are induced in a nanowire, it is said to be in the “topological regime”. Inducing this requires cooling the nanowire to a temperature that induces superconducting behavior in superconductor materials, along with a magnetic field, which is traditionally applied externally. It may also require gating part of the nanowire with an electrostatic potential.

[0002] By forming a network of such nanowires and inducing a topological regime in places in the network, it is possible to create quantum bits (qubits) that can be manipulated for the purposes of quantum computing. A quantum bit, or qubit, is an element on which a measurement can be made that has two possible outcomes, but which at any given time (when not being measured) can actually be in a quantum superposition of two states corresponding to those distinct outcomes.

[0003] To induce MZMs, the device is cooled to a temperature where the superconductor (e.g., aluminum, Al) exhibits superconducting behavior. The superconductor induces a proximity effect in the adjacent semiconductor, which causes the region of the semiconductor near the interface with the superconductor to also exhibit superconducting properties, i.e., topological phase behavior is induced in the superconductor and the adjacent semiconductor. It is within this region of the semiconductor that the MZMs form.

[0004] Another condition for inducing a topological phase in which MZM can occur is the application of a magnetic field to lift the spin degeneracy in the semiconductor. Degeneracy in the context of quantum systems refers to the case where different quantum states have the same energy levels. Lifting the degeneracy refers to forcing the states to adopt different energy levels. Spin degeneracy refers to the case where different spin states have the same energy levels. Spin degeneracy can be lifted by a magnetic field, resulting in energy level splitting between differently spin-polarized electrons. This is known as the Zeeman effect. Typically, the magnetic field is applied by an external electromagnet. However, it is also possible to use a layer of ferromagnetic insulator placed between the superconductor and the semiconductor to internally apply a magnetic field to lift the spin degeneracy without the need for an external magnet.

[0005] Inducing an MZM also requires gating the nanowire with an electrostatic potential to control the carrier density within the nanowire. The terminal for applying this potential is called the gate.

[0006] Structures such as the semiconductor cores of a nanowire network can be formed on a substrate by a process known as selective area growth (SAG), which refers to selective epitaxial growth through an amorphous mask. Epitaxy is a known deposition technique that involves growing one crystalline material on another. The first material acts as a seed crystal for a second material to be grown on the first material. Selective growth is achieved by forming a patterned mask on a layer of a first material (e.g., a crystalline substrate) and growing the deposited material (e.g., the semiconductor of the nanowire) in the areas that remain exposed by the mask. Because the mask is amorphous, the deposited material does not grow on the mask, but only in the openings where the underlying crystalline substrate is exposed. Examples of techniques for epitaxial growth itself include, for example, electron beam physical vapor deposition, plasma enhanced chemical vapor deposition, or atomic layer deposition, and molecular beam epitaxy.

[0007] The gates can be formed as top gates or bottom gates. In the case of top gates, they are formed from a patterned metal layer formed on top of the semiconductor of the nanowire. In such a configuration, the semiconductor core of the nanowire can be grown “in-plane” (i.e., horizontally on the substrate of the device itself) by selective area growth (SAG). However, a drawback of top gates is that additional chemical processing steps must be applied on top of the semiconductor of the nanowire after the semiconductor is formed in order to pattern the gate material to form the individual gates. Such processing steps can damage the nanowire. For example, they can involve depositing and removing resist, which can damage the surface of the underlying semiconductor or leave behind resist residues when removed. Such damage can affect the ability to induce MZMs in the nanowire.

[0008] Also, in a top gate, the superconducting metal coating on the nanowire somewhat shields the semiconductor from the gate, reducing the effectiveness of the gate.

[0009] Bottom gates avoid these problems. In existing methods for fabricating devices with bottom gates, a metal gate is formed in the substrate of the device being fabricated. The nanowires must be grown vertically separately and then "cut" and transferred to the device so that they lie flat on top of the gate, in the plane of the substrate. These are known as "out-of-plane" nanowires because they are grown away from the plane of the substrate of the device being fabricated, as opposed to in-plane nanowires, which are grown in place on the plane of the substrate. Summary of the Invention

[0010] Existing methods for fabricating devices with bottom gates do not allow the growth of nanowire semiconductors on the substrate itself because the metals traditionally used to form the gates are traditionally deposited by evaporation or sputtering and are thus polycrystalline when deposited. If one were to grow in-plane nanowires on such a surface, it would lead to defects in the wires. Therefore, the nanowires must be grown separately and then transferred to the substrate. However, this out-of-plane approach is problematic in that the nanowire formation method is not scalable to large or complex networks of nanowires. To address this and other issues, it would be desirable to provide an alternative method for forming devices with bottom gates.

[0011] According to one aspect disclosed herein, there is provided a method of fabricating a device having a plurality of semiconductor-superconductor nanowires, each of the nanowires having a respective semiconductor core and a coating of superconductor material on the respective core, the method comprising forming a first mask over a substrate, the substrate defining a plane, the first mask being formed from an amorphous material and having a pattern of first openings formed over trenches in the substrate, the substrate having a crystalline material at least on surfaces of the trenches, forming a monocrystalline conductive material in the first openings by selective area growth to form gates for the nanowires in the substrate trenches, the method further comprising forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of second openings, forming an insulating crystalline buffer in the second openings, forming a crystalline semiconductor material on the buffer in the second openings by selective area growth to form cores for the nanowires, the gates intersecting the cores in the substrate plane, and forming a coating of superconductor material on at least a portion of each of the cores.

[0012] By embedding the gates in the substrate and forming them by selective area growth of single crystal material, this allows for the growth of in-plane nanowires on top of the bottom gate.

[0013] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the disadvantages discussed herein. [Brief description of the drawings]

[0014] To aid in the understanding of embodiments of the present disclosure and to show how those embodiments may be carried into effect, reference is made, by way of example only, to the accompanying drawings, in which: [Figure 1] 1 is a flow chart illustrating a method of manufacturing a device according to an exemplary embodiment disclosed herein. [Figure 2A] 2A-2B show schematic side views of the device at various stages of the manufacturing method of FIG. [Figure 2B] 2A-2B show schematic side views of the device of FIG. 1 at various stages of the manufacturing method. [Diagram 3] 2A-2B. FIG. 2B shows a schematic of the layers of a device formed according to the method of FIG. [Figure 4] FIG. 2 is a schematic side view showing the formation of a superconducting coating on a device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present disclosure provides a selective-area grown bottom gate (eg, "finger" gate) configuration for gating a network of in-plane nanowires.

[0016] As mentioned above, two existing gate types can be distinguished: top-gate and bottom-gate. A common approach in the case of in-plane wires is to fabricate the gate on top of the nanowire, i.e. top-gate. This type of gate has at least two drawbacks. First, it adds an additional processing step after the growth of the nanowire, which can contaminate and possibly damage the nanowire surface, resulting in scattering sites. This is particularly problematic for quantum applications, since these scattering sites have a negative impact on the carrier mobility and coherence length of the device.

[0017] Also, the material platform for topological quantum computing works with semiconducting-superconducting hybrid heterostructures: in the case of in-plane growth, the superconductor is deposited on top of the nanowires, which shields the effect of the top gate and makes it less effective.

[0018] These problems can be avoided if the gates are fabricated prior to nanowire epitaxy. Such gates are also known as bottom gates. Bottom gates are traditionally only used to work with out-of-plane nanowires, where the wires are grown separately and then transferred to a pre-patterned substrate that contains a bottom "finger" gate structure. However, out-of-plane methods are not scalable to large or complex networks of nanowires. Also, it is very difficult to grow large structures, and furthermore, the probability of successfully creating a given structure decreases exponentially with the number of wires.

[0019] Given that gate metals and dielectrics are typically amorphous, it is not possible to grow in-plane wires on top of existing substrates that contain bottom gates, which severely limits the quality of subsequent growth.

[0020] Note that to form individual gates to selectively control individual nanowires in a network, or even individual sections of a given nanowire, the gate material must be patterned, i.e., a patterned gate structure is needed to be able to select what to gate and what not to gate (where to apply the desired electrostatic potential). A global backgate (i.e., one large uniform backgate) only allows for non-local tuning of the overall chemical potential, but does not allow for gating individual nanowires, as would be required to operate as nanowires in a quantum computing device.

[0021] It would be desirable to enable the fabrication of in-plane semiconductor nanowires by selective area epitaxy. This scalable approach would allow the growth of complex networks while preserving the advantage of nanowire geometry, i.e., quasi-one-dimensionality. Gate electrodes have traditionally been used to control the carrier density in these nanowires during transport measurements, e.g., to induce tunneling barriers or manipulate the chemical potential of the wire. As mentioned above, these gate structures are typically fabricated following nanowire epitaxy and require chemical treatments, which can leave residues or damage the nanowire surface, leading to degradation of material quality.

[0022] The methods disclosed herein achieve the construction of a local bottom gate (e.g., a "finger" gate) by selective area epitaxy, which preserves the crystal structure of the substrate in the gate and semi-insulating material, thus enabling the subsequent growth of a nanowire network on top of the gate.

[0023] As mentioned above, it is not possible to grow in-plane wires on conventional substrates that include bottom gates, since the gate metal and dielectric are generally amorphous. Therefore, according to the present disclosure, the gate material and substrate (e.g., dielectric) are instead made crystalline. Using selective area growth, a network of patterned bottom gates (e.g., finger gates) can be formed, and nanowires can then be formed on top of them. This combines the flexibility of selective area growth with the precision of local gates. Also, many more advanced applications require a large number of gates, in which case it is necessary to have the option to gate from below the network as well. Therefore, selective area grown finger gates are an excellent option to control the carrier density of in-plane nanowire networks using finger gates to maintain high material quality. Enabling effective gating of nanowires below a superconductor is important for tunability towards topological phases.

[0024] One material option for the gate is degenerately doped InGaAs lattice matched to InP, a common substrate material used for in-plane InSb and InAs growth. There are several options for the crystalline semi-insulating layer, with the preferred choice depending on the crystal structure of the subsequent nanowire material. Two viable options are InP or InAlSb.

[0025] Figure 1 is a flow chart of a method according to an exemplary embodiment of the present disclosure. Figure 2A shows a side view of a device fabricated at various stages of the method, with the x direction from left to right (horizontal in the plane of the paper) and the y direction into the plane of the paper (perpendicular to the plane of the paper). Figure 2B shows a side view of a device fabricated at a further stage of the method, with the y direction from left to right in the plane of the paper and the x direction into the plane of the paper. Figure 3 shows the corresponding isometric views of the various layers shown in Figures 2A and 2B. The x and y axes are in the plane of the substrate 11.

[0026] The device fabricated comprises a substrate 11, gates 13, buffers 15, nanowire semiconductor cores 16, and a superconducting coating 17 on some or all of each semiconductor core 16. It is understood that the orientation of the xy axes relative to the plane of the substrate 11 may be design dependent, and the linear design shown here is given by way of example only. It is not necessary that the gates 13 or nanowires 16 / 17 form a straight line, nor that the gates 13 are necessarily perpendicular to the nanowires 16 / 17.

[0027] As a point of terminology, "over" herein can mean either directly on or indirectly on with one or more intermediate layers between. "On" herein means directly on or in contact with, without any intermediate layers. Also, the terms "on" or "over" or the like, as used herein, do not necessarily imply a particular orientation relative to gravity (in some growth chambers devices may be fabricated upside down relative to the orientation shown). Rather, the terms refer to a position relative to the plane of the substrate 11 being processed, i.e., the positive z-direction is outward from the plane of the substrate 11 being processed. The opposite interpretation is given to terms such as "below" or "under."

[0028] Step S1 comprises providing a substrate 11. The substrate 11 may comprise one or more constituent layers. The substrate 11 is preferably a dielectric or other insulator, or at least has a substantially larger bandgap (i.e. more insulating) than the semiconductor material 16 to be used for the nanowire core. The substrate 11 (at least where the gate 13 is to be formed) comprises a crystalline material, such as InP (indium phosphide). Although InP is a semiconductor, it has a significantly larger bandgap than, for example, InSb, and therefore can act as an insulating material in such a context. More generally, the substrate material may be any insulator, such as GaAs, GaSb, or Si. In an embodiment, the substrate material 11 is single crystalline. In an embodiment, the substrate material has a crystalline structure of zinc blende (named after the crystal lattice structure found in the mineral zinc blende, but this does not imply the use of the mineral zinc blende itself or the presence of zinc).

[0029] At step S2, the method includes applying a layer 12 of a first mask material, such as silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or boron nitride. The mask material is amorphous (i.e., non-crystalline) since it will provide a mask for a subsequent selective area growth (SAG) step.

[0030] In step S3, the method comprises patterning the mask material of the first layer 12. In an embodiment, this may comprise etching away parts of the mask to leave openings. In one particularly efficient implementation, the etching is allowed to proceed part way down through the mask material 12 into the substrate 11, thus also forming, in one etching step, trenches in the substrate 11 that coincide with the openings of the first mask 12 in the plane of the substrate 11. Gates 13 will be formed in these openings and trenches. The etching may be performed, for example, using lithographic techniques (such as electron beam lithography) or a stencil mask.

[0031] However, in alternative implementations, it is not necessary that the trench and opening are formed in the same etch step, for example the trench may be formed in a first etch step and then the first mask material 12 may be applied and patterned, for example by lithography.

[0032] In any event, the openings in the first mask 12 are aligned in the plane of the substrate with the trenches in the substrate 11. The substrate 11 is formed from a crystalline material, or at least the upwardly facing surface at the bottom of the trench is crystalline.

[0033] In step S4, a gate material 13 is formed in the trench through the openings in the first mask 12. This is done using selective area growth (SAG), where the surface of the trench hole in the substrate 11 acts as a seed crystal for the epitaxial growth of the gate material 13. Therefore, the gate material 13 is also selected to be crystalline. Furthermore, the gate material 13 is single crystalline to support the epitaxial growth of nanowires thereon. Conventionally, gates are formed by sputtering or depositing metals that are polycrystalline when deposited or sputtered. Also, the dielectrics required to electrically insulate the bottom gate are typically amorphous. However, to form in-plane nanowires on top of the bottom gate, a single crystalline layer needs to be grown to minimize defects in the in-plane wire. Thus, the techniques disclosed herein form a single crystalline material by selective area growth. In an embodiment, the gate material 13 has a zinc blende crystal structure to provide a good crystal match with the substrate material 11 on which it is grown. However, other suitably matching crystal combinations are possible. The gate material 13 is electrically conductive. The gate material 13 may be non-metallic. For example, in an embodiment, the gate material 13 is a doped semiconductor, such as doped InGaAs (indium gallium arsenide) or doped InP (indium phosphide), doped sufficiently to act as an electrical conductor for gate control purposes. The doping shifts the Fermi level into the conduction / valence band depending on the dopant that makes the material conductive. Preferably, the substrate 11 (or at least its top surface) is a dielectric or other insulator, and in an embodiment, it also has a larger bandgap than the nanowire semiconductor 16. Thus, the substrate separates the gates from each other.

[0034] In an embodiment, the gate 13 is formed to a height that is flush with the top surface of the substrate 11 to provide a flat surface for subsequent processing. However, this is not absolutely essential. In an embodiment, the width of the opening in the first mask 12 and the trench in the substrate 11, and therefore the width of the gate 13, is between 20 nm and 100 nm. These are the lengths desired for the length of the gate 13 in the design for the application in question. There is no strict limit to the width of the gate 13, but above about 100 nm, the quality of the growth may start to be affected. The depth of the gate 13 may be between about 10 nm and 100 nm. In principle, the gate can be any depth, but a larger width makes it more difficult to align the gate height with the substrate.

[0035] At step S5 the method comprises removing the first mask 12. This may be done using any suitable known chemical treatment process, however at this stage no nanowires have yet been formed which may be damaged by the chemical treatment.

[0036] At step S6, the method comprises forming a layer of second mask material 14, which may be formed, for example, from any of the possible materials described with respect to the first mask 12. At step S7, the method comprises patterning the second mask 14 to form openings therethrough. These openings may not coincide with the first openings or the gates 13, but they may overlap. The openings in the second mask define where the semiconductor 16 cores of the nanowires will be formed. These openings may again be formed, for example, by any suitable known lithographic technique.

[0037] In step S8, the method comprises forming a buffer 15 in the openings of the second mask 14. In an embodiment, this is done by SAG. However, other deposition techniques are not excluded for this step. The buffer 15 is insulating and crystalline, preferably single crystalline. It is insulating so as to electrically insulate the gate 13 from the nanowire 16 / 17 (so it has a larger bandgap than the semiconductor 16). An electrostatic field can penetrate from the gate 13 to the nanowire core 16, but there is no electrical contact. In an embodiment, the buffer 15 is a dielectric. It also has a crystalline material so as to act as a seed substrate for the semiconductor 16 of the nanowire formed in the next step. In an embodiment, the buffer 15 is formed from a single buffer material that is insulating and crystalline, although a bilayer buffer with a lower insulating layer and an upper crystalline layer is not excluded. In an embodiment, the crystalline buffer material 15 has a zinc-blende crystal structure to provide a good crystal match with the zinc-blende gate material 13 on which it is grown, and with the semiconductor 16 (which may also have a zinc-blende structure) grown on the buffer 15. Examples of suitable single materials for use as the buffer 15 include InAlSb (indium aluminum antimonide) or InP, although other suitable crystal matches are possible.

[0038] In step S9, the method comprises growing the semiconductor nanowires 16 on the buffer 15 in the openings of the second mask 14, thus forming a network of nanowire cores, again by SAG. Based on this approach, it is possible to lithographically define a nanowire network of virtually any structure the designer desires, which is not possible using the out-of-plane nanowire approach. The nanowire pattern is also arranged in the plane of the substrate such that it at least partially crosses the underlying gate 13 (but does not make electrical contact in the z-direction). This makes it possible to specifically select where the nanowire network is gated and where it is not with this device. For example, in the illustrated example, the gate 13 is formed as a long thin line (a so-called "finger gate") and the nanowires 16 / 17 are formed perpendicular to the finger gate 13.

[0039] In an embodiment, the width of the opening in the second mask 14, and therefore the width of the nanowire core 16, is between 20 and 100 nm. These may be as desired for the design of the application in question. There is no strict limit to this width, but above about 100 nm the effectiveness of 1D confinement to form the MZM begins to decrease.

[0040] The nanowire's semiconductor material 16 is crystalline, preferably single crystalline. In an embodiment, the nanowire's semiconductor 16 is a III-V semiconductor, such as InSb, InAs, InP, or GaAs. In an alternative example, it may be silicon (Si). In an embodiment, the semiconductor 16 used in the nanowire has a zinc blende crystal structure to provide a good crystal match with the buffer 15 on which it is grown. However, other suitably matching crystal structures are possible. The nanowire's semiconductor 16 also has a smaller bandgap than the insulators or dielectrics used for such properties elsewhere in the device, such as the substrate 11 or the buffer 15.

[0041] In step S10, a superconducting coating 17 is formed on at least a portion of each nanowire core 16. This is also shown diagrammatically in Figure 4, which shows the same orientation as Figure 2B (x into the page). The superconductor 17 may be formed all around the top periphery of the semiconductor core 16 (all facets left exposed in step S9), as shown in Figure 4, or only part way around it (e.g. when formed by angled deposition where only one or two facets need to be coated). It may be formed all along the length of the nanowire (into the page), or only part way around. Any superconducting material may be used, for example Al, Pb, Sn, or Nb.

[0042] It will be understood that the above embodiments have been described by way of example only.

[0043] More generally, according to one aspect disclosed herein, there is provided a method of fabricating a device having a plurality of semiconductor-superconductor nanowires, each of the nanowires having a respective semiconductor core and a coating of superconductor material on the respective core, the method comprising forming a first mask over a substrate, the substrate defining a plane, the first mask being formed from an amorphous material and having a pattern of first openings formed over trenches in the substrate, the substrate having a crystalline material at least on surfaces of the trenches, forming a monocrystalline conductive material in the first openings by selective area growth to form gates for the nanowires in the trenches of the substrate, forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of second openings, forming an insulating crystalline buffer in the second openings, forming a crystalline semiconductor material on the buffer in the second openings by selective area growth to form the cores of the nanowires, the gates intersecting the cores in the substrate plane, and forming the coating of superconductor material on at least a portion of each of the cores.

[0044] In an embodiment, the forming of the first mask may be performed by forming a layer of mask material over the substrate and etching the first opening and the trench in the same etching step.

[0045] In embodiments, the semiconductor material may have a zinc blende crystal structure.

[0046] In embodiments, the semiconductor material may be a III-V semiconductor.

[0047] In embodiments, the semiconductor material may be one of InSb, InAs, InP, GaAs, or silicon.

[0048] In embodiments, the conductive material of the gate may have a zinc blende crystal structure.

[0049] In embodiments, the conductive material of the gate may comprise a doped semiconductor.

[0050] In embodiments, the conductive material of the gate may be doped InGaAs or doped InP.

[0051] In embodiments, the substrate may be a dielectric or other insulator.

[0052] In an embodiment, the substrate has a zinc blende crystal structure, at least where the gate is to be formed.

[0053] In an embodiment, the substrate has at least a top layer of crystalline material where the trench is to be formed.

[0054] In embodiments, the crystalline material of the substrate may have a zinc blende crystal structure.

[0055] In embodiments, the substrate may be formed of InP, GaAs, GaSb, or Si.

[0056] In an embodiment, the buffer may also be formed by selective area growth through the second opening in the second mask.

[0057] In embodiments, the buffer may have a zinc blende crystal structure.

[0058] In an embodiment, the buffer may be InAlSb or InP.

[0059] In embodiments, the superconductor may be Al, Pb, Sn, or Nb.

[0060] In embodiments, the first and / or second mask may be a dielectric or other insulator.

[0061] In embodiments, the first and / or second mask may be formed from any of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or boron nitride.

[0062] According to another aspect of the present disclosure, there is provided a device manufactured by the method of the embodiments disclosed herein.

[0063] According to another aspect, a method of operating the device is provided, the method comprising cooling the device to a temperature at which the superconductor becomes superconducting, applying a magnetic field from an internal or external source, and applying an electrostatic potential to the gate to induce a Majorana zero mode in at least a portion of the plurality of nanowires.

[0064] Given the disclosure herein, other variations or use cases of the disclosed technologies may become apparent to one of ordinary skill in the art. The scope of the present disclosure is not limited by the described embodiments, but only by the appended claims.

Claims

1. 1. A method of manufacturing a device having a plurality of semiconductor-superconductor nanowires, each of the nanowires having a respective semiconductor core and a cladding of superconductor material on the respective core, the method comprising: forming a first mask over a substrate, the substrate defining a plane, the first mask being formed from an amorphous material and having a pattern of first openings formed over trenches in the substrate, the substrate having a crystalline material at least on surfaces of the trenches; forming a single crystalline conductive material in the first opening by selective area growth to form a gate for the nanowire in the trench of the substrate; forming a second mask over the substrate and the gate, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer in the second opening; forming a crystalline semiconductor material on the buffer in the second opening by selective area growth to form the core of the nanowire, the gate intersecting the core in the plane of the substrate; forming said coating of superconductor material on at least a portion of each of said cores; The method comprises:

2. 2. The method of claim 1, wherein said forming said first mask is performed by forming a layer of mask material over said substrate and etching said first opening and said trench in the same etching step.

3. The method of claim 1 or 2, wherein the semiconductor material has a zinc blende crystal structure.

4. The method according to any one of claims 1 to 3, wherein the semiconductor material is a III-V semiconductor.

5. The method of claim 1 , wherein the semiconductor material is one of InSb, InAs, InP, GaAs, or silicon.

6. The method of claim 1 , wherein the conductive material of the gate has a zinc blende crystal structure.

7. The method of claim 1 , wherein the conductive material of the gate comprises a doped semiconductor.

8. The method of claim 7 , wherein the conductive material of the gate is doped InGaAs or doped InP.

9. The method of claim 1 , wherein the substrate is a dielectric or other insulator.

10. 10. The method of claim 1, wherein the substrate has a zinc blende crystal structure, at least where the gate is to be formed.

11. 11. A method according to any preceding claim, wherein the buffer is also formed by selective area growth through the second opening in the second mask.

12. 12. The method of claim 1, wherein the buffer has a zinc blende crystal structure.

13. The method of any of claims 1 to 12, wherein the buffer is InAlSb or InP.

14. A device having a plurality of semiconductor-superconductor nanowires, each of the plurality of nanowires having a respective semiconductor core and a superconductor coating on the respective core, the device comprising: a substrate having a trench formed on an upper surface thereof, the substrate having a crystalline material on at least a surface of the trench; a gate for the nanowire formed within and along the trench, the gate having a single crystalline conductive material; a buffer formed on the top surface of the substrate intersecting the gate, the buffer comprising an insulating crystalline material; the semiconductor core being crystalline and formed on and along the buffer; a coating of the superconductor formed on at least a portion of each of the semiconductor cores; A device having

15. A method of operating a device according to claim 14, comprising the steps of: cooling the device to a temperature at which the superconductor becomes superconducting; Applying a magnetic field from an internal or external source; applying an electrostatic potential to the gate to induce Majorana zero modes in at least some of the nanowires; How to have that.

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