Semiconductor Device

Abstract

To manufacture a semiconductor device which uses a thin film transistor having favorable electrical characteristics and high reliability as a switching element and has a pixel part and a drive circuit part capable of high-speed operation on the same substrate to achieve high display quality and high reliability.SOLUTION: In a semiconductor device, in a drive circuit part and a pixel part two types of thin film transistors each using an oxide semiconductor layer having a crystalline region on one surface as an active layer are formed, and by selecting a region where a channel is formed by arrangement of a gate electrode layer, electric characteristics of the thin film transistor is selected thereby to allow the semiconductor device having the pixel part and the drive circuit part capable of a high-speed operation on the same substrate to be manufactured.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all electro-optical devices such as liquid crystal displays and light-emitting devices, semiconductor circuits, and electronic devices. It is a semiconductor device. [Background technology]

[0003] In recent years, a technique for forming a transistor using a semiconductor film formed on a substrate having an insulating surface has been developed. Transistors are widely used in electronic devices such as ICs and electro-optical devices. In particular, development of these devices as switching elements for image display devices is being accelerated.

[0004] Metal oxides are one of the materials that exhibit semiconducting properties. Examples of oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. There are transistors that use metal oxides that exhibit such semiconducting properties as their channel formation regions. This is already known (Patent Document 1 and Patent Document 2).

[0005] In addition, a transistor using an oxide semiconductor has high field-effect mobility. A driver circuit of a display device or the like can also be formed using a transistor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0007] When forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit are formed on the same substrate. In this case, the transistor used in the pixel portion should have excellent switching characteristics, e.g. A large on-off ratio is required, and the transistors used in the drive circuit must have a high operating speed. In particular, the higher the resolution of the display, the longer the time it takes to write the displayed image. Therefore, it is preferable that the transistors used in the driver circuit have a high operating speed. Furthermore, by improving the aperture ratio, which is contrary to the need for high definition, it is possible to improve the display quality.

[0008] One embodiment of the present invention is to use a transistor with favorable electrical characteristics and high reliability as a switching element. The display device has a pixel section and a driver circuit section capable of high-speed operation on the same substrate, and is therefore superior in display quality and signal quality. An object of the present invention is to manufacture a highly reliable semiconductor device. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a driver circuit portion and a semiconductor device including a transistor, both of which are formed over the same substrate. The present invention relates to a semiconductor device and a manufacturing method thereof, in which a pixel portion including a crystalline silicon is formed on one surface (surface portion). Two types of transistors are formed using an oxide semiconductor layer having a gate electrode layer. This is a semiconductor device in which a region where a channel is formed is selected by a device. For example, the following configuration can be used.

[0010] A semiconductor device according to one embodiment of the present invention includes a pixel portion having a first transistor and a second transistor, both of which are formed over the same substrate. a drive circuit section having a first transistor and a second transistor, the first transistor being a first transistor disposed on a substrate; a gate electrode layer, and a first insulating layer that functions as a gate insulating layer on the first gate electrode layer; a first oxide semiconductor layer having a crystalline region made of nanocrystals in a surface layer portion on the first insulating layer; a first source electrode layer and a first drain electrode layer overlapping with a part of the first oxide semiconductor layer; a second insulating layer in contact with a part of the first oxide semiconductor layer, A first insulating layer is formed on the substrate, and a crystalline region made of nanocrystals is formed on the surface of the first insulating layer. a second oxide semiconductor layer overlapping the second oxide semiconductor layer; and a second source electrode layer overlapping a portion of the second oxide semiconductor layer. and a second drain electrode layer in contact with a part of the second oxide semiconductor layer and serving as a gate insulating layer. A second insulating layer is functionalized, and a second gate electrode layer is formed on the second insulating layer.

[0011] In the semiconductor device, the crystalline region is formed in the first oxide semiconductor layer or the second oxide semiconductor layer. Nanocrystals with c-axis orientation perpendicular to the surface of each semiconductor layer are formed. .

[0012] In the semiconductor device, between the second oxide semiconductor layer and the second source electrode layer, and an oxide conductive layer is provided between the second oxide semiconductor layer and the second drain electrode layer. It's okay to do so.

[0013] In the semiconductor device, the second transistor is It is preferable to use it in the following cases.

[0014] The oxide semiconductor layer is made of a quaternary metal oxide, In-Sn-Ga-Zn-O system. and ternary metal oxides such as In-Ga-Zn-O, In-Sn-Zn-O, and In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO system, binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al-Zn -O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn The oxide semiconductor layer may be an oxide semiconductor layer such as a Zn-O-based layer or a Zn-O-based layer. The body layer may contain SiO2.

[0015] The oxide semiconductor layer is InMO3(ZnO) m Use a thin film expressed as (m>0) Here, M can be one or more selected from Ga, Al, Mn and Co. It represents a metal element. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m Oxide semiconductor with a structure represented by (m>0) Among them, oxide semiconductors with a structure containing Ga as M are referred to as the In-Ga-Zn-O oxides mentioned above. In this paper, we call these thin films In-Ga-Zn-O based semiconductors.

[0016] In addition, the oxide semiconductor layer is decomposed at high temperature for a short time using the RTA (rapid thermal annealing) method. Water or a dehydrogenated oxide semiconductor layer is used. The part has a crystalline region made up of a group of microcrystals made up of nanocrystals, and the other part The material is amorphous, a mixture of amorphous and microcrystalline with microcrystalline interspersed in amorphous regions, or entirely microcrystalline. It becomes a crystal cluster.

[0017] Further, a driver circuit portion and a pixel portion can be formed on the same substrate using a transistor according to one embodiment of the present invention. and fabricating a semiconductor device using an EL element, a liquid crystal element, an electrophoretic element, or the like. It is possible.

[0018] In this specification, the gate electrode layer refers to a part of the gate wiring in addition to the gate electrode. The gate wiring is a wiring that connects at least one gate electrode of a transistor and another electrode For example, the wiring in a display device is used to electrically connect a line to another line. The scan lines are also included in the gate wiring.

[0019] The source electrode layer includes a part or all of the source wiring in addition to the source electrode. The wiring is a wiring that electrically connects the source electrode of at least one transistor to another electrode or another wiring. For example, the signal line in a display device is connected to the source electrode. When electrically connected, the source wiring also includes the signal line.

[0020] The drain electrode layer includes a part or the whole of the drain wiring in addition to the drain electrode. The drain wiring is a wiring that connects the drain electrode of at least one transistor to another electrode or another wiring. For example, the signal lines in a display device are used to electrically connect When electrically connected to the drain electrode, the drain wiring also includes the signal line.

[0021] In addition, in the present specification, claims, drawings, etc., the source and drain of a transistor The two types of transistors are interchangeable depending on the structure and operating conditions of the transistors. Therefore, it is difficult to define whether the source or drain is a In the range or drawings, the source and drain are arbitrarily selected. One terminal is referred to as one of the source and drain, and the other terminal is referred to as the other of the source and drain. do.

[0022] In this specification, the term "light emitting device" refers to an image display device, a light emitting device, or a light It also refers to a light source (including lighting devices) that has a connector, such as an FPC (Flexible Printed Circuit). le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packaging) e) is attached to the module, and the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) on a substrate on which a light emitting element is formed. s) All modules in which ICs (integrated circuits) are directly mounted using this method are also included in the light-emitting device. Let's say.

[0023] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate [Effects of the Invention]

[0024] By implementing one aspect of the present invention, a driver circuit portion capable of high-speed operation and a pixel circuit portion can be formed on the same substrate. A semiconductor device having an element portion can be manufactured. [Brief explanation of the drawings]

[0025] [Figure 1] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 4] 1A and 1B are a circuit diagram and a timing chart illustrating the operation of a shift register; [Figure 5] FIG. 4 is a diagram showing the operation of a pulse output circuit. [Figure 6] FIG. 4 is a diagram showing the operation of a pulse output circuit. [Figure 7] FIG. 4 is a diagram showing the operation of a pulse output circuit. [Figure 8] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 9] FIG. 2 is a diagram showing the configuration of a signal line driver circuit. [Figure 10] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 11] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 15] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 16] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 17] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 18] FIG. 1 is an external view showing an example of an electronic book. [Figure 19] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 20] FIG. 1 is an external view showing an example of a gaming machine. [Figure 21] FIG. 1 is an external view showing an example of a mobile phone. [Figure 22] FIG. 10 is a longitudinal cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Figure 23] Energy band diagram (schematic diagram) between A-A' shown in Figure 22. (A) When the voltage between the source and drain is equipotential (VD=0), (B) when a positive potential (VD>0) is applied to the drain relative to the source. [Figure 24] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 25] 22. Energy band diagram (schematic diagram) between B-B' in FIG. 22 when the gate voltage is 0V. [Figure 26] Energy band diagram (schematic diagram) between B-B' in Figure 22. (A) When a positive potential (VG>0) is applied to the gate (GE1), (B) When a negative potential (VG<0) is applied to the gate (GE1). DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In the drawings in this specification, parts having the same parts or similar functions are The same reference numerals are used to denote corresponding parts, and their explanations may be omitted.

[0027] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. Figure 1(E) shows two transistors with different structures fabricated on the same substrate. 1(E) shows an example of a cross-sectional structure of the transistors 440 and 450. The transistor 440 shown in FIG. It is one of the bottom gate structures called inverted staggered type, and the transistor 450 is a top gate It is a transistor with a gate structure.

[0028] The transistor 440 disposed in the pixel is formed on a substrate 400 having an insulating surface, and includes a gate electrode layer 451, the first insulating layer 402 which functions as a gate insulating layer, and an oxide layer including a channel forming region. The semiconductor layer 404 includes a nitride semiconductor layer 404b, a source electrode layer 455c, and a drain electrode layer 455d. In addition, the second insulating layer 404b covers the transistor 440 and is in contact with part of the oxide semiconductor layer 404b. 28 will be established.

[0029] The transistor 440 disposed in the pixel is a transistor with a single gate structure. However, if necessary, a multi-gate structure transistor or a channel forming region may be used. It is also possible to form a dual gate structure in which gate electrode layers are placed above and below the region via insulating films. can.

[0030] A source electrode layer 455c and a drain electrode layer 455b are provided above the oxide semiconductor layer 404b. The oxide semiconductor layer 404b is formed so that the first The gate electrode layer 451 overlaps the insulating layer 402. The channel formation region of the oxide semiconductor layer 404b is formed by the source electrode layer 455c. and a region in contact with the drain electrode layer 455d. This is a region that is in contact with and overlaps with the gate electrode layer 451 .

[0031] The transistor 440 includes a gate electrode layer 451, a source electrode layer 455c, and a drain electrode layer 456. By using a light-transmitting conductive film for the light-transmitting electrode layer 455d, a semiconductor device having a high aperture ratio can be obtained. The light-transmitting material is a conductive material that is transparent to visible light. Materials such as In-Sn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn -Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn- O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based acids When sputtering is used, SiO2 should be added in an amount of 2% by weight or more. The film is formed using a target containing 10% by weight or less of SiOx It is preferable to include (X>0) to make it amorphous.

[0032] The transistor 450 disposed in the driver circuit section is formed on a substrate 400 having an insulating surface. An insulating layer 402, an oxide semiconductor layer 404a having a channel formation region, and a source electrode layer 455 a, the drain electrode layer 455b, the second insulating layer 428 serving as a gate insulating layer, and the gate insulating layer 455c. The substrate 420 includes a gate electrode layer 421 .

[0033] The gate electrode layer 421, the source electrode layer 455a, and the drain electrode layer 455b of the transistor 450 55b (including wiring formed on the same layer) is Al, Cu, Cr, Ta, Ti, M It is made of a metal material such as Al or W, or an alloy material containing such a metal material. A high melting point metal layer such as Cr, Ta, Ti, Mo, or W is applied to one or both of the metal layers such as Cu. It may also be a laminated structure of Si, Ti, Ta, W, Mo, Cr, Nd, Sc A, which contains elements such as Y that prevent the occurrence of hillocks and whiskers that occur in Al films. By using l material, it is possible to improve heat resistance.

[0034] The source and drain electrodes (including the wiring formed in the same layer) are made of conductive metal oxide. Conductive metal oxides include indium oxide (In2O3), oxide Tin oxide (SnO2), zinc oxide (ZnO), indium oxide tin oxide alloy (In2O3- SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3-ZnO) Alternatively, the metal oxide material may contain silicon or silicon oxide. can.

[0035] A source electrode layer 455a and a drain electrode layer 455b are provided above the oxide semiconductor layer 404a. The oxide semiconductor layer 404a is formed so as to overlap with a part of the gate electrode layer 4b. 21 through the second insulating layer 428. Transistors arranged in the drive circuit section The channel formation region 450 is formed by the source electrode layer 455a and the gate electrode layer 455b of the oxide semiconductor layer 404a. The region in contact with the drain electrode layer 455b is sandwiched between the region in contact with the second insulating layer 428 and the region in contact with the drain electrode layer 455c. The gate electrode layer 421 overlaps the insulating film 421 .

[0036] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Sn-Ga-Zn-O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system In addition, an oxide semiconductor layer such as a Zn—O-based oxide semiconductor layer can be used. It may contain SiO2.

[0037] The oxide semiconductor layer is InMO3(ZnO) m Use a thin film expressed as (m>0) Here, M can be one or more selected from Ga, Al, Mn and Co. It represents a metal element. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m Oxide semiconductor with a structure represented by (m>0) Among them, oxide semiconductors with a structure containing Ga as M are referred to as the In-Ga-Zn-O oxides mentioned above. In this paper, we call these thin films In-Ga-Zn-O based semiconductors.

[0038] In addition, the oxide semiconductor layer is subjected to RTA (Rapid Thermal Anneal). Use materials that have been dehydrated or dehydrogenated at high temperature for a short time using methods such as hot thermal annealing. This heating process reduces the grain size of the surface layer of the oxide semiconductor layer to 1 nm or more and 20 nm or less. It has a crystalline region composed of so-called nanocrystals (also written as nanocrystals). The other parts are amorphous or a mixture of amorphous and microcrystalline regions with microcrystalline scattered throughout the amorphous regions. The size of the nanocrystals is merely an example, and the invention is not limited to the above numerical range. It is not to be interpreted.

[0039] By using an oxide semiconductor layer with such a structure, the surface layer is made up of nanocrystals. Because of the presence of dense crystalline regions, the n-type structure is formed by the re-intrusion of moisture from the surface and the desorption of oxygen. In addition, the surface portion of the oxide semiconductor layer can be prevented from being damaged by the boron. In the Tom gate type transistor 440, it is on the opposite side to the channel, and the prevention of the n-type It is also effective in suppressing the formation of raw channels. In addition, the surface layer has improved conductivity due to the presence of crystalline regions. The contact resistance between the portion and the source electrode layer or the drain electrode layer can be reduced.

[0040] The crystalline region in the surface layer of the oxide semiconductor layer has a crystal structure in the direction substantially perpendicular to the surface of the oxide semiconductor layer. The crystal grains have an oriented c-axis. For example, the oxide of In-Ga-Zn-O system When using a semiconductor material, the crystalline region is formed by oxidizing the c-axis of the In2Ga2ZnO7 crystal grains. For example, in the case of an oxide semiconductor layer, When using In-Ga-Zn-O oxide semiconductor materials, In2Ga2ZnO7 crystal The c-axis of the grains is perpendicular to the substrate surface (or the surface of the oxide semiconductor layer). By arranging the crystals, the direction of current flow in the transistor is controlled 7 This is the b-axis (or a-axis) direction of the crystal grain.

[0041] The crystalline region may include other elements than crystal grains. The crystal structure is not limited to the above, and may include crystal grains of other crystal structures. For example, In-Ga-Zn When using an oxide semiconductor material of the In-O system, in addition to the crystal grains of In2Ga2ZnO7, It may contain crystal grains of nGaZnO4.

[0042] Hereinafter, with reference to FIGS. 1A to 1E, a transistor 440 and a transistor The steps for producing the star 450 will now be described.

[0043] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 451 is formed by a process. It is preferable to etch the edge of the gate electrode layer 451 so that it has a tapered shape. .

[0044] The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs. It can be applied not only to the first photolithography process but also to other photolithography processes. Cut.

[0045] The substrate 400 may be made of barium borosilicate glass, aluminoborosilicate glass, or Alkali-free glass such as aluminosilicate glass produced by the fusion method or float method In addition to glass substrates and ceramic substrates, we also use heat-resistant plastic substrates that can withstand the processing temperatures of this manufacturing process. In addition, an insulating substrate such as a stainless steel alloy substrate can be applied to the surface of the metal substrate. A substrate provided with a film may also be applied.

[0046] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, crystallized glass or the like may also be used.

[0047] The gate electrode layer 451 is made of a light-transmitting oxide conductive film in order to improve the aperture ratio of the pixel portion. The oxide conductive layer is preferably formed using a layer of, for example, indium oxide, Indium oxide tin oxide alloy, indium oxide zinc oxide alloy, zinc oxide, zinc aluminum oxide For example, zinc oxide, zinc aluminum oxynitride, or zinc gallium oxide can be used.

[0048] The conductive film forming the gate electrode layer 451 may be Al, Cr, Ta, Ti, Mo, W, or an alloy containing the above elements, or a combination of the above elements Alternatively, an alloy film or a laminated film may be used.

[0049] Further, an insulating layer serving as a base film may be provided between the substrate 400 and the gate electrode layer 451. The film has a function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, a silicon oxide film, A stack of one or more films selected from a silicon nitride film, a silicon oxide nitride film, and a silicon oxynitride film. It can be formed in a layer structure.

[0050] Next, a first insulating layer 402 is formed over the gate electrode layer 451. The first insulating layer 402 is Silicon oxide, silicon oxynitride, silicon nitride oxide formed by CVD or sputtering It uses a single layer or a laminated film of silicon, silicon nitride, aluminum oxide, tantalum oxide, etc. The thickness of the first insulating layer 4 is set to 50 nm or more and 250 nm or less. 02 serves as the gate insulating layer of the transistor 440 and the underlying insulating layer of the transistor 450. It functions as a marginal layer.

[0051] The first insulating layer 402 can also be formed using a high-density plasma device. The high-density plasma device is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, A first insulating layer 402 is formed.

[0052] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and insulating materials such as glass are An insulating layer is formed on the substrate having a surface. Then, the supply of monosilane gas is stopped and the substrate is exposed to the atmosphere. Plasma treatment was performed on the insulating layer surface by introducing nitrous oxide (N2O) and rare gases without exposing it to heat. It may be performed on the surface of the insulating layer by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is performed after the insulating layer is formed. It is an insulating layer that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0053] When forming the first insulating layer 402, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar include helium, argon, krypton, and xenon. Among these, it is preferable to use argon, which is inexpensive.

[0054] In addition, the insulating layer obtained by the high-density plasma device can be formed with a consistent thickness. The insulating layer obtained by the high density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0055] The insulating layer obtained through the above process sequence is different from the insulating layer obtained using a conventional parallel plate PCVD device. The etching rates are significantly different when the same etchant is used. The insulating layer obtained by the parallel plate PCVD equipment is 10% or more or 20% slower and more highly The insulating layer obtained using a high-density plasma device can be said to be a dense film.

[0056] The first insulating layer 402 is formed by depositing silicon oxide by a CVD method using organic silane gas. It is also possible to form a layer. The organic silane gas is ethyl silicate (TEOS: Formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane silane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (Si H(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. The following silicon-containing compounds can be used:

[0057] The first insulating layer 402 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two or more of the following compounds are used: Compounds containing the above can also be used.

[0058] In this specification, an oxynitride is a compound having a composition in which oxygen atoms are more abundant than nitrogen atoms. Nitrided oxide refers to a substance with a higher number of nitrogen atoms than oxygen atoms. For example, a silicon oxynitride film has a composition that contains a large number of nitrogen atoms. The number of oxygen atoms is greater than that of electrons, and Rutherford backscattering (RBS) Backscattering Spectrometry and Hydrogen Forward Scattering (H When measured using FS (Hydrogen Forward Scattering) In this case, the concentration range is 50 atomic % or more and 70 atomic % or less for oxygen and 0.5 atomic % or more and 1.5 atomic % or less for nitrogen. 5 atomic % or less, silicon is 25 atomic % to 35 atomic % and hydrogen is 0.1 atomic % to 10 The silicon nitride oxide film is a film containing silicon dioxide in an amount of 0.1 atomic % or less. There are more nitrogen atoms than oxygen atoms, and the concentration is The range is 5 atomic % or more and 30 atomic % or less of oxygen, 20 atomic % or more and 55 atomic % or less of nitrogen, Silicon is between 25 atomic % and 35 atomic % and hydrogen is between 10 atomic % and 30 atomic % However, the atoms constituting silicon oxynitride or silicon nitride oxide are When the total of these is taken as 100 atomic %, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. shall be included within the scope.

[0059] Next, a thin film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the first insulating layer 402. An oxide semiconductor film 403 having a thickness of 20 nm or less is formed (FIG. 1A).

[0060] Note that before the oxide semiconductor film 403 was formed, argon gas was introduced to generate plasma. In this way, dust adhering to the surface of the first insulating layer 402 can be removed. Reverse sputtering is a method of sputtering a substrate in an argon atmosphere without applying a voltage to the target side. A method of modifying the surface by applying voltage to the substrate side using an RF power supply to generate plasma near the substrate. In place of the argon atmosphere, nitrogen, helium, etc. may be used. It may be performed in an atmosphere containing oxygen, N2O, etc. in an argon atmosphere. It may be performed in an atmosphere containing Cl2, CF4, etc. After the reverse sputtering process, it is necessary to expose it to the atmosphere. By forming the oxide semiconductor film without using the first insulating layer 402, the first insulating layer 402 and the oxide semiconductor film 40 This can prevent dust and moisture from adhering to the interface of 3.

[0061] The oxide semiconductor film is made of In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Z nO system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system , In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Alternatively, a Zn—O-based oxide semiconductor film can be used. , in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) atmosphere. It can be formed by sputtering in an atmosphere of argon and oxygen. When using the target deposition method, deposition is performed using a target containing 2% to 10% by weight of SiO2. The oxide semiconductor film may contain SiOx (x>0) which inhibits crystallization.

[0062] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: I n2O3:Ga2O3:ZnO=1:1:1 [molar ratio], or In2O3:Ga2 O3:ZnO=1:1:2 [molar ratio]) and the distance between the substrate and the target 100mm, pressure 0.6Pa, direct current (DC) power supply 0.5kW, oxygen (oxygen flow rate 100 %) atmosphere. When a pulsed direct current (DC) power supply is used, the This is preferred because it reduces powdery substances (also called particles or dust) and makes the film thickness distribution uniform. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor film. Using a film formation target, a 15 nm thick In-Ga-Zn-O system film was formed by sputtering. A film is formed.

[0063] Note that the thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the semiconductor material, and the thickness may be selected appropriately depending on the material.

[0064] In addition, it is preferable to form an oxide semiconductor film successively over the first insulating layer 402. The multi-chamber sputtering equipment is a silicon or silicon oxide (artificial quartz) ter and a target for an oxide semiconductor film. The deposition chamber in which the target is installed has a cryopump as an exhaust means. Instead of the lion pump, a turbo molecular pump is used, and water is placed on the intake port of the turbo molecular pump. A cold trap may be provided to adsorb the components.

[0065] The deposition chamber evacuated using a cryopump contains, for example, hydrogen atoms and hydrogen atoms such as H2O. Since compounds containing carbon atoms, carbon atoms, and compounds containing carbon atoms are exhausted, the film formation chamber The concentration of impurities contained in the deposited oxide semiconductor film can be reduced.

[0066] The oxide semiconductor film may be formed while the substrate is heated. The temperature is set to 200°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor film, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. do.

[0067] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to form insulating films, while the DC sputtering method is mainly used to form metal conductive films. It is used when forming a film.

[0068] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0069] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0070] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0071] Next, a second photolithography process is performed to form a resist mask, and an In-Ga-Z The nO film is etched using organic solvents such as citric acid and oxalic acid. Acid can be used as an etchant. By etching the surface into a tapered shape, it is possible to prevent the wiring from being cut off due to the step shape. The etching here is not limited to wet etching, but may be dry etching. It's fine.

[0072] Next, the oxide semiconductor layers 404a and 404b are dehydrated or dehydrogenated. Alternatively, the first heat treatment for dehydrogenation may be performed by resistance heating or lamp irradiation under an inert gas atmosphere. What method should be used? At 500℃ to 750℃ (or below the distortion point of the glass substrate) RTA for 1 minute or more and 10 minutes or less, preferably 650°C, 3 minutes or more and 6 minutes or less By using the RTA method, dehydration or dehydrogenation can be carried out in a short time. Therefore, the heat treatment can be performed at a temperature exceeding the strain point of the glass substrate. It is not limited to the timing of the above, but can be performed multiple times before and after the photolithography process or film formation process. good.

[0073] In this specification, the heat treatment under an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is also called heat treatment for dehydrogenation. Dehydrogenation does not only mean that H, OH, etc. are eliminated. For convenience, this process will be referred to as dehydration or dehydrogenation.

[0074] The heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is The reactor was used in the same furnace where the hydrogenation took place, without exposing it to the atmosphere and without re-contaminating it with water or hydrogen. It is important to lower the temperature as soon as possible. The nitride semiconductor layer is made n-type (n - , n + etc.) In other words, after reducing the resistance, oxygen is replenished. When a transistor is fabricated using an oxide semiconductor layer that has been made i-type by increasing the resistance by SiO 2 , The threshold voltage of the resistor can be set to a positive value, and the switch has a so-called normally-off characteristic. The gate voltage of the transistor is set to a positive threshold voltage as close as possible to 0V. It is desirable for a display device that a channel is formed by a voltage. If the gate voltage is negative, even if the gate voltage is 0V, a voltage is generated between the source and drain electrodes. Active matrix display devices are prone to current flow, which is known as normally-on characteristics. In this case, the electrical characteristics of the transistors that make up the circuit are important, and these electrical characteristics are displayed. The performance of the device is affected. In particular, the threshold voltage (Vth) of the transistor is an important electrical characteristic. Even if the field effect mobility is high, the threshold voltage is high, or If the threshold voltage is negative, it is difficult to control the circuit. In the case of a transistor with a large absolute value of the threshold voltage, the transistor The switching function of the n-channel transistor cannot be performed as a master, and the n-channel transistor may become a load. In the case of a diode-type transistor, a channel is formed only when a positive voltage is applied to the gate. A transistor in which the drain current flows out due to the applied voltage is desirable. There are transistors in which a channel is not formed, and transistors in which a channel is formed even under negative voltage conditions and a drain current is generated. A transistor through which current flows is unsuitable for use in a circuit.

[0075] In addition, the gas atmosphere when the temperature is lowered from the heating temperature T is the same as the gas atmosphere heated to the heating temperature T. For example, the same gas atmosphere as that used for dehydration or dehydrogenation may be used. The furnace is kept free from exposure to the atmosphere and is filled with high-purity oxygen gas or N2O gas, ultra-dry air, and Cooling is carried out by filling the tank with water (dew point of -40°C or less, preferably -60°C or less).

[0076] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0077] When the heat treatment is performed in an inert gas atmosphere, the oxide semiconductor layer It becomes oxygen deficient and has low resistance, i.e., it becomes n-type (n - Then, the oxide semiconductor layer By forming an oxide insulating layer in contact with the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be compensated for. This results in high resistance, i.e., i-type. This results in good electrical properties and reliability. Therefore, a transistor with good characteristics can be manufactured.

[0078] The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by thermal desorption spectroscopy. (TDS: Thermal Desorption Spectroscopy) 45 Even when the temperature was raised to 0°C, two peaks in the spectrum indicating the desorption of water were observed, at least 250-3 One peak that appears around 00°C is not detected.

[0079] Note that the oxide semiconductor layers 404a and 404b have many dangling bonds when they are formed. However, by carrying out the first heating step of the dehydration or dehydrogenation treatment, The dangling bonds at the distances bond with each other, forming an ordered amorphous structure. As the ordering progresses, a mixture of amorphous and microcrystalline regions with microcrystals scattered throughout the amorphous regions can be obtained, and The oxide semiconductor layers 404a and 404b are entirely amorphous, and the surface layers of the oxide semiconductor layers 404a and 404b are composed of nanocrystals. Crystal regions 405a and 405b are formed (FIG. 1B). The other regions of the layers 404a and 404b are amorphous, or amorphous with microcrystals scattered in the amorphous regions. The crystalline regions 405a and 405b are a mixture of crystalline and microcrystalline oxide semiconductor layers 404. Hereinafter, the oxide semiconductor layers 404a and 404b are referred to as crystalline oxide semiconductor layers. The regions 405a and 405b are included. The grain size of the microcrystals is 1 nm or more. These are so-called nanocrystals of 20 nm or less, and are generally called microcrystals. It is smaller in size than the microcrystalline particles.

[0080] In the crystalline regions 405a and 405b, the c-axis is oriented perpendicular to the film surface. Preferably, nanocrystals are formed, with the long axis along the c-axis and the short axis along the 1 It is preferable that the thickness is between 20 nm and 20 nm.

[0081] Depending on the order of steps, a crystalline region may not be formed on the side surface of the oxide semiconductor layer. However, the area ratio of the side surface is small. Even if the temperature is low, the effect of preventing deterioration of electrical characteristics can be maintained.

[0082] After the first heat treatment, the oxide semiconductor layers 404a and 404b become oxygen-deficient. The carrier concentration is higher than 1×10 18 / cm 3 With a carrier concentration of As a result, the resistance of the oxide semiconductor layers 404a and 404b is reduced.

[0083] The gate electrode layer 421 may also be crystallized depending on the conditions of the first heat treatment or the material. For example, the gate electrode layer 421 may be made of an oxide film. When indium tin oxide is used, it is crystallized by the first heat treatment at 450°C for 1 hour, but when silicon oxide is used, When indium oxide tin oxide containing ZnO is used, crystallization is unlikely to occur.

[0084] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography step for processing into an island-shaped oxide semiconductor layer.

[0085] Next, although not shown, a gate electrode layer and a source electrode layer or a drain electrode layer (to be described later) are formed. An opening (also called a contact hole) for connecting layers is formed in the first insulating layer 402. A mask is formed on the first insulating layer 402 by photolithography, inkjet printing, or the like. The first insulating layer 402 is selectively etched using the mask to form contacts. The contact holes are formed by oxidizing the first insulating layer 402 after the first insulating layer 402 is formed. This may be performed before the formation of the compound semiconductor film 403 .

[0086] Next, a thin film is formed on the oxide semiconductor layers 404a and 404b by sputtering, vacuum deposition, or the like. Conductive films of W, Ta, Mo, Ti, Cr, etc., or alloys combining the above elements The conductive film is 100 nm to 500 nm, preferably 200 nm to 300 nm. The conductive film is not limited to a single layer containing the above-mentioned elements, but may be formed to a thickness of two or more layers. Note that the conductive film can be formed by at least the second heat treatment to be performed later. It is preferable that the material has a heat resistance that can be endured.

[0087] The conductive film may be a transparent conductive oxide containing indium, tin, or zinc. For example, indium oxide (In2O3) or an indium oxide tin oxide alloy ( It is preferable to use In2O3-SnO2 (abbreviated as ITO). A transparent conductive oxide containing an insulating oxide such as silicon oxide may be used. By using the conductive film, the aperture ratio of the display device can be improved.

[0088] The conductive film in contact with the oxide semiconductor layers 404a and 404b is made of a material containing a metal with high oxygen affinity. Metals with high oxygen affinity are preferably titanium (Ti), manganese (Mn), magnesium (Mg), and the like. Magnesium (Mg), zirconium (Zr), beryllium (Be), or thorium (Th) In this embodiment, the material is preferably a titanium film. is used.

[0089] When an oxide semiconductor layer is formed in contact with a conductive film having high oxygen affinity, the carrier density near the interface The amount of the oxide semiconductor increases, a low-resistance region is formed, and the contact resistance between the oxide semiconductor and the conductive film can be reduced. This is because the conductive film with high oxygen affinity extracts oxygen from the oxide semiconductor layer. At the interface between the oxide semiconductor layer and the conductive film, a layer containing excess metal in the oxide semiconductor layer (also called a composite layer) is formed. This is due to the formation of either a thin film or an oxidized conductive film, or both. For example, in a configuration in which an In-Ga-Zn-O-based oxide semiconductor layer is in contact with a titanium film, A layer containing excess indium and a titanium oxide layer are formed near the interface between the oxide semiconductor layer and the titanium film. Indium oxide may be generated near the interface between the oxide semiconductor layer and the titanium film. Either an excessive titanium layer or a titanium oxide layer may form. Oxygen is lost from the O-based oxide semiconductor layer, and the layer with excess indium has high electrical conductivity and is This can reduce the contact resistance between the compound semiconductor layer and the conductive film.

[0090] Note that a conductive titanium oxide film may be used as the conductive film in contact with the oxide semiconductor layer. In this case, in a configuration in which an In-Ga-Zn-O-based oxide semiconductor layer and a titanium oxide film are in contact with each other, In this case, a layer containing excessive indium is generated near the interface between the oxide semiconductor layer and the titanium oxide film. This may be achieved.

[0091] The conductive film can be formed by arc discharge ion plating or spraying. Alternatively, a conductive nanopaste such as silver, gold, or copper may be used for the screen printing method. It may be formed by discharging using an ink jet method or the like and baking it.

[0092] Next, a mask is formed on the conductive film by photolithography, ink jetting, or the like. The conductive film is then etched using the mask to form source electrode layers 455a and 455c. In this embodiment, the conductive film is formed on the conductive electrode layers 455b and 455d. A 200 nm thick Ti film was formed as a resist mask by sputtering. The conductive film is selectively etched by wet etching or dry etching to form a Source electrode layers 455a and 455c and drain electrode layers 455b and 455d are formed.

[0093] Next, the source electrode layers 455a and 455c, the drain electrode layers 455b and 455d, and the exposed A second insulating layer 428 is formed to cover the oxide semiconductor layers 404a and 404b (FIG. 1(D)). The second insulating layer 428 is a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like. An oxide insulating film such as a tantalum oxide film can be used for the second insulating layer 428. serves as a gate insulating layer for the transistor 450.

[0094] Note that the second insulating layer 428 functioning as a gate insulating layer of the transistor 450 is a stacked film When the second insulating layer is formed using a laminated film, the first layer (oxide Silicon oxide film, silicon oxynitride film, aluminum oxide film The second and subsequent layers are not limited to oxides, but may be nitrides. A first insulating layer 40 such as silicon oxide, silicon nitride, aluminum oxide, or tantalum oxide A film can be formed using the same materials as in 2.

[0095] The second insulating layer 428 is formed by mixing impurities such as water and hydrogen into an oxide insulating film by a method such as sputtering. In this embodiment, the second insulating layer and the The silicon oxide film is formed by sputtering. The substrate temperature during film formation is set to 300°C above room temperature. In this embodiment, the temperature is set to 100° C. Here, water, hydrogen As a method to prevent the inclusion of impurities such as fluorine, the film is heated to 150°C or higher and 350°C or lower under reduced pressure before film formation. Pre-bake at 375°C for 2 to 10 minutes, and then apply the second insulating layer without exposing it to the air. It is desirable to form a silicon oxide film by sputtering. In an atmosphere of noble gas (typically argon), oxygen, or a mixture of noble gas (typically argon) and oxygen, The target may be a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and rare earth elements. Silicon oxide can be formed by sputtering in a gas atmosphere. The oxide insulating film formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, and OH - etc. An inorganic insulating film that does not contain impurities and blocks the intrusion of these impurities from the outside is preferred.

[0096] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0097] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. RTA treatment may be performed for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor The conductor layers are heated in contact with each other. Oxygen is supplied to the oxide semiconductor layers 404a and 404b that have been made resistive, and oxygen vacancies are compensated for. Therefore, it is possible to make it highly resistive (i-type).

[0098] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if it is done after the silicon dioxide film is formed, and it is not limited to being done immediately after the silicon oxide film is formed.

[0099] Next, a photolithography process is performed to form a resist mask, and the second insulating layer 428 A contact hole reaching the drain electrode layer 455d is formed by etching. After forming a conductive film over the second insulating layer 428, a photolithography process is performed on the conductive film. This is performed to form a gate electrode layer 421 and a connection electrode layer 44 which will be connected to the pixel electrode layer in a later process. 2 is formed (Fig. 1(E)). The conductive film can be made of Al, Cr, Cu, Ta, Ti, Mo, A film containing an element selected from W can be used as a single layer or a laminated layer. When the drain electrode layer 455d and the pixel electrode layer are directly connected to each other, the connection electrode layer 442 is omitted. That's fine.

[0100] Although not shown, in this step, a region overlapping with a channel formation region of the oxide semiconductor layer 404b is formed. A conductive layer may be formed at a position overlapping with a channel formation region of the oxide semiconductor layer 404b. By providing a conductive layer in the device, the reliability of the transistor can be improved. The transistor 440 is subjected to a bias-thermal stress test (hereinafter referred to as B In the BT test, the change in the threshold voltage of the transistor before and after the BT test is The conductive layer may have the same potential as the gate electrode layer 451. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential may be GND, 0V, or may be in a floating state.

[0101] Note that a protective insulating layer may be formed to cover the transistors 440 and 450. The layer may be a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or the like.

[0102] Further, a planarization insulating layer may be provided over the transistors 440 and 450. For example, heat-resistant materials such as acrylic, polyimide, benzocyclobutene, polyamide, and epoxy are used. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) ) can be used. It is also possible to laminate multiple insulating layers made of these materials. Furthermore, the color filter layer can also be used as a planarizing insulating layer.

[0103] In addition, the gate electrode layer 451 and the capacitor wiring, which can be manufactured using the same material and process as the gate electrode layer 451, are The insulating layer 402 or the second A storage capacitor sandwiching a dielectric including the insulating layer 428 may also be formed on the same substrate. The pixel section is configured by arranging the capacitors 440 and the storage capacitors in a matrix corresponding to the individual pixels. By arranging a driving circuit section having a transistor 450 around the element section, an active matrix It can be used as one of the substrates for manufacturing a trix type display device.

[0104] In addition, when a display device is manufactured using the transistors 440 and 450, A power supply line is provided which is electrically connected to the source electrode layer of the gate electrode. and is formed of the same material and in the same process as the connection electrode layer 442 made of a metal conductive film. .

[0105] In addition, when a light emitting device is manufactured, one electrode of the light emitting element is connected to the source electrode of the driving transistor. The electrode layer or drain electrode layer is electrically connected to the other electrode of the light-emitting element. The common potential line is connected to the connecting electrode layer 4 made of a metal conductive film. Alternatively, the common potential line may be formed of the same material and in the same process as the gate electrode layer 451. It is made from the same material and through the same process.

[0106] When a transistor is manufactured by the above method, the oxide semiconductor layers 404a and 404b The hydrogen concentration was reduced, and the off-state current of the transistor was reduced to 1×10 -13 A or less. The hydrogen concentration is sufficiently reduced and the oxide semiconductor layers 404a and 404b are highly purified. By applying the above, a transistor with excellent characteristics can be obtained.

[0107] In addition, examples of semiconductor materials that can be compared with oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The Fermi-Dirac distribution at room temperature is used to calculate the lattice density of oxide semiconductors. The body's minority carriers are 10 -7 / cm 3 This is estimated to be about 6.7 x 10 -11 / cm3 This is an extremely low value, similar to the intrinsic carriers in silicon. Density (1.4×10 10 / cm 3 Compared to the degree of I can understand that very well.

[0108] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0109] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. For example, activation of dopants in silicon carbide typically requires 1500°C. Since heat treatment at temperatures up to 2000°C is required, it is difficult to carbonize semiconductor elements made of other semiconductor materials. It is difficult to form semiconductor devices using silicon. On the other hand, oxide semiconductors have a resistance of 300 to 5 It can be produced by heat treatment at 00°C (below the glass transition temperature, at most about 700°C). In this case, an integrated circuit is formed using other semiconductor materials, and then a semiconductor element is formed using an oxide semiconductor. It is possible to form the following.

[0110] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, it has the advantage that it does not require high-temperature heat treatment, making it more energy efficient than silicon carbide. This has the advantage that the energy cost can be sufficiently reduced.

[0111] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type can be achieved by removing water and hydrogen. It can be said that this is not an i-type product made by adding pure substances, but rather involves a technological concept that has never been seen before.

[0112] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 22 to 26. The following explanation is merely a consideration, and the validity of the invention is not denied based on this. It should be noted that this is not a

[0113] FIG. 22 is a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the electrode (GE1) via a gate insulating film (GI), A source electrode (S) and a drain electrode (D) are provided on the insulating layer. A back gate (GE2) is provided via the edge layer.

[0114] FIG. 23 shows an energy band diagram (schematic diagram) between A and A' shown in FIG. 3(A) is the voltage between the source and drain as equipotential (V D = 0), as shown in Figure 23. (B) A positive potential (V D >0) is added.

[0115] 25 and 26 show energy band diagrams (schematic diagrams) between B and B' in FIG. FIG. 25 shows the state when the gate voltage is 0V. FIG. 26(A) shows the state when the gate (GE1) is positive. potential (V G >0) is applied, and carriers (electrons) are generated between the source and drain. 26(B) shows the ON state where a negative potential (V G<0) is applied, and the transistor is in the off state (no minority carriers flow). vinegar.

[0116] The thickness of the oxide semiconductor is about 50 nm, and the oxide semiconductor is highly purified, so The concentration of toner is 1×10 18 / cm 3 If the depletion layer is below 1000 kJ / s, the entire oxide semiconductor It can be considered as a fully depleted state.

[0117] Figure 24 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0118] Conventional oxide semiconductors are generally n-type, and in this case the Fermi level (Ef) is It is located closer to the conduction band, away from the intrinsic Fermi level (Ei) located in the center of the gap. It is known that hydrogen acts as a donor in oxide semiconductors and is one of the factors that makes them n-type. It is being done.

[0119] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. By removing impurities other than the main components of the oxide semiconductor and purifying it to the utmost, It is intrinsic (type i) or intended to be intrinsic. Instead of turning it into i-type, we have removed impurities such as hydrogen and water as much as possible to create a highly purified i The feature of this method is that it is an intrinsic semiconductor or close to it. The Fermi level (Ef) can be made to be the same as the intrinsic Fermi level (Ei).

[0120] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The electron affinity function is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the interface between the layers, no Schottky barrier is formed for electrons.

[0121] That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the surface, an energy band diagram (schematic diagram) such as that shown in FIG. 23(A) is displayed.

[0122] In Figure 23(B), the black circles (●) represent electrons, and a positive voltage (V D >0) is applied If no voltage is applied to the gate (V G =0) is shown by a dashed line, and a positive voltage is applied to the gate (V G The solid line shows the case where a positive voltage (V G >0) is applied. In this case, when a positive potential is applied to the drain, electrons cross the barrier (h) and are injected into the oxide semiconductor. In this case, the height of the barrier (h) is determined by the gate voltage and the drain voltage. The gate voltage (V G >0) is applied to the positive drain When a voltage is applied, the barrier height, i.e., the band, of Figure 23(A) without voltage application The barrier height (h) is smaller than half the gap (Eg). When no voltage is applied, the high potential barrier prevents carriers from flowing from the electrode to the oxide semiconductor. This indicates the off state, where no electrons are injected and no current flows. On the other hand, when a positive voltage is applied to the gate, As a result, the potential barrier decreases, and the device enters an on-state where current flows.

[0123] At this time, the electrons injected into the oxide semiconductor pass through the oxide semiconductor as shown in FIG. In addition, in FIG. 26(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. become.

[0124] In this way, the oxide semiconductor is highly purified so that it does not contain impurities other than the main component as much as possible. By making it intrinsic (i-type) or substantially intrinsic, the interface characteristics with the gate insulating film Therefore, the gate insulating film is required to be separated from the bulk characteristics. It is necessary to have a good interface with the semiconductor. For example, VHF band to microwave band An insulating film or a silicon dioxide film is produced by a CVD method using high density plasma generated at a power supply frequency of 1000 kHz. It is preferable to use an insulating film formed by a sputtering method.

[0125] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating film is improved. As a result, the transistor characteristics are such that the channel width W is 1×10 4 The channel length in μm Even with a 3 μm element, the off-state current at room temperature is 10 -13 A or less, and A threshold swing (S value) of 0.1V / dec. (gate insulating film thickness 100nm) is fully expected. Be waited for.

[0126] In this way, it is possible to purify the oxide semiconductor to the extent possible so that it does not contain impurities other than the main component. As a result, the operation of the transistor can be improved.

[0127] In this embodiment, the channel formation region of the transistor 450 is formed in the oxide semiconductor layer 40 4a, a region in contact with the source electrode layer 455a and a region in contact with the drain electrode layer 455b The second insulating layer 428 is sandwiched between the first insulating layer 428 and the second insulating layer 428, and overlaps with the gate electrode layer 421. In the transistor 450, the oxide semiconductor layer in contact with the first insulating layer 402 The region is amorphous or a mixture of amorphous and microcrystalline, and the surface layer in contact with the second insulating layer 428 Therefore, the channel formation region is formed in the oxide semiconductor layer 404a. The oxide semiconductor layer 404a is also a crystalline region, and the c-axis (ca xis) are oriented. For example, In-Ga-Zn-O oxide semiconductor materials When using a material, the c-axis of the crystal grains is aligned with the substrate plane (or the surface of the oxide semiconductor layer). By aligning the nanocrystals in the vertical direction, The direction of the current is the b-axis (or a-axis) direction of the crystal grain. 0 realizes high dynamic characteristics (on characteristics and frequency characteristics (called f characteristics)), for example, high speed This is suitable as a transistor to be used in a drive circuit section where operation is required.

[0128] The channel formation region of the transistor 440 is formed in the source region of the oxide semiconductor layer 404b. The first electrode layer 455c is sandwiched between a region in contact with the source electrode layer 455a and a region in contact with the drain electrode layer 455b. This region is in contact with the insulating layer 402 and overlaps with the gate electrode layer 451. The oxide semiconductor layer is made i-type or substantially i-type by the above process (highly purified oxide semiconductor). The carrier concentration in the oxide semiconductor layer is suppressed. The dense crystalline region composed of nanocrystals exists on the opposing surface, which prevents moisture from re-entering from the surface. Therefore, the transistor having the oxide semiconductor layer can be prevented from becoming n-type due to the penetration or desorption of oxygen. The resistor 440 offers extremely low off-state current and excellent reliability, including low leakage current. This is suitable for a transistor used in a pixel portion where reduction in charge is required.

[0129] As described above, in the driver circuit section and the pixel section, an oxide film having a crystalline region on one surface (surface layer) is used. Two types of transistors were formed using a nitride semiconductor layer as the active layer, and the gate electrode layer was By selecting the region where the channel is formed, the electrical characteristics of the transistor can be selected. In addition, a semiconductor device having a driver circuit section and a pixel section that can operate at high speed on the same substrate can be used. You can create devices.

[0130] Note that this embodiment mode can be freely combined with other embodiment modes.

[0131] (Embodiment 2) In this embodiment mode, a semiconductor device and a manufacturing method thereof different from those in Embodiment Mode 1 will be described. This will be explained with reference to FIG. 2. In this embodiment, the same parts as those in the first embodiment and The parts and steps having the same functions as those in the first embodiment can be carried out in the same manner as in the first embodiment, and can be repeated. The explanation of this will be omitted.

[0132] First, a substrate having an insulating surface is prepared according to the steps shown in FIGS. 1(A) and 1(B) of the first embodiment. A gate electrode layer 451, a first insulating layer 402, and an island-shaped oxide semiconductor layer 453 are formed over a substrate 400. The oxide semiconductor layers 404a and 404b are formed (FIG. 2A). The surface layers of 404a and 404b are crystallized by the first heat treatment and consist of nanocrystals. The oxide semiconductor layers 404a and 405b have crystalline regions 405a and 405b. The other regions of 4b are amorphous or amorphous with microcrystals scattered in the amorphous regions and microcrystals. The crystalline regions 405a and 405b are formed by the oxide semiconductor layers 404a and 404b. 4b, and hereinafter, when the oxide semiconductor layers 404a and 404b are referred to, the crystalline region 40 5a, 405b are included.

[0133] After the first heat treatment, the oxide semiconductor layers 404a and 404b become oxygen-deficient. The carrier concentration is higher than 1×10 18 / cm 3 With a carrier concentration of As a result, the resistance of the oxide semiconductor layers 404a and 404b is reduced.

[0134] The gate electrode layer 451 may also be crystallized depending on the conditions of the first heat treatment or the material. For example, the gate electrode layer 451 may be made of an oxide film. When indium tin oxide is used, it is crystallized by the first heat treatment at 450°C for 1 hour, but when silicon oxide is used, When indium oxide tin oxide containing ZnO is used, crystallization is unlikely to occur.

[0135] Next, although not shown, a gate electrode layer and a source electrode layer or a drain electrode layer (to be described later) are formed. An opening (also called a contact hole) for connecting layers is formed in the first insulating layer 402. A mask is formed on the first insulating layer 402 by photolithography, inkjet printing, or the like. The first insulating layer 402 is selectively etched using the mask to form contacts. The contact holes are formed by oxidizing the first insulating layer 402 after the first insulating layer 402 is formed. This may be performed before the formation of the compound semiconductor film 403 .

[0136] Next, an oxide conductive layer was formed over the first insulating layer 402 and the oxide semiconductor layers 404a and 404b. The oxide conductive layer 480 and the metal conductive film 482 are laminated together. The lamination of the metal conductive film 482 and the silicon dioxide film 480 can be performed continuously without exposure to the air ( See Figure 2(B)).

[0137] The oxide conductive layer 480 may be made of any of the above-described materials applicable to the gate electrode layer 451, including visible light. It is preferable to use a conductive material that transmits light. Indium tin oxide containing

[0138] The metal conductive film 482 is made of a material selected from Ti, Mo, W, Al, Cr, Cu, and Ta. The elements mentioned above, or alloys containing the elements mentioned above, or alloys combining the elements mentioned above, etc. In addition, the layer is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers may be used. The conductive film can be formed by sputtering, vacuum deposition (electron beam deposition, etc.), or Arc discharge ion plating or spraying is used. In this embodiment, sputtering is used. Titanium formed by the method described above is used.

[0139] Next, a resist mask is formed by a photolithography process, and the metal conductive film 482 is selected. The source electrode layer 484 of the transistor 470 disposed in the driving circuit section is selectively etched. After the drain electrode layer 484b is formed, the resist mask is removed. The metal conductive film 482 is etched away so as not to remain on the transistor 460 to be formed.

[0140] Next, a resist mask is formed by a photolithography process, and the oxide conductive layer 480 is The source electrode layer 48 of the transistor 470 disposed in the driving circuit section is selectively etched. The oxide conductive layer 486a overlapping the drain electrode layer 484a, and the oxide conductive layer 48 6b, the source electrode layer 486c and the drain electrode layer 486d of the transistor 460 disposed in the pixel portion After the electrode layer 486d is formed, the resist mask is removed (see FIG. 2(C)).

[0141] Here, the oxide conductive layer 480 is etched using a mixed acid containing phosphoric acid, acetic acid, and nitric acid. For example, a solution consisting of 72.3% phosphoric acid, 9.8% acetic acid, 2.0% nitric acid, and 15.9% water is The oxide conductive layer 480 and the oxide semiconductor layers 404a and 404b can be used. Since the compositions of these materials are similar, the etching selectivity is often small. The oxide conductive layer (indium tin oxide containing silicon oxide) used in this embodiment is amorphous. A group of nanocrystals is formed on the surface of the oxide semiconductor layer (In-Ga-Zn-O film). Therefore, a relatively large etching selectivity can be obtained. The grafting rate of the oxide conductive layer was 18.6 nm / sec., while that of the nanocrystals was 18.6 nm / sec. The growth rate of the oxide semiconductor layer in which the crystal groups were formed was 4.0 nm / sec. By etching with the mixed acid under time control, the oxide semiconductor layer on the surface of the lower oxide semiconductor layer can be removed. The nanocrystal clusters can be left largely unetched.

[0142] Further, an oxide conductive layer is provided between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. This reduces the contact resistance and realizes a transistor capable of higher speed operation. The source electrode layer 484a of the transistor 470 provided in the driver circuit section and the oxide semiconductor The oxide conductive layer 486a provided between the oxide conductive layer 404a and the gate electrode 404b functions as a source region, and the drain region An oxide conductive layer 486b provided between the electrode layer 484b and the oxide semiconductor layer 404a functions as a drain region, and therefore is used to improve the frequency characteristics of the peripheral circuit (drive circuit). It is effective for this purpose.

[0143] On the other hand, the source electrode layer 486c and the drain electrode layer 486d of the transistor 460 disposed in the pixel portion Since the layer 486d is formed using a light-transmitting conductive oxide layer, the aperture ratio can be improved. can.

[0144] Next, the source electrode layers 484a and 486c, the drain electrode layers 484b and 486d, and the exposed A second insulating layer 428 is formed to cover the oxide semiconductor layers 404a and 404b. The edge layer 428 may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or a tantalum oxide film. The second insulating layer 428 can be an oxide insulating layer such as a thin film. It serves as a gate insulating layer for the gate electrode 470.

[0145] Note that the second insulating layer 428 functioning as a gate insulating layer of the transistor 470 is a stacked film When the second insulating layer 428 is formed using a stacked film, one layer The layer in contact with the oxide semiconductor layer is made of silicon oxide, silicon oxynitride, or aluminum oxide. The second and subsequent layers are not limited to oxides. The first insulating material is silicon oxide nitride, silicon nitride, aluminum oxide, tantalum oxide, etc. A film using a material similar to that of the layer 402 can be formed.

[0146] The second insulating layer 428 is formed by mixing impurities such as water and hydrogen into an oxide insulating film by a method such as sputtering. In this embodiment, the second insulating layer and the The silicon oxide film is formed by sputtering. The substrate temperature during film formation is set to 300°C above room temperature. In this embodiment, the temperature is set to 100° C. Here, water, hydrogen As a method to prevent the inclusion of impurities such as fluorine, the film is heated to 150°C or higher and 350°C or lower under reduced pressure before film formation. Pre-bake at 375°C for 2 to 10 minutes, and then apply the second insulating layer without exposing it to the air. It is desirable to form a silicon oxide film by sputtering. In an atmosphere of noble gas (typically argon), oxygen, or a mixture of noble gas (typically argon) and oxygen, The target may be a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and rare earth elements. Silicon oxide can be formed by sputtering in a gas atmosphere. The oxide insulating film formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, and OH - etc. An inorganic insulating film that does not contain impurities and blocks the intrusion of these impurities from the outside is preferred.

[0147] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0148] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. RTA treatment may be performed for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor The conductor layers are heated in contact with each other. Oxygen is supplied to the oxide semiconductor layers 404a and 404b that have been made resistive, and oxygen vacancies are compensated for. Therefore, it is possible to make it highly resistive (i-type).

[0149] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if it is done after the silicon dioxide film is formed, and it is not limited to being done immediately after the silicon oxide film is formed.

[0150] Next, a photolithography process is performed to form a resist mask, and the second insulating layer 428 A contact hole reaching the drain electrode layer 486d is formed by etching. After forming a conductive film over the second insulating layer 428, a photolithography process is performed on the conductive film. This is performed to form a gate electrode layer 421 and a connection electrode layer 44 which will be connected to the pixel electrode layer in a later process. 2 is formed (Fig. 2(D)). The conductive film can be made of Al, Cr, Cu, Ta, Ti, Mo, A film containing an element selected from W can be used as a single layer or a laminated layer. When the drain electrode layer 486d and the pixel electrode layer are directly connected to each other, the connection electrode layer 442 is omitted. That's fine.

[0151] Although not shown, in this step, a region overlapping with a channel formation region of the oxide semiconductor layer 404b is formed. A conductive layer may be formed at a position overlapping with a channel formation region of the oxide semiconductor layer 404b. By providing a conductive layer in the transistor 460, the reliability of the transistor 460 can be improved. Specifically, in a BT test to check the reliability of a transistor, In addition, the conductive layer can reduce the amount of change in the threshold voltage of the transistor. The position of the gate electrode layer 451 may be the same as or different from the gate electrode layer 451. The potential of the conductive layer can be set to GND, 0V, or floating. It may be in a locked state.

[0152] In this embodiment, the channel formation region of the transistor 470 is formed in the oxide semiconductor layer 40 4a, a region in contact with the oxide conductive layer 486a and a region in contact with the oxide conductive layer 486b The region is sandwiched between the first insulating layer 428 and the second insulating layer 428, and overlaps with the gate electrode layer 421. In addition, in the transistor 470, a region of the oxide semiconductor layer in contact with the first insulating layer 402 The surface area is amorphous or a mixture of amorphous and microcrystalline. Therefore, the channel formation region is a crystalline region of the oxide semiconductor layer 404a. The c-axis (c-ax) of the oxide semiconductor layer 404a is perpendicular to the surface of the oxide semiconductor layer 404a. For example, an In-Ga-Zn-O oxide semiconductor material When using a semiconductor layer, the c-axis of the crystal grains is perpendicular to the substrate plane (or the surface of the oxide semiconductor layer). By aligning the nanocrystals in a perpendicular direction, the current in transistor 470 The direction of the flow is the b-axis (or a-axis) direction of the crystal grain. realizes high dynamic characteristics (on-state characteristics and frequency characteristics (called f characteristics)), and This is suitable for transistors used in drive circuits where high performance is required.

[0153] In addition, a thin film transistor 470 is provided between the source electrode layer 484a and the oxide semiconductor layer 404a. The oxide conductive layer 486a functions as a source region, and the oxide conductive layer 486b and the drain electrode layer 484b are The oxide conductive layer 486b provided between the oxide semiconductor layer 404a and the gate insulating layer 404b functions as a drain region. This is effective in improving the frequency characteristics of peripheral circuits (drive circuits).

[0154] The channel formation region of the transistor 460 is formed in the source region of the oxide semiconductor layer 404b. The first electrode layer 486c is sandwiched between a region in contact with the source electrode layer 486c and a region in contact with the drain electrode layer 486d. This region is in contact with the insulating layer 402 and overlaps with the gate electrode layer 451. The oxide semiconductor layer is made i-type or substantially i-type by the above process (highly purified oxide semiconductor). The carrier concentration in the oxide semiconductor layer is suppressed. The dense crystalline region composed of nanocrystals exists on the opposing surface, which prevents moisture from re-entering from the surface. Therefore, the transistor having the oxide semiconductor layer can be prevented from becoming n-type due to the penetration or desorption of oxygen. The transistor 460 offers extremely low off-state current and excellent reliability, including low leakage current. This is suitable for a transistor used in a pixel portion where reduction in charge is required.

[0155] In the transistor 460, the gate electrode layer 451, the source electrode layer 486c, and the The rain electrode layer 486d is formed of a conductive layer having light-transmitting properties, and therefore the aperture ratio can be improved. This can be done.

[0156] As described above, in the driver circuit section and the pixel section, an oxide film having a crystalline region on one surface (surface layer) is used. Two types of transistors were formed using a nitride semiconductor layer as the active layer, and the gate electrode layer was By selecting the region where the channel is formed, the electrical characteristics of the transistor can be selected. In addition, a semiconductor device having a driver circuit portion and a pixel portion capable of high-speed operation on the same substrate can be provided. can be created.

[0157] Note that this embodiment mode can be freely combined with other embodiment modes.

[0158] (Embodiment 3) In this embodiment, an example of the structure of a terminal portion provided on the same substrate as a transistor is shown in FIG. 10, the same parts as those in FIG. 1 will be described using the same reference numerals.

[0159] 10(A1) and 10(A2) are a cross-sectional view and a top view of the gate line terminal portion, respectively. FIG. 10(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 10(A2). In FIG. 10(A1), the conductive layer 415 formed on the second insulating layer 428 is It is a terminal electrode for connection that functions as a terminal. The first terminal 411 is made of the same material as the gate wiring of the transistor 440, and the source The connection electrode 412 made of the same material as the wiring is overlapped with the first insulating layer 402 interposed therebetween. The connection electrode 412 and the conductive layer 415 are in contact with the second insulating layer 428. The electrodes are in direct contact with each other through contact holes provided therein for electrical continuity.

[0160] 10(B1) and 10(B2) are a cross-sectional view and a top view of a source wiring terminal portion. Also, Fig. 10(B1) is taken along the line C3-C4 in Fig. 10(B2). In FIG. 10(B1), a conductive layer formed on the second insulating layer 428 is The layer 418 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, the electrode layer 4 is made of the same material as the gate wiring of the transistor 440. 16 is formed on the first insulating layer 402 below the second terminal 414 electrically connected to the source wiring. The electrode layer 416 is not electrically connected to the second terminal 414, and the electrode layer 416 is set to a potential different from that of the second terminal 414, for example, floating, GND, 0V, etc. By setting the capacitor, it is possible to form a capacitance for noise countermeasures or static electricity countermeasures. The second terminal 414 is electrically connected to the conductive layer 418 via the second insulating layer 428. It continues.

[0161] A plurality of gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. In addition, in the terminal section, a first terminal having the same potential as the gate wiring, a source wiring, a second terminal at the same potential as the line, a third terminal at the same potential as the power supply line, and a fourth terminal at the same potential as the common potential line. The number of each terminal can be set to any number. The implementer should decide as appropriate. The terminal connection should be as shown in Figure 10. It is not limited to the above.

[0162] This embodiment mode can be freely combined with other embodiment modes.

[0163] (Fourth embodiment) In this embodiment, as a semiconductor device according to one embodiment of the present invention, two types of transistors are provided over the same substrate. A pulse output circuit is created using a shift register, and multiple pulse output circuits are connected to form a shift register. An example of the configuration of the register will be described with reference to FIGS.

[0164] A transistor is a device having at least three terminals including a gate, a drain, and a source. The element has a channel region between the drain region and the source region, A current can flow through the in-region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is difficult to know which is the source or drain. Therefore, it is difficult to define whether the source or drain is the In some cases, the region that functions as a source or drain is not called a source or drain. In this case, they may be referred to as the first terminal and the second terminal, respectively.

[0165] FIG. 3A shows the configuration of the shift register. The shift register includes the first pulse output circuit 1 The pulse output circuit 10_N includes pulse output circuits 0_1 to N (N is a natural number of 3 or more).

[0166] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to the first wiring 11, the second wiring 12, the third wiring 13, and the fourth wiring 14 are connected to the first wiring 1 1 transmits a first clock signal CK1, and a second clock signal CK2 transmits from the second wiring 12. A third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. No. CK4 will be supplied.

[0167] The clock signal (CK) goes high (high signal, high power supply potential level) at regular intervals. It is a signal that alternates between a high level (also called a low signal or low power supply potential level) and a low level (also called a low signal or low power supply potential level). Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially clocked at 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are delayed by one period. The clock signal (CK4) is used to control the driving of the pulse output circuit. Depending on the input drive circuit, it may be called GCK or SCK, but here it is called CK. and provide an explanation.

[0168] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 3(B)). Although not shown, the power supply lines 51, 52, and 53 are connected to the power supply lines 51, 52, and 53. .

[0169] The first input terminal 21, the second input terminal 22, and the third input terminal 23 of the pulse output circuit are It is electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. In A), the first pulse output circuit 10_1 has a first input terminal 21 connected to a first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. are actively connected.

[0170] In addition, in the first pulse output circuit 10_1, a start pulse SP1 ( The first start pulse is input to the n-th pulse output circuit 10_n in the second stage or later. (n is a natural number between 2 and N), the signal from the previous stage pulse output circuit (previous stage signal OUT(n-1) (n is a natural number greater than or equal to 2) is input.

[0171] In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages later, Similarly, in the n-th pulse output circuit 10_n at the second stage or later, The signal from the (n+2)th pulse output circuit 10_(n+2) of the stage (the subsequent signal OUT(n+ 2) is input. Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or the second stage. A first output signal OUT((1)(SR) to OU) is input to the pulse output circuit of the previous stage. T(N)(SR)), a second output signal (OUT(1)~ OUT(N)) is output.

[0172] That is, in the first pulse output circuit 10_1, a first clock is input to a first input terminal 21. A clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, A third clock signal CK3 is input to the third input terminal 23, and a start signal CK4 is input to the fourth input terminal 24. A first pulse is input to the fifth input terminal 25, a second signal OUT(3) is input to the fifth input terminal 26, and a first The first output signal OUT(1)(SR) is output from the output terminal 26, and the second output terminal 27 As a result, the second output signal OUT(1) is output.

[0173] As shown in FIG. 3(A), the last two stages of the shift register (10_N-1, and The next stage signal OUT(n+2) is not input to the first stage (10_N). The sixth wiring 16 outputs the second start pulse SP2, and the seventh wiring 17 outputs the third start pulse SP3. Alternatively, you can configure the shift register to input the pulses SP3 and SP4. For example, the (N+1)th signal that does not contribute to the pulse output to the pixel unit may be used. ) pulse output circuit 10_(N+1), (N+2)th pulse output circuit 10_(N+2) (also called a dummy stage), and a second start pulse (SP2) and Alternatively, a signal equivalent to the start pulse (SP3) of No. 3 may be generated.

[0174] Next, the structure of a pulse output circuit of one embodiment of the present invention will be described with reference to FIG.

[0175] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to a power supply line 51 to a power supply The power supply line 51 is connected to a first high power supply potential VDD, and the power supply line 52 is connected to a second high power supply potential VDD. The power supply line 51 supplies a high power supply potential VCC, and the power supply line 53 supplies a low power supply potential VSS. The magnitude relationship of the power supply potential of the power supply line 53 is, for example, as follows: The potential is equal to or higher than the second high power supply potential VCC, and the second high power supply potential VC The potential C is higher than the low power supply potential VSS. By making the potential of the power supply line 51 lower than VDD, the transistor The potential applied to the gate electrode of the transistor can be kept low, and the threshold voltage of the transistor can be shifted. This reduces the risk of damage and suppresses deterioration.

[0176] The first clock signal (CK1) to the fourth clock signal (CK4) are generated at regular intervals. This signal alternates between H and L levels, but when it is H it is VDD and when it is L it is V Assume it is SS.

[0177] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N is a first transistor. The present embodiment includes a first transistor 31 to an eleventh transistor 41 (see FIG. 3(C)). In this embodiment, two types of transistors are fabricated on the same substrate to form a pulse output circuit. The first pulse output circuit 10_1 to the second pulse output circuit 10_2 included in the shift register exemplified in this embodiment are Since the Nth pulse output circuit 10_N has the same configuration, the first pulse output The configuration and operation of the circuit 10_1 will be explained.

[0178] The first pulse output circuit 10_1 includes a first transistor 31 to an eleventh transistor 41. The first transistor 31 to the eleventh transistor 41 are n-channel transistors. The transistor includes a highly purified oxide semiconductor layer. The oxide semiconductor layer is highly purified and has a suppressed carrier concentration, and the device has a positive threshold voltage. A bottom-gate transistor with extremely low off-state current is used as the second transistor. This applies to the fifth transistor 32 and the fifth transistor 35.

[0179] The pulse output circuit of this embodiment and a configuration in which a plurality of such pulse output circuits are connected together In a shift register, an external signal is input directly to the gate electrode of a transistor. A bottom gate type transistor is preferable. For example, the first pulse output circuit 10_1 In this case, the first input terminal 24 is connected to the fourth input terminal 24 to which a start pulse is input from the outside. Examples include the transistor 31 and the fifth transistor 35. Gate-type transistors have high withstand voltage between the gate and source or between the gate and drain. For example, abnormal input such as static electricity can cause a fault such as a change in the transistor threshold. can be suppressed.

[0180] Also, the third transistor 33, the sixth transistor 36, the tenth transistor 40, and the eleventh transistor 41 is formed in a surface portion of a highly purified oxide semiconductor layer. The top-layer semiconductor has high field-effect mobility and excellent f characteristics, using a crystal region with a high-temperature property as the channel formation region. A gate type transistor is applied.

[0181] The top gate transistor and the bottom gate transistor are described in the embodiment. The top-gate transistors 450 and 470 and the bottom-gate transistors 460 and 470 described in Embodiment 1 or 2 are Since the transistors 440 and 460 can be fabricated according to the fabrication method of the multi-gate transistors 440 and 460, The explanation of the form will be omitted.

[0182] In addition, the first transistor 31, the fourth transistor 34, the seventh transistor 37 to The ninth transistor 39 may be, for example, a top-gate transistor or a bottom-gate transistor. Although either a bottom-gate transistor or a bottom-gate transistor may be used, a bottom-gate transistor is applied in this embodiment. This shall be done.

[0183] In FIG. 3C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39. The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the first transistor. The second terminal is electrically connected to the first terminal of the ninth transistor 39. and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal The fourth transistor 34 has a terminal electrically connected to the first output terminal 26. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal The terminals are connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The sixth input terminal 24 is electrically connected to the sixth gate electrode 22. The transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The gate electrode is electrically connected to the fifth input terminal 25. The first terminal is electrically connected to the power supply line 52, and the second terminal is the third terminal of the eighth transistor 38. The gate electrode is electrically connected to the second input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a fourth terminal connected to the gate electrode of the fourth transistor 33. the gate electrode of the transistor 34, the gate electrode of which is connected to the second input terminal 22 The ninth transistor 39 has a first terminal electrically connected to the first transistor The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically connected. The gate electrode is electrically connected to the power supply line 52. The first terminal of the inverter 40 is electrically connected to the first input terminal 21, and the second terminal of the inverter 40 is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The first terminal of the eleventh transistor 41 is electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. .

[0184] In FIG. 3C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 40 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 , the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is In order to maintain the potential of node B, one electrode is electrically connected to node B. Specifically, one electrode of the capacitor may be connected to the node B. The other end may be electrically connected to the power supply line 53.

[0185] Next, the operation of the pulse output circuit shown in FIG. 4(A) will be explained with reference to FIG. 4(B) and FIGS. 5 to 7. Specifically, in the first period shown in the timing chart of FIG. 61, the second period 62, the third period 63, the fourth period 64, and the fifth period 65. The operation of the pulse output circuit will be described. In Figures 5 and 6, transistors are indicated by solid lines. When a transistor is shown, it is indicated by a dashed line that the transistor is in an on state (conducting state). In this case, it is assumed that the transistor is in an off state (non-conducting state).

[0186] Here, the output of the first pulse output circuit 10_1 will be described. The circuit 10_1 is a first circuit whose first input terminal 21 supplies a first clock signal (CK1). A second input terminal 22 electrically connected to line 11 provides a second clock signal (CK2). The third input terminal 23 is electrically connected to the second wiring 12 that corresponds to the third clock signal (C K3).

[0187] In the following description, the first transistor 31 to the eleventh transistor 41 are N The gate-source voltage (Vgs) is the threshold voltage (Vt h), the conduction state is established.

[0188] For the sake of simplicity, VSS=0 is used here, but this is not limiting. The difference between VCC and D, and the difference between VCC and VSS (if VDD > VCC) The threshold voltage of the transistor is set to be greater than the threshold voltage of the transistor, i.e., the transistor is set to the ON state ( The potential of the power supply line 52 is set lower than the potential of the power supply line 51. As a result, the second transistor 32, the fourth transistor 34, the ninth transistor 3 The potential applied to the gate electrodes of the ninth and eleventh transistors 41 is kept low, and the pulse The second transistor 32, the fourth transistor 34, and the ninth transistor 3 Therefore, the threshold shift of the ninth and eleventh transistors 41 can be reduced, and deterioration can be suppressed. Cut.

[0189] In the first period 61, the first start pulse (SP1) becomes H level, and the first start pulse A fourth input terminal 2 of the first pulse output circuit 10_1 to which a start pulse (SP1) is input The first transistor 31 and the fifth transistor 35 electrically connected to the first transistor 4 are in a conductive state. In addition, since the third clock signal (CK3) is also at the H level, the seventh transistor 3 The ninth transistor 39 is also turned on. The second high power supply potential VCC is applied to the gate of the ninth transistor 39. When the voltage Vcc is applied, the ninth transistor 39 is also turned on (see FIG. 5(A)).

[0190] At this time, the first transistor 31 and the ninth transistor 39 are on, so that the node The potential at node A rises. Also, since the fifth transistor 35 is on, the potential at node B Descend.

[0191] The potential of the second terminal of the first transistor 31 is serves as a source, and the potential of the first power supply line 51 is changed to the threshold voltage of the first transistor 31. Therefore, it is VDD-Vth31 (Vth31 is the voltage of the first transistor 31). The threshold voltage Vth39 of the ninth transistor 39 and Vt In h31, if (VDD-Vth31) is equal to or greater than (VCC-Vth39), The potential of node A becomes VCC-Vth39, the ninth transistor 39 turns off, and node A It becomes floating while maintaining the potential (VCC-Vth39). 1) is less than (VCC-Vth39), the ninth transistor 39 will not be turned off. The potential at node A rises to (VDD-Vth31).

[0192] In this embodiment, the first to eleventh transistors 31 to 41 are all the same Since they have the same threshold voltage Vth0, the potential of node A is (VCC-Vth0). The ninth transistor 39 is turned off, and the node A maintains the potential (VCC-Vth0). It becomes floating.

[0193] Here, in the third transistor 33, the potential of the gate electrode is (VCC-Vth0). When the voltage between the gate and source of the third transistor 33 exceeds its threshold, That is, VCC-Vth0>Vth33 (Vth33 is the voltage of the third transistor 3 3, which is Vth0 in this embodiment, The inverter 33 turns on.

[0194] In the second period 62, the first input terminal 21 of the first pulse output circuit 10_1 is The clock signal (CK1) switches from L level to H level. Since the transistor 33 is on, a current flows between the source and drain, and appears at the output terminal 26. The potential of the output signal (OUT(1)(SR)) output from the third transistor 33, i.e., the potential of the second The potential of the electrode (in this case, the source electrode) begins to rise. There is a capacitive coupling due to parasitic capacitance between the output terminal 26 and the source, and as the potential at the output terminal 26 rises, The potential of the gate electrode of the third transistor 33, which is in the free state, rises (bootstrapping). Finally, the potential of the gate electrode of the third transistor 33 becomes (VDD+ Vth33), and the potential of the output terminal 26 becomes equal to VDD (FIG. 4(B), 5(B)).

[0195] At this time, the fourth input terminal 24 of the first pulse output circuit 10_1 is connected to the first start Since the pulse (SP1) is at H level, the fifth transistor 35 is turned on and the node B is maintained at the L level. Therefore, when the potential of the output terminal 26 changes from the L level to the H level, When the output voltage rises, the problem caused by the capacitive coupling between the output terminal 26 and the node B can be suppressed. do.

[0196] Next, in the first half of the third period 63, the first start pulse (SP1) becomes L level. The first transistor 31 and the fifth transistor 35 are turned off. Following step 2, the first clock signal (CK1) is maintained at the H level, and the potential of node A is also changed. Therefore, a signal of H level is supplied to the first electrode of the third transistor 33 ( (See FIG. 5(C)). In the first half of the third period 63, each transistor connected to node B The capacitor is turned off and node B is in a floating state, but the potential of output terminal 26 does not change, so node The influence of the problem caused by the capacitive coupling between the node B and the output terminal 26 is almost negligible.

[0197] As shown in FIG. 4A, the ninth transistor, whose gate is applied with the second high power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0198] If the ninth transistor 39, to whose gate electrode the second high power supply potential VCC is applied, is not present, When the potential of the node A rises due to the bootstrap operation, the first transistor 31 The potential of the source, which is the second terminal, rises and becomes higher than the first high power supply potential VDD. As a result, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and the source, the gate and the drain During this period, a large bias voltage is applied, which causes a large stress on the transistor. This can be a factor in the deterioration of the sensor.

[0199] Therefore, a ninth transistor 39 is provided to the gate electrode of which the second high power supply potential VCC is applied. By keeping the voltage at node A low, the voltage at node A rises due to the bootstrap operation. This can prevent the potential of the second terminal of the first transistor 31 from increasing. By providing the ninth transistor 39, the gate and the source of the first transistor 31 are connected to each other. Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By configuring the circuit in this form, a voltage is applied between the gate and source of the first transistor 31. Since the negative bias voltage applied can be reduced, the first transistor 31 can be prevented from being damaged by stress. This can suppress deterioration of the material.

[0200] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of soft registers, the signal line driver circuit requires higher dynamic characteristics than the scanning line driver circuit. The ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0201] In the second half of the third period 63, the third clock signal (CK3) is switched to the H level. , the seventh transistor 37 is turned on. The clock signal (CK2) is held at the H level, and the eighth transistor 38 is on. , the potential at node B rises to VCC.

[0202] Since the potential of the node B has risen, the second transistor 32, the fourth transistor 34, and The eleventh transistor 41 is turned on, and the potential of the output terminal 27 (OUT(1)) becomes L level. It becomes a bell.

[0203] In the second half of the third period 63, the second transistor 32 is turned on, and the ninth transistor Since an L-level signal is supplied to the first terminal of the ninth transistor 39, is turned on, and the potential at node A drops.

[0204] Furthermore, the fourth transistor 34 is turned on, and the potential of the output terminal 26 drops. (See Figure 5(D)).

[0205] In the first half of the fourth period 64, the second clock signal (CK2) changes from the H level to the L level. , the eighth transistor 38 is turned off. 25 (OUT(3)) is held at the H level, the sixth transistor 36 is turned on. Since the node B is in the VCC state, the node B holds the VCC (see FIG. 6(A)).

[0206] Thereafter, in the second half of the fourth period 64, the fifth input terminal 25 of the first pulse output circuit 10_1 (OUT(3)) becomes L level, and the sixth transistor 36 is turned off (see FIG. 6(B)). At this time, node B goes from being held at the VCC level to being in a floating state. Therefore, the second transistor 32, the fourth transistor 34, and the eleventh transistor 4 However, as shown in FIG. 4B, the potential of node B is V It drops from the CC level due to the off current of the transistor and the like.

[0207] After that, the circuit repeats the periodic operation. This period is called the fifth period (see Fig. 6(C) and 6(D). During a certain period of the fifth period 65 (the second clock signal (CK2) and When the third clock signal (CK3) is at the H level, the seventh transistor 37 and the eighth transistor 38 are turned on, and a signal of the VCC level is periodically supplied to node B. (See FIG. 6(D)).

[0208] In this way, a signal of VCC level is periodically supplied to node B during the fifth period 65. By doing so, it is possible to suppress malfunction of the pulse output circuit. By periodically turning on or off the eighth transistor 37 and the eighth transistor 38, This makes it possible to reduce the shift in the threshold voltage of the transistor.

[0209] During the fifth period 65, a signal of the VCC level is supplied to the node B from the power supply line 52. If the potential of node B drops while the node B is not connected, a capacitance element is provided in advance at node B. A configuration may be adopted in which the drop in the potential of B is alleviated.

[0210] The connection between the second input terminal 22 and the gate electrode of the eighth transistor 38 and the third input The connection between the terminal 23 and the gate electrode of the seventh transistor 37 is interchanged to form the eighth transistor. The clock signal supplied to the gate electrode of the seventh transistor 38 is changed to the gate voltage of the seventh transistor 37. The clock signal supplied to the gate electrode of the seventh transistor 37 is then supplied to the eighth transistor 38. The same effect can be achieved by supplying the same voltage to the gate electrode of the transistor 38.

[0211] In the pulse output circuit shown in FIG. 4(A), the second input terminal 22 and the third input terminal 23 By controlling the potential of the seventh transistor 37 and the eighth transistor 38, both the seventh transistor 37 and the eighth transistor 38 are turned on. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. Then, when the seventh transistor 37 and the eighth transistor 38 are both turned off, The potential of the gate electrode of the seventh transistor 37 is lowered, and the potential of the gate electrode of the eighth transistor 38 is lowered. The drop in the potential of the left electrode causes the potential of node B to drop twice.

[0212] On the other hand, in the pulse output circuit shown in FIG. 4(A), as in the period of FIG. 4(B), The seventh transistor 37 and the eighth transistor 38 are both in an on state. The seventh transistor 37 is turned on and the eighth transistor 38 is turned off. When the seventh and eighth transistors 38 are both turned off, the gate of the eighth transistor 38 The potential drop of the port electrode causes the potential of node B to drop only once, and the number of times the potential drops The number can be reduced to one.

[0213] That is, the gate electrode of the seventh transistor 37 receives the clock signal from the third input terminal 23. and supplies the clock signal from the second input terminal 22 to the gate electrode of the eighth transistor 38. Supplying this voltage is preferable because it reduces fluctuations in the potential of node B, resulting in reduced noise. It is suitable.

[0214] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a VCC level signal during this period, This can suppress malfunctions of the output circuit.

[0215] The node B of the pulse output circuit described in this embodiment is connected to the VCC level in the second half of the fourth period 64. The potential of node B in the floating state changes from the state where the bell is held to the floating state. However, in this embodiment, the voltage may drop from the VCC level due to the off-current of the transistor 35. The fifth transistor 35 of the pulse output circuit of this type has a highly purified layer in the channel forming region. A bottom-gate transistor with extremely low off-state current using a thin oxide semiconductor layer Because a resistor is used, the potential of the floating node B is well maintained and is As a result, malfunction of the semiconductor device is suppressed and reliability is improved.

[0216] In addition, to suppress the off-state current of the transistor, the gate electrode is made into a double gate structure and a tri-gate structure. Since there is no need for a multi-gate structure such as a pull gate structure, the transistor can be made smaller. Furthermore, a capacitance element for maintaining the potential of node B is not required or can be made smaller. A pulse output circuit configured using such a miniaturized element, or a miniaturized By using a shift register configured using the pulse output circuit, This makes it possible to miniaturize the entire system.

[0217] In addition, a bottom-gate transistor using a highly purified oxide semiconductor layer in a channel formation region The transistor not only has an extremely small off-state current but also has a positive threshold voltage. In the pulse output circuit of this embodiment, the second transistor 32 is made of a highly purified oxide. Because it uses a bottom-gate transistor with a compound semiconductor layer, bootstrap When the potential of node A is increased by this operation, it can be increased quickly with little loss. Malfunctions of the semiconductor device are suppressed, improving reliability.

[0218] In the pulse output circuit of this embodiment, the third transistor 33 and the sixth transistor The tenth transistor 36, the tenth transistor 40, and the eleventh transistor 41 are made of highly purified A top-gate transistor using a crystalline region of an oxide semiconductor layer formed on the surface of the transistor as a channel formation region is also disclosed. A transistor using a crystalline region of a highly purified oxide semiconductor layer as a channel formation region is used. Top-gate transistors have excellent f characteristics and high field-effect mobility, the third transistor 33, the sixth transistor 36, the tenth transistor 40, and the first The switching speed of the transistor 41 can be increased. It can be shaped.

[0219] A pulse output circuit configured using such high-speed elements, or a high-speed By using a shift register configured using a pulse output circuit, the entire semiconductor device This makes it possible to speed up the process.

[0220] In addition, the shift register shown in this embodiment mode is configured to receive the m-th pulse as shown in FIG. The pulse output from the output circuit and the pulse output from the (m+1)th pulse output circuit are The driving method is half (1 / 4 period) overlapped. This is different from the conventional shift register. The pulse output from the mth pulse output circuit and the pulse output from the (m+1)th pulse output circuit are Compared to the driving method in which the output pulses do not overlap (see Figure 7(B)), the wiring is charged. In this way, the pulse output time from the mth pulse output circuit can be approximately doubled. The pulse output from the (m+1)th pulse output circuit overlaps by half (1 / 4 period). By using this driving method, it is possible to apply a large load and operate at a high frequency. Furthermore, it is possible to provide a pulse output circuit that can output a wide range of pulses. It is possible.

[0221] Note that the shift register and the pulse output circuit shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be implemented in combination with the configuration of the shift register and pulse output circuit shown in the embodiment. The present invention can also be applied to semiconductor devices. The term "semiconductor device" refers to a device that can function by utilizing semiconductor properties.

[0222] (Embodiment 5) In this embodiment, two types of transistors are used on the same substrate as described in Embodiment 4. The fabricated shift register has a highly purified oxide semiconductor layer in a channel formation region. Active matrix display devices are made by combining switching circuits using transistors. First, an example of configuring a driving circuit for an active matrix display device will be described. The outline of the display device will be explained using a block diagram, and then the shift register of the display device will be explained. The signal line driver circuit and scanning line driver circuit used will be explained below.

[0223] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and the second scanning line driver circuit 5303. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is made of FPC (Flexible Printed Circuit). Through a connection part such as a timing control circuit 5305 (controller, control IC (also called the "interface")

[0224] The transistors arranged in the pixel portion 5301 are the same as those described in Embodiment 1 or 2. The transistor of one embodiment of the present invention can be used. The Tom gate type is particularly preferred, for example, the transistor 44 shown in the first or second embodiment. 0 or transistor 460 can be preferably used. The low off-state current of the transistor not only increases the contrast of the displayed image, but also The power consumption of the device can be reduced.

[0225] The transistors described in Embodiment 1 or 2 are n-channel transistors. Therefore, it is one of the driver circuits that can be configured with n-channel transistors. The pixel portion and the transistors are formed on the same substrate.

[0226] In FIG. 8A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of components such as drive circuits provided outside the display device is reduced, which leads to cost reduction. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring. The number of connections between the wirings increases. If a driver circuit is provided on the same board 5300, the number of connections between the wirings increases. The number of connections can be reduced, and the reliability or yield can be improved.

[0227] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0228] In FIG. 8B, a circuit with a relatively low driving frequency (for example, the first scanning line driving circuit 5302 , and the second scanning line driver circuit 5303) are formed on the same substrate 5300 as the pixel portion 5301, and A signal line driver circuit 5304 with a relatively high frequency is formed on a substrate separate from the pixel portion 5301. For example, a transistor using a single crystal semiconductor is used to achieve a driving frequency The signal line driver circuit 5304, which has a relatively high resistance, can also be formed on a separate substrate. It is possible to increase the size of display devices, reduce the number of processes, reduce costs, or improve yields. can.

[0229] In this embodiment, a signal line driver circuit 5304 having a relatively high driving frequency is connected to the pixel portion 53 It is to be noted that the driving circuit is formed on the same substrate 5300 as that of the substrate 5300. In this case, the number of connections between wirings can be reduced, improving reliability and yield. It is possible.

[0230] Next, an example of the configuration and operation of a signal line driver circuit configured with n-channel transistors will be described. This will be explained using Figures 9(A) and 9(B).

[0231] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of transistors 5603_1 to 5603_k (k is a natural number) In this embodiment, the transistors 5603_1 to 5603_k have n-channel A configuration in which a loop-type transistor is applied will be described.

[0232] Regarding the connection relationship of the signal line driver circuit, the switching circuit 5602_1 is taken as an example and is shown in FIG. 9(A The first terminals of the transistors 5603_1 to 5603_k are connected to the Transistors 5603_1 to 5603_k are connected to the lines 5604_1 to 5604_k. The second terminals of the transistors 5603_1 to 5603_56 are connected to the signal lines S1 to Sk, respectively. The gate of 03_k is connected to the wiring 5605_1.

[0233] The shift register 5601 sequentially sends H-level signals to the wires 5605_1 to 5605_N. The switching circuit 5602_1 to 5602_N has a function of outputting a signal and selecting the switching circuits 5602_1 to 5602_N in order. The shift register 5601 can be produced by the method explained in the fourth embodiment. A detailed explanation will be omitted.

[0234] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function for controlling the conduction state between the wirings S1 to Sk, that is, the wirings 5604_1 to 5604_k. The transistor 5603_1 has a function of supplying a voltage to the signal lines S1 to Sk. .about.5603_k each function as a switch.

[0235] In this embodiment, a transistor used in the switching circuit 5602 is, for example, As in the transistor 450 of the first embodiment, a crystal region of a highly purified oxide semiconductor layer is formed on the A top-gate transistor is used in the channel formation region. The transistor has excellent f characteristics and fast switching operation. This allows for the high-speed writing required by next-generation display devices. The transistor using the layer in the channel formation region is manufactured by the method described in the first or second embodiment. Since it can be fabricated, detailed description will be omitted here.

[0236] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0237] Next, the operation of the signal line driver circuit of FIG. 9(A) will be explained with reference to the timing chart of FIG. 9(B). 9B, the signals Sout_1 to Sout_N and the signal Vda ta_1 to Vdata_k. 5601, and signals Vdata_1 to Vdata_k are , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. For example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to the selected row.

[0238] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0239] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 03_1~5603_k will be turned on, so wires 5604_1~5604_k and signal line At this time, the wirings 5604_1 to 5604_k are connected to Da ta(S1)~Data(Sk) is input. Data(S1)~Data(Sk) is , each of which is connected to a pixel belonging to a selected row via a transistor 5603_1 to 5603_k. In this way, during the periods T1 to TN, the selected pixels are written to the pixels in the first to k-th columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. can be.

[0240] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0241] The shift register 5601 of the driver circuit of this embodiment has the same structure as that described in the fourth embodiment. The use of shift registers prevents malfunctions and ensures high reliability. By using a miniaturized shift register, the entire drive circuit can be miniaturized. do.

[0242] In addition, the switching circuit 5602 of the driver circuit of this embodiment is made of a highly purified oxide. A top-gate transistor using the crystalline region of the semiconductor layer as the channel formation region is applied. Therefore, the driver circuit exemplified in this embodiment has a high speed of switching. This allows high-speed writing to the liquid crystal, making it suitable for next-generation high-resolution display devices with a large number of pixels.

[0243] The shift register described in the fourth embodiment can also be applied to the scanning line driving circuit. The driving circuit includes a shift register, and in some cases a level shifter and a buffer. In the scanning line driver circuit, a clock signal (CL A selection signal is generated by inputting a start pulse signal (SP) and a start pulse signal (K). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must all be turned on at once, the buffer is large. A device capable of passing a large current is used.

[0244] The active matrix display device described in this embodiment and the external device communicate with each other via the terminal section. Therefore, abnormal input from the outside (such as static electricity) To prevent malfunctions such as fluctuations in the threshold of the transistor, a protection circuit is provided in the drive circuit. The high breakdown voltage between the gate and source and between the gate and drain makes it suitable for transistors used in protection circuits. The bottom gate type transistor shown in the first or second embodiment is suitable as the transistor. be.

[0245] (Embodiment 6) The transistor described in Embodiment 1 or 2 is manufactured and used in a pixel portion and A semiconductor device (also called a display device) having a display function can be manufactured by using the driver circuit. In addition, the transistor described in Embodiment 1 or 2 can be used in part or the whole of a driver circuit. It can be formed integrally on the same substrate as the pixel section to form a system-on-panel.

[0246] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0247] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0248] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0249] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 11A1 and 11A2 show a structure formed on a first substrate 4001. The In-Ga-Zn-O based film shown in the first or second embodiment is used as an oxide semiconductor layer. The second substrate includes highly reliable transistors 4010 and 4011 and a liquid crystal element 4013. 11 is a top view of the panel sealed between the plate 4006 and the sealing material 4005. (B) corresponds to a cross-sectional view taken along line MN in FIGS. 11(A1) and 11(A2).

[0250] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0251] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. This is an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which the signal line driver circuit 4003 is mounted by the method.

[0252] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 11B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4010 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided over the transistor 4010. An insulating layer 4021 is provided on the transistor 4011. The insulating layer 4020 It functions as a gate insulating layer for MOSFET 1.

[0253] The channel shape of the oxide semiconductor layer of the transistor 4010 in the pixel portion is formed on the insulating layer 4020. The conductive layer 4042 is formed of an oxide semiconductor. By placing the layer at a position that overlaps with the channel formation region, the The amount of change in the threshold voltage of the transistor 4010 can be reduced. The potential of the gate electrode layer of the transistor 4010 may be the same as or different from that of the gate electrode layer of the transistor 4010. In addition, the conductive layer 4042 can function as a second gate electrode layer. The conductive layer 4042 may be in a ND, 0V, or floating state. It can be manufactured using the same material and process as the gate electrode layer of the transistor 4011 .

[0254] The transistors 4010 and 4011 are made of an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable transistor described in Embodiment 1 or 2 can be applied. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. do.

[0255] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 and the counter electrode 4031 are formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033. However, the color filters are provided on either the first substrate 4001 or the second substrate 4006. is also good.

[0256] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Also, aluminum foil can be covered with PVF film or polyester film. It is also possible to use a sheet having a structure in which the sheet is sandwiched between two thin films.

[0257] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. The common connection portion is used to connect the opposing electrode layer via conductive particles disposed between the pair of substrates. The conductive particles can be electrically connected to the common potential line. Included in 4005.

[0258] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs. c. or more and 100 μsec or less, and because it is optically isotropic, no alignment treatment is required. The viewing angle dependency is small.

[0259] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. It can also be applied to a semi-transmissive liquid crystal display device.

[0260] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0261] In this embodiment, in order to reduce the surface irregularities caused by the transistor, In order to improve the reliability of the transistor, the transistor obtained in the first or second embodiment is provided with a protective film or The insulating layer 4020 and the insulating layer 4021 are covered with insulating layers that function as planarizing insulating films. The protective film also prevents contamination by organic matter, metals, water vapor, and other polluting impurities floating in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide aluminum film, aluminum nitride film, aluminum oxynitride film, or aluminum nitride oxide film In this embodiment, the protective film is formed by a sputtering method. Although an example is shown, there is no particular limitation and various methods may be used for forming the film.

[0262] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0263] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, mobile ions such as sodium penetrate into the semiconductor region, affecting the electrical properties of the transistor. It is possible to suppress the change.

[0264] After forming the protective film, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). may be performed.

[0265] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant resins such as styrene resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin In addition to the above organic materials, low dielectric constant materials (L low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) In addition, a plurality of insulating films made of these materials can be stacked. In this way, the insulating layer 4021 may be formed.

[0266] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0267] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, At the same time as the annealing process, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). The insulating layer 4021 may be baked and the oxide semiconductor layer may be annealed at the same time, which may increase efficiency. This makes it possible to manufacture semiconductor devices easily.

[0268] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0269] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0270] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0271] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0272] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive film as the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed of the same conductive film.

[0273] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0274] In FIG. 11, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0275] FIG. 12 shows a transistor manufactured by using the transistor described in Embodiment 1 or 2. This shows an example of a liquid crystal display module constructed as a semiconductor device using a substrate 2600. .

[0276] FIG. 12 shows an example of a liquid crystal display module, which includes a transistor substrate 2600 and an opposing substrate 260. 1 is fixed by a sealing material 2602, and a pixel portion 2603 including a transistor and the like is provided between them. A display element 2604 including a liquid crystal layer, a colored layer 2605, etc. are provided to form a display area. The colored layer 2605 is necessary for color display. In the case of the RGB system, it is red, green, and blue. A colored layer corresponding to each color is provided for each pixel. On the outer side of the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and is mounted on a circuit board 261. 2 is a wiring circuit portion 26 of the transistor substrate 2600 by a flexible wiring substrate 2609. It is connected to the 08 and incorporates external circuits such as control circuits and power supply circuits. The polarizing plate and the liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0277] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0278] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0279] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0280] (Embodiment 7) In this embodiment, a semiconductor device to which the transistor described in Embodiment 1 or 2 is applied is An example of electronic paper is shown below.

[0281] Figure 13 shows an active matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the transistor shown in the first or second embodiment. The data can be applied.

[0282] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0283] The transistor 581 sealed between the substrate 580 and the substrate 596 is a bottom gate transistor. The transistor is insulated from the first electrode layer 587 by a source electrode layer or a drain electrode layer. The first electrode layer 583 and the second electrode layer 585 are electrically connected to each other through openings formed in the first electrode layer 583 and the second electrode layer 585. Between the second electrode layer 587 and the second electrode layer 588, there are black areas 590a and white areas 590b. A spherical particle 589 is provided, which includes a cavity 594 filled with a liquid. The periphery of the shaped particle 589 is filled with a filler 595 such as a resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 corresponds to an electrode. The second electrode layer 588 is provided over the same substrate as the transistor 581. The common connection portion shown in either the first or second embodiment is electrically connected to a common potential line. 588 and the second electrode layer 589 through the conductive particles disposed between the pair of substrates. The wires can be electrically connected.

[0284] Also, instead of the twist ball, an electrophoretic element can be used. and a particle with a diameter of 10 μm or more that contains positively charged white particles and negatively charged black particles. Microcapsules with a size of approximately 0.1 μm or less are used. The microcapsules are subjected to an electric field by the first and second electrode layers. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. The display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lines No light is required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image that has been displayed will be retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device, or Even if the display device (also referred to as a semiconductor device having a display device) is placed far away, the displayed image It will be possible to save it.

[0285] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0286] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0287] (Embodiment 8) In this embodiment, a semiconductor device to which the transistor described in Embodiment 1 or 2 is applied is An example of a light-emitting display device is shown below. This is demonstrated using a light-emitting element that uses electroluminescence. Optical elements are generally classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0288] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0289] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0290] FIG. 14 shows a display device to which digital time gray scale driving can be applied as an example of a semiconductor device to which the present invention is applied. FIG. 2 is a diagram illustrating an example of an element configuration.

[0291] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. In this case, the oxide semiconductor layer (In—Ga—Zn—O-based film) shown in the first or second embodiment is used. An example in which two n-channel transistors are used in the channel forming region in one pixel is shown. vinegar.

[0292] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate. That's fine.

[0293] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0294] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0295] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0296] Also, when analog grayscale driving is used instead of digital time grayscale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 14 can be used.

[0297] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0298] Note that the pixel configuration shown in Fig. 14 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0299] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be explained using an example in which the capacitor is n-type. C) Transistors 7001 and 701 which are driving transistors used in the semiconductor device 1 and 7021 can be fabricated in the same manner as in the transistors described in Embodiment 1 or 2. This is a highly reliable transistor that contains an a-Zn-O based film as the oxide semiconductor layer.

[0300] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides. The present invention can also be applied to the above light-emitting devices.

[0301] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0302] The driving transistor 7011 is an n-type transistor, and light emitted from the light emitting element 7012 is incident on the first electrode 7013. FIG. 15(A) shows a cross-sectional view of a pixel when light is emitted to the driving transistor 7013 side. A light-transmitting conductive film 7017 electrically connected to the drain electrode layer of the transistor 7011 is , a first electrode 7013 of the light emitting element 7012 is formed, and E An L layer 7014 and a second electrode 7015 are laminated in this order.

[0303] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0304] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er. In FIG. 15A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through (preferably For example, an aluminum film having a thickness of 20 nm is used. is used as the first electrode 7013 .

[0305] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7017 and the first electrode 7013 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0306] The partition wall 7019 is formed on the protective insulating layer 7035 and the insulating layer 7032. A transparent conductive film 7017 is disposed over the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7013 may be covered with a partition wall. an organic resin film such as polyethyleneimide, acrylic resin, polyamide, or epoxy resin; an inorganic insulating film; or The partition wall 7019 is formed using organic polysiloxane. In particular, a photosensitive resin material is used. An opening is formed on the first electrode 7013, and the sidewall of the opening is formed with a continuous curvature. It is preferable to form the partition wall 7019 as an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0307] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is made of at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7014 is made up of a plurality of layers, An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole transport layer, a hole transport layer, a hole transport layer, a hole injection ... The hole injection layer is laminated in this order. Note that it is not necessary to provide all of these layers.

[0308] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. Layers of hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed. By stacking the layers in the order of their insertion, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0309] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0310] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. 15(A), the light-emitting element Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0311] In FIG. 15A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, and passes through the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7030, and The light is then emitted through the substrate 7010.

[0312] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0313] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. 15A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as acrylic resin, and is colored. It has the function of flattening the unevenness caused by the filter layer 7033.

[0314] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0315] In FIG. 15B, the drain electrode layer of the driving transistor 7021 is electrically connected to the drain electrode layer of the driving transistor 7022. A first electrode 7023 of the light-emitting element 7022 is formed over a light-transmitting conductive film 7027. An EL layer 7024 and a second electrode 7025 are laminated in this order on a first electrode 7023. There are.

[0316] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0317] In addition, various materials can be used for the first electrode 7023. For example, When 23 is used as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and its film thickness is set to a thickness that allows light to pass through. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode.

[0318] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7027 and the first electrode 7023 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0319] The partition wall 7029 is formed on the protective insulating layer 7045 and the insulating layer 7042, and A transparent conductive film 7027 is placed over the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7023 may be covered with a partition wall. an organic resin film such as polyethyleneimide, acrylic resin, polyamide, or epoxy resin; an inorganic insulating film; or The partition wall 7029 is formed using organic polysiloxane. In particular, a photosensitive resin material is used. An opening is formed on the first electrode 7023, and the sidewall of the opening is formed with a continuous curvature. It is preferable to form the partition wall 7029 as an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0320] The EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It can be made up of a single layer or multiple layers stacked together. When the EL layer 7024 is made up of multiple layers, it functions as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed. It is not necessary to provide all of these layers.

[0321] The stacking order is not limited to the above, and the first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. The power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because

[0322] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment mode, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as an anode. Form.

[0323] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. 15(B), the light-emitting element The light emitted from 7022 travels between the second electrode 7025 and the first electrode 70 as shown by the arrows. 23It is fired on both sides.

[0324] In FIG. 15B, light emitted from the light-emitting element 7022 toward the first electrode 7023 One light passes through the color filter layer 7043 and enters the insulating layer 7042 and the oxide insulating layer 704 1. The light is emitted through the gate insulating layer 7040 and the substrate 7020.

[0325] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0326] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0327] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0328] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0329] In FIG. 15C, a transistor 7001 serving as a driving transistor is an n-type transistor, and a light-emitting element 7 7 shows a cross-sectional view of a pixel in the case where light emitted from 002 exits to the second electrode 7005 side. In FIG. 15C, the drain electrode layer of the driving transistor 7001 is electrically connected to the drain electrode layer of the driving transistor 7002. A first electrode 7003 of the light emitting element 7002 is formed on the first electrode 7003. An L layer 7004 and a second electrode 7005 are laminated in this order.

[0330] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, Li or Cs, Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0331] The partition wall 7009 is formed on the protective insulating layer 7052 and the insulating layer 7055, and The first electrode 7003 is placed on the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7003 may be covered with a partition wall. The partition wall 7009 may be made of polyimide, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, or organic polymer films The partition wall 7009 is formed by using a photosensitive resin material, and the first electrode An opening is formed on 7003, and the sidewall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so that it has a flat surface. In this case, the step of forming a resist mask can be omitted.

[0332] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7004 is made up of a plurality of layers, On the first electrode 7003 used as a light-emitting layer, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport ... The insulating layer, the insulating film, and the insulating film are laminated in this order. Note that it is not necessary to provide all of these layers.

[0333] The stacking order is not limited to the above, and the hole injection layer may be formed on the first electrode 7003 used as an anode. Alternatively, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order.

[0334] In Figure 15(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0335] However, when the transistor 7001 is an n-type, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the drive circuit. This is preferable because it can suppress a voltage rise and reduce power consumption.

[0336] The second electrode 7005 is formed using a light-transmitting conductive material, for example, an acid. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Transparent films such as indium tin oxide, indium zinc oxide, and indium tin oxide doped with silicon oxide A conductive film having optical properties may also be used.

[0337] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 15(C), the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0338] The planarization insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene, or polyamide. In addition to the above resin materials, resin materials with low dielectric constant such as epoxy resin can be used. Materials (low-k materials), siloxane resins, PSG (phosphor glass), BPSG (phosphor silicon dioxide) In addition, multiple insulating films made of these materials can be stacked. The planarization insulating layer 7053 may be formed by layering the planarization insulating layer 7053. The method is not particularly limited, and may be a sputtering method, a SOG method, a spin coating method, a direct coating method, or the like, depending on the material. Spray coating, droplet ejection method (inkjet method, screen printing, offset printing etc.), doctor knife, roll coater, curtain coater, knife coater, etc. It is possible.

[0339] In the structure of FIG. 15C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also included, making a total of four A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0340] In the structure of FIG. 15(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0341] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0342] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0343] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0344] The transistor that controls the driving of the light-emitting element (drive transistor) and the light-emitting element are electrically However, a current control transistor may be connected between the driving transistor and the light emitting element. A transistor may be connected.

[0345] Note that the semiconductor device shown in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0346] Next, a semiconductor device according to one embodiment of the present invention will be described. The appearance and cross section of the light-emitting display panel (also called a light-emitting panel) will be explained using FIG. FIG. 16A shows a case where a transistor and a light-emitting element formed on a first substrate are connected to a second substrate. 16(B) is a top view of the panel sealed with a sealing material between the panel and the substrate. This corresponds to the cross-sectional view at HI in 6(A).

[0347] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0348] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. 16B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0349] The transistors 4509 and 4510 are made of an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable transistor described in Embodiment 1 or 2 can be applied. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. do.

[0350] The channel shape of the oxide semiconductor layer of the transistor 4510 in the pixel portion is formed over the insulating layer 4544. The conductive layer 4540 is formed of an oxide semiconductor. By placing the layer at a position that overlaps with the channel formation region, the The amount of change in the threshold voltage of the transistor 4510 can be reduced. The potential of the gate electrode layer of the transistor 4510 may be the same as or different from that of the gate electrode layer of the transistor 4510. In addition, when the potential of the conductive layer 4040 is G It may be ND, 0V, or floating.

[0351] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light-emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the stacked structure of the second electrode layer 4513 is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0352] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0353] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0354] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon nitride oxide film, a DLC film, etc.

[0355] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0356] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source electrode layer and the drain electrode layer of the transistor 10 are formed from the same conductive film as the source electrode layer and the drain electrode layer of the transistor 10.

[0357] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0358] The substrate located in the direction in which light from the light emitting element 4511 is extracted needs to be light-transmitting. In this case, use a glass plate, plastic plate, polyester film or acrylic resin film. A light-transmitting material such as a film is used.

[0359] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of PVC (polyvinyl chloride), acrylic resin or thermosetting resin. Oil, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Nitrogen was used as the gas.

[0360] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0361] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0362] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0363] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0364] (Embodiment 9) The semiconductor device to which the transistor described in Embodiment 1 or 2 is applied can be used as electronic paper. Electronic paper can be applied to any electronic device that displays information. For example, electronic paper can be used to display electronic books (e-books). posters, advertisements on trains and other vehicles, and on various cards such as credit cards. Examples of electronic devices are shown in Figures 17 and 18.

[0365] FIG. 17(A) shows a poster 2631 made of electronic paper. When printed materials are used, the advertisements are replaced manually, but when electronic paper is used, The display of the advertisement can be changed in a short time. Also, the display is stable without any distortion. The poster may be configured to be capable of transmitting and receiving information wirelessly.

[0366] FIG. 17(B) shows an advertisement 2632 inside a vehicle such as a train. When using printed paper, advertisements are exchanged manually, but with electronic paper, This allows you to change the display of your advertisements in a short time without requiring a lot of manpower. It is possible to obtain a stable image without any distortion. It may also be possible to use the following.

[0367] 18 shows an example of an electronic book. For example, an electronic book 2700 is housed in a housing 27 It consists of two housings, housing 2701 and housing 2703. 3 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. With this configuration, it is possible to operate like a paper book.

[0368] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 18) and An image can be displayed on the display unit 2707 in FIG.

[0369] 18 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0370] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0371] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0372] (Embodiment 10) The semiconductor device using the transistor described in Embodiment 1 or 2 can be used in various electronic devices ( The present invention can be applied to electronic devices such as television sets. (also called television or television receiver), computer monitors, digital digital cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, (also known as mobile telephone devices), portable game machines, personal digital assistants, audio playback devices, pachinko machines, etc. Examples include large game consoles.

[0373] FIG. 19A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0374] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0375] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0376] FIG. 19(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0377] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0378] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0379] FIG. 20(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient if the configuration includes the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. 20(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading out the game program or data and displaying it on the display, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 20(A) has the following functions: The function is not limited to this and may have various functions.

[0380] FIG. 20(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to this, and it is sufficient that the device is provided with at least the semiconductor device according to the present invention. The configuration can be such that appropriate equipment is provided.

[0381] 21A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002 incorporated in the It is equipped with a speaker 1005, a microphone 1006, etc.

[0382] The mobile phone 1000 shown in FIG. 21A displays information by touching the display unit 1002 with a finger or the like. You can also make calls, write emails, and perform other operations. This can be done by touching the display portion 1002 with a finger or the like.

[0383] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0384] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. Desirable.

[0385] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0386] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0387] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0388] The display unit 1002 can also function as an image sensor. By touching 02 with the palm or fingers and capturing an image of the palm print, fingerprint, etc., identity authentication can be performed. In addition, a backlight that emits near-infrared light in the display unit or a sensing device that emits near-infrared light By using a light source, it is also possible to capture images of finger veins, palm veins, etc.

[0389] FIG. 21B is also an example of a mobile phone. The mobile phone in FIG. 21B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

[0390] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so. [Explanation of symbols]

[0391] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 63 period 64 period 65 period 400 boards 402 Insulating layer 403 Oxide semiconductor film 404a Oxide semiconductor layer 404b Oxide semiconductor layer 405a Crystal region 405b Crystal region 411 terminal 412 connecting electrode 414 terminal 415 Conductive Layer 416 Electrode layer 418 Conductive Layer 421 Gate electrode layer 428 Insulating Layer 440 transistors 442 Connection electrode layer 450 transistors 451 Gate electrode layer 455a Source electrode layer 455b Drain electrode layer 455c Source electrode layer 455d Drain electrode layer 460 transistors 470 transistors 480 Oxide conductive layer 482 Metallic conductive film 484a Source electrode layer 484b Drain electrode layer 486a Oxide conductive layer 486b Oxide conductive layer 486c Source electrode layer 486d Drain electrode layer 580 board 581 Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 2600 Transistor Board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Conductive layer 4042 Conductive layer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 board 7011 Drive transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 board 7021 Drive transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate insulating layer 7031 Oxide insulating layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulating layer 7041 Oxide insulating layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide insulating layer 7052 Protective insulation layer 7053 Planarization insulating layer 7055 Insulation layer 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Controlled Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

1. A first conductive layer; and a first insulating layer having an area on the first conductive layer; a first oxide semiconductor layer having a region on the first insulating layer; a second conductive layer having a region on the first oxide semiconductor layer; a third conductive layer having a region on the first oxide semiconductor layer, the first oxide semiconductor layer has a channel formation region of a first transistor, a surface portion of the first oxide semiconductor layer has a first crystalline region, the first crystalline region has a plurality of crystallites; a region of the first oxide semiconductor layer that is in contact with the first insulating layer has fewer microcrystals than a region of the first crystalline region; the first crystal region has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region sandwiched between the first region and the second region and overlapping with the first conductive layer; The third region has a region having a c-axis oriented in a first direction, The first region and the second region each have a region whose c-axis is oriented in a direction different from the first direction.

2. A first conductive layer; and a first insulating layer having an area on the first conductive layer; a first oxide semiconductor layer having a region on the first insulating layer; a second oxide semiconductor layer having a region on the first insulating layer; a second conductive layer having a region on the first oxide semiconductor layer; a third conductive layer having a region on the first oxide semiconductor layer; a fourth conductive layer having a region on the second oxide semiconductor layer; a fifth conductive layer having a region on the second oxide semiconductor layer; a sixth conductive layer having a region on the second oxide semiconductor layer, the first conductive layer has a region overlapping with the second oxide semiconductor layer, the first oxide semiconductor layer has a channel formation region of a first transistor, the second oxide semiconductor layer has a channel formation region of a second transistor, the sixth conductive layer has a region that functions as a gate electrode of the second transistor, a surface portion of the first oxide semiconductor layer has a first crystalline region, the first crystalline region has a plurality of crystallites; a region of the first oxide semiconductor layer that is in contact with the first insulating layer has fewer microcrystals than a region of the first crystalline region; the first crystal region has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region sandwiched between the first region and the second region and overlapping with the first conductive layer; The third region has a region having a c-axis oriented in a first direction, the first region and the second region have a region whose c-axis is oriented in a direction different from the first direction, a surface portion of the second oxide semiconductor layer has a second crystal region, the second crystalline region has a plurality of crystallites; a region of the second oxide semiconductor layer that is in contact with the first insulating layer has fewer microcrystals than a region of the second crystalline region; the second crystal region has a fourth region in contact with the fourth conductive layer, a fifth region in contact with the fifth conductive layer, and a sixth region sandwiched between the fourth region and the fifth region and overlapping with the sixth conductive layer; The second crystalline region has a region whose c-axis is oriented in the first direction.

3. In claim 2, a conductive layer functioning as a gate electrode of the second transistor is not provided below the second oxide semiconductor layer.

Images