Overcurrent suppression circuit, DC / DC converter, power supply device, and overcurrent suppression method

Abstract

An overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method for suppressing an overcurrent that occurs when a load suddenly changes, etc., are provided. [Solution] In a DC / DC converter of a power supply device, an overcurrent suppression circuit 5 includes an output section 6 that receives a DC current and outputs a DC current, and a control section 7. The output section includes a plurality of semiconductor switches Q1 to Qn connected in parallel, and output capacitors C1 to Cn connected in series to each semiconductor switch. When a sudden change occurs in the load current from the output section, the control section switches the plurality of semiconductor switches to a non-conductive state, and then sequentially switches them to a conductive state.

Description

[Technical field]

[0001] The present disclosure relates to an overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method. [Background technology]

[0002] In DC / DC converters, for example, step-down DC / DC converters, feedback control is generally performed. In this feedback control, the voltage on the load side of the DC / DC converter is monitored, and the output voltage of the DC / DC converter is controlled so that this voltage becomes a constant voltage value. In such DC / DC converters, when a sudden load change occurs, the feedback operation cannot follow the load change, and the output voltage fluctuates greatly, so an output capacitor is implemented to prevent this. During the period when the DC / DC converter cannot follow the load change, the charge stored in the output capacitor is supplied to the load side to suppress the output voltage fluctuation. When the operation of the DC / DC converter catches up, the DC / DC converter charges the output capacitor and supplies current to the load, and the voltage returns to the set voltage value (for the circuit configuration, see, for example, Patent Document 1). Note that "DC" is an abbreviation for "Direct Current". [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-93909 A Summary of the Invention [Problem to be solved by the invention]

[0004] The above prior art documents are incorporated herein by reference.

[0005] The following analysis was performed by the inventors.

[0006] For example, to handle larger load changes or output voltage fluctuations, DC / DC converters may have multiple output capacitors connected in parallel. However, in this case, all the capacitors are charged at the same time during the charging process, so a large inrush current flows. This may cause the overcurrent protection to activate and the DC / DC converter to stop working.

[0007] An object of the present disclosure is to provide an overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method that contribute to suppressing an overcurrent that occurs when a sudden load change or the like occurs. [Means for solving the problem]

[0008] (1) A first aspect of the present disclosure provides an overcurrent suppression circuit including an output section that receives a direct current and outputs a direct current, and a control section. The output section includes a plurality of semiconductor switches connected in parallel, and an output capacitor connected in series to each of the semiconductor switches. The control section is configured to, when a sudden change occurs in the load current from the output section, perform control to switch the semiconductor switches to a non-conductive state and then to sequentially switch them to a conductive state. (2) A second aspect of the present disclosure provides a DC / DC converter including the overcurrent suppression circuit of the present disclosure and a DC / DC converter circuit disposed upstream of the overcurrent suppression circuit. (3) A third aspect of the present disclosure provides a power supply device including a DC / DC converter according to the present disclosure and a DC power supply unit disposed upstream of the DC / DC converter. (4) According to a fourth aspect of the present disclosure, there is provided a DC / DC converter circuit, An overcurrent suppression circuit including a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each of the semiconductor switches, and a control unit, and which outputs a direct current input from the DC / DC converter circuit to a load as a direct load current. A method for suppressing overcurrent in a DC / DC converter is provided. When a sudden change occurs in the load current, the control unit switches the semiconductor switches to a non-conductive state, and then sequentially switches them to a conductive state. Effect of the Invention

[0009] The present disclosure and each of its aspects can contribute to suppressing overcurrent that occurs when a load suddenly changes, etc. [Brief description of the drawings]

[0010] [Figure 1] 1 is a conceptual diagram of an example of a power supply device including an example of an overcurrent suppression circuit of the present disclosure. [Diagram 2] 4 is a conceptual diagram of an example of an output section included in an example of an overcurrent suppression circuit of the present disclosure. [Diagram 3] 3 is a flowchart of an example of an embodiment of suppressing an overcurrent that occurs when a load R suddenly changes by the overcurrent suppression circuit 5 including the output unit 6 shown in FIG. 2. [Figure 4] 1 is a conceptual diagram of a specific example of a power supply device including an overcurrent suppression circuit according to the present disclosure. [Diagram 5] 5 is a time chart of an example of the operation of the power supply device 10 shown in FIG. 4. [Figure 6] 5 is a detailed time chart of an example of the operation of the power supply device 10 shown in FIG. 4. [Figure 7] FIG. 1 is a conceptual diagram of another specific example of a power supply device including an example of an overcurrent suppression circuit of the present disclosure. [Figure 8] 1 is an example of a hardware resource configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Preferred embodiments of the present disclosure will be described below, but the present disclosure is not limited thereto. (Mode 1) See the first aspect of this disclosure above. (Feature 2) In the overcurrent suppression circuit according to feature 1, the control unit includes a plurality of timer circuits each having a different settling time; It is preferable that each of the plurality of timer circuits is assigned to one semiconductor switch. (Feature 3) In the overcurrent suppression circuit according to the feature 2, It is preferable that the timer circuit is configured to be activated when a sudden change in the load current occurs, to bring the semiconductor switch to a non-conductive state to which the timer circuit is assigned, and to bring the semiconductor switch to a conductive state again after a settling time of the timer circuit has elapsed. (Feature 4) In the overcurrent suppression circuit according to the feature 1, The control unit is preferably configured to execute control when a sudden change in the load current occurs, when a differential value of the voltage calculated from the load current is greater than a predetermined reference voltage value. (Feature 5) In the overcurrent suppression circuit according to the feature 1, the semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor; The sudden change in the load current is preferably a sudden increase in the load current. (Feature 6) In the overcurrent suppression circuit according to feature 1, the semiconductor switch has a conduction direction opposite to a charging direction of the output capacitor; The sudden change in the load current is preferably a sudden decrease in the load current. (Feature 7) In the overcurrent suppression circuit according to the feature 1, The output section preferably includes a rectifier connected in parallel to each semiconductor switch and having a forward direction opposite to the conduction direction of the semiconductor switch. (Mode 8) See the second aspect of this disclosure above. (Mode 9) See the third aspect of this disclosure above. (Mode 10) See the fourth aspect of this disclosure above.

[0012] The present disclosure can also be embodied as a computer-executable program, and the program can be recorded in a computer-readable non-transient (non-transient) storage medium. That is, the present disclosure can also be embodied as a computer program product. The program is input to a computer device from an input device or an external device via a communication interface, stored in a storage device, and drives a processor according to a predetermined step or process, and can display the processing result, including an intermediate state, at each stage via a display device as necessary, or can communicate with the outside via the communication interface. For example, a computer device for this purpose typically includes a processor, a storage device, an input device, a communication interface, and a display device as necessary, which are connectable to each other via a bus.

[0013] The outline of the present disclosure will be described below. The reference numerals in the drawings attached to this outline are intended solely to aid in the understanding of the present disclosure, and are not intended to limit the present disclosure to the illustrated embodiment. The connecting lines between the blocks in each drawing include both bidirectional and unidirectional. The unidirectional arrows are intended to diagrammatically indicate the flow of signals, information, data, etc., and do not exclude bidirectionality. Furthermore, the connections between the blocks in each drawing can be either wired or wireless. Furthermore, the program is executed via a computer device, which includes, for example, a processor, a storage device, an input device, a communication interface, and a display device as necessary, and the computer device is configured to be capable of communicating with devices (including computers) within or outside the device via the communication interface, regardless of whether it is wired or wireless.

[0014] Furthermore, in the following description and drawings, elements having the same or common functionality are designated with the same drawing reference numbers.

[0015] FIG. 1 shows a conceptual diagram of an example of a power supply device including an example of an overcurrent suppression circuit of the present disclosure.

[0016] The power supply device 1 includes a DC / DC converter 2 and a DC power supply unit 3 connected to the input side of the DC / DC converter 2. A load R is connected to the output side of the power supply device 1.

[0017] The DC / DC converter 2 includes a DC / DC converter circuit 4 to which a direct current is supplied from a direct current power supply unit 3, and an overcurrent suppression circuit 5 connected to the output side of the DC / DC converter circuit 4.

[0018] The overcurrent suppression circuit 5 includes an output section 6 that receives a direct current from the DC / DC converter circuit 4, and particularly smoothes the direct current and outputs it to a load R, and a control section 7 that controls the output section 6.

[0019] FIG. 2 shows a conceptual diagram of an example of the output unit.

[0020] The output section 6 includes a plurality of semiconductor switches Q 1 , Q 2 , … Q n (n is an integer of 2 or more), and each semiconductor switch Q 1 , Q 2 , … Q n The output capacitor C 1 , C 2 , … C n (n is an integer of 2 or more). And each semiconductor switch Q 1 , Q 2 , … Q n The respective conductive states are controlled by the control unit 7 (or an external computer (not shown) or the like).

[0021] FIG. 3 is a flow chart showing an example of a mode in which an overcurrent occurring when a load R suddenly changes is suppressed by the overcurrent suppression circuit 5 including the output unit 6 shown in FIG. 1 , Q 2 , … Q n Normally, it is always ON, i.e., in a conductive state.

[0022] First, it is determined whether or not a sudden change in the load current has occurred (step 1). Note that in the following, step 1 etc. will be abbreviated as S1 etc.

[0023] When a sudden change in the load current occurs (YES), the control unit 7 turns off all the semiconductor switches Q 1 , Q 2 , … Q n All output capacitors C 1 , C 2 , … C n The charging and discharging of the battery is limited.

[0024] Next, the control unit 7 turns on the semiconductor switch Q 1 , Q 2 , … Q n are switched ON, i.e., to a conductive state, sequentially (i.e., with a staggered timing for switching ON) (S3). 1 , C 2 , … C n Therefore, all the output capacitors C 1 , C 2 , … C n This makes it possible to suppress overcurrent that occurs when the multiple capacitors are simultaneously charged or discharged.

[0025] For example, each semiconductor switch Q 1 , Q 2 , … Q n is the output capacitor C 1 , C 2 , … C n In the case where the conduction direction is the same as the charging direction of the semiconductor switches Q, the load current (corresponding to the output current of the power supply device 1, the DC / DC converter 2, or the output unit 6) increases suddenly due to a sudden change in the load R (see S1). In this case, the control unit 7 controls all the semiconductor switches Q 1 , Q 2 , … Q n are switched OFF, i.e., non-conducting, at the same time (see S2), which causes all the output capacitors C 1 , C 2 , … C nNext, the control unit 7 turns on the semiconductor switch Q 1 , Q 2 , … Q n (see S3), which switches the output capacitor C 1 , C 2 , … C n Therefore, all the output capacitors C 1 , C 2 , … C n This makes it possible to prevent a large inrush current from flowing (i.e., suppress overcurrent) by charging all the batteries at once.

[0026] Also, for example, each semiconductor switch Q 1 , Q 2 , … Q n is the output capacitor C 1 , C 2 , … C n In the case where the conduction direction is opposite to the charging direction of the semiconductor switches Q, it is assumed that the load current is suddenly decreased due to a sudden change in the load R (see S1). In this case, the control unit 7 controls all the semiconductor switches Q 1 , Q 2 , … Q n are switched OFF, i.e., non-conducting, at the same time (see S2), which causes all the output capacitors C 1 , C 2 , … C n Next, the control unit 7 turns on the semiconductor switch Q 1 , Q 2 , … Q n (see S3), which switches the output capacitor C 1 , C 2 , … C n Therefore, all the output capacitors C 1 , C 2 , … C n By discharging all of the capacitors at once, it is possible to prevent a large amount of reverse current from flowing to the switching element of the DC / DC converter circuit 4, for example (that is, to suppress an overcurrent).

[0027] FIG. 4 shows a conceptual diagram of a specific example of a power supply device including an overcurrent suppression circuit of the present disclosure.

[0028] The power supply device 10 includes a DC / DC converter 20 and a DC power supply unit 30 connected to the input side of the DC / DC converter 20. A load R is connected to the output side of the power supply device 10. The voltage of the DC power supply unit 30, and therefore the input voltage of the DC / DC converter 20, is Vin, the output voltage of the DC / DC converter 20 is Vout(t), and the current flowing through the load R is i R It is expressed as (t), where the symbol t represents time (and so on).

[0029] The DC / DC converter 20 includes a DC / DC converter circuit 40 to which a DC current is supplied from a DC power supply unit 30, and an overcurrent suppression circuit 50 connected to the output side of the DC / DC converter circuit 40. Note that although this DC / DC converter 20 is a step-down type, the present disclosure may also be applied to other types of DC / DC converters.

[0030] The DC / DC converter circuit 40 includes a high-side FET (Field Effect Transistor) Q_H as a high-side switching element on the input side of the DC / DC converter circuit 40, a low-side FET Q_L as a low-side switching element on the ground side of the DC / DC converter circuit 40, and an output inductor L between the midpoint between the high-side FET Q_H and the low-side FET Q_L and the output side of the DC / DC converter circuit 40. The inductor current flowing through the output inductor L is i L This is expressed as (t).

[0031] The overcurrent suppression circuit 50 includes an output unit 60 that receives a direct current from the DC / DC converter circuit 40 and outputs the direct current to a load R, and a control unit 70 that controls the output unit 60. The output unit 60 also has a smoothing function for stabilizing the output of the power supply device 10.

[0032] The output section 60 includes a plurality of semiconductor switches Q 1 , Q 2 , … Q n(n is an integer of 2 or more), and each semiconductor switch Q 1 , Q 2 , … Q n The output capacitor C 1 , C 2 , … C n (n is an integer of 2 or more). In the illustrated example, a semiconductor switch Q 1 , Q 2 , … Q n Q is the FET 1 , Q 2 , … Q n and FET Q 1 , Q 2 , … Q n is the output capacitor C 1 , C 2 , … C n Therefore, the FET Q 1 , Q 2 , … Q n When the output capacitor C 1 , C 2 , … C n Charging is limited.

[0033] Each FET Q 1 , Q 2 , … Q n The rectifier D has a forward current opposite to the forward current of each of the two. 1 , D 2 , …D n (n is an integer of 2 or more) are connected in parallel. In the example shown in the figure, rectifier D 1 , D 2 , …D n are the corresponding FET Q 1 , Q 2 , … Q n This is the internal body diode of the FET Q 1 , Q 2 , … Q n When the output capacitor C 1 , C 2 , … C n are the body diodes D 1 , D 2 , …D nThe discharge can be performed through the semiconductor switch Q 1 , Q 2 , … Q n is, for example, a bipolar transistor, the rectifier D 1 , D 2 , …D n can be a discrete diode or the like.

[0034] The control unit 70 controls each FET Q 1 , Q 2 , … Q n A plurality of timer circuits T 1 , T 2 , …T n (n is an integer of 2 or more). Timer circuit T 1 , T 2 , …T n have different settling times, and the intervals between successive settling times are constant or at least partially different. 1 , T 2 , …T n Settling time of T' 1 , T' 2 , …T' n Then, (T' n -T' n-1 ) are all the same or at least partially different, i.e., all (T' n -T' n-1 At least one of (T') is different from the others (all (T' n -T' n-1 ) may be different from each other.

[0035] In the illustrated example, the control unit 70 further includes an amplifier circuit 71 that amplifies the potential difference across a shunt resistor (resistance value Rdet) that serves as a current detector inserted in a power supply line between the output unit 60 and the load R, a differentiation circuit 72 that extracts the fluctuation of the output voltage vdet(t) of the amplifier circuit 71, and a comparator 73 that compares the output voltage vdiff(t) of the differentiation circuit 72 with a reference voltage Vref. The output terminal of the comparator 73 is connected to a timer circuit T 1 , T 2 , …T nVia, each FET Q 1 , Q 2 , …Q n is connected to the gate terminals of.

[0036] Here, the output voltage vdet(t) of the amplifier circuit 71 is, assuming the amplification factor is A, vdet(t)=A×Rdet×i R (t) (Equation 1) is represented by.

[0037] Also, the output voltage vdiff(t) of the differential circuit 72 is, vdiff(t)=dvdet(t) / dt (Equation 2) is represented by.

[0038] And when vdiff(t)>Vref, the timer circuits T 1 , T 2 , …T n are activated, and in response, the FETs Q 1 , Q 2 , …Q n are turned OFF for a certain period of time. Note that the value of Vref is set to a value such that vdiff(t)>Vref does not occur under steady state or a small load sudden change.

[0039] Figure 5 shows a time chart of an example of the operation of the power supply device 10 shown in Figure 4.

[0040] First, assume that there has been no load sudden change and it has been in a steady state until a certain point in time (t 0 ). In this case, the load current i R (t) is a steady current and there is almost no current fluctuation. Therefore, since the output voltage of the differential circuit is vdiff(t)≒0V, vdiff(t)<Vref and the timer circuits T 1 , T 2 , …T n are not activated, and the FETs Q 1 , Q 2 , …Q n are always in the ON state. Therefore, the output capacitors C 1 , C 2 , …Cn is constantly charging and discharging, suppressing voltage ripple.

[0041] Next, at a certain point (t 0 ) a sudden load change occurs, and the load current i R Suppose that (t) suddenly increases. In this case, dvdet(t) / dt increases, so vdiff(t) also increases. As a result, vdiff(t)>Vref holds, so the timer circuit T 1 , T 2 , …T n starts, and FET Q 1 , Q 2 , … Q n are simultaneously turned OFF (t 0 ).

[0042] The DC / DC converter circuit 40 cannot respond quickly enough to pass a large current, but the output capacitor C 1 , C 2 , … C n It is possible to supply current by discharging the charge stored in the 0 ~t 1 In this case, the FET Q 1 , Q 2 , … Q n are in the OFF state, but the charge is 1 , D 2 , …D n Supplied via.

[0043] Output capacitor C 1 , C 2 , … C n The charge discharge of each output capacitor C 1 , C 2 , … C n The voltage across both ends of the inductor current i drops, and Vout(t) drops. However, the response of the DC / DC converter circuit 40 gradually catches up, and the inductor current i L (t) increases (t 0 onwards).

[0044] Inductor current i L(t) increases, i L (t)=i R (t) became (t 1 ) the output capacitor C 1 , C 2 , … C n To charge the inductor current i L (t) tries to increase further, but the FET Q 1 , Q 2 , … Q n Since is in the OFF state, the output capacitor C 1 , C 2 , … C n The FETs Q and Q are not charged at the same time. 1 , Q 2 , … Q n After the switch is turned OFF, for example, t 1 sec later FET Q 1 Switch to ON state, t 2 sec later FET Q 2 Switch to ON state...t n sec later FET Q n The FET Q 1 , Q 2 , … Q n By sequentially switching these on, the charging periods can be spread out, thereby making it possible to limit the flow of large amounts of inrush current when the load suddenly changes.

[0045] In this way, the DC / DC converter 20 including the overcurrent suppression circuit 50 of this example and the DC / DC converter circuit 40 placed in front of the overcurrent suppression circuit 50, or the power supply device 10 including the DC / DC converter 20 and the DC power supply unit 30, can avoid, for example, operation being stopped by overcurrent protection, because the overcurrent suppression circuit 50 restricts the flow of large amounts of inrush current during a sudden load change.

[0046] FIG. 6 shows a detailed time chart of an example of the operation of the power supply device 10 shown in FIG.

[0047] In this example, the load current i R (t) is 0 seconds (t0 ) to t d Δi in seconds R fluctuates by Δi R The current fluctuation range is set so that vdiff(t)>Vref holds. Also, the output capacitor C 1 , C 2 , … C n Assume that all of the capacitances are equal, C [F].

[0048] load current i R (t) is initially set to i R (0) [A], t d Seconds later, i R (t d )=i R (0) + Δi R (Formula 3) It becomes.

[0049] Time t d In this case, the output voltage vdet(t) of the amplifier circuit 71 is expressed by the following equation (1): d )=A×Rdet×i R (t d ), and the output voltage vdiff(t) of the differentiation circuit 72 is expressed by (Equation 2): d )=dvdet(t d ) / dt.

[0050] Due to the preconditions, vdiff(t d )>Vref, so FET Q 1 , Q 2 , … Q n are simultaneously turned OFF (However, FET Q 1 (Only shown for

[0051] On the other hand, the DC / DC converter circuit 40 operates such that the inductor current i L It acts to increase (t).

[0052] i L (t)=i R (t d ) at time tr is expressed using the crossover frequency fbw [Hz] of the DC / DC converter circuit 40 as follows: t r =1 / 4fbw (Equation 4) Therefore, i L (t r )=i R (t d ) holds true.

[0053] This t r For seconds, the output capacitor C 1 , C 2 , … C n serves to release charge to the load R. At this time, the FET Q 1 , Q 2 , … Q n are all in the OFF state, so the output capacitor C 1 , C 2 , … C n The current flowing through the output capacitor C 1 , C 2 , … C n The power supply lines are connected to the corresponding body diodes D 1 , D 2 , …D n Since current flows through, a charge can be supplied to the load R.

[0054] Since the time from when the load suddenly changes until vdiff(t)>Vref is very short, the total charge Δq discharged during this period is Δq ≒ Δi R ×t r / 2 (formula 5) can be approximated as

[0055] t r After 2 seconds, the DC / DC converter circuit 40 turns on the output capacitor C 1 , C 2 , … C n In order to charge the FET Q 1 , Q 2 , … Q n Since is in the OFF state, the output capacitor C1 , C 2 , … C n It won't charge immediately.

[0056] And t 1 (t r ) seconds, FET Q 1 is switched to the ON state, and accordingly, the output capacitor C 1 Charging will begin.

[0057] Output capacitor C 1 , C 2 , … C n Since all the capacitances are equal, the amount of charge required to charge them is Δq / n.

[0058] Output capacitor C 1 The time (point) when charging is completed is t 1 ' and (t 1 '-t 1 ) seconds, the output capacitor C 1 The maximum value of the current flowing through is Im1.

[0059] (t 1 '-t 1 ) seconds L If the waveform related to charging (t) is approximated by a triangle, the area of ​​the triangle is equal to Δq / n. Therefore, if Im1 is expressed using Δq, Δq / n=Im1×(t 1 '-t 1 ) / 2 (Equation 6) Im1 = 2Δq / n(t 1 '-t 1 ) (Equation 7) It becomes.

[0060] Therefore, if the time when Im1 occurs is tm1, then i L (tm1) is the load current + output capacitor C 1 The charging current to i L (tm1)=i R (t d )+Im1 (Equation 8) It becomes.

[0061] Output capacitor C 1 After charging is completed, the FET Q 2 is switched to the ON state, and the output capacitor C 2 is charged in the same way. The output capacitor C n It will continue to charge until the battery level reaches 100%.

[0062] Output capacitor C 2 ~C n Since all of the capacitances are equal, the current required for charging is also equal, and the maximum inrush current is the current value shown in (Equation 8).

[0063] Therefore, according to the present disclosure, the inrush current associated with charging the capacitor can be limited to the current value shown in (Equation 8).

[0064] As shown in (Equation 7), the more the number of output capacitors connected in parallel, i.e. the number of parallel connections n, is increased, the more the inrush current can be reduced, but this increase can lead to problems such as higher costs due to the increase in the number of FETs and longer charging times. Therefore, it is desirable to determine the optimal number of parallel connections as appropriate depending on the usage required of the power supply device.

[0065] FIG. 7 shows a conceptual diagram of another specific example of a power supply device including an overcurrent suppression circuit of the present disclosure.

[0066] The configuration of the power supply device 100 in this example is basically the same as that of the power supply device 10 in the example shown in FIG. 4, but the FET Q 1 , Q 2 , … Q n and body diode D 1 , D 2 , …D n The difference is that the sense of each FET Q is reversed, and an inverting circuit is additionally included between the differentiation circuit and the comparator. 1 , Q 2 , … Q n is the output capacitor C 1 , C 2 , … C n The conduction direction is opposite to the charging direction of the

[0067] An example of the operation of the overcurrent suppression circuit 500 of this example will be briefly described below. In this example, too, in the steady state, the FET Q 1 , Q 2 , … Q n is always ON, and the output capacitor C 1 , C 2 , … C n can be repeatedly charged and discharged at any time.

[0068] First, the load current i R Suppose (t) suddenly decreases.

[0069] Then, the output voltage of the differentiation circuit 702, which extracts the fluctuation of the output voltage vdet(t) of the amplifier circuit 701, which amplifies the potential difference across the shunt resistor (resistance value Rdet) acting as a current detector inserted in the power supply line between the output section 600 and the load R, falls (vdiff(t)), but the output voltage of the inversion circuit 704 to which this voltage is input rises (-vdiff(t)).

[0070] The output voltage of the inverting circuit 704 is input to a comparator 703 and compared with a reference voltage Vref.

[0071] When the output voltage of the inverter circuit 704 exceeds the reference voltage Vref (or threshold), the timer circuit T 1 , T 2 , …T n is activated and in response, the FET Q 1 , Q 2 , … Q n is switched to the OFF state. 1 , Q 2 , … Q n However, the excessive inductor current i due to the sudden drop in the load current L (t) is FET Q 1 , Q 2 , … Q n The forward direction of the body diode D is opposite to the conduction direction of 1 , D 2 , …D nThrough the output capacitor C 1 , C 2 , … C n Can be charged.

[0072] Timer circuit T 1 , T 2 , …T n have different settling times, but the timer circuit T 1 , T 2 , …T n If the settling times of the FET Q 1 , Q 2 , … Q n are switched to the ON state in this order. 1 , C 2 , … C n Since the charge is not released all at once but is discharged sequentially, excessive reverse current flow can be suppressed.

[0073] Therefore, the DC / DC converter 200 including the overcurrent suppression circuit 500 of this example and the DC / DC converter circuit 400 placed in front of the overcurrent suppression circuit 500 can operate, for example, as follows.

[0074] load current i R When (t) suddenly decreases, the DC / DC converter circuit 400 cannot keep up with the response, and the inductor current i L (t) does not decrease suddenly but gradually.

[0075] Meanwhile, the excess inductor current i L (t) is the output capacitor C 1 , C 2 , … C n is charged.

[0076] Inductor current i L (t) and load current i R When (t) is equal, the output capacitor C 1 , C 2 , … C n The charge stored in the load current i RWhen (t) is small, a phenomenon occurs in which charge does not flow to the load R but flows back to the DC / DC converter circuit 400.

[0077] In particular, the load current i R If (t) suddenly drops to near 0 A and the reverse current is large, there is a risk that the switching elements (high-side FET Q_H and low-side FET Q_L) inside the DC / DC converter circuit 400 will break down.

[0078] However, the overcurrent suppression circuit 500 in this example is R If (t) suddenly decreases, all FETs Q 1 , Q 2 , … Q n is switched to the OFF state, and the output capacitor C 1 , C 2 , … C n This prevents charge from flowing out of the FET Q 1 , Q 2 , … Q n By switching ON the output capacitor C 1 , C 2 , … C n This can prevent the current from flowing backwards all at once.

[0079] In this way, in the DC / DC converter 200 including the overcurrent suppression circuit 500 of this example and the DC / DC converter circuit 400 placed in front of the overcurrent suppression circuit 500, or the power supply device 100 including the DC / DC converter 200 and the DC power supply unit 300, the overcurrent suppression circuit 500 restricts the flow of large amounts of backflow current during a sudden load change, so that it is possible to avoid, for example, failure of the switching element of the DC / DC converter circuit 400.

[0080] The control circuit according to the above embodiment can be configured using so-called hardware resources (information processing device, computer), and can use one having the configuration shown in Fig. 8. For example, the hardware resources 1000 can include a processor 1001, a memory 1002, a network interface 1003, etc., which are connected to each other by an internal bus 1004.

[0081] 8 is not intended to limit the hardware configuration of the hardware resource 1000. The hardware resource 1000 may include hardware (e.g., an input / output interface) that is not shown. The processor 1001 may be, for example, a central processing unit (CPU), a microprocessor unit (MPU), or a graphics processing unit (GPU).

[0082] Furthermore, for example, a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), etc. can be used for the memory 1002. Here, the memory 1002 can store a predetermined threshold value related to the above-mentioned predetermined physical quantity, and can also store a control program for performing the above-mentioned control.

[0083] Furthermore, the network interface 1003 may be, for example, a LAN (Local Area Network) card, a network adapter, a network interface card, or the like.

[0084] Furthermore, the functions of the hardware resource 1000 are realized by a processing module. The processing module is realized, for example, by the processor 1001 executing a program stored in the memory 1002. The program can be updated by downloading it via a network or by using a storage medium storing the program. Furthermore, the processing module may be realized by a semiconductor chip. That is, it is sufficient that the functions performed by the processing module can be realized by executing software on some kind of hardware.

[0085] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes. [Appendix 1] An overcurrent suppression circuit including an output section that receives a direct current and outputs a direct current, and a control section. The output section includes a plurality of semiconductor switches connected in parallel, and an output capacitor connected in series to each of the semiconductor switches. The control section is configured to, when a sudden change occurs in the load current from the output section, perform control to switch the semiconductor switches to a non-conductive state and then to sequentially switch them to a conductive state. [Appendix 2] In the above overcurrent suppression circuit, The control unit includes a plurality of timer circuits each having a different settling time. Each of the plurality of timer circuits is assigned to one semiconductor switch. [Appendix 3] In the above overcurrent suppression circuit, The timer circuit is configured to be activated when a sudden change in the load current occurs, to bring the semiconductor switch to which the timer circuit is assigned into a non-conductive state, and to bring the semiconductor switch into a conductive state again after a settling time of the timer circuit has elapsed. [Appendix 4] In the above overcurrent suppression circuit, The control unit is configured to execute control when a sudden change in the load current occurs, when a differential value of the voltage calculated from the load current is greater than a predetermined reference voltage value. [Appendix 5] In the above overcurrent suppression circuit, The semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor. The sudden change in the load current is a sudden increase in the load current. [Appendix 6] In the above overcurrent suppression circuit, The semiconductor switch has a conduction direction opposite to the charging direction of the output capacitor. The sudden change in the load current is a sudden decrease in the load current. [Appendix 7] In the above overcurrent suppression circuit, The output section includes a rectifier, particularly a diode, connected in parallel to each semiconductor switch and having a forward direction opposite to the conduction direction of the semiconductor switch. [Appendix 8] In the above overcurrent suppression circuit, The semiconductor switch is a field effect transistor, and the rectifier is a body diode of the field effect transistor. [Appendix 9] In the above overcurrent suppression circuit, The semiconductor switches are bipolar transistors and the rectifiers are discrete diodes. [Appendix 10] In the above overcurrent suppression circuit, The control unit is configured to perform control to sequentially switch the semiconductor switches to the conductive state at regular time intervals or at least partially at different time intervals. [Appendix 11] In the above overcurrent suppression circuit, The intervals between settling times of the plurality of timer circuits passing in sequence may be constant or at least partially different. [Appendix 12] In the above overcurrent suppression circuit, The control unit includes a comparator that compares a differential value of a voltage determined from the load current with the predetermined reference voltage value. [Appendix 13] In the above overcurrent suppression circuit, The control section includes a differentiation circuit for generating a desired differential value of a voltage from the load current via an amplifier circuit as required, and includes an amplifier circuit as required. [Appendix 14] In the above overcurrent suppression circuit, The load current is a current detected by a current detector, particularly a shunt resistor, connected to the output side of the overcurrent suppression circuit. [Supplementary Note 15] A DC / DC converter including an overcurrent suppression circuit according to the present disclosure and a DC / DC converter circuit arranged upstream of the overcurrent suppression circuit (connected to the input side of the overcurrent suppression circuit). [Appendix 16] In the above DC / DC converter, The DC / DC converter circuit includes a high-side switching element (such as a field effect transistor) on the input side of the DC / DC converter circuit, a low-side switching element (such as a field effect transistor) on the ground side of the DC / DC converter circuit, and an output inductor between the midpoint between the high-side switching element and the low-side switching element and the output side of the DC / DC converter circuit. [Supplementary Note 17] A power supply device including a DC / DC converter according to the present disclosure, and a DC power supply unit placed upstream of the DC / DC converter (connected to the input side of the DC / DC converter). [Appendix 18] In the above power supply device, The DC power supply unit is an AC / DC converter. Note that "AC" is an abbreviation for "Alternating Current." [Appendix 19] A method for suppressing overcurrent in a DC / DC converter (or a power supply device including a DC / DC converter). The DC / DC converter comprises: A DC / DC converter circuit, and An overcurrent suppression circuit including a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each of the semiconductor switches, and a control unit, and which outputs a direct current input from the DC / DC converter circuit to a load as a direct load current. Includes. In the overcurrent suppression method, when a sudden change occurs in the load current, the control unit switches the semiconductor switches to a non-conductive state and then sequentially switches them to a conductive state. [Appendix 20] In the above overcurrent suppression method, The control unit performs control to sequentially switch the semiconductor switches to the conductive state at regular time intervals or at least partially at different time intervals. [Appendix 21] In the above overcurrent suppression method, The control unit executes control for when a sudden change in the load current occurs, when a differential value of the voltage calculated from the load current is greater than a predetermined reference voltage value. [Appendix 22] In the above overcurrent suppression method, The sudden change in the load current is a sudden increase in the load current, The semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor. [Appendix 23] In the above overcurrent suppression method, The sudden change in the load current is a sudden decrease in the load current, The semiconductor switch has a conduction direction opposite to the charging direction of the output capacitor. [Appendix 24] A control program for a DC / DC converter (or a power supply device including a DC / DC converter). The DC / DC converter comprises: A DC / DC converter circuit, and An overcurrent suppression circuit including a plurality of semiconductor switches connected in parallel and an output capacitor connected in series to each of the semiconductor switches, and which outputs a direct current input from the DC / DC converter circuit to a load as a direct load current. Includes. The control program causes a computer to execute control to switch the semiconductor switches to a non-conductive state and then to sequentially switch them to a conductive state when a sudden change occurs in the load current. [Appendix 25] The above control program is The computer executes control to sequentially switch the plurality of semiconductor switches to the conductive state at regular time intervals or at least partially at different time intervals. [Appendix 26] The above control program is When the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value, the computer is caused to execute control for when a sudden change in the load current occurs. [Appendix 27] In the above control program, The sudden change in the load current is a sudden increase in the load current, The semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor. [Appendix 28] In the above control program, The sudden change in the load current is a sudden decrease in the load current, The semiconductor switch has a conduction direction opposite to the charging direction of the output capacitor. [Appendix 29] The above DC / DC converter is a step-down DC / DC converter.

[0086] Within the scope of the entire disclosure of the present invention (including the scope of claims), modifications and adjustments of the embodiments and examples are possible based on the basic technical ideas. Furthermore, within the scope of the entire disclosure of the present invention, various combinations and selections (including partial deletions) of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and alterations that a person skilled in the art would be able to make based on the entire disclosure including the scope of claims and the technical ideas. [Explanation of symbols]

[0087] 1, 10, 100 power supplies 2, 20, 200 DC / DC Converters 3, 30, 300 DC power supply section 4, 40, 400 DC / DC converter circuits 5, 50, 500 overcurrent suppression circuit 6, 60, 600 Output section 7, 70, 700 Control Unit 71, 701 Amplification circuit 72, 702 Differential circuit 73, 703 Comparator 704 Inverting Circuit C 1 , C 2 , … C n Output Capacitor D1 , D 2 , …D n (Body) Diode Q 1 , Q 2 , … Q n FET T 1 , T 2 , …T n Timer Circuit R load L Output inductor i R load current i L Inductor Current 1000 Hardware Resources 1001 Processor 1002 Memory 1003 Network Interface 1004 Internal Bus

Claims

1. An overcurrent suppression circuit including an output section that receives a direct current and outputs a direct current, and a control section, the output section includes a plurality of semiconductor switches connected in parallel and an output capacitor connected in series to each of the semiconductor switches; The control unit is configured to, when a sudden change occurs in the load current from the output unit, switch the semiconductor switches to a non-conductive state and then sequentially switch them to a conductive state. An overcurrent suppression circuit comprising:

2. 2. The overcurrent suppression circuit according to claim 1, the control unit includes a plurality of timer circuits each having a different settling time; Each of the plurality of timer circuits is assigned to one semiconductor switch. An overcurrent suppression circuit comprising:

3. 3. The overcurrent suppression circuit according to claim 2, The timer circuit is configured to be activated when a sudden change in the load current occurs, to bring the semiconductor switch to which the timer circuit is assigned into a non-conductive state, and to bring the semiconductor switch into a conductive state again after a settling time of the timer circuit has elapsed. An overcurrent suppression circuit comprising:

4. 2. The overcurrent suppression circuit according to claim 1, The control unit is configured to execute control when a sudden change in the load current occurs when a differential value of the voltage calculated from the load current is greater than a predetermined reference voltage value. An overcurrent suppression circuit comprising:

5. 2. The overcurrent suppression circuit according to claim 1, the semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor; The sudden change in the load current is a sudden increase in the load current. An overcurrent suppression circuit comprising:

6. 2. The overcurrent suppression circuit according to claim 1, the semiconductor switch has a conduction direction opposite to a charging direction of the output capacitor; The sudden change in the load current is a sudden decrease in the load current. An overcurrent suppression circuit comprising:

7. 2. The overcurrent suppression circuit according to claim 1, the output section includes a rectifier connected in parallel to each semiconductor switch and having a forward direction opposite to the conduction direction of the semiconductor switch; An overcurrent suppression circuit comprising:

8. 8. A DC / DC converter comprising: an overcurrent suppression circuit according to claim 1; and a DC / DC converter circuit disposed upstream of the overcurrent suppression circuit.

9. A power supply device comprising: a DC / DC converter according to claim 8; and a DC power supply section disposed upstream of the DC / DC converter.

10. A DC / DC converter circuit, and An overcurrent suppression circuit including a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each of the semiconductor switches, and a control unit, and outputs a direct current input from the DC / DC converter circuit to a load as a direct current load current. A method for suppressing an overcurrent in a DC / DC converter, comprising: When a sudden change occurs in the load current, the control unit switches the plurality of semiconductor switches to a non-conductive state, and then switches the semiconductor switches to a conductive state in sequence. An overcurrent suppression method comprising:

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