Semiconductor Device

Abstract

To provide a semiconductor device capable of enhancing heat dissipation characteristics.SOLUTION: A semiconductor device 20 has a second member 22 bonded in surface contact to the first face 21A of the first member 21 that includes a semiconductor region made of a single semiconductor. A second member 22 includes a compound semiconductor-based high-frequency amplifier circuit. A conductor projection 82 protrudes from the second member 22 on a side opposite to the side of the first member 21. The first member 21 includes internally a temperature measuring element 46 for detecting temperature.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] RF front-end modules that integrate the transmission and reception functions of high-frequency signals are built into electronic devices used in mobile communications, satellite communications, etc. RF front-end modules include a monolithic microwave integrated circuit (MMIC) with high-frequency amplification functions, a control IC that controls the high-frequency amplification circuit, a switch IC, a duplexer, etc.

[0003] A high-frequency module that is miniaturized by stacking a control IC on an MMIC is disclosed in the following Patent Document 1. The high-frequency module disclosed in Patent Document 1 includes an MMIC mounted on a module substrate and a control IC stacked on top of the MMIC. Electrodes of the MMIC, electrodes of the control IC, and electrodes on the module substrate are electrically connected by wire bonding. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2015 / 0303971 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, heterojunction bipolar transistors (HBTs) are used in high-frequency amplifier circuits. HBTs generate heat due to collector loss during operation. The increase in temperature of the HBT due to heat generation acts to further increase the collector current. When this positive feedback condition is met, the HBT goes into thermal runaway. To prevent thermal runaway, an upper limit is set on the output power of the HBT.

[0006] In order to increase the output power of a high-frequency amplifier circuit, it is desirable to improve the heat dissipation characteristics of semiconductor devices including HBTs, etc. With the high-frequency module disclosed in Patent Document 1, it is difficult to satisfy the recent demand for high-frequency amplifier circuits with high output power.

[0007] An object of the present invention is to provide a semiconductor device capable of improving heat dissipation characteristics. [Means for solving the problem]

[0008] According to one aspect of the present invention, a first member having a first surface and including a semiconductor region made of a single semiconductor; A second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with A semiconductor device comprising: The first member includes a temperature sensor element for detecting temperature. fruit, The conductor projection is configured to mount the semiconductor device on a module substrate. A semiconductor device is provided. Effect of the Invention

[0009] Two heat transfer paths are formed: one from the high frequency amplifier circuit of the second member through the joint interface between the first member and the second member to the first member, and the other from the second member through the conductor protrusion to the module substrate on which the semiconductor device is mounted. This improves the heat dissipation characteristics from the high frequency amplifier circuit. Since the temperature measuring element is included inside the first member and the second member and the first member are in surface contact, there is also an excellent effect that the temperature of the second member in which the high frequency amplifier circuit is provided is easily reflected in the temperature detection value by the temperature measuring element. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to a first embodiment. [Diagram 2]FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3A is an equivalent circuit diagram of each of a plurality of cells constituting a power stage amplifier circuit of a semiconductor device according to a first embodiment, and FIG. 3B is a schematic cross-sectional view of one cell constituting the power stage amplifier circuit formed in a second member. [Figure 4] 4A to 4F are cross-sectional views of a semiconductor device during its manufacturing process. [Diagram 5] 5A to 5C are cross-sectional views of a semiconductor device during its manufacturing process, and FIG. 5D is a cross-sectional view of the completed semiconductor device. [Figure 6] FIG. 6 is a diagram showing the positional relationship of some components of a semiconductor device according to the second embodiment in a plan view. [Figure 7] FIG. 7A is a diagram showing the positional relationship of some components of a semiconductor device according to a third embodiment in a plan view, and FIG. 7B is a diagram showing the arrangement of a plurality of transistors and temperature measuring elements in a plan view. [Figure 8] FIG. 8 is a block diagram of a semiconductor device according to the fourth embodiment. [Figure 9] FIG. 9 is a graph showing the temperature dependency of the output of the transistor in the power stage amplifier circuit of the semiconductor device according to the fourth embodiment, and the magnitude of the bias current that is changed according to the temperature. [Figure 10] FIG. 10 is a block diagram showing a part of the functions of the semiconductor device according to the fifth embodiment. [Figure 11] FIG. 11 is a graph showing the relationship between the attenuation rate of a high-frequency signal from an input terminal to a driver stage amplifier circuit of the semiconductor device according to the fifth embodiment and the temperature detected by the temperature measuring element. [Figure 12] FIG. 12 is a block diagram showing a part of the functions of a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a block diagram of a semiconductor device according to the seventh embodiment. [Figure 14] FIG. 14 is a block diagram of a semiconductor device according to the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [First Example] A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 5D. 1 is a block diagram of a semiconductor device 20 according to a first embodiment. The semiconductor device 20 according to the first embodiment includes a first member 21 and a second member 22. The semiconductor device 20 is flip-chip mounted on a module substrate. A plurality of duplexers 90 and receiving circuits 91 are mounted on the module substrate. The semiconductor device 20 according to the first embodiment is used for communication using a frequency division duplex (FDD) system.

[0012] The first member 21 includes an input switch circuit 31, an interstage matching circuit 32, an output matching circuit 33, an output switch circuit 34, an antenna switch circuit 35, a charge pump circuit 40, bias control circuits 41 and 42, an input switch control circuit 43, an output switch control circuit 44, an antenna switch control circuit 45, a temperature measuring element 46, and a digital circuit 47. As another configuration example, the input switch circuit 31, the interstage matching circuit 32, the output matching circuit 33, the output switch circuit 34, and the antenna switch circuit 35 may be configured by surface mount type components mounted on a module substrate, or by a metal pattern in the module substrate. The second member 22 includes a high-frequency amplifier circuit 50 having a two-stage configuration of a driver stage amplifier circuit 51 and a power stage amplifier circuit 52. The second member 22 may include the interstage matching circuit 32.

[0013] The two input contacts of the input switch circuit 31 are respectively connected to the two input terminals IN1 and IN2 of the module substrate. The input switch control circuit 43 selects one input terminal from the two input contacts, and inputs the high frequency signal input to the selected input terminal to the driver stage amplifier circuit 51. The input switch circuit 31 is controlled by the input switch control circuit 43.

[0014] The high frequency signal amplified by the driver stage amplifier circuit 51 is input to the power stage amplifier circuit 52 via the interstage matching circuit 32. The high frequency signal amplified by the power stage amplifier circuit 52 is input to the input contact of the output switch circuit 34 via the output matching circuit 33. Bias control circuits 41 and 42 control the bias current or bias voltage supplied to the driver stage amplifier circuit 51 and the power stage amplifier circuit 52, respectively.

[0015] The output switch circuit 34 selects one output contact from among the multiple output contacts, and transmits the high-frequency signal input to the input contact to the selected output contact. The multiple output contacts of the output switch circuit 34 are connected to the transmission signal input ports of the multiple duplexers 90, respectively. The output switch circuit 34 is controlled by an output switch control circuit 44.

[0016] The multiple circuit side contacts of the antenna switch circuit 35 are respectively connected to the transmission / reception common ports of the multiple duplexers 90. The antenna switch circuit 35 selects one circuit side contact from the multiple circuit side contacts and connects the selected circuit side contact to the antenna side contact. The antenna switch circuit 35 is controlled by an antenna switch control circuit 45. The antenna side contact of the antenna switch circuit 35 is connected to an antenna terminal ANT of the module board. An antenna 92 ​​is connected to the antenna terminal ANT. The reception signal output ports of the multiple duplexers 90 are respectively connected to a reception circuit 91.

[0017] The high-frequency signal amplified by the power stage amplifier circuit 52 passes through the output matching circuit 33, the output switch circuit 34, and the duplexer 90, and is radiated from the antenna 92. The signal received by the antenna 92 ​​is input to the receiving circuit 91 via the antenna switch circuit 35 and the duplexer 90.

[0018] The charge pump circuit 40 is connected to a power supply terminal VDD of the module board. A voltage boosted to a predetermined voltage by the charge pump circuit 40 is applied to an input switch control circuit 43, an output switch control circuit 44, and an antenna switch control circuit 45. Furthermore, a power supply voltage is applied to bias control circuits 41 and 42 from the power supply terminal VDD.

[0019] The temperature measuring element 46 measures the temperature. The measurement result is input as an analog signal to the digital circuit 47. For example, a semiconductor temperature sensor such as a silicon diode is used as the temperature measuring element 46. The digital circuit 47 converts the measured temperature value input from the temperature measuring element 46 into a digital value and outputs it from a digital input / output terminal I / O. The digital circuit 47 functions as a temperature detection circuit that performs AD conversion on the analog measured temperature value and outputs it. Furthermore, the digital circuit 47 decodes a command input from the outside and outputs a control signal to each control circuit in the first member 21.

[0020] FIG. 2 is a schematic cross-sectional view of a semiconductor device 20 according to a first embodiment. The first member 21 includes a substrate 211, a multilayer wiring structure 212 disposed thereon, and a first member protective film 213 covering the surface of the multilayer wiring structure 212. The substrate 211 includes a semiconductor region of a single semiconductor system. For example, a silicon substrate or a silicon-on-insulator (SOI) substrate is used as the substrate 211. The semiconductor elements and wiring constituting the input switch circuit 31 and the like shown in FIG. 1 are composed of semiconductor elements formed on the surface layer of the substrate 211 and wiring in the multilayer wiring structure 212. The passive elements constituting the interstage matching circuit 32 and the like are composed of metal patterns in the multilayer wiring structure 212. The temperature measuring element 46 is composed of a diode formed on the surface layer of the substrate 211. In FIG. 2, the regions in which the bias control circuit 42, the digital circuit 47, and the temperature measuring element 46 are formed are surrounded by dashed lines.

[0021] The surface of the first member protective film 213 is referred to as the first surface 21A of the first member 21. The second member 22 is joined in surface contact with the first surface 21A of the first member 21. In Fig. 2, the area in which the power stage amplifier circuit 52 formed on the second member 22 is arranged is shown surrounded by a dashed line.

[0022] An interlayer insulating film 67 is disposed on the first surface 21A so as to cover the second member 22. A plurality of openings are provided at predetermined positions in the interlayer insulating film 67. Pads 62, 63 and wiring 61 are disposed on the interlayer insulating film 67. The wiring layer in which the pads 62, 63 and wiring 61 are disposed may be referred to as a rewiring layer. The wiring 61 in the rewiring layer may be referred to as a rewiring.

[0023] The wiring 61 passes through an opening provided in the interlayer insulating film 67 and is connected to the bias control circuit 42 via a wiring 215 in the multilayer wiring structure 212, and is also connected to the power stage amplifier circuit 52 through another opening provided in the interlayer insulating film 67. In addition to the wiring 61, a plurality of other wirings are arranged in the redistribution layer. The wiring in the redistribution layer is used, for example, to connect the input switch circuit 31 and the driver stage amplifier circuit 51 shown in FIG. 1 .

[0024] The pad 62 is included in the second member 22 in a plan view, and is connected to a circuit formed in the second member 22. The other pad 63 is disposed outside the second member 22 in a plan view, and is connected to a digital circuit 47 formed in the first member 21 via a wiring 216 in the multilayer wiring structure 212. The temperature measuring element 46 is connected to the digital circuit 47 via a wiring 217 in the multilayer wiring structure 212.

[0025] A protective film 68 is disposed on the interlayer insulating film 67 so as to cover the rewiring layer. Openings are provided in the protective film 68 to expose partial regions of the upper surfaces of the pads 62 and 63. Conductor protrusions 82 and 83 are disposed on the pads 62 and 63, respectively. The conductor protrusion 82 includes a Cu pillar 82P connected to the pad 62 and a solder layer 82S disposed on the upper surface of the Cu pillar 82P. The conductor protrusion 82 having such a structure is called a Cu pillar bump.

[0026] An under-bump metal layer may be disposed on the bottom surface of the Cu pillar 82P in order to improve adhesion. The other conductor protrusions 83 have the same layered structure as the conductor protrusion 82. Instead of the Cu pillar bump, the conductor protrusions 82, 83, etc. may be an Au bump, a solder ball bump, a conductor post erected on a pad, etc. A bump without a solder layer, such as an Au bump, is also called a pillar. A conductor post erected on a pad is also called a post.

[0027] The conductor protrusion 82 is used, for example, to connect a ground conductor in the second member 22 to a ground conductor of a module substrate. In addition to the conductor protrusion 83, a plurality of conductor protrusions are arranged on the outside of the second member 22 in a plan view. These conductor protrusions are used, for example, to connect the input switch circuit 31 and input terminals IN1 and IN2 shown in FIG. 1 and to connect the output switch circuit 34 and the duplexer 90, etc.

[0028] 3A is an equivalent circuit diagram of each of a plurality of cells constituting the power stage amplifier circuit 52 (FIG. 1) of the semiconductor device 20 according to the first embodiment. The power stage amplifier circuit 52 is composed of a plurality of cells connected in parallel to each other. The driver stage amplifier circuit 51 (FIG. 1) also has a circuit configuration similar to that of the power stage amplifier circuit 52. However, the number of cells constituting the driver stage amplifier circuit 51 is smaller than the number of cells constituting the power stage amplifier circuit 52.

[0029] Each cell includes a transistor Q, an input capacitor Cin, and a ballast resistor Rb. The base of the transistor Q is connected to a high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of the transistor Q is connected to a base bias wiring 104BB via a ballast resistor Rb. The emitter of the transistor Q is grounded. The collector of the transistor Q is connected to a collector wiring 104C. A power supply voltage is applied to the collector of the transistor Q via the collector wiring 104C, and an amplified high-frequency signal is output from the collector.

[0030] 3B is a schematic cross-sectional view of one cell constituting the power stage amplifier circuit 52 (FIG. 1) formed in the second member 22. The second member 22 includes an underlying semiconductor layer 101. The underlying semiconductor layer 101 is in surface contact with the first member 21, thereby bonding the second member 22 to the first member 21. The underlying semiconductor layer 101 is divided into a conductive region 101A and an element isolation region 101B. The underlying semiconductor layer 101 is made of, for example, GaAs. The conductive region 101A is formed of n-type GaAs, and the element isolation region 101B is formed by ion-implanting an insulating impurity into the n-type GaAs layer.

[0031] A transistor Q is disposed on the conductive region 101A. The transistor Q includes a collector layer 102C, a base layer 102B, and an emitter layer 102E, which are stacked in this order from the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is formed of n-type GaAs, the base layer 102B is formed of p-type GaAs, and the emitter layer 102E is formed of n-type InGaP. That is, the transistor Q is a heterojunction bipolar transistor. Other compound semiconductor-based semiconductor elements may also be used as the transistor Q.

[0032] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0033] A first interlayer insulating film 111 is disposed on the underlying semiconductor layer 101 so as to cover the transistor Q, the collector electrode 103C, the base electrode 103B, and the emitter electrode 103E. The first interlayer insulating film 111 is formed of an inorganic insulating material such as SiN. Openings are provided at a plurality of predetermined positions in the interlayer insulating film 111.

[0034] An emitter wiring 104E, a base wiring 104B, a collector wiring 104C, and a base bias wiring 104BB of the first layer are disposed on the interlayer insulating film 111. Furthermore, a ballast resistor element Rb is disposed on the interlayer insulating film 111. The emitter wiring 104E is connected to the emitter electrode 103E through an opening provided in the interlayer insulating film 111. The base wiring 104B is connected to the base electrode 103B through another opening provided in the interlayer insulating film 111. The collector wiring 104C is connected to the collector electrode 103C through another opening provided in the interlayer insulating film 111.

[0035] The base wiring 104B extends to an area where the transistor Q is not arranged, and its tip overlaps one end of the ballast resistance element Rb. At the overlapping portion, the base wiring 104B and the ballast resistance element Rb are electrically connected. The other end of the ballast resistance element Rb overlaps the base bias wiring 104BB. At the overlapping portion, the ballast resistance element Rb and the base bias wiring 104BB are electrically connected.

[0036] A second interlayer insulating film 112 is disposed on the interlayer insulating film 111 so as to cover the first emitter wiring 104E, the base wiring 104B, the base bias wiring 104BB, and the ballast resistor element Rb. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0037] A second-layer emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second-layer emitter wiring 105E is connected to the first-layer emitter wiring 104E through an opening provided in the interlayer insulating film 112. A portion of the high-frequency signal input wiring 105RF overlaps with the first-layer base wiring 104B in a plan view. An input capacitor Cin is formed in the overlapping region between the two.

[0038] A third interlayer insulating film 67 is disposed so as to cover the second-layer emitter wiring 105E and the high-frequency signal input wiring 105RF. The third interlayer insulating film 67 is formed of an organic insulating material such as polyimide. The third interlayer insulating film 67 extends up to above the first member 21 as shown in FIG. 2.

[0039] A pad 62 is disposed on the third interlayer insulating film 67. The pad 62 passes through an opening provided in the interlayer insulating film 67 and is connected to the second emitter wiring 105E.

[0040] Next, a method for manufacturing the semiconductor device 20 according to the first embodiment will be described with reference to Figures 4A to 5D. Figures 4A to 5C are cross-sectional views of the semiconductor device 20 during the manufacturing process, and Figure 5D is a cross-sectional view of the completed semiconductor device 20.

[0041] As shown in FIG. 4A, a release layer 201 is epitaxially grown on a mother substrate 200 of a single crystal of a compound semiconductor such as GaAs, and an element formation layer 202 is formed on the release layer 201. In the element formation layer 202, the underlying semiconductor layer 101 of the second member 22 shown in FIG. 3B, the transistor Q, the first wiring layer, the second wiring layer, and the like are formed. These circuit elements and wiring layers are formed by a general semiconductor process. In FIG. 4A, the element structure formed in the element formation layer 202 is omitted. At this stage, the element formation layer 202 is not separated into individual second members 22.

[0042] 4B, the element formation layer 202 (FIG. 4A) and the release layer 201 are patterned using a resist pattern (not shown) as an etching mask. At this stage, the element formation layer 202 (FIG. 4A) is separated into each second member 22.

[0043] Next, as shown in Fig. 4C, a connecting support 204 is attached onto the separated second member 22. As a result, the multiple second members 22 are connected to each other via the connecting support 204. Note that the resist pattern used as an etching mask in the patterning step of Fig. 4B may be left to interpose a resist pattern between the second member 22 and the connecting support 204.

[0044] 4D, the release layer 201 is selectively etched with respect to the mother substrate 200 and the second member 22. As a result, the second member 22 and the connecting support 204 are peeled off from the mother substrate 200. In order to selectively etch the release layer 201, a compound semiconductor having an etching resistance different from that of both the mother substrate 200 and the second member 22 is used as the release layer 201.

[0045] 4E, a substrate 210 is prepared on which a bias control circuit 42 (FIG. 2), a temperature measuring element 46 (FIG. 2), a digital circuit 47 (FIG. 2), a multilayer wiring structure 212 (FIG. 2), and the like are formed, which are to be provided on a first member 21 (FIG. 2). At this stage, the substrate 210 is not separated into individual first members 21.

[0046] As shown in Fig. 4F, the second member 22 is bonded to the substrate 210. The second member 22 and the substrate 210 are bonded by van der Waals bonds or hydrogen bonds. Alternatively, the second member 22 may be bonded to the substrate 210 by electrostatic forces, covalent bonds, eutectic alloy bonds, or the like. For example, when a portion of the surface of the substrate 210 is formed of Au, the second member 22 may be bonded to the substrate 210 by closely contacting the Au region and applying pressure thereto.

[0047] Next, as shown in Fig. 5A, the connecting support 204 is peeled off from the second member 22. After the connecting support 204 is peeled off, as shown in Fig. 5B, an interlayer insulating film 67 and a rewiring layer are formed on the substrate 210 and the second member 22. The rewiring layer includes wiring 61, pads 62 and 63 (Fig. 2), and the like.

[0048] 5C, a protective film 68 is formed on the redistribution layer, and openings are formed at predetermined positions in the protective film 68. Thereafter, a conductor protrusion 82 is formed in the opening and on the protective film 68. At the same time as the conductor protrusion 82 is formed, other conductor protrusions 83 (FIG. 2) and the like are also formed.

[0049] 5D, the substrate 210 is diced, whereby the substrate 210 is separated into individual first members 21, and the semiconductor devices 20 are obtained.

[0050] Next, the excellent effects of the first embodiment will be described. A plurality of transistors Q (FIGS. 3A and 3B) constituting a power stage amplifier circuit 52 formed on the second member 22 of the semiconductor device 20 (FIG. 1) according to the first embodiment are heat sources. In the first embodiment, as shown in FIG. 2, a heat transfer path is formed from the second member 22 to the first member 21. Since the second member 22 is in surface contact with the first member 21, the second member 22 and the first member 21 are thermally coupled with low thermal resistance.

[0051] The heat conducted from the second member 22 to the first member 21 is diffused within the first member 21. The heat diffused within the first member 21 is radiated to the outside from the surface of the first member 21. When the semiconductor device 20 is mounted on a module substrate and covered with a molded resin, heat is conducted from the first member 21 to the molded resin.

[0052] Furthermore, the conductor protrusion 82 functions as a heat transfer path from the second member 22 to the module substrate. In this way, heat is dissipated through two paths, the heat transfer path from the second member 22 toward the module substrate and the heat transfer path toward the first member 21. This improves the heat dissipation characteristics from the second member 22. In order to obtain a sufficient effect of improving the heat dissipation characteristics, it is preferable to use a semiconductor having a higher thermal conductivity than the compound semiconductor forming the semiconductor element formed in the second member 22, for example, an elemental semiconductor such as Si or Ge, in the semiconductor region of the substrate 211 of the first member 21. In addition, it is preferable to use a compound semiconductor-based semiconductor element having a higher electron mobility than the semiconductor portion of the substrate 211 of the first member 21 as the semiconductor element formed in the second member 22 in order to amplify a high-frequency signal.

[0053] In order to reduce the thermal resistance of the heat transfer path from the second member 22 to the first member 21, an opening may be provided in the first member protective film 213, and a metal film may be filled in the opening. The second member 22 may be joined to this metal film. Furthermore, a metal pattern and vias included in the multilayer wiring structure 212 may be disposed in a region overlapping with the second member 22 in a plan view. A heat transfer path with low thermal resistance is formed by the metal film in the opening of the first member protective film 213, and the metal pattern and vias in the multilayer wiring structure 212.

[0054] Furthermore, in the first embodiment, since the second member 22 is joined to the first member 21, it is possible to reduce the size of the module substrate compared to a configuration in which the first member 21 and the second member 22 are formed from separate semiconductor chips and mounted separately on the module substrate.

[0055] In the first embodiment, the temperature measuring element 46 (FIG. 2) is formed inside the first member 21, and the second member 22 including the heat source is in surface contact with the first member 21. Therefore, the heat generated in the second member 22 is easily conducted to the temperature measuring element 46. Therefore, the heat generated in the second member 22 is easily reflected in the measurement value of the temperature measuring element 46. The temperature of the second member 22 can be detected with high accuracy by reading the measurement value of the temperature measuring element 46 from the digital input / output terminal I / O (FIG. 1). Furthermore, since the temperature measuring element 46 is formed in the first member 21, the digital circuit 47 (temperature detection circuit) formed in the first member 21 and the temperature measuring element 46 can be easily connected.

[0056] In a configuration in which the first member 21 and the second member 22 are formed of separate semiconductor chips and separately mounted on a module substrate, in order to measure the temperature of the second member 22 with high accuracy, the temperature measuring element 46 must be formed on the second member 22. In this configuration, the temperature measuring element 46 of the second member 22 and the digital circuit 47 (FIG. 1) of the first member 21 must be connected by wiring within the module substrate, which makes the wiring design of the module substrate complicated. In the first embodiment (FIG. 1), the temperature measuring element 46 and the digital circuit 47 can be connected closed to the semiconductor device 20 without passing through wiring within the module substrate. This makes it possible to reduce the complexity of the wiring design of the module substrate.

[0057] Next, a modification of the first embodiment will be described. In the first embodiment, one temperature measuring element 46 (FIG. 2) is disposed in the first member 21, but multiple temperature measuring elements 46 may be disposed. By disposing multiple temperature measuring elements 46, it is possible to obtain temperature distribution information within the first member 21.

[0058] In the first embodiment, the semiconductor device 20 is used for communication in accordance with the Frequency Division Duplex (FDD) system, but it may also be used for communication in accordance with the Time Division Duplex (TDD) system.

[0059] In order to use the semiconductor device 20 for TDD communication, a transmit / receive switch may be used as the output switch circuit 34. The transmit / receive switch has two contacts and one common terminal. One of the two contacts is connected to the power stage amplifier circuit 52 via the output matching circuit 33 (FIG. 1), and the other contact is connected to the receiving circuit 91 (FIG. 1). When TDD communication is performed, a filter is mounted on the module board instead of the duplexer 90. The common terminal of the transmit / receive switch is connected to the antenna terminal via the filter.

[0060] [Second Example] Next, a semiconductor device 20 according to a second embodiment will be described with reference to Fig. 6. Below, a description of the configuration common to the semiconductor device 20 according to the first embodiment described with reference to Figs. 1 to 5D will be omitted.

[0061] 6 is a diagram showing the positional relationship in a plan view of some of the components of the semiconductor device 20 according to the second embodiment. In the first embodiment, the position of the temperature measuring element 46 (FIG. 2) within the plane of the first member 21 (FIG. 2) is not particularly limited, and the temperature measuring element 46 is disposed at an arbitrary position on the first member 21. In contrast, in the second embodiment, the temperature measuring element 46 is disposed at a position overlapping with the second member 22 in a plan view.

[0062] Next, the advantageous effects of the second embodiment will be described. In the second embodiment, the temperature measuring element 46 is disposed at a position overlapping with the second member 22 in a plan view, and therefore the heat transfer path from the second member 22 to the temperature measuring element 46 is short. As a result, the temperature of the second member 22 is more easily reflected in the detection value of the temperature measuring element 46. This makes it possible to further improve the measurement accuracy of the temperature of the second member 22.

[0063] [Third Example] Next, a semiconductor device 20 according to a third embodiment will be described with reference to Figures 7A and 7B. Below, a description of the configuration common to the semiconductor device 20 according to the second embodiment described with reference to Figure 6 will be omitted. In the second embodiment (Figure 6), the temperature measuring element 46 is disposed at a position overlapping with the second member 22 in a plan view, but in the third embodiment, the position of the temperature measuring element 46 in a plan view is further limited.

[0064] 7A is a diagram showing the positional relationship in a plan view of some components of a semiconductor device 20 according to a third embodiment. In a plan view, a second member 22 is contained in a first member 21. A driver stage amplifier circuit 51 and a power stage amplifier circuit 52 are disposed in the second member 22. The power stage amplifier circuit 52 includes a plurality of transistors Q. Similarly, the driver stage amplifier circuit 51 also includes a plurality of transistors.

[0065] 7B is a diagram showing the arrangement of the multiple transistors Q and the temperature measuring element 46 in a plan view. The collector layer 102C and base layer 102B of each of the multiple transistors Q are substantially overlapped in a plan view, and have a shape that is elongated in one direction (the up-down direction in FIG. 7B). That is, each of the multiple transistors Q also has a shape that is elongated in one direction in a plan view. The multiple transistors Q are arranged in a direction perpendicular to the longitudinal direction (the left-right direction in FIG. 7B, hereinafter referred to as the first direction D1) with their longitudinal directions parallel to each other. The longitudinal direction of each of the multiple transistors Q is referred to as the second direction D2.

[0066] Next, the positional relationship between the multiple transistors Q and the temperature measuring element 46 will be described. The multiple transistors Q are lined up in the first direction D1 at an equal pitch P. Note that a part of the center-to-center distance between the multiple transistors Q is wider than the equal pitch P. For example, in FIG. 7B, the center-to-center distance in the middle of the row of the multiple transistors Q lined up in the first direction D1 is slightly wider than the equal pitch P. Note that all the transistors Q may be arranged at the equal pitch P.

[0067] With respect to the first direction D1, at least one temperature measuring element 46 is arranged within a range 56 obtained by extending a range 55 from a transistor Q at one end to a transistor Q at the other end in the first direction D1 by a length LE at both ends in the first direction D1. The length LE is three times or less, more preferably two times or less, of the uniform pitch P. With respect to the second direction D2, the temperature measuring element 46 is arranged within a range 57 in which the multiple transistors Q are arranged.

[0068] As shown in Fig. 7A, two emitter conductor projections 82A, 82B are arranged so as to encompass multiple transistors Q in a plan view. In the central portion of the row of multiple transistors Q, the two conductor projections 82A and 82B are separated from each other at a location where the center-to-center distance of the transistors Q is wider than the uniform pitch P. The conductor projections 82A, 82B are connected to the emitters of multiple transistors Q. The two conductor projections 82A, 82B may be joined to form a single conductor projection.

[0069] Next, the excellent effects of the third embodiment will be described. In the third embodiment, the temperature measuring element 46 is disposed in the vicinity of the transistor Q. Therefore, the accuracy of measuring the temperature of the transistor Q by the temperature measuring element 46 can be further improved.

[0070] Next, a modification of the third embodiment will be described. In the third embodiment, the multiple transistors Q are arranged at equal pitch P in the first direction D1, but they do not necessarily have to be arranged at equal pitch. If the multiple transistors Q are not arranged at equal pitch, it is preferable to make the extension distance LE from the transistors Q at both ends equal to the center-to-center distance between each of the transistors Q at both ends and the transistor Q adjacent to it.

[0071] In the third embodiment, a plurality of transistors Q (FIG. 7B) constituting the power stage amplifier circuit 52 are arranged in a row, but a plurality of transistor rows each consisting of a plurality of transistors Q may be arranged in a direction perpendicular to the direction in which the transistors Q are arranged. In this case, the ranges 55 and 56 in which the transistors Q shown in FIG. 7B are arranged may be defined for each transistor row.

[0072] [Fourth Example] Next, a semiconductor device according to a fourth embodiment will be described with reference to Figures 8 and 9. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 5D will be omitted.

[0073] 8 is a block diagram of a semiconductor device 20 according to the fourth embodiment. In the semiconductor device according to the fourth embodiment, the temperature measured by the temperature measuring element 46 is input to bias control circuits 41 and 42 in addition to a digital circuit 47. The bias control circuit 41 changes the bias current supplied to the transistor of the driver stage amplifier circuit 51 based on the detection value of the temperature measuring element 46. The other bias control circuit 42 changes the bias current supplied to the transistor Q (FIG. 3A) of the power stage amplifier circuit 52 based on the detection value of the temperature measuring element 46.

[0074] Next, an example of a method for controlling the bias current will be described with reference to FIG. 9 is a graph showing the temperature dependency of the output of the transistor Q of the power stage amplifier circuit 52 (FIG. 1) and the magnitude of the bias current that changes according to the temperature. The horizontal axis represents the temperature detected by the temperature measuring element 46, the left vertical axis represents the output level of the transistor Q, and the right vertical axis represents the bias current. When the transistor Q is operated with a constant bias current, if the temperature of the transistor Q rises, the output level drops even if the input signal level is constant, as shown by the dashed line in FIG. 9. The output of the transistor of the driver stage amplifier circuit 51 has the same temperature dependency as the transistor Q of the power stage amplifier circuit 52.

[0075] The bias control circuit 42 (Fig. 1) increases the bias current Ib supplied to the transistor Q as the temperature measurement value by the temperature measuring element 46 increases, as shown by the thick solid line in Fig. 9. When the bias current Ib increases, the output level Po of the transistor Q also increases, as shown by the thin solid line in Fig. 9. In this way, the decrease in the output level due to the increase in temperature is compensated for by increasing the bias current, and the output level Po of the transistor approaches a constant value independent of temperature.

[0076] If the temperature further rises and exceeds the allowable upper limit Tth, the bias control circuit 42 (FIG. 1) stops the bias current supplied to the transistor Q of the power stage amplifier circuit 52 (FIG. 1). As a result, the output level Po of the transistor Q also becomes almost zero.

[0077] The control by the bias control circuit 41 for the driver stage amplifier circuit 51 is similar to the control by the bias control circuit 42 for the power stage amplifier circuit 52 .

[0078] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, the temperature detection value by the temperature measuring element 46 is fed back to the bias control circuits 41 and 42, and the bias current supplied to the transistor Q is changed according to the temperature. This reduces the temperature dependency of the output of the transistor Q, and makes it possible to maintain the output level Po at a constant input signal level. Furthermore, when the temperature exceeds the allowable upper limit Tth, the supply of the bias current is stopped, thereby preventing the transistor Q from being destroyed by an excessive rise in temperature.

[0079] Next, a modification of the fourth embodiment will be described. In the fourth embodiment, the bias current supplied to all the transistors Q constituting the power stage amplifier circuit 52 is changed uniformly. As a modification of the fourth embodiment, the multiple transistors Q (FIG. 7B) arranged in the first direction D1 may be divided into multiple groups, and the temperature measuring element 46 may be arranged for each group. In this case, the bias current may be changed for each group according to the temperature measurement value of each of the multiple temperature measuring elements 46. For example, the bias current supplied to the transistor Q of a group having a relatively high temperature may be made larger than the bias current supplied to the transistor Q of a group having a relatively low temperature. This makes it possible to reduce the variation in the output level of all the transistors Q constituting the power stage amplifier circuit 52.

[0080] [Fifth Example] Next, a semiconductor device according to a fifth embodiment will be described with reference to Figures 10 and 11. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 5D will be omitted.

[0081] 10 is a block diagram showing a part of the functions of a semiconductor device 20 according to a fifth embodiment. In the first embodiment (FIG. 1), the input switch circuit 31 has one input contact for each of the two input terminals IN1 and IN2. In contrast, in the fifth embodiment, the input switch circuit 31 has two input contacts 31A and 31B for one input terminal IN1, and also has two input contacts 31A and 31B for the other input terminal IN2. One input contact 31A is directly connected to the input terminal IN1 or IN2, and the other input contact 31B is connected to the input terminal IN1 or IN2 via an attenuation circuit 31C.

[0082] The input switch control circuit 43 selects one of the two input terminals IN1 and IN2, and further selects one of the input contacts 31A and 31B according to the temperature detected by the temperature measuring element 46. When one input contact 31A is selected, the high-frequency signal input to the input terminal IN1 or IN2 is input to the driver stage amplifier circuit 51 without attenuation. When the other input contact 31B is selected, the high-frequency signal input to the input terminal IN1 or IN2 is attenuated by the attenuation circuit 31C and input to the driver stage amplifier circuit 51. Furthermore, the input switch control circuit 43 can stop the input of the high-frequency signal to the driver stage amplifier circuit 51 by putting the input switch circuit 31 into a non-conductive state.

[0083] FIG. 11 is a graph showing the relationship between the attenuation rate of the high-frequency signal from the input terminal IN1 or IN2 to the driver stage amplifier circuit 51 and the temperature detection value by the temperature measuring element 46. The horizontal axis represents the detected temperature value, and the vertical axis represents the attenuation rate. When the detected temperature value is in a range equal to or less than the first threshold value Tth1, the input switch control circuit 43 selects the input contact 31A to which the attenuation circuit 31C is not inserted. Therefore, the attenuation rate of the high-frequency signal is almost zero. When the detected temperature value is in a range equal to or more than the first threshold value Tth1 and less than the second threshold value Tth2, the input switch control circuit 43 selects the input contact 31B to which the attenuation circuit 31C is inserted. Therefore, the attenuation rate of the high-frequency signal increases from zero.

[0084] When the detected temperature value is in a range equal to or greater than the second threshold value Tth2, the input switch control circuit 43 turns off the input switch circuit 31. This stops the input of the high-frequency signal to the driver stage amplifier circuit 51. In other words, the attenuation rate of the high-frequency signal becomes infinite.

[0085] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, the level of the high frequency signal input to the driver stage amplifier circuit 51 is adjusted by feeding back the temperature detection value by the temperature measuring element 46 to the control of the input switch circuit 31. When the temperature detection value increases, the level of the high frequency signal input to the driver stage amplifier circuit 51 is reduced or set to zero, thereby suppressing further temperature increase. The input switch control circuit 43 and the input switch circuit 31 function as protection circuits to prevent the transistor Q from being destroyed by an excessive temperature increase.

[0086] [Sixth Example] Next, a semiconductor device according to a sixth embodiment will be described with reference to Fig. 12. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 5D will be omitted.

[0087] 12 is a block diagram showing a part of the functions of the semiconductor device 20 according to the sixth embodiment. In the first embodiment (FIG. 1), the output switch circuit 34 has one output contact for each duplexer 90. In contrast, in the sixth embodiment, the output switch circuit 34 has two output contacts 34A, 34B for each duplexer 90. One output contact 34A is directly connected to the transmission signal input port of the duplexer 90, and the other output contact 34B is connected to the transmission signal input port of the duplexer 90 via an impedance adjustment circuit 34C.

[0088] When one output contact 34A is selected, the high frequency signal output from the power stage amplifier circuit 52 is input to the transmission signal input port of the duplexer 90 via the output matching circuit 33. At this time, the load impedance seen from the power stage amplifier circuit 52 to the load side is approximately matched to the output impedance of the power stage amplifier circuit 52. When the other output contact 34B is selected, the high frequency signal output from the power stage amplifier circuit 52 is input to the transmission signal input port of the duplexer 90 via the output matching circuit 33 and the impedance adjustment circuit 34C. At this time, the impedance adjustment circuit 34C is configured so that the impedance seen from the power stage amplifier circuit 52 to the load side is higher than the output impedance of the power stage amplifier circuit 52.

[0089] The output switch control circuit 44 selects one duplexer 90 from the plurality of duplexers 90, and selects one of the output contacts 34A and 34B according to the temperature detected by the temperature measuring element 46.

[0090] Next, the excellent effects of the sixth embodiment will be described. In the sixth embodiment, when the temperature detected by the temperature measuring element 46 exceeds a certain threshold value, the output switch control circuit 44 switches the connection state of the output switch circuit 34 from a state in which the input contact is connected to one output contact 34A to a state in which the input contact is connected to the other output contact 34B. This increases the impedance seen from the power stage amplifier circuit 52 to the load side, and the output current decreases. By decreasing the output current, it is possible to suppress damage to the transistor Q of the power stage amplifier circuit 52 due to an excessive rise in temperature.

[0091] Furthermore, by reducing the level of the signal input to the duplexer 90, damage to the duplexer 90 can be suppressed.

[0092] When the output of the power stage amplifier circuit 52 increases, the temperature of the power stage amplifier circuit 52 increases, and the power of the high frequency signal input to the duplexer 90 also increases. As a result, the transmission loss in the duplexer 90 increases, and the temperature of the duplexer 90 also increases. In addition, when the temperature of the power stage amplifier circuit 52 increases, the heat is conducted to the duplexer 90, and the temperature of the duplexer 90 also increases. That is, it is considered that there is a correlation between the temperature of the power stage amplifier circuit 52 and the temperature of the duplexer 90. Therefore, it can be considered that the temperature detection value by the temperature measuring element 46 also reflects the temperature of the duplexer 90. For this reason, it is possible to obtain the amount of shift of the pass frequency band due to the temperature change of the duplexer 90 based on the temperature detection value by the temperature measuring element 46, and adjust the impedance matching between the power stage amplifier circuit 52 and the duplexer 90 according to the amount of shift.

[0093] [Seventh Example] Next, a semiconductor device according to a seventh embodiment will be described with reference to Fig. 13. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 5D will be omitted.

[0094] 13 is a block diagram of a semiconductor device 20 according to a seventh embodiment. In the first embodiment (FIG. 1), the impedance conversion ratio of the interstage matching circuit 32 is a fixed value. In contrast to this, in the seventh embodiment, the impedance conversion ratio of the interstage matching circuit 32 is variable. For example, a switch element is inserted in parallel or series to at least one passive element included in the interstage matching circuit 32. The impedance conversion ratio can be changed by turning on and off this switch element. An interstage matching control circuit 48 included in the first member 21 controls the on and off of the switch element of the interstage matching circuit 32, thereby changing the impedance conversion ratio of the interstage matching circuit 32.

[0095] For example, the inter-stage matching circuit 32 has two states: a matching state in which the impedance seen from the driver stage amplifier circuit 51 to the load side is approximately matched to the output impedance of the driver stage amplifier circuit 51, and a high impedance state in which the impedance seen from the driver stage amplifier circuit 51 to the load side is higher than the output impedance of the driver stage amplifier circuit 51.

[0096] When the temperature measured by the temperature measuring element 46 exceeds a certain threshold value, the inter-stage matching control circuit 48 switches the state of the inter-stage matching circuit 32 from the matching state to a high impedance state.

[0097] Next, the excellent effects of the seventh embodiment will be described. When the temperature measured by the temperature measuring element 46 exceeds the threshold value and the state of the inter-stage matching circuit 32 switches to a high impedance state, the signal level of the high frequency signal input to the power stage amplifier circuit 52 decreases. This makes it possible to prevent damage to the transistor Q of the power stage amplifier circuit 52 due to an excessive rise in temperature.

[0098] [Eighth Example] Next, a semiconductor device according to an eighth embodiment will be described with reference to Fig. 14. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 5D will be omitted.

[0099] 14 is a block diagram of a semiconductor device 20 according to the eighth embodiment. In the first embodiment (FIG. 1), the impedance conversion ratio of the output matching circuit 33 is a fixed value. In contrast to this, in the eighth embodiment, the impedance conversion ratio of the output matching circuit 33 is variable. For example, a switch element is inserted in parallel or series with at least one passive element included in the output matching circuit 33. The impedance conversion ratio can be changed by turning this switch element on and off. An output matching control circuit 49 controls the on and off of the switch element of the output matching circuit 33 to change the impedance conversion ratio of the output matching circuit 33.

[0100] Next, the excellent effects of the eighth embodiment will be described. When excessive heat is generated in the transistor Q of the power stage amplifier circuit 52 due to a fluctuation in the load impedance as seen from the antenna terminal ANT to the antenna 92 ​​side, the output matching control circuit 49 controls the output matching circuit 33 to increase the impedance as seen from the power stage amplifier circuit 52 to the load side. This reduces the output level of the power stage amplifier circuit 52, making it possible to prevent the transistor Q from being destroyed by an excessive rise in temperature.

[0101] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0102] 20 Semiconductor Devices 21 First member 21A 1st page 22 Second member 31 Input switch circuit 31A, 31B Input contacts 31C Attenuation circuit 32 Interstage matching circuit 33 Output matching circuit 34 Output switch circuit 34A, 34B Output Contact 34C Impedance adjustment circuit 35 Antenna switch circuit 40 Charge pump circuit 41, 42 Bias control circuit 43 Input switch control circuit 44 Output switch control circuit 45 Antenna switch control circuit 46 Temperature measuring element 47 Digital circuit (temperature detection circuit) 48 Interstage matching control circuit 49 Output matching control circuit 50 High frequency amplifier circuit 51 Driver stage amplifier circuit 52 Power stage amplifier circuit 55 Area in which transistors are arranged 56 The area where the transistors are arranged is extended 57 Area in which transistors are arranged 61 Wiring 62, 63 Pad 67 Interlayer insulating film 68 Protective film 82 Conductor protrusion 82A, 82B Conductor projection for emitter 82P Cu pillar 82S solder layer 83 Conductor protrusion 90 Duplexer 91 Receiving circuit 92 Antenna 101 Underlying semiconductor layer 101A conductive area 101B Element isolation area 102B Base layer 102C Collector layer 102E Emitter layer 103B Base electrode 103C Collector electrode 103E Emitter electrode 104B Base wiring 104BB Base bias wiring 104C Collector wiring 104E Emitter wiring 105E Emitter wiring 105RF High frequency signal input wiring 111, 112 Interlayer insulating film 200 Motherboard 201 Peeling layer 202 Device formation layer 204 Connecting members 210, 211 Substrate 212 Multilayer wiring structure 213 First component protective film 215, 216, 217 Wiring

Claims

1. a first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; A semiconductor device comprising: The first member includes a temperature sensor therein for detecting a temperature, The semiconductor device is configured such that the conductor projection is adapted to mount the semiconductor device on a module substrate.

2. The semiconductor device according to claim 1 , wherein the temperature measuring element is disposed at a position overlapping with the second member in a plan view.

3. A first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first member includes a temperature sensor therein for detecting a temperature, the high frequency amplifier circuit includes a plurality of transistors connected in parallel with each other; The plurality of transistors are arranged side by side in a first direction in a plan view, The temperature measuring element is arranged in a range extending on both sides from the transistor at one end to the transistor at the other end by the distance between the centers of each of the transistors at both ends and their adjacent transistors in the first direction, and is arranged in a range in which the multiple transistors are arranged in a second direction perpendicular to the first direction in a planar view.

4. 4. The semiconductor device according to claim 1, wherein the first member further includes a temperature detection circuit that converts a detection value of the temperature measuring element into a digital value and outputs the digital value to an outside.

5. 5. The semiconductor device according to claim 1, wherein the first member further includes a bias control circuit that changes a bias current supplied to a transistor of the high frequency amplifier circuit based on a detection value of the temperature measuring element.

6. 6. The semiconductor device according to claim 5, wherein the bias control circuit performs control to increase the bias current as the temperature detected by the temperature measuring element increases.

7. A first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first member includes a temperature sensor therein for detecting a temperature, the first member further includes a bias control circuit that changes a bias current supplied to a transistor of the high frequency amplifier circuit based on a detection value of the temperature measuring element; The bias control circuit is a semiconductor device that stops the supply of bias current to a transistor of the high frequency amplifier circuit when the temperature detected by the temperature measuring element exceeds a preset allowable upper limit value.

8. The first member is an input switch circuit that changes an attenuation rate of a high frequency signal input to the high frequency amplifier circuit by switching the input switch; an input switch control circuit that controls the input switch circuit based on a detection value of the temperature measuring element; The semiconductor device according to claim 1 , further comprising:

9. A first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first member includes a temperature sensor therein for detecting a temperature, The first member is an output switch circuit for outputting the high frequency signal output from the high frequency amplifier circuit from one output contact selected from a plurality of output contacts; an output switch control circuit that controls the output switch circuit based on a detection value of the temperature measuring element; Further comprising: The output switch circuit is a semiconductor device including an impedance adjustment circuit connected to some of the plurality of output contacts.

10. A first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first member includes a temperature sensor therein for detecting a temperature, The high frequency amplifier circuit has a multi-stage configuration, The first member is an inter-stage matching circuit having a variable impedance conversion rate inserted between stages of the high frequency amplifier circuit; an inter-stage matching control circuit that changes an impedance conversion rate of the inter-stage matching circuit based on a detection value of the temperature measuring element; The semiconductor device further comprises:

11. A first member having a first surface and including a semiconductor region made of a single semiconductor; a second member that is joined in surface contact with the first surface of the first member and includes a compound semiconductor-based high-frequency amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first member includes a temperature sensor therein for detecting a temperature, The first member is an output matching circuit having a variable impedance conversion ratio connected to an output port of the high-frequency amplifier circuit; an output matching control circuit that changes an impedance conversion rate of the output matching circuit based on the detection value of the temperature measuring element; The semiconductor device further comprises:

Images