Compiling device, compiling method, and compiling program

Abstract

To increase the speed of list operation targeting an array of structure types having a first variable and a second variable as components.SOLUTION: A compilation device is a compiler 100 for compiling a source program to generate an object code and includes: a code analysis unit 10 which determines whether or not the source program includes list operation targeting an array of structure types having a first variable and a second variable as components; and a vector instruction generation unit 20 which generates a vector gather instruction, a vector AND instruction, and a vector shift instruction if the source program includes list operation targeting an array of structure types having the first variable and the second variable as components.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present invention relates to a compiling device, a compiling method, and a compiling program, and more particularly to speeding up a program. [Background technology]

[0002] The access time from the arithmetic unit of a computer to the main memory is longer than the calculation time of the arithmetic unit, and the data transfer performance between the main memory and the arithmetic unit is insufficient. To fill this widening performance gap, scalar computers generally provide high-speed cache memory between the arithmetic unit and the main memory to reduce the access time to the main memory. On the other hand, vector computers reduce the access time to the main memory by transferring a large amount of data at once using vector instructions. The memory access time per data item can be considered to be 1 / the number of data items transferred simultaneously. The maximum value of this number is determined by the vector length of the vector computer; if the vector length is 256, the memory access time will be 1 / 256, which is a small value.

[0003] In addition, vector computers load data stored in main memory into vector registers and perform high-speed calculations via the vector registers. Therefore, in order to increase speed, it is important to know how to bring data from main memory into the registers as efficiently as possible.

[0004] Patent Document 1 relates to an information processing device, and proposes speeding up vector operations on complex data.

[0005] Patent Document 2 relates to a compiling method used in a computer, and proposes extracting an array in a source program and allocating it to a main memory or a temporary storage device according to the number of times it is accessed.

[0006] Here, we consider how to compile the source program shown in Figure 1. The source program in Figure 1 includes indirect references, and operations that include indirect references are called list operations. The source program in Figure 1 is written in Fortran, and its content is to extract the real and imaginary parts of the IX(I)th element of single-precision complex array A, and assign the addition result to array B.

[0007] Array IX is called a list, and when it is the I-th element of array IX, it stores the value of the ordinal number of the array element of A to be referenced. In this case, the array elements of A are called "indirectly referenced" because they are accessed using elements of array IX. Note that in the source program in Figure 1, the formula that references the real part of the IX(I)th element of array A is written as real(A(IX(I))), and the formula that references the imaginary part of the IX(I)th element of array A is written as aimag(A(IX(I))).

[0008] In the compilation method of the background art, the source program in FIG. 1 is translated into the sequence of assembler instructions shown in FIG. 11. In the sequence of instructions in FIG. 11, first, a vector load instruction (VLD instruction) loads the value of array IX into vector register VR1. Next, a vector logical shift instruction (VSLL instruction) logically shifts each element of vector register VR1 left by 3 bits, and sets the resultant value in vector register VR2. This is equivalent to setting the value of each element of vector register VR1 multiplied by 8, the size of one element of array A, in other words, the size of a single-precision complex number type, in vector register VR2. The value obtained in this way is the relative offset value from the beginning of array A.

[0009] Next, a vector addition instruction (VADD instruction) is used to add each element of vector register VR2 (the above relative offset value) to the starting address of array A, and the result is set in vector register VR3. The result of this VADD instruction is shown in "VR3" in Figure 12. As shown in "A (memory)" in Figure 12, the memory layout of a single-precision complex number array is such that the real and imaginary parts are arranged alternately every 4 bytes, so that the addresses of the real parts of each element of A(IX(I)) are set in vector register VR3.

[0010] Next, the 4-byte vector gather instruction (VGT4 instruction) loads (gathers) the 4-byte-wide values ​​at the addresses stored in each element of vector register VR3 from memory to vector register VR4 as shown in "VR4 (real part of A)" in Figure 12.

[0011] Next, a vector addition instruction (VADD instruction) is used to set each element of vector register VR5 with the sum of each element of vector register VR2 and 4. This is because, as shown in "A (memory)" in Figure 12, the real and imaginary parts of single-precision complex numbers are arranged alternately every 4 bytes, and when obtaining the address of the imaginary part, it is necessary to load (gather) 4 bytes beyond the address of each element of array A. As a result, the addresses of the imaginary parts of each element of A(IX(I)) are set in vector register VR5.

[0012] Next, the 4-byte vector gather instruction (VGT4 instruction) loads (gathers) the 4-byte value at the address stored in each element of this vector register VR5 from memory to vector register VR6 as shown in "VR6 (imaginary part of A)" in Figure 12. Since the memory layout of single-precision complex numbers is such that the real and imaginary parts are arranged alternately every 4 bytes as shown in "A (memory)" in Figure 12, loading (gathering) the 4-byte value at the address obtained by adding 4 to the address of A(IX(I)) of the element of array A is equivalent to loading (gathering) the imaginary part value of one element of array A of single-precision complex type.

[0013] Finally, a vector add instruction (VADD instruction) is used to set vector register VR7 to the sum of vector register VR4 and vector register VR6, and a vector store instruction (VST instruction) is used to store the value of vector register VR7 in array B.

[0014] List operations are frequently used in numerical analysis in the fields of science and technology. These analytical processes require huge amounts of computation time to simulate complexly changing phenomena, and the computational cost of list operations is particularly high, making it desirable to speed up such processing. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] International Publication No. 2020 / 066375 [Patent Document 2] JP 2013-182293 A Summary of the Invention [Problem to be solved by the invention]

[0016] However, the compilation method of the background art described with reference to FIGS. 11 and 12 has the following problems.

[0017] The values ​​loaded (gathered) into the vector register by the 4-byte vector gather instruction (VGT4 instruction) in the instruction sequence shown in Figure 11 are not arranged consecutively in memory, and the arrangement in memory is not evenly spaced, so it is necessary to access widely within the array. When accessing widely within the array, the probability that the values ​​to be loaded (gathered) are in the memory cache is low, and the execution time of the vector gather instruction is significantly longer than other instructions.

[0018] The 4-byte vector gather instruction (VGT4 instruction) loads (gathers) values ​​into the upper 4 bytes of an 8-byte wide vector register, so the lower 4 bytes of each element of the vector register VR4 and vector register VR6 do not store significant values ​​and are empty, as shown in "VR4 (real part of A)" and "VR6 (imaginary part of A)" in Figure 12. In addition, the vector gather instruction, which takes a long time to execute, is issued twice, and these instructions are executed for each loop iteration, which causes the execution time of the list operation itself to be long, which is an issue.

[0019] Note that this issue is not limited to list operations targeting single-precision complex type arrays, but may arise in list operations targeting structure type arrays having a first variable and a second variable as components.

[0020] An object of the present invention is to provide a compiling device, a compiling method, and a compiling program that can speed up list operations on an array of a structure type having a first variable and a second variable as components. [Means for solving the problem]

[0021] In order to achieve the above object, a compiling device according to the present invention comprises: a code analysis unit that determines whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; and a vector instruction generation unit that generates a vector gather instruction, a vector logical product instruction, and a vector shift instruction when the above components include a list operation targeting an array of a structure type having a first variable and a second variable.

[0022] A compiling method according to the present invention comprises the steps of: A code analysis unit determines whether the source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; When a list operation targeting an array of a derived type having a first variable and a second variable as the above components is included, the vector instruction generates a vector gather instruction, a vector logical AND instruction, and a vector shift instruction.

[0023] The compile program according to the present invention comprises: Computer, a code analysis means for determining whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; When the above components include a list operation targeting an array of a structure type having a first variable and a second variable, the means functions as a vector instruction generating means for generating a vector gather instruction, a vector logical product instruction, and a vector shift instruction. Effect of the Invention

[0024] According to the present invention, it is possible to increase the speed of list operations that target an array of a structure type having a first variable and a second variable as components. [Brief description of the drawings]

[0025] [Figure 1] 2 is an example of a source program to which the embodiment of the present invention is applied; [Diagram 2] 1 is a flowchart illustrating a compiling method according to a first embodiment of the present invention. [Diagram 3] 3 is a sequence of instructions generated according to the first embodiment of the present invention. [Figure 4A] FIG. 1 is a block diagram for explaining a compiler according to a first embodiment of the present invention. [Figure 4B] 1 is a block diagram illustrating a configuration of a computer that executes an object program in relation to a compiling device, a compiling method, and a compiling program according to an embodiment of the present invention. [Diagram 5] FIG. 2 is a conceptual diagram for explaining operations on vector registers in the compiling method according to the first embodiment of the present invention. [Figure 6] FIG. 2 is a conceptual diagram for explaining an operation on a vector register in the compiling method according to the first embodiment of the present invention. [Figure 7] FIG. 2 is a conceptual diagram for explaining operations on vector registers in the compiling method according to the first embodiment of the present invention. [Figure 8] 13A is an instruction sequence generated by the background art, and FIG. 13B is an instruction sequence generated by an embodiment of the present invention. [Figure 9] FIG. 13A is an example of a source program targeted by the second embodiment of the present invention, and FIG. 13B is a conceptual diagram for explaining a memory arrangement used in the second embodiment of the present invention. [Figure 10] FIG. 13A is an example of a source program targeted by the third embodiment of the present invention, and FIG. 13B is a conceptual diagram for explaining a memory arrangement used in the third embodiment of the present invention. [Figure 11] 2 is a sequence of instructions generated by the background art. [Figure 12] FIG. 1 is a conceptual diagram for explaining the operation of vector calculation in the compilation method according to the background art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Before describing specific embodiments of the present invention, an overview of the embodiments will be described.

[0027] The compiling device, compiling method, and compiling program according to the embodiments of the present invention are used for list operations targeting a structure type array having a first variable and a second variable as components, and as an example, are used for list operations targeting a complex type array. In the embodiments of the present invention, in order to store the values ​​of the real and imaginary parts of a complex type array, as an example of an array, in the same vector register, a vector gather instruction that loads (gathers) a double precision value is issued once, rather than issuing two vector gather instructions that load (gather) a single precision value. This provides a compiler that reduces the number of memory accesses and speeds up list operations.

[0028] The compiling device, the compiling method, and the compiling program according to the embodiments of the present invention are used in a computer that executes an object program. Such a computer is computer 150 shown in FIG. 4B, and is configured to include an arithmetic unit 151, a main memory 152, and a temporary storage device 153. Computer 150 is a computer, and is a vector computer capable of vector operations. A computer configured in this way is proposed in Patent Document 2.

[0029] 4B is a device for the computer 150 to execute calculations based on a program. Specifically, the calculation device 151 is a calculation device in a processor such as a central processing unit (CPU) or a graphics processing unit (GPU) of a computer, and is configured, for example, by an arithmetic logic unit (ALU) in a CPU. The calculation device 151 obtains data from a main memory 152 or a temporary storage device 153, and executes calculations accordingly.

[0030] 4B is a primary storage device accessible by the arithmetic unit 151 in the computer 150. The main memory 152 can hold data necessary for the arithmetic unit 151 to execute an operation and data resulting from the execution of the operation.

[0031] 4B is a storage device that the arithmetic unit 151 can access faster than the main memory 152, and corresponds to, for example, a register. For example, when the arithmetic unit 151 and the temporary storage unit 153 configure a CPU, the arithmetic unit 151 is an ALU in the CPU, and the temporary storage unit 153 is a register in the CPU.

[0032] The compiling device according to the embodiment of the present invention is a compiler that generates an object program to be executed by the computer 150 based on a source program. The compiler compiles the source program to generate object code and generate an object program. Specific embodiments of the present invention will be described in detail below with reference to the drawings.

[0033] [First embodiment] First, a compiling device, a compiling method, and a compiling program according to a first embodiment of the present invention will be described.

[0034] (Configuration of the embodiment) Fig. 4A is a block diagram for explaining a compiling device according to this embodiment. The compiling device in Fig. 4A is a compiler 100 that compiles a source program to generate object code. The compiler 100 in Fig. 4A includes a code analysis unit 10 that analyzes the source program as a program, and an instruction generation unit 20 that generates instructions based on the analysis result in the code analysis unit 10. The compiling device according to this embodiment is used in the above-mentioned computer, and is a function incorporated in the compiler.

[0035] The code analysis unit 10 includes a list operation syntax analysis means 11 that analyzes whether the list operations in the source program are in a vectorizable format.

[0036] The instruction generation unit 20 includes a vector instruction generation unit that generates vectorized code based on the analysis result by the code analysis unit 10. The vector instruction generation unit of the instruction generation unit 20 includes a list operation determination unit 21, a vector load instruction generation means 22, a vector logical shift instruction generation means 23, a vector add instruction generation means 24, an 8-byte vector gather instruction generation means 25, a vector logical AND instruction generation means 26, and a vector store instruction generation means 27.

[0037] In the vector instruction generation unit, the list operation determination unit 21 determines whether or not a list operation is included, and if a list operation is included, determines whether the list operation is an operation on a single-precision complex array. If the list operation is an operation on a single-precision complex array, the vector instruction generation unit generates an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction), thereby generating instructions to load (gather) the values ​​of the real and imaginary parts of the array.

[0038] (Operation of the embodiment) Next, the operation will be described with reference to the drawings. FIG. 2 is a flowchart for explaining the compiling method according to the first embodiment of the present invention. FIG. 1 is an example of a source program targeted by the first embodiment of the present invention. The compiling device, compiling method, and compiling program of this embodiment compile the source program shown in FIG. 1 to generate object code. The source program in FIG. 1 includes an indirect reference, and the content of the source program is to extract the real part and the imaginary part of the IX(I)th element of a single-precision complex number array A, and assign the addition result to an array B.

[0039] First, the list operation syntax analysis means 11 of the code analysis unit 10 analyzes the list operation syntax of the target source program (step S1). It is determined whether it is a list operation, and if it is not a list operation, a normal vector instruction is generated (step 6), and then the object program is generated (step S8) and the process ends.

[0040] If it is a list operation, the process proceeds to step S3. In step S3, list operation determination unit 21 of instruction generation unit 20 determines whether the target of the list operation is a single-precision complex array. Here, based on information from code analysis unit 10, it is determined to be a list operation when an array reference is included in the subscript expression when defining or referencing an array, and the subscript expression of the array increases or decreases at a fixed rate for each loop iteration, and the list operation generation process begins. If the target of the list operation is not a single-precision complex array (NO in step S3), a list operation instruction similar to that in the background art is generated (step S7), and then the object program is generated (step S8) and the process ends.

[0041] If the target of the list operation is a single-precision complex array, proceed to step S4. In the case of the source program in Figure 1, the subscript expression of array reference A(IX(I)) includes a reference to array IX(I), and the subscript expression I of array reference IX(I) increments by 1 with each iteration of the loop, so it is determined to be a list operation.

[0042] It is determined whether there is an access to the real part and the imaginary part of the same array element in the list operation (step S4). If there is an access to the real part and the imaginary part of the same array element in the list operation (YES in step S4), a vector instruction according to this embodiment is generated (step S5), and then an object program is generated (step S8) and the process ends. The vector instruction generated in step S5 includes the above-mentioned 8-byte vector gather instruction (VGT8 instruction), vector logical AND instruction (VAND instruction), and vector logical shift instruction (VSLL instruction).

[0043] The vector instructions generated by this embodiment will be described below. FIG. 3 is an instruction sequence generated by the first embodiment of the present invention. FIGS. 5 to 7 are conceptual diagrams for explaining operations on vector registers in the compiling method according to the first embodiment of the present invention. In the instruction sequence of FIG. 3, first, a vector load instruction (VLD instruction) loads the value of array IX into vector register VR1. Next, a vector logical shift instruction (VSLL instruction) sets the value obtained by logically shifting each element of vector register VR1 by 3 bits to vector register VR2. This is equivalent to setting the value obtained by multiplying each element of vector register VR1 by 8, which is the size of one element of array A, that is, the size of a single-precision complex number type, into vector register VR2. The value obtained in this way is a relative offset value from the beginning of array A.

[0044] Next, a vector addition instruction (VADD instruction) is used to add each element of vector register VR2 (the above relative offset value) to the starting address of array A, and the result is set in vector register VR3. The result of this VADD instruction is shown in "VR3" in Figure 5. As shown in "A (memory)" in Figure 5, the memory layout of a single-precision complex number array is such that the real and imaginary parts are arranged alternately every 4 bytes, so as a result, the addresses of the real parts of each element of A(IX(I)) are set in vector register VR3.

[0045] Next, the 8-byte vector gather instruction (VGT8 instruction) loads (gathers) the 8-byte values ​​at the addresses stored in each element of vector register VR3 from memory to vector register VR4 as shown in "VR4 (real part, imaginary part of A)" in Figure 5. The memory layout of single-precision complex array A is such that the real and imaginary parts are arranged alternately every 4 bytes as shown in "A (memory)" in Figure 5, so loading (gathering) the 8-byte value at the address A(IX(I)), which is an element of array A, is equivalent to simultaneously loading (gathering) the real and imaginary part values ​​of one element of single-precision complex array A.

[0046] Next, the vector logical product instruction (VAND instruction) extracts only the upper 4 bytes of each element of vector register VR4 into vector register VR5 by logical product, as shown in "VR5 (real part of A)" in Figure 6. Since vector register VR4 stores the real and imaginary parts of single-precision complex array A, the value extracted from only the upper 4 bytes is equal to the value of the real part of single-precision complex array A.

[0047] Next, the vector logical shift instruction (VSLL instruction) sets the value obtained by logically shifting each element of vector register VR4 4 bytes to the left in vector register VR6 as "VR6 (imaginary part of A)" in Figure 7. Because vector register VR4 stores the real and imaginary parts of single-precision complex array A, the value obtained by logically shifting 4 bytes to the left is equal to the value of the imaginary part of single-precision complex array A.

[0048] Finally, a vector add instruction (VADD instruction) is used to set vector register VR7 to the sum of vector register VR5 and vector register VR6, and the value of vector register VR7 is stored in array B using a vector store instruction (VST instruction).

[0049] (Effects of the embodiment) According to the compiling device, compiling method, and compiling program of the present embodiment, it is possible to speed up list operations that target single-precision complex number arrays.

[0050] 8(a) shows an instruction sequence generated by the compiling method of the background art, and (b) shows an instruction sequence generated by the compiling method of the embodiment of the present invention. In the background art, two 4-byte vector gather instructions (VGT4 instructions) are generated, whereas the compiling method of the embodiment of the present invention generates an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction). In this embodiment, the number of executions of vector gather instructions that take a long time to execute can be reduced, thereby reducing memory accesses. By reducing the number of executions of vector gather instructions, memory accesses can be reduced, thereby speeding up programs.

[0051] Second Embodiment Next, a compiling device, a compiling method, and a compiling program according to a second embodiment of the present invention will be described. Regarding the compiling device, the compiling method, and the compiling program according to this embodiment, detailed descriptions of the same contents as those of the first embodiment will be omitted, and differences will be described.

[0052] In the above-mentioned first embodiment, a program including list operations targeting a single-precision complex number array has been described as an example, but the present invention is not limited to this. For example, the present invention can also be applied to a program including list operations targeting a 2-row, N-column single-precision floating-point number array.

[0053] Figure 9(a) is a source program including a list operation targeting 2-row, N-column single-precision floating-point array C, and Figure 9(b) is a conceptual diagram showing the memory arrangement of 2-row, N-column single-precision floating-point array C. The content of the source program in Figure 9(a) is to extract C(1,IX(I)) and C(2,IX(I)) of the IX(I)-th element of 2-row, N-column single-precision floating-point array C, and assign the addition result to array B.

[0054] As shown in FIG. 9(b), in a 2-row, N-column single-precision floating-point array C, C(1,1), C(2,1) to C(1,N), C(2,N) are arranged alternately every 4 bytes.

[0055] In list operations targeting such a 2-row, N-column single-precision floating-point array C, as in the first embodiment described above, an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction) are generated, thereby generating instructions to load (gather) the values ​​of C(1, IX(I)) and C(2, IX(I)) of array C.

[0056] In this embodiment, instead of step S3 in Fig. 2 of the first embodiment, the instruction generation unit 20 determines whether the target of the list operation is a 2-row, N-column array of single-precision floating-point numbers. Furthermore, in this embodiment, instead of step S4 in Fig. 2 of the first embodiment, it determines whether there is access to C(1, IX(I)) and C(2, IX(I)) in the same row of the 2-row, N-column array of single-precision floating-point numbers in the list operation. If this is the case, the vector instruction of this embodiment is generated.

[0057] (Effects of the embodiment) According to the compiling device, compiling method, and compiling program of this embodiment, as in the first embodiment, it is possible to speed up list operations by generating an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction).

[0058] In this embodiment, the number of executions of vector gather instructions that have a long execution time can be reduced to reduce memory accesses. By reducing the number of executions of vector gather instructions, the number of accesses to memory can be reduced, and the program can be speeded up.

[0059] Furthermore, according to this embodiment, it is possible to speed up list operations targeting a 2-row, N-column array of single-precision floating-point numbers, thereby expanding the range of programs that can be speeded up.

[0060] Third Embodiment Next, a compiling device, a compiling method, and a compiling program according to a third embodiment of the present invention will be described. The compiling device, the compiling method, and the compiling program according to this embodiment will be described with the same contents as those of the first embodiment omitted, and only the differences will be described. In the first embodiment, a program including a list operation targeted at a single-precision complex type array was described as an example, and in the second embodiment, a program including a list operation targeted at a 2-row, N-column single-precision floating-point type array was described as an example, but the present invention is not limited to this. For example, the present invention can also be applied to a program including a list operation targeted at a structure type array having two single-precision floating-point numbers as components.

[0061] Figure 10(a) is a source program including a list operation targeting derived array D having single-precision variables aa and bb as components, and Figure 10(b) is a conceptual diagram showing the memory arrangement of derived array D having single-precision variables aa and bb as components. The content of the source program in Figure 10(a) is to extract the single-precision variable aa and single-precision variable bb of the IX(I)th element of derived array D having single-precision variables aa and bb as components, and assign the addition result to array B.

[0062] As shown in Figure 10(b), in a structure type array D having single precision variables aa and bb as components, D(1)%aa, D(1)%bb, D(2)%aa, D(2)%bb to D(N)%aa, D(N)%bb are arranged alternately every 4 bytes.

[0063] In list operations targeting a structure type array D having single-precision variables aa and bb as components, as in the first embodiment described above, an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction) are generated, thereby generating instructions to load (gather) the values ​​of the single-precision variables aa and bb of array D.

[0064] In this embodiment, instead of step S3 in Fig. 2 of the first embodiment, the instruction generation unit 20 judges whether the target of the list operation is a structure type array having single-precision variables aa and bb as components. Furthermore, in this embodiment, instead of step S4 in Fig. 2 of the first embodiment, it judges whether there is access to the single-precision variables aa and bb of the same array element in the list operation. If this is the case, the vector instruction of this embodiment is generated.

[0065] (Effects of the embodiment) According to the compiling device, compiling method, and compiling program of this embodiment, as in the first embodiment, it is possible to speed up list operations by generating an 8-byte vector gather instruction (VGT8 instruction), a vector logical AND instruction (VAND instruction), and a vector logical shift instruction (VSLL instruction).

[0066] In this embodiment, the number of executions of vector gather instructions that have a long execution time can be reduced to reduce memory accesses. By reducing the number of executions of vector gather instructions, the number of accesses to memory can be reduced, and the program can be speeded up.

[0067] Furthermore, according to this embodiment, it is possible to speed up list operations that target arrays of a structure type having single-precision variables aa and bb as components, thereby expanding the range of programs that can be accelerated.

[0068] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this. For example, the present invention is not limited to the specific array names mentioned in the first to third embodiments, and can also be applied to a source program including a list operation targeting a structure type array having a first variable and a second variable as components. Various modifications are possible within the scope of the invention described in the claims, and it goes without saying that these are also included in the scope of the present invention.

[0069] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes. (Note 1) A code analysis unit that determines whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; a vector instruction generating unit that generates a vector gather instruction, a vector logical product instruction, and a vector shift instruction when a list operation targeting an array of a derived type having a first variable and a second variable as the components is included, Compilation device. (Note 2) The structure type array has first variables and second variables arranged alternately in memory every 4 bytes as the components, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; The vector shift instruction fetches the values ​​obtained by shifting each element of the second vector register to the left by 4 bytes into a fourth vector register. 2. A compiling device as described in claim 1. (Note 3) The structure type array having the first variable and the second variable as components is a single-precision complex type array in which the real part and the imaginary part are alternately arranged every 4 bytes. 3. A compiling apparatus as claimed in claim 2. (Note 4) The structure type array having the first variable and the second variable as components is a 2-row, N-column single-precision floating-point array in which elements are alternately arranged every 4 bytes. 3. A compiling apparatus as claimed in claim 2. (Note 5) The structure type array having a first variable and a second variable as components is a 2-row, N-column single-precision floating-point array in which the first single-precision variable and the second single-precision variable are alternately arranged every 4 bytes. 3. A compiling apparatus as claimed in claim 2. (Appendix 6) A code analysis unit determines whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; When a list operation targeting an array of a derived type having a first variable and a second variable as the components is included, the vector instruction generates a vector gather instruction, a vector logical product instruction, and a vector shift instruction. How to compile. (Note 7) The structure type array has first variables and second variables arranged alternately in memory every 4 bytes as the components, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; The vector shift instruction fetches the values ​​obtained by shifting each element of the second vector register to the left by 4 bytes into a fourth vector register. A compilation method as described in Appendix 6. (Note 8) The structure type array having the first variable and the second variable as components is a single-precision complex type array in which the real part and the imaginary part are alternately arranged every 4 bytes. 8. The compilation method according to claim 7. (Note 9) The array of structure type having the first variable and the second variable as components is a 2-row, N-column array of single-precision floating-point numbers, in which elements are alternately arranged every 4 bytes. 8. The compilation method according to claim 7. (Note 10) The structure type array having a first variable and a second variable as components is a 2-row, N-column single-precision floating-point array in which the first single-precision variable and the second single-precision variable are alternately arranged every 4 bytes. 8. The compilation method according to claim 7. (Appendix 11) A computer, code analysis means for determining whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; when a list operation targeting an array of a derived type having a first variable and a second variable as the components is included, the vector instruction generating means functions as a vector instruction generating means for generating a vector gather instruction, a vector logical product instruction, and a vector shift instruction. Compile program. (Additional Note 12) The structure type array has first variables and second variables arranged alternately in memory every 4 bytes as the components, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; The vector shift instruction fetches the values ​​obtained by shifting each element of the second vector register to the left by 4 bytes into a fourth vector register. 12. The compilation program according to claim 11. (Note 13) The structure type array having the first variable and the second variable as components is a single-precision complex type array in which the real part and the imaginary part are alternately arranged every 4 bytes. 13. The compilation program according to claim 12. (Note 14) The structure type array having the first variable and the second variable as components is a 2-row, N-column single-precision floating-point array in which elements are alternately arranged every 4 bytes. 13. The compilation program according to claim 12. (Note 15) The structure type array having a first variable and a second variable as components is a 2-row, N-column single-precision floating-point array in which the first single-precision variable and the second single-precision variable are alternately arranged every 4 bytes. 13. The compilation program according to claim 12. [Explanation of symbols]

[0070] 10 Code Analysis Section 11 List operation parser 20 Instruction generator 21 List operation determination section 22 Vector load instruction generation means 23 Vector logical shift instruction generator 24 Vector addition instruction generator 25 8-byte vector gather instruction generator 26 Vector AND instruction generation means 27 Vector store instruction generation means 100 Compiler

Claims

1. a code analysis unit that determines whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; a vector instruction generating unit that generates a vector gather instruction, a vector logical product instruction, and a vector shift instruction when a list operation targeting an array of a derived type having a first variable and a second variable as the components is included, The structure type array has a first variable and a second variable as components arranged alternately in a memory every four bytes, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte wide values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; the vector shift instruction fetches values ​​obtained by shifting each element of the second vector register left by 4 bytes into a fourth vector register; Compilation device.

2. 2. The compiling device according to claim 1, wherein the structure type array having the first variable and the second variable as components is a single-precision complex type array in which real parts and imaginary parts are alternately arranged every four bytes.

3. 2. The compiling device according to claim 1, wherein the array of structure type having the first variable and the second variable as components is a 2-row, N-column array of single-precision floating-point numbers, with elements arranged alternately every 4 bytes.

4. 2. The compiling device according to claim 1, wherein the array of structure type having a first variable and a second variable as components is a 2-row, N-column array of single-precision floating-point numbers in which the first single-precision variable and the second single-precision variable are alternately arranged every 4 bytes.

5. A code analysis unit determines whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; a vector instruction generating unit generating a vector gather instruction, a vector logical product instruction, and a vector shift instruction when a list operation targeting an array of a derived type having a first variable and a second variable as the components is included; The structure type array has a first variable and a second variable as components arranged alternately in a memory every four bytes, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte wide values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; the vector shift instruction fetches values ​​obtained by shifting each element of the second vector register left by 4 bytes into a fourth vector register; How to compile.

6. 6. The compiling method according to claim 5, wherein the array of structure type having the first variable and the second variable as components is a single-precision complex type array in which real parts and imaginary parts are alternately arranged every 4 bytes.

7. 6. The compilation method according to claim 5, wherein the array of structure type having the first variable and the second variable as components is a 2-row, N-column array of single-precision floating-point numbers, with elements arranged alternately every 4 bytes.

8. Computer, a code analysis means for determining whether a source program includes a list operation targeting an array of a derived type having a first variable and a second variable as components; functioning as a vector instruction generating means for generating a vector gather instruction, a vector logical product instruction, and a vector shift instruction when a list operation targeting an array of a derived type having a first variable and a second variable as the components is included; The structure type array has a first variable and a second variable as components arranged alternately in a memory every four bytes, the vector gather instruction is an 8-byte vector gather instruction that loads 8-byte wide values ​​located at addresses stored in each element of a first vector register from the memory into a second vector register; the vector AND instruction fetches only the most significant four bytes of each element of the second vector register into a third vector register; the vector shift instruction fetches values ​​obtained by shifting each element of the second vector register left by 4 bytes into a fourth vector register; Compile program.

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