Signal processing device, image forming device, and program

Abstract

To provide a technique which can reduce waste of a bandwidth when transmitting data to an engine side in high-speed serial communication.SOLUTION: Synchronous signals and image signals of a plurality of channels of YMCK are received and the synchronous signals and the image signals of any two or more channels of the plurality of channels are time-division multiplexed by an integration unit 15YM and output. Also, a reference signal prescribing the initiation time of communication is superimposed on the synchronous signal and output. A serial converter 16YM performs serial conversion on the reference signal and the time-division multiplexed synchronous signals and image signals and transfers them to an image output unit (engine) in the high-speed serial communication via a transmission path 18.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to a signal processing device, an image forming device, and a program. [Background technology]

[0002] Patent Document 1 describes an image processing device in which multiple devices with a common structure extract different data from common data. When the notification unit is notified of the first identification information among the above-mentioned multiple identification information, it notifies the external device of the second identification information that is next in order. The notification unit supplies the first identification information notified to itself to a storage unit, and the storage unit stores the supplied first identification information. When the receiving unit and the selector receive second data including the first data identified by the identification information stored in the storage unit, they extract the first data from the second data. The transmitting unit transmits the second data received by the extracting unit to the external device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-182742 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in the case where each of the multiple channels is equipped with an image processing unit, a video output unit, and a serial conversion unit, and data is sent to the engine side of the image forming device, which then receives the data and forms an image, if the data is sent to the engine side via high-speed serial communication, the transfer will be completed in a short time because the bandwidth for high-speed serial communication is relatively large, resulting in wasted bandwidth.

[0005] An object of the present invention is to provide a technique capable of reducing waste of bandwidth when transmitting data to the engine side through high-speed serial communication. [Means for solving the problem]

[0006] The invention described in claim 1 includes a receiving means for receiving a synchronization signal and an image signal of each of a plurality of channels, a integrating means for time-division multiplexing and integrating the synchronization signals and the image signals of any two or more of the plurality of channels, and a reference signal for specifying the start of communication. 、 The above Integrated by integration means a reference timing generating means for outputting the reference timing signal superimposed on a synchronization signal; from the reference timing generating means The reference signal, the time division multiplexed synchronization signal, and the image signal are serially converted. Image forming means and a serial conversion means for outputting the For image formation It is a signal processing device.

[0007] The invention described in claim 2 is the signal processing device described in claim 1, wherein the integration means operates on a transmission reference clock signal that is multiplied by the number n (n is an integer greater than or equal to 2) of channels to be time-division multiplexed, relative to a reference clock signal that is a basis for generating the synchronization signals of each channel of the multiple channels and the image signals.

[0008] In the invention described in claim 3, the integration means comprises: a sampling means for sampling the synchronization signal and the image signal received by the receiving means based on the transmission reference clock signal; send standard clock Based on signals determining a transmission timing for each of the channels, and The signal processing device according to claim 2, further comprising: a selection control means for outputting a selection signal for selecting a channel to be transmitted; a synchronization signal selection means for selecting a synchronization signal of a channel to be time-division multiplexed based on the selection signal from the synchronization signals of each channel sampled by the sampling means; and an image signal selection means for selecting an image signal of a channel to be time-division multiplexed based on the selection signal from the image signals of each channel sampled by the sampling means.

[0009] The invention described in claim 4 is a signal processing device described in any of claims 1 to 3, wherein the synchronization signal includes a line synchronization signal, a page synchronization signal, and a data enable signal, and the reference signal is superimposed on either the line synchronization signal or the page synchronization signal.

[0010] The invention described in claim 5 is the signal processing device described in claim 1, wherein the integration means time-division multiplexes and integrates the synchronization signals and image signals of any two or more of the multiple channels for each line.

[0011] In the invention described in claim 6, the synchronization signal includes a line synchronization signal, and the integration means A line synchronization signal of any two or more channels among the plurality of channels, The reference signal No. Different delay times are used for each At that time division multiplexing and integrate The signal processing device according to claim 5.

[0012] In accordance with a seventh aspect of the present invention, the synchronization signal includes a data enable signal, The integration means includes: The data enable signals of any two or more of the plurality of channels are set relative to the reference signal. Each uses a different delay time. At that time 7. The signal processing device according to claim 6, wherein the signal processing device performs division multiplexing and integration.

[0013] The invention described in claim 8 is a signal processing device described in any of claims 1 to 7, further comprising a separation means for receiving the serial signal output from the serial conversion means and separating it into the time-division multiplexed synchronization signal and image signal, and an extraction means for extracting the synchronization signal and image signal of each channel from the time-division multiplexed synchronization signal and image signal based on the reference signal.

[0014] The invention described in claim 9 is an image forming device comprising the signal processing device described in claim 8 and a forming means for forming an image on a medium based on the synchronization signal and image signal of each channel output from the extraction means of the signal processing device.

[0015] The invention described in claim 10 is a computer including a receiving means for receiving a synchronization signal and an image signal of each of a plurality of channels, a integrating means for time-division multiplexing and integrating the synchronization signals and the image signals of any two or more of the plurality of channels, and a reference signal for specifying a start time of communication. 、 The above Integrated by integration means a reference timing generating means for outputting the reference timing signal superimposed on a synchronization signal; from the reference timing generating means The reference signal, the time division multiplexed sync signal and the image signal are serially converted. Image forming means It functions as a serial conversion means for output. For image formation It is a program. Effect of the Invention

[0016] According to the invention as set forth in claims 1 to 10, when data is transmitted to the engine side by high-speed serial communication, it is possible to reduce waste of bandwidth.

[0017] According to the invention as defined in claim 4, there is furthermore no need to transfer the reference signal over a separate signal line. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a diagram illustrating a configuration of an image forming apparatus according to a comparative example. [Diagram 2] 11 is a timing chart of a line synchronization signal and a data enable signal in a comparative example. [Figure 3A] 2 is a configuration diagram of an image processing unit (controller) in the image forming apparatus according to the embodiment. [Figure 3B] FIG. 2 is a configuration diagram of an image output unit (engine) in the image forming apparatus according to the embodiment. [Figure 4] FIG. 2 is a detailed configuration diagram of an integration unit according to the embodiment. [Diagram 5] 4 is a timing chart according to the embodiment. [Figure 6] 4 is a timing chart of a reference signal according to the embodiment. [Figure 7] FIG. 2 is a detailed configuration diagram of an extraction unit according to the embodiment. [Figure 8] 4 is a process flowchart of an image processing unit (controller) according to the embodiment. [Figure 9] 4 is a process flowchart of an image output unit (engine) according to the embodiment. [Figure 10] 13 is a timing chart of a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0020] First, before describing the present embodiment, an image forming apparatus of a comparative example that is the premise of the present embodiment will be described. The configuration of the image forming apparatus is described in, for example, Patent Document 1. The image forming apparatus forms a color image on a medium such as paper by, for example, an electrophotographic method using toners of the respective colors of Y (yellow), M (magenta), C (cyan), and K (black). The image forming apparatus includes, as its main components, an exposure control unit, an LPH (LED Print Head), a photoconductor drum, and a forming unit.

[0021] The LPH has an LED (Light Emitting Diode) array, which is a plurality of light sources arranged in the main scanning direction, and illuminates each LED to irradiate the photoconductor drum with exposure light. The exposure control unit controls the lighting timing of each LPH. The photoconductor drum has a photosensitive layer and is an image carrier that holds a latent image on the surface of the photosensitive layer and a toner image formed by developing the latent image. For example, one LPH exposes the photoconductor drum to form a latent image developed with yellow (Y) toner. The photoconductor drums are provided corresponding to the light sources (LPHs of each color). The formation unit develops the latent image formed on the photoconductor drum exposed by the LPHs of each color to form an image on a medium.

[0022] The exposure control unit includes an image processing unit, an image output unit, and a transmission unit that connects them to transmit data. The image processing unit generates image data for each color of YMCK from image data transmitted from an external device. The image data for each color generated by the image processing unit is transmitted to the image output unit via the transmission unit. The image output unit outputs an image on a medium in which toner images of each color represented by the transmitted image data for each color are superimposed. The transmission unit forms a data transmission path for serial communication (high-speed serial communication) that complies with the V-by-one (registered trademark) standard, for example, and includes a signal line that transmits up to two synchronization signals and a signal line that transmits a serial data signal.

[0023] The image processing unit includes a data control unit, a signal line, and a conversion unit. The data control unit generates a data signal including image data for each color, a synchronization signal, and a data enable signal, and supplies these signals to the conversion unit via the signal line. The conversion unit is connected to the transmission unit, and converts the supplied signal into a serial data signal in which multiple signal trains are arranged in time series, and transfers the serial data signal to the image output unit via the transmission unit.

[0024] The configurations of an image processing unit and an image output unit of the comparative example are shown in Fig. 1. The image processing unit functions as a controller, and the image output unit functions as an engine.

[0025] The image processing unit is provided with an image processor, a video interface (IF), and a serial converter for each color to generate image data for each color of YMCK. Specifically, for Y color, the image processor is provided with an image processor 12Y, a video interface (IF) 14Y, and a serial converter 16Y. Here, the subscript "Y" of the symbol indicates that the configuration is related to Y color. For M color, the image processor is provided with an image processor 12M, a video interface (IF) 14M, and a serial converter 16M. For C color, the image processor is provided with an image processor 12C, a video interface (IF) 14C, and a serial converter 16C. For K color, the image processor is provided with an image processor 12K, a video interface (IF) 14K, and a serial converter 16K. If each color of YMCK is called a channel, it can be said that the channel Y is composed of the image processor 12Y, the video interface (IF) 14Y, and the serial converter 16Y. The same applies to the other channels.

[0026] The image processing unit also includes a timing generator 10. The timing generator 10 generates a page synchronization signal PS as a vertical synchronization signal and a line synchronization signal LS as a horizontal synchronization signal for each channel, and outputs them to the video IFs 14Y, 14M, 14C, and 14K of each channel. Specifically, the timing generator 10 generates a page synchronization signal PS(Y) and a line synchronization signal LS(Y) for channel Y, and outputs them to the video IF 14Y of channel Y. The timing generator 10 also generates a page synchronization signal PS(M) and a line synchronization signal LS(M) for channel M, and outputs them to the video IF 14M of channel M. The timing generator 10 also generates a page synchronization signal PS(C) and a line synchronization signal LS(C) for channel C, and outputs them to the video IF 14C of channel C. The timing generator 10 also generates a page synchronization signal PS(K) and a line synchronization signal LS(K) for channel K, and outputs them to the video IF 14K of channel K.

[0027] The video IFs 14Y, 14M, 14C, and 14K of each channel generate a data signal Data, a page synchronization signal PS, a line synchronization signal LS, and a data enable signal DE indicating image data for each channel based on the page synchronization signal PS and the line synchronization signal LS from the timing generator 10, and output them to the serial converter.

[0028] The serial converters 16Y, 16M, 16C, and 16K of each channel convert the data signal Data, page synchronization signal PS, line synchronization signal LS, and data enable signal DE from the video IFs 14Y, 14M, 14C, and 14K of each channel into serial signals and transfer them to the image output unit via the transmission unit 18.

[0029] The transmission unit 18 is shown as a harness in the figure, and transfers the data signal Data, the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE to the image output unit by serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard, for example. If the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE are collectively referred to as synchronization signals, the image signal (data signal Data) and the synchronization signals are transferred to the image output unit by high-speed serial communication.

[0030] The image output unit (engine) includes a deserializer and an output unit for each color (channel) to output image data for each color of YMCK. Specifically, for channel Y, it includes a deserializer 20Y and an output unit 22Y. For channel M, it includes a deserializer 20M and an output unit 22M. For channel C, it includes a deserializer 20C and an output unit 22C. For channel K, it includes a deserializer 20K and an output unit 22K.

[0031] The deserializers 20Y, 20M, 20C, and 20K of each channel convert the received serial signal back into the pre-serial conversion data signal Data, page synchronization signal PS, line synchronization signal LS, and data enable signal DE, and output them to the respective output sections 20Y, 20M, 22C, and 22K.

[0032] The output units 20Y, 22M, 22C, and 22K of each channel include an LPH lighting control unit, an LPH, a photoconductor drum, and a forming unit. The LPH lighting control unit controls the lighting timing of the LPH using the supplied data signal Data, etc., and develops the latent image formed on the photoconductor drum exposed by the LPH of each channel in the forming unit to form an image on a medium.

[0033] 2 shows a timing chart for transferring a data signal Data, a page synchronization signal PS, a line synchronization signal LS, and a data enable signal DE to an image output unit by serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard. For convenience of explanation, the figure shows a timing chart for any one of channels Y, M, C, and K.

[0034] It is sufficient to transfer one line's worth of image data from the image processing unit (controller) to the image output unit (engine) during one period of the line synchronization signal LS, i.e., during the section from the rising timing of one pulse to the rising timing of the next pulse (LS section), but the transmission of one line's worth of image data is completed during the section where the pulse of the data enable signal DE, which indicates the section for transmitting the data signal Data, is rising, and the remaining section is wasted.

[0035] Specifically, assuming that one line of image data is 1200 x 2400 dpi and 30 ppm, a bandwidth of approximately 270 Mbps per channel would suffice, but the transfer bandwidth of V-by-one (registered trademark) (lower limit in 4-byte mode) is 600 Mbps, which is more than twice the required bandwidth for high-speed serial communication, resulting in excess bandwidth being wasted.

[0036] Therefore, in this embodiment, instead of transferring data signals etc. from the image processing unit to the image output unit independently for each channel, at least two or more of the four YMCK channels are merged to reduce waste of bandwidth. For example, in this embodiment, data signals etc. of channel Y and channel M are merged and transferred to the image output unit as a single channel signal by serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard. This expands the bandwidth compared to when signals of one channel are transferred independently, and makes it possible to effectively utilize the transfer bandwidth of V-by-one (registered trademark) (lower limit of 4-byte mode).

[0037] However, in the V-by-one (registered trademark) standard, there is only one signal line each for the page synchronization signal PS, line synchronization signal LS, and data enable signal DE, so the page synchronization signal PS, line synchronization signal LS, and data enable signal DE of multiple channels cannot be output simultaneously.

[0038] For this reason, in this embodiment, a transmission reference clock signal (TCLK) is newly generated by multiplying the clock signal (VCLK) that is the reference for generating the data signal Data, page synchronization signal PS, line synchronization signal, and data enable signal DE of each channel by a factor n corresponding to the number of channels to be integrated (n is an integer of 2 or more), and this transmission reference clock signal is used to time-division multiplex and integrate the n channels. For example, two channels, channel Y and channel M, are time-division multiplexed and integrated, and then transferred from the image processing unit (controller) to the image output unit (engine). By time-division multiplexing, the page synchronization signal PS, line synchronization signal LS, and data enable signal DE of multiple channels can be transferred using a single signal line, respectively, without being output simultaneously.

[0039] Next, the image forming apparatus of this embodiment will be described based on the above comparative example. FIG. 3A shows the configuration of an image processing unit as a signal processing device in the image forming apparatus of this embodiment. For convenience of explanation, a case where two channels, channel Y and channel M, are integrated among four channels, YMCK, is illustrated. The difference from FIG. 1 is that a merge unit 15YM is provided between the video IFs 14Y, 14M of channels Y and M and the serial converters 16Y, 16M, and that the serial converters 16Y, 16M are integrated into one to form a serial converter 16YM. The subscript "YM" of the symbol indicates that the channel Y and channel M are integrated. The image processors 12Y, 12M and the video IFs 14Y, 14M function as receiving means, the merge unit 15YM functions as integration means, and the serial converter 16YM functions as serial conversion means. In the following description, the merge unit 15YM is appropriately referred to as an "integration unit".

[0040] The integration unit 15YM samples the data signals Data, page synchronization signal PS, line synchronization signal LS, and data enable signal DE from the video IFs 14Y and 14M with a transmission reference clock signal (TCLK) that is doubled with respect to a reference clock signal (VCLK), and transmits the signals of the channels Y and M to the serial converter 16YM in time series order. That is, in synchronization with the transmission reference clock signal (TCLK), first transmit the data signals Data, etc. of the channel Y, then transmit the data signals Data, etc. of the channel M, then transmit the data signals Data, etc. of the channel Y, and then transmit the data signals Data, etc. of the channel M. That is, the data signals, etc. of the two channels Y and M to be integrated are time-division multiplexed by alternately transmitting them. The integration unit 15YM outputs the integrated data signals, etc., which have been time-division multiplexed, to the serial converter 16YM. The transmission reference clock signal (TCLK) can be generated by the timing generator 10 from the reference clock signal (VCLK).

[0041] The integrator 15YM also integrates data signals and the like of two channels, channel Y and channel M, and generates a reference signal indicating which timing of a transmission reference clock signal (TCLK) obtained by doubling the reference clock signal (VCLK) corresponds to the integrated signal of each channel, and outputs the reference signal to the serial converter 16YM. Specifically, as described later, the reference signal is added to the integrated line synchronization signal and the result is output to the serial converter 16YM.

[0042] The serial converter 16YM serially converts the integrated data signals of the channels Y and M, and transfers them to the image output unit (engine) via the transmission unit 18.

[0043] Similarly, data signals of channels C and K can be time-division multiplexed and integrated using an integration unit.

[0044] Fig. 3B shows the configuration of an image output unit as a signal processing device in this embodiment. For convenience of explanation, a case where two channels, channel Y and channel M, of the four channels YMCK are integrated is shown in accordance with the configuration in Fig. 3A. The difference from Fig. 1 is that extraction units 21Y, 21M are provided between deserializers 20Y, 20M of channels Y and M and output units 22Y, 22M.

[0045] The extraction units 21Y and 21M are provided for each channel. For example, the extraction unit 21Y is provided for the channel Y, and is supplied with the data signal Data, the page synchronization signal PS, the line synchronization signal LS, and the data enable signal from the deserializer 20Y. The extraction unit 21Y detects which timing of the transmission reference clock signal is the reference for the signals of the channels Y and M according to the reference signal generated and transferred by the integration unit 15YM (see FIG. 3A), and controls the timing of selecting the data signal Data, etc. in each channel. For example, the extraction unit 21Y for the channel Y selects and reads the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of the channel Y from the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of the channel Y, and the data signal Data(M), page synchronization signal PS(M), line synchronization signal LS(M), and data enable signal DE(M) of the channel M, which are time-division multiplexed and transferred. On the other hand, the data signal Data(M), page synchronization signal PS(M), line synchronization signal LS(M), and data enable signal DE(M) of channel M are not selected and are skipped over (skipped).Then, the extracted data signal of channel Y and the like are output to the output unit 22Y.

[0046] The extraction unit 21M of the channel M selects and reads the data signal Data(M), page synchronization signal PS(M), line synchronization signal LS(M), and data enable signal DE(M) of the channel M from the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of the channel Y, which have been time-division multiplexed and transferred. On the other hand, the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of the channel Y are not selected but are skipped. Then, the extracted data signals, etc. are output to the output unit 22M. It can be said that the extraction units 21Y and 21M perform the inverse conversion of the integration unit 15YM to extract the data signals, etc. of each channel (separate the time-division multiplexed signals from each other).

[0047] The extraction units 21Y, 21M of each channel extract the data signals, etc. of their own channel. Since these are signals sampled by the integration unit 15YM using the transmission reference clock signal (TCLK), when they are output to the output units 22Y, 22M, they are converted back to the original reference clock signal (VCLK) before being output.

[0048] Fig. 4 shows a detailed configuration of the integrating unit 15YM in Fig. 3A. For convenience of explanation, a case where two channels, channel Y and channel M, out of four channels YMCK, are integrated according to the configuration in Fig. 3A will be illustrated.

[0049] The integration unit 15YM includes sampling units 30Y, 30M, a control signal selector unit (LS) 32, a control signal selector unit (PS) 34, a control signal selector unit (DE) 36, an image data selector unit 38, a reference timing generation unit 40, a selector control unit 42, a reference signal generation unit 44, and a reference signal selector unit 46.

[0050] The sampling units 30Y and 30M sample the data signal Data, page synchronization signal, line synchronization signal, and data enable signal of each channel using the transmission reference clock signal (TCLK) and output them to the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38, respectively. For example, the sampling unit 30Y of channel Y samples the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of channel Y using the transmission reference clock signal (TCLK) and output them to the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38, respectively. In addition, the sampling unit 30M of channel M samples the data signal Data(M), page synchronization signal PS(M), line synchronization signal LS(M), and data enable signal DE(M) of channel M using the transmission reference clock signal (TCLK), and outputs them to the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38, respectively.

[0051] The reference timing generation unit 40 inputs a transmission reference clock signal (TCLK) and determines which timing (edge) will be the transmission timing for each channel. For example, the reference timing generation unit 40 determines the transmission timing of the channel Y signal based on the rising edge of a certain pulse of the transmission reference clock signal (TCLK), and determines the transmission timing of the channel M signal based on the rising edge of the next pulse following that pulse.

[0052] The selector control unit 42 controls the selection of a channel to be transmitted with the transmission reference clock signal (TCLK) in accordance with the timing determined by the reference timing generation unit 40. The selector control unit 42 outputs a selection signal of a channel to be currently transmitted with the transmission reference clock signal (TCLK) to the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38.

[0053] The control signal selector unit (LS) 32 time-division multiplexes these two signals by alternately selecting the line synchronization signal LS(Y) of channel Y from the sampling unit 30Y and the line synchronization signal LS(M) of channel M from the sampling unit 30M in a time series in response to a selection signal from the selector control unit 42.

[0054] The control signal selector unit (PS) 34 time-division multiplexes these two signals by alternately selecting the page synchronization signal PS(Y) for channel Y from the sampling unit 20Y and the page synchronization signal PS(M) for channel M from the sampling unit 20M in a time series in response to a selection signal from the selector control unit 42.

[0055] The control signal selector unit (DE) 36 time-division multiplexes these two signals by alternately selecting the data enable signal DE(Y) of channel Y from the sampling unit 20Y and the data enable signal DE(M) of channel M from the sampling unit 20M in a time series in response to a selection signal from the selector control unit 42.

[0056] In response to a selection signal from the selector control unit 42, the image data selector unit 38 time-division multiplexes these two signals by alternately selecting the data signal Data(Y) of channel Y from the sampling unit 20Y and the data signal Data(M) of channel M from the sampling unit 20M in a time series.

[0057] The reference signal generation unit 44 generates a reference signal that serves as a reference for extracting the time-division multiplexed signal for each channel in the image output unit (engine) in accordance with the timing determined by the reference timing generation unit 40, and outputs the reference signal to the reference signal selector unit 46.

[0058] The reference signal selector unit 46 superimposes (adds) the reference signal from the reference signal generation unit 44 onto the integrated line synchronization signal from the control signal selector unit (LS) 32 and outputs the superimposed signal to the serial converter 16YM. The reference timing generation unit 40, the reference signal generation unit 44, and the reference signal selector unit 46 function as a reference timing generation means.

[0059] At least one of the functional blocks of the integration unit 15YM shown in Fig. 4 and the functional blocks including the serial converter 16YM, or all of them, can be realized by a computer having one or more processors reading out and executing a processing program from a memory storing the processing program. The processor refers to a processor in a broad sense, and includes a general-purpose processor (e.g., a CPU (Central Processing Unit) and a dedicated processor (e.g., a GPU (Graphics Processing Unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), a programmable logic device, and the like). The operation of a processor may not only be performed by one processor, but may also be performed by multiple processors located at physically separate locations working together. The order of the operation of the processors may be changed as appropriate.

[0060] 5 shows a timing chart of each signal in the integration unit 15YM. In the figure, from the top, the timing charts of the reference clock signal (VLCK), the line synchronization signal LS(Y), the data enable signal DE(Y), the data signal Data(Y), the line synchronization signal LS(M), the data enable signal DE(M), and the data signal Data(M) are shown. Here, in the figure, the line synchronization signal LS(Y) is shown as LS_Y, the data enable signal DE(Y) as DE_Y, the data signal Data(Y) as DATA_Y, the line synchronization signal LS(M) as LS_M, the data enable signal DE(Y) as DE_M, and the data signal Data(Y) as DATA_M. In addition, below these signals, the transmission reference clock signal (TCLK), the integrated line synchronization signal LS_0, the integrated data enable signal DE_0, and the integrated data signal DATA_0 are shown.

[0061] For channel Y, the line synchronization signal LS_Y rises from L (Low) to H (Hi) at a certain rising edge of the reference clock signal VCLK. The data enable signal DE_Y rises from L (Low) to H (Hi) at the next rising edge of the reference clock signal VCLK. During the section in which the data enable signal DE_Y is H, the data signal DATA_Y is D_Y0, D_Y1, D_Y2,... are transmitted in sequence.

[0062] For channel M, the line synchronization signal LS_M rises from L to H at another rising edge of the reference clock signal VCLK. The data enable signal DE_M rises from L to H at the following rising edge of the reference clock signal VCLK. During the section in which the data enable signal DE_M is H, the data signal DATA_M is D_M0, D_M1, D_M2,... are transmitted in sequence.

[0063] On the other hand, the transmission reference clock signal TCLK is multiplied by two times the reference clock signal VCLK in accordance with the number of channels to be integrated, n=2. The reference timing generation unit uses this transmission reference clock signal TCLK to determine the timing for transmitting the data signal of channel Y and the timing for transmitting the data signal of channel M. In the figure, if the timing of the circled number 1 (hereinafter referred to as timing "1") is the transmission timing of channel Y and the timing of the circled number 2 (hereinafter referred to as timing "2") is the transmission timing of channel M, at the timing of "1", the line synchronization signal LS_Y of channel Y is selected and LS_0 rises from L to H, and at the timing of the next pulse, the line synchronization signal LS_M of channel M is selected at the timing of "2". However, since the line synchronization signal LS_M is L at this timing, the line synchronization signal LS_0 after integration becomes L. Similarly, the line synchronization signal LS_Y of channel Y and the line synchronization signal LS_M of channel M are integrated in a time-division manner at timings "1" and "2" synchronized with the transmission reference clock signal. Then, at the timing when the line synchronization signal LS_M of channel M changes from L to H, the line synchronization signal LS_M of channel M also rises to H at timing "2", so from this point onwards the integrated line synchronization signal LS_0 remains H.

[0064] Furthermore, at the timing of "1", the data enable signal DE_Y of channel Y is selected and DE_0 rises from L to H, and at the timing of the next pulse, the data enable signal DE_M of channel M is selected at the timing of "2", but since the data enable signal DE_M is L at this timing, the combined data enable signal DE_0 becomes L. Similarly, the data enable signal DE_Y of channel Y and the data enable signal DE_M of channel M are integrated in a time-division manner at the timing of "1" and timing of "2" synchronized with the transmission reference clock signal. Then, at the timing when the data enable signal DE_M of channel M changes from L to H, the data enable signal DE_M of channel M also rises to H at the timing of "2", so the combined data enable signal DE_0 remains H from this point on.

[0065] Then, at the timing of "1" when the data enable signal DE_0 is at H, the data signal DATA_Y of channel Y is selected, and at the timing of "2" when the data enable signal DE_0 is at H, the data signal DATA_M of channel M is selected, thereby integrating the image data of the two channels. As a result, the data signals of the two channels Y and M are D_Y0,D_Y1,D_Y2,...D_Y(N),D_M0,D_Y(N+1),D_M1,... and are integrated in a time-division manner.

[0066] In Figure 5, the combined data signal at the timing when the data enable signal DE_M of channel M is L is expressed as D_MX, but this indicates that it can be arbitrary because no significant image data is transmitted when the data enable signal DE_M is L.

[0067] In addition, in Figure 5, the timing chart of the integrated page synchronization signal is omitted, but like the integrated line synchronization signal, the integrated page synchronization signal is also integrated in a time-division manner at timings "1" and "2" synchronized with the transmission reference clock signal, with the page synchronization signal PS_Y of channel Y and the page synchronization signal PS_M of channel M being integrated at timings "1" and "2" synchronized with the transmission reference clock signal.

[0068] In this manner, the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38 synchronize with the transmission reference clock signal and alternately select the channel Y signals and the channel M signals in a time series using the timing determined by the reference timing generation unit 40, thereby integrating the data signals etc. of channel Y and the data signals etc. of channel M and outputting them to the serial converter 16YM.

[0069] Although the reference signal generated by the reference signal generating unit 44 is not shown in the timing chart of FIG. 5, the reference signal is added to the start timing of the integrated line synchronization signal LS_0.

[0070] FIG. 6 shows a timing chart of the reference signal generated by the reference signal generating unit 44 and added to the integrated line synchronization signal LS_0 by the reference signal selector unit 46. In FIG.

[0071] 6. In FIG. 6, from the top, the timing chart shows the reference clock signal VCLK, the transmission reference clock signal TCLK, the combined line synchronization signal LS_0, the combined data enable signal DE_0, and the combined data signal DATA_0.

[0072] The reference signal is superimposed (added) on the start timing of the line synchronization signal LS_0 as a pulse-like signal that rises from L to H in one cycle of the reference clock signal VCLK and then falls from H to L. The reference signal can be said to be a signal that toggles every 1VCLK. Note that the reference signal needs to have a signal waveform that can be clearly distinguished from the line synchronization signal LS of each channel, and when the line synchronization signal LS does not toggle every 1VCLK, a pulse-like reference signal that toggles every 1VCLK as shown in FIG. 6 is effective.

[0073] As described above, the image output unit (engine) extracts the data signal for each channel from the integrated and transferred signal, and at this time detects a reference signal from the line synchronization signal LS_0 shown in Fig. 6, and determines the timing of the data signal for channel Y and the timing of the data signal for channel M by detecting this reference signal. In other words, the reference signal functions as a signal that determines the start of communication of the integrated signal.

[0074] In Fig. 6, the reference signal is a signal that toggles at 1VCLK, but the signal waveform is not limited to this. In this embodiment, the reference signal is added to the integrated line synchronization signal LS_0, but it may be added to the integrated page synchronization signal PS_0. Furthermore, the reference signal may be added to the integrated data signal DATA_0. However, in the last example, it is sufficient to change the integrated data enable signal DE_0 to H at the timing when the reference signal is added.

[0075] Fig. 7 shows a detailed configuration of the extraction unit 21Y in Fig. 3B. The extraction unit 21M has a similar configuration.

[0076] The extraction unit 21Y of channel Y includes a control signal selector unit (LS) 50, a control signal selector unit (PS) 52, a control signal selector unit (DE) 54, an image data selector unit 56, a reference timing detection unit 58, a selector control unit 60, and a clock conversion unit 62.

[0077] The reference timing detection unit 58 detects a reference signal from the integrated line synchronization signal LS_0 output from the deserializer 20Y. That is, when a reference signal is added to the integrated line synchronization signal LS_0 as shown in FIG. 6, the reference timing detection unit 58 detects the reference signal that is added to the integrated line synchronization signal LS_0 and toggles at 1VCLK, and outputs the reference signal to the selector control unit 60.

[0078] The selector control unit 60 determines the timing of channel Y of the two integrated channels Y and M in response to the reference signal detected by the reference timing detection unit 58, and outputs a selection signal to the control signal selector unit (LS) 50, the control signal selector unit (PS) 52, the control signal selector unit (DE) 54, and the image data selector unit 56. Specifically, when the reference signal is detected, the selector control unit 60 sets one period of the transmission reference clock signal that is advanced by a predetermined period based on the rising timing of the reference signal as the section of channel Y, and sets the next period of the transmission reference clock signal as the section of channel M, and generates and outputs a selection signal.

[0079] The control signal selector unit (LS) 50 selects signals in a section defined by a selection signal from the integrated line synchronization signal LS_0 output from the deserializer 20Y, and extracts the line synchronization signal LS_Y of channel Y by skipping over signals in other sections without selecting them.

[0080] The control signal selector unit (PS) 52 selects signals in a section specified by a selection signal from the integrated line synchronization signal PS_0 output from the deserializer 20Y, and extracts the page synchronization signal PS_Y of channel Y by skipping over signals in other sections without selecting them.

[0081] The control signal selector unit (DE) 54 extracts the data enable signal DE_Y of channel Y by selecting signals in a section defined by a selection signal from the integrated data enable signal DE_0 output from the deserializer 20Y, and skipping signals in other sections without selecting them.

[0082] The image data selector unit 56 extracts the data signal DATA_Y of channel Y by selecting signals in a section defined by a selection signal from the integrated data signal DATA_0 output from the deserializer 20Y and skipping signals in other sections without selecting them.

[0083] The clock conversion unit 62 converts the clock signal from the transmission reference clock signal TCLK to the reference clock signal VCLK by re-sampling the line synchronization signal LS_Y, page synchronization signal PS_Y, data enable signal DE_Y, and data signal DATA_Y of channel Y output from the control signal selector unit (LS) 50, the control signal selector unit (PS) 52, the control signal selector unit (DE) 54, and the image data selector unit 56 with the reference clock signal VCLK, and outputs the converted clock signal.

[0084] At least some of the functional blocks of the extraction unit 21Y shown in Fig. 7 can be realized by a computer having one or more processors reading out and executing a processing program from a memory storing the processing program. The term "processor" refers to a processor in a broad sense, and includes a general-purpose processor (e.g., a CPU (Central Processing Unit) and a dedicated processor (e.g., a GPU (Graphics Processing Unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), a programmable logic device, and the like). The operation of a processor may not only be performed by one processor, but may also be performed by multiple processors located at physically separate locations working together. The order of the operations of the processors may also be changed as appropriate.

[0085] FIG. 8 shows a main processing flowchart of the image processing unit (controller).

[0086] The reference timing generation unit 40 determines the timing of the two channels Y and M to be integrated, and outputs the timing to the reference signal generation unit 44. The reference signal generation unit 44 generates a reference signal according to this timing, and transmits it to the reference signal selector unit 46 (S101). Furthermore, the selector control unit 42 outputs a selection signal according to the timing determined by the reference timing generation unit 40 to the control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38.

[0087] The control signal selector unit (LS) 32, the control signal selector unit (PS) 34, the control signal selector unit (DE) 36, and the image data selector unit 38 select the line synchronization signal LS, the page synchronization signal, the data enable signal DE, and the data signal in response to the selection signal, respectively, to time-division multiplex and integrate the data signals of channels Y and M, etc. (S102). In addition, the reference signal selector unit 46 further adds a reference signal to the integrated line synchronization signal.

[0088] The serial converter 16YM transfers the integrated data, i.e., the integrated line synchronization signal, the integrated page synchronization signal, the integrated data enable signal, and the integrated data signal, to the image output unit (engine) via high-speed serial communication conforming to standards such as V-by-one (registered trademark) (S103).

[0089] FIG. 9 shows a main process flowchart of the image output unit (engine).

[0090] The reference timing detection unit 58 receives a reference signal included in the integrated line synchronization signal (S201), and outputs a detection signal to the selector control unit 60. The selector control unit 60 outputs a selection signal to the control signal selector unit (LS) 50, the control signal selector unit (PS) 52, the control signal selector unit (DE) 54, and the image data selector unit 56 according to the detection timing of the reference signal.

[0091] The control signal selector unit (LS) 50, the control signal selector unit (PS) 52, the control signal selector unit (DE) 54, and the image data selector unit 56 receive the integrated data (S202), and each judges whether or not it is the clock timing of its own channel (ch) according to the selection signal (S203). For example, as described above, if the timing of "1" is the timing of a data signal of channel Y, and the timing of "2" is the timing of a data signal of channel Y, the control signal selector unit (LS), the control signal selector unit (PS), the control signal selector unit (DE), and the image data selector unit of channel Y each judge the timing of "1" to be the clock timing of their own ch (YES in S203), and read a signal from the received integrated data (S204). Also, they judge the timing of "2" to be not the clock timing of their own ch (NO in S203), and skip without reading a signal from the received integrated data (S205).

[0092] As described above, in this embodiment, image signals and synchronization signals of multiple channels are integrated in a time-division manner in synchronization with a transmission reference clock signal that is a multiplied version of the reference clock signal VCLK, and then transferred to the image output unit via serial communication (high-speed serial communication) that complies with standards such as V-by-one (registered trademark), thereby reducing waste of bandwidth compared to the case where each channel is transferred independently.

[0093] In this embodiment, the image signals and synchronizing signals of two channels, channel Y and channel M, are time-division multiplexed, but the image signals and synchronizing signals of two channels, channel C and channel K, can also be time-division multiplexed in a similar manner. Furthermore, the image signals and synchronizing signals of two or more channels of channels Y, M, C, and K may be time-division multiplexed as necessary. For example, when integrating the image signals and synchronizing signals of channels Y, M, and C, the image signals and synchronizing signals may be sampled and time-division multiplexed using a transmission reference clock signal TCLK that is three times the reference clock signal VCLK.

[0094] In addition, in this embodiment, the image signals and synchronization signals of multiple channels are time-division multiplexed using the clock period of the transmission reference clock signal. However, as a modified example, a reference timing for each color may be set separately from the clock period, and the image signals and synchronization signals of multiple channels may be time-division multiplexed using different delay times from the reference timing.

[0095] For example, when integrating image signals and synchronization signals of two channels, channel Y and channel C, the image signal and synchronization signal of channel Y are selected at a first delay time from the reference timing for channel Y, and then the image signal and synchronization signal of channel C are selected at a second delay time from the reference timing for channel C and integrated.

[0096] FIG. 10 shows a timing chart of the modified example.

[0097] 10, timing charts of the combined line synchronization signal LS_0, the combined data enable signal DE_0, and the combined data signal DATA_0 are shown from the top.

[0098] A reference timing signal for channel Y (reference LS(Y)) is inserted into the line synchronization signal, and the line synchronization signal LS_Y of channel Y is selected at a first delay time from this reference timing signal. Next, a reference timing signal for channel M (reference LS(M)) is inserted, and the line synchronization signal LS_M of channel M is selected at a second delay time from this reference timing signal. Also, the data enable signal DE_Y of channel Y is selected at a first delay time from the reference timing signal for channel Y, and then the data enable signal DE_M of channel M is selected at a second delay time from the reference timing signal for channel M.

[0099] Additionally, a data signal DATA_Y of channel Y is selected at a first delay time from the reference timing signal for channel Y, and then a data signal DATA_M of channel M is selected at a second delay time from the reference timing signal for channel M.

[0100] In this way, by time-division multiplexing and integrating the image signals and synchronization signals of multiple channels in the section of the line synchronization signal LS per color and switching the signals of the multiple channels on a line-by-line basis, the number of image processors and video IFs provided for each channel can be reduced. [Explanation of symbols]

[0101] 10 timing generator, 12Y~12K image processor, 14Y~14K video IF, 15YM merging section (channel Y and channel M), 16Y~16K serial converter, 18 transmission path, 20Y~20K deserializer, 21Y, 21M extraction section, 22Y~22K output section.

Claims

1. A receiving means for receiving a synchronization signal and an image signal of each of a plurality of channels; an integration unit that time-division multiplexes and integrates the synchronization signals and the image signals of any two or more of the plurality of channels; a reference timing generating means for superimposing a reference signal, which defines the start of communication, on the synchronization signal integrated by the integration means and outputting the superimposed signal; a serial conversion means for converting the reference signal from the reference timing generation means, the time division multiplexed synchronization signal, and the image signal into serial signals and outputting the serial signals to an image forming means; A signal processing device for image formation comprising:

2. The integrating means operates with a transmission reference clock signal that is multiplied by the number n (n is an integer of 2 or more) of channels to be time-division multiplexed with respect to a reference clock signal that is a reference for generating the synchronization signals of each of the plurality of channels and the image signals. The signal processing device according to claim 1 .

3. The integration means includes: a sampling means for sampling the synchronization signal and the image signal received by the receiving means based on the transmission reference clock signal; a selection control means for determining a transmission timing for each of the channels based on the transmission reference clock signal, and outputting a selection signal for selecting a channel to be transmitted according to the determined timing; a synchronization signal selection means for selecting a synchronization signal of a channel to be time-division multiplexed based on the selection signal from the synchronization signals of the channels sampled by the sampling means; an image signal selection means for selecting an image signal of a channel to be time-division multiplexed based on the selection signal from the image signals of each channel sampled by the sampling means; The signal processing device according to claim 2 , comprising:

4. The synchronization signals include a line synchronization signal, a page synchronization signal, and a data enable signal; the reference signal is superimposed on either the line sync signal or the page sync signal; The signal processing device according to any one of claims 1 to 3.

5. the integrating means integrates the synchronization signals and the image signals of any two or more channels among the plurality of channels by time division multiplexing each of the synchronization signals and the image signals for each line. The signal processing device according to claim 1 .

6. the synchronization signal includes a line synchronization signal; the integrating means integrates line synchronization signals of any two or more channels among the plurality of channels by time division multiplexing the line synchronization signals of the two or more channels using different delay times with respect to the reference signal; The signal processing device according to claim 5 .

7. the synchronization signal includes a data enable signal; the integrating means integrates the data enable signals of any two or more of the plurality of channels by time division multiplexing the data enable signals of the channels using different delay times with respect to the reference signal; The signal processing device according to claim 6.

8. a separation means for receiving the serial signal output from the serial conversion means and separating the serial signal into the time-division multiplexed sync signal and the image signal; an extracting means for extracting a synchronizing signal and an image signal of each channel from the synchronizing signal and the image signal which are time-division multiplexed based on the reference signal; The signal processing device according to any one of claims 1 to 7, further comprising:

9. A signal processing device according to claim 8 ; an image forming means for forming an image on a medium based on the synchronization signal and the image signal of each channel output from the extraction means of the signal processing device; An image forming apparatus comprising:

10. Computer, A receiving means for receiving a synchronization signal and an image signal of each of a plurality of channels; an integration unit that time-division multiplexes and integrates the synchronization signals and the image signals of any two or more of the plurality of channels; a reference timing generating means for superimposing a reference signal that specifies the start time of communication on the synchronization signal integrated by the integration means and outputting the superimposed signal; a serial conversion means for serially converting the reference signal from the reference timing generation means, and the time division multiplexed synchronization signal and image signal, and outputting the serially converted signals to an image forming means; A program for forming images that acts as a

Images