Speculative Execution Using a Page-Level Trace Load Order Queue.

Abstract

Speculative execution using the page-level tracking load order queue includes determining that a first load instruction targets a committed memory region, and, in response to the first load instruction targeting the committed memory region, adding an entry to the page-level tracking load order queue instead of the load order queue, the entry indicating a page address targeted by the first load instruction.

Description

[Background technology]

[0001] During out-of-order execution of instructions, speculatively executed load instructions can be added to a load order queue. When older loads from the same thread complete execution, speculatively executed loads can be removed from the load order queue. When the load order queue becomes full, no further speculative execution is allowed. [Brief description of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an example processor for speculative execution with page-level tracking load order queue in accordance with some embodiments. [Diagram 2] 1 is a flowchart of an example method for speculative execution using a page-level trace load order queue, according to some embodiments. [Diagram 3] 1 is a flowchart of an example method for speculative execution using a page-level trace load order queue, according to some embodiments. [Figure 4] 1 is a flowchart of an example method for speculative execution using a page-level trace load order queue, according to some embodiments. [Diagram 5] 1 is a flowchart of an example method for speculative execution using a page-level trace load order queue, according to some embodiments. [Figure 6] 1 is a flowchart of an example method for speculative execution using a page-level trace load order queue, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] In some embodiments, a method of speculative execution using a page-level tracked load order queue includes determining that a first load instruction targets a committed memory region, and in response to the first load instruction targeting the committed memory region, adding an entry to the page-level tracked load order queue on behalf of the load order queue, the entry indicating a page address targeted by the first load instruction.

[0004] In some embodiments, the method further includes determining that the second load instruction targets the defined memory region, determining that the second load instruction targets a page address specified in the entry, and updating an activity counter of the entry. In some embodiments, the method further includes determining that the second load instruction does not target the defined memory region, and adding an entry to the load order queue based on the second load instruction. In some embodiments, the method further includes determining to remove the entry from the page-level tracking load order queue based on a state of a reorder buffer. In some embodiments, determining to remove the entry from the page-level tracking load order queue based on the state of the reorder buffer includes decrementing an activity counter of the entry based on the state of the reorder buffer, and removing the entry from the page-level tracking load order queue based on the activity counter. In some embodiments, the defined memory region is a program stack, and determining that the load instruction targets the defined memory region includes determining that the first load instruction targets a memory address relative to a stack pointer. In some embodiments, the first load instruction is associated with a first thread, and the method further includes receiving a query from a second thread indicating a store instruction target, and in response to the store instruction target including the page address identified in the entry, initiating a pipeline flush.

[0005] In some embodiments, a load store unit for speculative execution using a page-level tracking load order queue performs steps including: determining that a first load instruction targets a committed memory region; and, in response to the first load instruction targeting the committed memory region, adding an entry to the page-level tracking load order queue in place of the load order queue, the entry indicating a page address targeted by the first load instruction.

[0006] In some embodiments, the steps further include determining that the second load instruction targets the defined memory region, determining that the second load instruction targets a page address specified in the entry, and updating an activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not target the defined memory region, and adding an entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove the entry from the page-level tracking load order queue based on a state of a reorder buffer. In some embodiments, determining to remove the entry from the page-level tracking load order queue based on the state of the reorder buffer includes decrementing an activity counter of the entry based on the state of the reorder buffer, and removing the entry from the page-level tracking load order queue based on the activity counter. In some embodiments, the defined memory region is a program stack, and determining that the load instruction targets the defined memory region includes determining that the first load instruction targets a memory address relative to a stack pointer. In some embodiments, the first load instruction is associated with the first thread, and the above steps further include receiving a query from a second thread indicating a store instruction target, and in response to the store instruction target including the page address specified in the entry, initiating a pipeline flush.

[0007] In some embodiments, a processor for speculative execution using a page-level tracking load order queue includes a load store unit that performs steps including determining that a first load instruction targets a committed memory region, and in response to the first load instruction targeting the committed memory region, adding an entry to the page-level tracking load order queue on behalf of the load order queue, the entry indicating a page address targeted by the first load instruction.

[0008] In some embodiments, the steps further include determining that the second load instruction targets the defined memory region, determining that the second load instruction targets a page address specified in the entry, and updating an activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not target the defined memory region, and adding an entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove the entry from the page-level tracking load order queue based on a state of a reorder buffer. In some embodiments, determining to remove the entry from the page-level tracking load order queue based on the state of the reorder buffer includes decrementing an activity counter of the entry based on the state of the reorder buffer, and removing the entry from the page-level tracking load order queue based on the activity counter. In some embodiments, the defined memory region is a program stack, and determining that the load instruction targets the defined memory region includes determining that the first load instruction targets a memory address relative to a stack pointer. In some embodiments, the first load instruction is associated with the first thread, and the above steps further include receiving a query from a second thread indicating a store instruction target, and in response to the store instruction target including the page address specified in the entry, initiating a pipeline flush.

[0009] In some embodiments, an apparatus for speculative execution using a page-level tracking load order queue includes a processor including a load store unit that performs steps including: determining that a first load instruction targets a committed memory region; and in response to the first load instruction targeting the committed memory region, adding an entry to the page-level tracking load order queue on behalf of the load order queue, the entry indicating a page address of a target of the first load instruction.

[0010] In some embodiments, the steps further include determining that the second load instruction targets the defined memory region, determining that the second load instruction targets a page address specified in the entry, and updating an activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not target the defined memory region, and adding an entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove the entry from the page-level tracking load order queue based on a state of a reorder buffer. In some embodiments, determining to remove the entry from the page-level tracking load order queue based on the state of the reorder buffer includes decrementing an activity counter of the entry based on the state of the reorder buffer, and removing the entry from the page-level tracking load order queue based on the activity counter. In some embodiments, the defined memory region is a program stack, and determining that the load instruction targets the defined memory region includes determining that the first load instruction targets a memory address relative to a stack pointer. In some embodiments, the first load instruction is associated with the first thread, and the above steps further include receiving a query from a second thread indicating a store instruction target, and in response to the store instruction target including the page address specified in the entry, initiating a pipeline flush.

[0011] 1 is a block diagram of a non-limiting exemplary processor 100 according to some embodiments. The exemplary processor 100 may be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, etc. The processor 100 includes a load store unit 102. The load store unit 102 is a dedicated execution unit (e.g., a combination of logic and / or circuitry) responsible for executing load and store instructions, generating virtual addresses for the load and store operations, loading data from memory, and / or storing data from registers to memory.

[0012] Processor 100 executes some instructions out of order to improve performance. Thus, load store unit 102 speculatively executes load instructions out of order relative to other instructions. To do so, load store unit 102 maintains load order queue 104. Load order queue 104 is a data structure that stores speculatively executed load instructions in each entry. When all older loads related to speculatively executed loads in an entry of load order queue 104 have committed, the entry may be removed from the load order queue.

[0013] Load store unit 102 may receive a query from another thread (e.g., from another processor or core via coherency interface 105) indicating a memory address being accessed (e.g., written to) by the other thread. If the memory address matches an entry in load order queue 104, an order violation has occurred because a speculatively executed load may be incorrect. Thus, the execution pipeline must be flushed.

[0014] In existing solutions, all speculatively executed load instructions are added to a load order queue 104 or a similar data structure (e.g., load store queue, load queue, etc.). When the load order queue 104 becomes full, additional load instructions cannot be speculatively executed, resulting in reduced performance. In contrast, the load store unit 102 of the processor 100 for speculative execution using a page-level trace load order queue determines whether a load instruction (e.g., a speculatively executed load instruction) targets a committed memory region. The committed memory region may include the program stack. Thus, the load store unit 102 determines whether the load instruction targets a memory address relative to a stack pointer stored in a stack register 106. For example, the instruction "mov regX, [rsp+offset]" targets the program stack (a committed memory region) because the memory address where data is loaded is calculated by adding an offset to the stack pointer in the stack register 106 (identified as "rsp" in the instruction). On the other hand, the instruction "regX, [regBase+regIndex+offset]" does not target a defined memory area since the memory address where the data is loaded is independent of the stack pointer.

[0015] Load instructions targeting the program stack are faster than other load instructions because most of them hit the data cache 108. In many program scenarios (e.g., highly looped or repetitive code), load instructions targeting the program stack will disproportionately outnumber other load instructions and thus will be disproportionately loaded into the load order queue 104, filling it up and stalling further speculative execution.

[0016] In response to a load instruction targeting a committed memory region, the load store unit 102 adds an entry to the page-level tracking load order queue 110 instead of the load order queue 104. The entry indicates a page address targeted by the load instruction (e.g., a page address of a storage location in the committed memory region). The page size indicated in the entry depends on the minimum page size of the operating system being executed. Thus, in an operating system that implements a minimum page size of 4 kilobytes, each entry indicates a page address of a 4 kilobyte page in the committed memory region.

[0017] Each entry in the page-level tracking load order queue 110 also includes an activity counter that indicates how recently each entry has had a load instruction that targets the page of that entry speculatively executed. For example, the activity counter may include multiple bits (e.g., 2 bits) that are initially all set to "1". As described below, as additional instructions are executed and / or committed, the activity counter may shift one bit to the right. For example, a 2-bit activity counter that is set to "11" will be shifted to "01". The activity counter may later be set to "00" to indicate that the entry may be removed from the page-level tracking load order queue 110.

[0018] Assuming that an entry for a first load instruction is stored in the page-level tracking load order queue 110, the load store unit 102 can determine that a second load instruction targets the committed memory region. If the second load instruction targets the page address identified in the entry, the load store unit 102 updates the activity counter of the entry. For example, if the activity counter of the entry is set to "01", the activity counter is updated to "11". As another example, if the activity counter of the entry is set to "11", the activity counter remains at "11". Thus, instead of adding a new entry to the page-level tracking load order queue 110 for the second load instruction, the activity counter is updated. This allows multiple load instructions speculatively executed targeting the same page address of the committed memory region to be reflected by one entry in the page-level tracking load order queue 110. Thus, this provides a more efficient memory usage method compared to existing solutions in which every load instruction is reflected by a corresponding entry in the load order queue 104 or an equivalent data structure, respectively. If the second load instruction instead targets a page address that is not included in an entry in the page-level tracking load order queue 110, a new entry is created in the page-level tracking load order queue for the second load instruction.

[0019] Load store unit 102 may also determine that the received speculatively executed load instruction does not target a committed memory region. In that case, load store unit 102 adds an entry to load order queue 104 based on the second load instruction. In other words, a speculatively executed load instruction that does not target a committed memory region causes an entry to be added to load order queue 104, while a speculatively executed load instruction that does target a committed memory region causes an entry to be added or updated in page-level tracking load order queue 110.

[0020] Assume that an entry for a first load instruction is stored in page-level tracking load order queue 110, and the first load instruction is associated with a first thread (e.g., executed by processor 100). Load store unit 102 receives a query (e.g., via coherency interface 105) from a second thread (e.g., executed by another processor or core) indicating a store instruction target. If the store instruction target includes a page address of an entry in page-level tracking load order queue 110, the store instruction target indicates that an order violation has occurred. Thus, the execution pipeline is flushed.

[0021] Load-store unit 102 determines to remove an entry from page-level track load order queue 110 based on the state of reorder buffer 112. Reorder buffer 112 stores speculatively executed instructions and their results for "commitment" to program order. For example, load-store unit 102 decrements (e.g., shifts) an activity counter of each entry in page-level track load order queue 110 for each buffer commitment cycle of reorder buffer 112. A buffer commitment cycle is when reorder buffer 112 commits a number of instructions equal to the number of entries in reorder buffer 112. For example, assuming reorder buffer 112 has 100 entries, a buffer commit cycle occurs every time 100 instructions are committed. When an entry's activity counter reaches "00" or another committed state, the entry may be removed from the page-level track load order queue.

[0022] For further explanation, FIG. 2 shows a flow chart illustrating an example method for speculative execution using a page-level track load order queue according to an embodiment of the present disclosure, the method including determining (202) (e.g., by load store unit 102) that a first load instruction 204 (e.g., a speculatively executed load instruction) targets a defined memory region. The defined memory region may include a program stack. Thus, determining (202) includes determining that the first load instruction 204 targets a memory address relative to a stack pointer stored in stack register 106. For example, the instruction "mov regX, [rsp+offset]" targets the program stack (defined memory region) because the memory address where data is loaded is calculated by adding an offset to the stack pointer in stack register 106 (identified in the instruction as "rsp"). On the other hand, the instruction "mov regX,[regBase+regIndex+offset]" does not target a defined memory area since the memory address where the data is loaded is independent of the stack pointer.

[0023] 2 also includes adding (206) an entry 208 (e.g., by the load store unit 102) to the page-level tracking load order queue 110 on behalf of the load order queue 104 in response to the first load instruction 204 targeting the committed memory region, where the entry 208 indicates a page address (e.g., a page address of a storage location in the committed memory region) targeted by the first load instruction 204. The page size indicated in the entry is determined by the minimum page size of the executing operating system. Thus, for an operating system that implements a minimum page size of 4 kilobytes, each entry 208 indicates a page address of a 4 kilobyte one of the pages in the committed memory region.

[0024] The entries 208 of the page-level tracking load order queue 110 also include an activity counter that indicates the recency of each entry in which a load instruction targeting the page of that entry 208 was speculatively executed. For example, the activity counter may include multiple bits (e.g., 2 bits) that are initially all set to "1". As additional instructions are executed and / or committed, the activity counter may shift one bit to the right. For example, a 2-bit activity counter that was set to "11" would be shifted to "01". The activity counter may later be set to "00" to indicate that the entry may be removed from the page-level tracking load order queue 110.

[0025] For further explanation, FIG. 2 shows a flowchart illustrating an example method for speculative execution using a page-level tracking load order queue in accordance with an embodiment of the present disclosure, the method including determining (202) (e.g., by the load-store unit 102) that a first load instruction 204 (e.g., a speculatively executed load instruction) targets a determined memory region, and, in response to the first load instruction 204 targeting the determined memory region, adding (206) (e.g., by the load-store unit 102) an entry 208 to the page-level tracking load order queue 110 on behalf of the load order queue 104, where the entry 208 indicates a target page address of the first load instruction 204.

[0026] The method of FIG. 3 differs from the method of FIG. 2 in that the method of FIG. 3 includes determining (302) (e.g., by the load store unit 102) that the second load instruction 304 targets a defined memory region (e.g., the program stack pointed to by the stack pointer in the stack register 106). The method of FIG. 3 differs from the method of FIG. 2 in that the method of FIG. 3 includes determining (306) that the second load instruction 304 targets a page address identified in an entry 208. For example, the load store unit 102 determines whether the page address targeted by the second load instruction 304 "hits" or matches an entry 208 in the page-level tracking load order queue 110. The method of FIG. 3 differs from the method of FIG. 2 in that the method of FIG. 3 includes updating (308) an activity counter of the entry 208 (e.g., by the load store unit 102).

[0027] For example, if the activity counter of entry 208 is set to "01", the activity counter is updated to "11". As another example, if the activity counter of entry 208 is set to "11", the activity counter remains at "11". Thus, instead of a new entry being added to page-level tracking load order queue 110 for second load instruction 304, the activity counter is updated. This allows multiple speculatively executed load instructions targeting the same page address of a committed memory region to be reflected by a single entry 208 in page-level tracking load order queue 110.

[0028] For further explanation, FIG. 4 shows a flowchart illustrating an example method for speculative execution using the page-level tracking load order queue 110 in accordance with an embodiment of the present disclosure, the method including determining (202) (e.g., by the load-store unit 102) that a first load instruction 204 (e.g., a speculatively executed load instruction) targets a determined memory region, and, in response to the first load instruction 204 targeting the determined memory region, adding (206) (e.g., by the load-store unit 102) an entry 208 to the page-level tracking load order queue 110 on behalf of the load order queue 104, where the entry 208 indicates a target page address of the first load instruction 204.

[0029] The method of Figure 4 differs from the method of Figure 2 in that the method of Figure 4 includes determining (402) (e.g., by load store unit 102) that the second load instruction 404 does not target a defined memory region (e.g., the program stack pointed to by a stack pointer in stack register 106). The method of Figure 4 differs from the method of Figure 2 in that the method of Figure 4 includes adding (406) an entry 408 to load order queue 104 based on the second load instruction 404. In other words, speculatively executed load instructions that do not target a defined memory region add an entry to load order queue 104, while speculatively executed load instructions that do target a defined memory region add or update an entry to page-level tracking load order queue 110.

[0030] For further explanation, FIG. 5 shows a flowchart illustrating an example method for speculative execution using the page-level tracking load order queue 110 in accordance with an embodiment of the present disclosure, the method including determining (202) (e.g., by the load-store unit 102) that a first load instruction 204 (e.g., a speculatively executed load instruction) targets a committed memory region, and, in response to the first load instruction 204 targeting the committed memory region, adding (206) an entry 208 to the page-level tracking load order queue 110 on behalf of the load order queue 104, where the entry 208 indicates a page address targeted by the first load instruction 204.

[0031] The method of FIG. 5 differs from the method of FIG. 2 in that the method of FIG. 5 includes determining (e.g., by load store unit 102) to remove an entry from page-level track load order queue 110 based on a state of reorder buffer 112 (502). Reorder buffer 112 stores speculatively executed instructions and their results for "commitment" to program order. For example, load store unit 102 decrements (e.g., shifts) an activity counter for each entry in page-level track load order queue 110 for each buffer commitment cycle of reorder buffer 112. A buffer commitment cycle is when reorder buffer 112 commits a number of instructions equal to the number of entries in reorder buffer 112. For example, assuming reorder buffer 112 has 100 entries, a buffer commit cycle occurs every time 100 instructions are committed. When an entry's activity counter reaches "00" or another committed state, the entry may be removed from the page-level track load order queue. Thus, determining 502 an entry 208 based on the state of the reorder buffer 112 includes decrementing an activity counter for the entry 208 based on the state of the reorder buffer 112 (e.g., buffer commitment cycles) and removing the entry 208 from the page-level tracking load order queue 110 based on the activity counter.

[0032] For further explanation, FIG. 6 shows a flowchart illustrating an example method for speculative execution using the page-level tracking load order queue 110 in accordance with an embodiment of the present disclosure, the method including determining (202) (e.g., by the load-store unit 102) that a first load instruction 204 (e.g., a speculatively executed load instruction) targets a determined memory region, and, in response to the first load instruction 204 targeting the determined memory region, adding (206) (e.g., by the load-store unit 102) an entry 208 to the page-level tracking load order queue 110 on behalf of the load order queue 104, where the entry 208 indicates a target page address of the first load instruction 204.

[0033] The method of FIG. 6 differs from the method of FIG. 2 in that the method of FIG. 6 includes receiving (602) a query (e.g., via coherency interface 105) from a second thread (e.g., executed by another processor or core) indicating a store instruction target. The query corresponds to another executed or speculatively executed instruction that stores data (e.g., a memory address) of the store instruction target. The method of FIG. 6 differs from the method of FIG. 2 in that the method of FIG. 6 includes initiating (606) a pipeline flush in response to the store instruction target including a page address identified in entry 208. For example, the load store unit may determine whether a page address included in the store instruction target matches a page address of the entry. Thus, an order violation occurs and the execution pipeline is flushed.

[0034] In view of the above discussion, the reader will recognize that the advantages of speculative execution using a page-level trace load order queue, according to embodiments of the present disclosure, are as follows: Improves computing system performance by improving the storage efficiency of queued speculatively executed load instructions by allowing multiple loads targeting the same page of a defined memory region to be represented by a single entry. Improves the performance of a computing system by providing more efficient space usage in the load order queue and reducing the likelihood that the load order queue will become full with load instructions targeting committed memory regions, thereby preventing speculative execution stalls.

[0035] Exemplary embodiments of the present disclosure are described primarily in the context of a fully functional computer system for speculative execution with a page-level tracking load order queue. However, the skilled reader will recognize that the present disclosure may also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others that may occur to one skilled in the art. One skilled in the art will immediately recognize that any computer system with suitable programming means is capable of executing the steps of the method of the present disclosure embodied in a computer program product. One skilled in the art will also recognize that, although some of the exemplary embodiments described herein are adapted to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0036] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium(s) having computer-readable program instructions thereon for causing a processor to execute aspects of the present disclosure.

[0037] A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of computer-readable storage media include, but are not limited to, portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridges in grooves with instructions recorded thereon, and any suitable combinations of the above. As used herein, a computer-readable storage medium should not be interpreted as a transitory signal itself, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0038] The computer readable program instructions described herein can be downloaded from a computer readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface of each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0039] The computer readable program instructions for carrying out the operations of the present disclosure may be either assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk, C++, and the like, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may run entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to implement aspects of the present disclosure.

[0040] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0041] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to generate a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored on a computer readable storage medium that has instructions stored therein that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such as including an article of manufacture that includes instructions that implement aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0042] Furthermore, computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device to execute a series of operational steps on the computer, other programmable data processing apparatus, or other device to create a computer-implemented process such that the instructions executing on the computer, other programmable data processing apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0043] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that executes the specified functions or operations, or a combination of special-purpose hardware and computer instructions.

[0044] From the foregoing description, it will be understood that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. A load store unit for speculative execution using a page level trace load order queue, comprising: determining that the first load instruction targets a defined memory region; adding an entry to the page-level tracking load order queue in place of a load order queue in response to the first load instruction targeting the determined memory region, the entry indicating a page address targeted by the first load instruction; configured to perform the steps including: Load store unit.

2. The load store unit includes: determining that a second load instruction targets the determined memory region; determining that the second load instruction is targeted to the page address identified in the entry; updating an activity counter for said entry; configured to perform the steps including: The load store unit of claim 1 .

3. The load store unit includes: determining that a second load instruction does not target the determined memory region; adding an entry to the load order queue based on the second load instruction; configured to perform the steps including: The load store unit of claim 1 .

4. the load store unit is configured to perform steps including determining to remove the entry from the page-level tracking load order queue based on a state of a reorder buffer. The load store unit of claim 1 .

5. determining to remove the entry from the page-level trace load order queue based on a state of the reorder buffer includes: decrementing an activity counter of the entry based on a state of the reorder buffer; and removing the entry from the page-level tracking load order queue based on the activity counter. The load store unit of claim 4.

6. the determined memory area includes a program stack, and determining that the load instruction targets the determined memory area includes determining that the first load instruction targets a memory address relative to a stack pointer. The load store unit of claim 1 .

7. the first load instruction is associated with a first thread; The load store unit includes: receiving a query indicating a store instruction target from a second thread; Initiating a pipeline flush in response to the store instruction target including the page address identified in the entry; configured to perform the steps including: The load store unit of claim 1 .

8. 1. A processor for speculative execution using a page-level trace load order queue, comprising: determining that the first load instruction targets a defined memory region; adding an entry to the page-level tracking load order queue in place of a load order queue in response to the first load instruction targeting the determined memory region, the entry indicating a page address targeted by the first load instruction; a load store unit configured to perform steps including: Processor.

9. The processor, determining that a second load instruction targets the determined memory region; determining that the second load instruction is targeted to the page address identified in the entry; updating an activity counter for said entry; configured to perform the steps including: The processor of claim 8.

10. The processor, determining that a second load instruction does not target the determined memory region; adding an entry to the load order queue based on the second load instruction; configured to perform the steps including: The processor of claim 8.

11. The processor is configured to perform steps including determining to remove the entry from the page-level trace load order queue based on a state of a reorder buffer. The processor of claim 8.

12. determining to remove the entry from the page-level trace load order queue based on a state of the reorder buffer includes: decrementing an activity counter of the entry based on a state of the reorder buffer; and removing the entry from the page-level tracking load order queue based on the activity counter. The processor of claim 11.

13. the determined memory area includes a program stack, and determining that the load instruction targets the determined memory area includes determining that the first load instruction targets a memory address relative to a stack pointer. The processor of claim 8.

14. the first load instruction is associated with a first thread; The processor, receiving a query indicating a store instruction target from a second thread; Initiating a pipeline flush in response to the store instruction target including the page address identified in the entry; configured to perform the steps including: The processor of claim 8.

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