Shadow ring kit for plasma etched wafer singulation process.

Abstract

A shadow ring kit and a method for dicing a semiconductor wafer are described. In one embodiment, an etching apparatus includes a chamber and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber, the electrostatic chuck including a conductive pedestal for supporting a substrate carrier sized to support a wafer having a first diameter. A shadow ring assembly is between the plasma source and the electrostatic chuck, the shadow ring assembly being sized to process a wafer having a second diameter smaller than the first diameter.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Non-provisional Application No. 17 / 064,470, filed October 6, 2020, the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of semiconductor processing, and more particularly to an apparatus and method for dicing semiconductor wafers, each wafer having multiple integrated circuits thereon. [Background technology]

[0003] Semiconductor wafer processing involves the creation of integrated circuits on wafers (also called substrates) composed of silicon or other semiconducting materials. Typically, layers of various materials that can be semiconductive, conductive, or insulating are utilized to create the integrated circuits. These materials are doped, deposited, and etched using various well-known processes to create the integrated circuits. Each wafer is processed to create many individual areas that contain the integrated circuits, called dice.

[0004] After the integrated circuit formation process, the wafer is "diced" to separate the individual dies from one another for packaging or for use in unpackaged form within a larger circuit. The two main techniques used in wafer dicing are scribing and sawing. In scribing, a diamond-tipped scribe is moved across the wafer surface along pre-formed scribe lines. The scribe lines extend along the spaces between the dies, commonly referred to as "streets." The diamond scribe creates shallow scratches in the wafer surface along the streets.

[0005] When pressure is applied, such as with a roller, the wafer is separated along the scribe lines, with the cracks following the crystal lattice structure of the wafer's substrate. Scribing can be used for wafers up to about 10 mils (thousandths of an inch) thick. For thicker wafers, sawing is now the preferred method for dicing.

[0006] In sawing, a diamond-tipped saw rotating at high RPM is brought into contact with the wafer surface and the wafer is sawed along the streets. The wafer is mounted on a support, such as an adhesive film stretched over a film frame, and the saw is run repeatedly across both the vertical and horizontal streets. A problem with both scribing and sawing is that chips and grooves can form along the cut edges of the die. Additionally, cracks can form and propagate from the edge of the die into the substrate, rendering the integrated circuit inoperable.

[0007] In particular, scribing requires that only one side of a square or rectangular die is etched. <110> Since scribing cannot be done in any direction, chipping and cracking become an issue.

[0008] As a result, when the die is broken on the other side, the separation line is jagged. Due to the chips and cracks, additional spacing is required between the die on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are kept away from the actual integrated circuits. Due to this spacing requirement, fewer dice can be formed on a standard size wafer, wasting wafer area that could be used for circuits. The use of saws further exacerbates the waste of semiconductor wafer area. The thickness of a saw blade is about 15 to 60 microns. Therefore, the circuitry of each die must often be separated by 60 microns to around 300-500 microns to prevent cracks and other damage around the cut made by the saw from adversely affecting the integrated circuits.

[0009] Additionally, after sawing, each die requires extensive cleaning to remove particles and other contaminants from the sawing process.

[0010] Plasma dicing has also been used but may have limitations as well. For example, one limitation that may prevent the implementation of plasma dicing may be cost. Standard lithography steps for patterning resist may be costly to implement. Another limitation that may prevent the implementation of plasma dicing is that plasma etching of metals (e.g., copper) commonly encountered in dicing along streets may cause production issues or throughput limitations. Summary of the Invention

[0011] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure include a method and apparatus for dicing a semiconductor wafer.

[0012] In an embodiment, an etching apparatus includes a chamber and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber, the electrostatic chuck including a conductive pedestal for supporting a substrate carrier sized to support a wafer having a first diameter. A shadow ring assembly is between the plasma source and the electrostatic chuck, the shadow ring assembly sized to process a wafer having a second diameter smaller than the first diameter.

[0013] In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask over the semiconductor wafer, the mask being or including a layer covering and protecting the integrated circuits, the semiconductor wafer being supported by a substrate carrier sized to support a wafer having a first diameter. The method also includes patterning the mask with a laser scribing process to provide a patterned mask having gaps that expose areas of the semiconductor wafer between the integrated circuits. The method also includes etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits while the semiconductor wafer is supported by the substrate carrier and while the substrate carrier is partially covered by a shadow ring assembly sized to process a semiconductor wafer having a second diameter smaller than the first diameter.

[0014] In another embodiment, a system for dicing a semiconductor wafer having a plurality of integrated circuits includes a factory interface. A laser scribe apparatus is coupled to the factory interface and includes a laser. An etching apparatus is coupled to the factory interface, the etching apparatus including a chamber, a plasma source within or coupled to the chamber, an electrostatic chuck within the chamber, the electrostatic chuck including a conductive pedestal for supporting a substrate carrier sized to support a wafer having a first diameter, and a shadow ring assembly between the plasma source and the electrostatic chuck, the shadow ring assembly sized to process a wafer having a second diameter smaller than the first diameter. [Brief description of the drawings]

[0015] [Figure 1A] FIG. 1 is a perspective view illustrating components of a shadow ring kit according to an embodiment of the present disclosure. [Figure 1B] 1A-1C are cross-sectional views of a chuck including a shadow ring kit in a raised position and a seated position, and a perspective view of a substrate carrier according to an embodiment of the present disclosure. [Figure 1C]1A and 1B are perspective and cross-sectional views of a chuck including a shadow ring kit according to an embodiment of the present disclosure, and a cross-sectional view of the shadow ring kit. [Figure 1D] FIG. 1 illustrates a cross-sectional view of a portion of a shadow ring assembly for housing a 200 mm wafer according to an embodiment of the present disclosure. [Figure 1E] FIG. 1 illustrates a cross-sectional view of a portion of a shadow ring assembly for housing a 200 mm wafer according to an embodiment of the present disclosure. [Figure 1F] FIG. 1 is a perspective view of an assembly including a lift hoop assembly and a supported shadow ring assembly according to an embodiment of the present disclosure. [Figure 2A] FIG. 1 is a perspective cross-sectional view of an electrostatic chuck according to an embodiment of the present disclosure. [Figure 2B] FIG. 2 illustrates a plan view of a substrate carrier suitable for supporting thin wafers during a singulation process according to an embodiment of the present disclosure. [Figure 2C] FIG. 1 is a perspective view illustrating various aspects and portions of an electrostatic chuck according to an embodiment of the present disclosure. [Figure 3A] FIG. 2 is a plan view illustrating various aspects and portions of an electrostatic chuck according to an embodiment of the present disclosure. [Figure 3B] 1A-1C are cross-sectional views illustrating various aspects and portions of an electrostatic chuck according to embodiments of the present disclosure. [Figure 3C] FIG. 1 is a perspective view illustrating various aspects and portions of an electrostatic chuck according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a cross-sectional view illustrating a plasma etching apparatus according to an embodiment of the present disclosure. [Diagram 5] FIG. 1 is a block diagram illustrating a tool layout for laser and plasma dicing of a wafer or substrate according to an embodiment of the present disclosure. [Figure 6] 1A-1C are cross-sectional views illustrating various steps of a method for dicing a semiconductor wafer according to an embodiment of the present disclosure. [Figure 7] 1 is a cross-sectional view illustrating a stack of materials that may be used in the street region of a semiconductor wafer or substrate according to an embodiment of the present disclosure. [Figure 8A-B] 1A-1D are cross-sectional views illustrating various steps in a method for dicing a semiconductor wafer according to an embodiment of the present disclosure. [Figure 8C-D] 1A-1D are cross-sectional views illustrating various steps in a method for dicing a semiconductor wafer according to an embodiment of the present disclosure. [Figure 9] FIG. 1 is a block diagram illustrating an exemplary computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] A method for dicing a semiconductor wafer and an apparatus therefor are described. In the following description, numerous specific details are set forth, such as electrostatic chuck configurations, laser scribing conditions, and plasma etching conditions and material regimes, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one of ordinary skill in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, have not been described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0017] One or more embodiments are particularly directed to a shadow ring kit for 200 mm wafer plasma dicing. The embodiments may be suitable for plasma dicing using a shadow ring kit for processing 200 mm wafers in a 300 mm etch chamber. The embodiments are applicable to laser and etch wafer dicing approaches and tooling for electronic device wafer singulation or dicing.

[0018] To provide context, currently, 200 mm wafers are processed using a 200 mm wafer mount tape frame with a 200 mm etch chamber. The embodiments described herein can be implemented to mount the 200 mm wafer on an approximately 400 mm wafer mount frame and process the 200 mm wafer using a 300 mm etch plasma dicing chamber. Additionally, the shadow ring kits described herein can be customized to accommodate wafers of different thicknesses for further process enhancement and yield improvement.

[0019] One or more embodiments are directed to a shadow ring process kit design that can process 200 mm wafers mounted on a tape frame sized to support a 300 mm wafer using a 300 mm etch plasma dicing chamber. The embodiments described herein can be implemented to enable processing of 200 mm wafers in a 300 mm plasma dicing etch chamber. The embodiments described herein can be implemented to reduce cost and footprint by not requiring a dedicated 200 mm etch chamber. The embodiments described herein can be implemented to provide flexibility to use a "standard 400 mm tape frame" for both 200 mm and 300 mm wafer dicing and / or processing. In the embodiments, switching between 300 mm and 200 mm wafers in processing is facilitated with minimal setup changes and tool downtime.

[0020] More specifically, in singulating a wafer into individual dies, the wafer is cut or sectioned along the dicing streets between the dies. Traditionally, dicing has been done with a mechanical saw. Mobile devices and other technology operators may require more advanced singulation approaches to reduce crack, delamination, and chip defects. A laser and etch wafer dicing approach may involve applying a water-soluble protective coating to the substrate and removing all device test layers in the laser scribed removed street areas to expose the underlying substrate material, typically silicon (Si). The exposed Si is then plasma etched through its entire thickness to singulate the wafer into individual dies. The protective coating is removed with a deionized water (DI) based cleaning process. A water-soluble protective coating may be desirable for environmental considerations and ease of processing.

[0021] Such a water-soluble coating can be used primarily as an etch mask during the plasma etching step and also as a layer to collect any debris generated during laser scribing.

[0022] To further elaborate, femtosecond lasers may be preferred for the laser scribing portion of the process. Unlike nanosecond and other long pulse lasers, femtosecond lasers have little thermal effects due to the associated ultrashort pulses. Another advantage of femtosecond lasers may be their ability to remove most materials, including absorbing, reflective, and transparent materials. In a typical wafer, there is a metal that is reflective and absorbing, a transparent dielectric, and a silicon substrate that absorbs most of the laser light. Water-soluble protective coatings may be totally or mostly transparent, or may be partially absorbing, for example, if they contain dye additives. These materials described are ablatable with femtosecond lasers. While many of the embodiments described below relate to femtosecond laser scribing, it should be understood that in other embodiments, laser scribing with other laser beam types may also be compatible with the masking materials described herein. Also, while many of the embodiments described below relate to scribing streets with metallized features, it should be understood that in other embodiments, scribing streets without metal may also be considered. It should also be understood that while many of the embodiments described below relate to a water soluble dicing mask, other mask materials are contemplated in other embodiments.

[0023] According to one or more embodiments of the present disclosure, a 300 mm wafer mount frame is used to mount and process 200 mm wafers in an existing 300 mm etch plasma dicing chamber. An embodiment may be implemented to allow for switching between 200 mm and 300 mm wafers with minimal setup time. In an embodiment, a shadow ring kit includes a carrier, an insert ring, and a heat shield. A shadow ring kit as described herein may be used to help prevent tape heating and burning during the etch process. The insert ring may function as an independent "floating" part without touching the carrier and heat shield during wafer processing (e.g., by being supported by the outermost portion of the wafer or substrate being processed). This arrangement may prevent heat transfer from the wafer to the carrier. The heat shield may help prevent heat transfer to the carrier during processing. In an embodiment, the profile of the insert ring and heat shield excludes the edge on the wafer during the etch process.

[0024] As an example assembly, FIG. 1A illustrates a perspective view of components of a shadow ring kit 100 according to an embodiment of the present disclosure.

[0025] 1A, the shadow ring kit includes a heat shield 102, an insert ring 104, and a carrier 106. In an embodiment, the heat shield 102, the insert ring 104, and the carrier 106 are all constructed of solid alumina. In an embodiment, the heat shield 102 includes a pocket therein for receiving the insert ring 104 without contacting the insert ring 104, e.g., to avoid thermal contact. In an embodiment, the insert ring 104 is sized to receive a 200 mm wafer. In one embodiment as described above, the insert ring 104 has an inner opening having a diameter of about 197 mm such that about 1.5 mm of the outermost periphery of the 200 mm wafer remains covered by the insert ring 104. In one embodiment as described above, the insert ring 104 rests on about the 1.5 mm periphery of the 200 mm wafer covered by the insert ring 104.

[0026] FIG. 1B illustrates a cross-sectional view of a chuck including a shadow ring kit in a raised position and a seated position, and a perspective view of a substrate carrier according to an embodiment of the present disclosure.

[0027] Referring to portion (i) of FIG. 1B, the chuck assembly 110A includes a shadow ring kit 112 in a raised position. In one embodiment, the shadow ring kit 112 is an assembly such as the shadow ring kit 100 described above. The shadow ring kit 100 rests on a substrate carrier assembly 114, which may include a tape frame supporting a 200 mm wafer. The substrate carrier assembly 114 is supported by an electrostatic chuck (ESC), such as an ESC, typically sized to support a 300 mm wafer or a substrate carrier for 300 mm wafers. The chuck assembly 110A also includes a lift hoop assembly 118. Referring to portion (ii) of FIG. 1B, the chuck assembly 110B includes the shadow ring kit 112 in a seated position. Referring to both portions (i) and (ii) of FIG. 1B, nail head lift pins 119 are included to lift up and down between positions 110A and 110B.

[0028] Referring to portion (iii) of FIG. 1B, an exemplary substrate carrier assembly 114 is shown including a wafer tape frame 114A (which may be sized to accommodate a 300 mm wafer), a dicing tape 114B, and a 200 mm wafer (e.g., in a position where a 300 mm wafer would typically sit).

[0029] FIG. 1C illustrates a perspective view 120 and a cross-sectional view 122 of a chuck including a shadow ring kit according to an embodiment of the present disclosure, as well as a cross-sectional view of the shadow ring kit.

[0030] 1C , the electrostatic chuck assembly 122 includes an electrostatic chuck (ESC) 121. A shadow ring assembly is located above the ESC 121 of the electrostatic chuck assembly 122. The shadow ring assembly includes a heat shield 102, an insert ring 104, and a carrier 106. In an embodiment, when in position for processing, the insert ring 104 is received within a pocket of the heat shield 102 without contacting the heat shield 102, as shown. In an embodiment, the insert ring 104 couples with the carrier 106, as shown.

[0031] In a first example, FIG. 1D is a cross-sectional view of a portion of a shadow ring assembly for housing a 200 mm wafer according to an embodiment of the present disclosure.

[0032] 1D, the shadow ring assembly 130A includes a heat shield 102A, an insert ring 104A, and a carrier 106A. In an embodiment, when in position for processing, the insert ring 104A is received within a pocket of the heat shield 102A without contacting the heat shield 102A, as shown. In one embodiment, the insert ring 104A couples with the carrier 106A, as shown.

[0033] In a second example, FIG. 1E is a cross-sectional view of a portion of a shadow ring assembly for housing a 200 mm wafer according to an embodiment of the present disclosure.

[0034] 1E, the shadow ring assembly 130B includes a heat shield 102B, an insert ring 104B, and a carrier 106B. In an embodiment, when in position for processing, the insert ring 104B is received in a pocket of the heat shield 102B without contacting the heat shield 102B as shown. In one embodiment, the insert ring 104B couples with the carrier 106B as shown. Compared to the carrier 106A of the shadow ring assembly 130A, the shape of the carrier 106B of the shadow ring assembly 130B provides a larger gap between the carrier 106B and the dicing tape of the substrate carrier, which may help avoid tape sticking issues.

[0035] As an example of a support and / or movement mechanism, FIG. IF is a perspective view showing an assembly 140 including a lift hoop assembly and a supported shadow ring assembly according to an embodiment of the present disclosure.

[0036] 1F, the lift hoop assembly 142 includes a lift hoop 144, lift pins 146, and a servo motor 148. The supported shadow ring assembly includes the heat shield 102, the insert ring (not visible in this view), and the carrier 106, as described in connection with FIG. 1A.

[0037] In another aspect, Figure 2A is a perspective cross-sectional view of an electrostatic chuck according to an embodiment of the present disclosure, which may be mated with a shadow ring assembly as described in connection with Figures 1A, 1D, and 1E.

[0038] 2A, an electrostatic chuck assembly 200 includes a shadow ring or heat shield 202, an associated shadow ring insert 204, and a shadow ring carrier 206. It should be understood that the illustrated shadow ring or heat shield 202, associated shadow ring insert 204, and shadow ring carrier 206 are sized to accommodate 300 mm wafer processing. However, in other embodiments, the shadow ring or heat shield 102, associated shadow ring insert 104, and shadow ring carrier 106 as described in FIG. 1A are instead included to accommodate 200 mm wafer processing. In one embodiment, the shadow ring or heat shield 202, shadow ring insert 204, and shadow ring carrier 206 are all constructed of a ceramic material, such as alumina. As shown in FIG. 2A, a substrate on a substrate carrier may be included below the shadow ring, and a tape frame 208 of the substrate carrier may be included below the heat shield. The tape frame 208 may be constructed of stainless steel. Adjustable lift pins 207 for lifting the shadow ring are included and may be constructed of aluminum.

[0039] The electrostatic chuck assembly 200 further includes an edge insulator ring 210 around the conductive pedestal 212. Below the conductive pedestal 212 is a bottom insulator ring 218. The edge insulator ring 210 and the bottom insulator ring 218 may be constructed of a ceramic material such as alumina, and the conductive pedestal 212 may be constructed of aluminum. The conductive pedestal 212 may be electrically coupled to ground and / or a DC voltage.

[0040] The electrostatic chuck assembly 200 further includes a plasma screen segment 214 and a plasma screen basket 216, both of which may be constructed of aluminum. The electrostatic chuck assembly 200 further includes a cathode insulator 220, a facility insulator 222, and a cathode liner 224. The cathode insulator 220 may be constructed of silicon dioxide, and the cathode liner 224 may be constructed of aluminum. The electrostatic chuck assembly 200 further includes a support pedestal 226 and a gas feedthrough 228, such as a helium feedthrough.

[0041] The lift pins 230 and lift pin fingers 232 are included in the electrostatic chuck assembly 200. The lift pins 230 may be constructed of alumina and the lift pin fingers 232 may be constructed of aluminum. It should be understood that a plurality of such lift pins 230 may be included in the electrostatic chuck assembly 200. In an embodiment, the plurality of lift pins 230 are located outside the periphery of the processing region of the conductive pedestal 212. In one embodiment, the plurality of lift pins 230 are positioned to contact the tape frame 208 of the substrate carrier.

[0042] In an embodiment, the exposed surface 260 and the covered surface 270 of the conductive pedestal 212 are coated with a ceramic material, such as alumina. In an embodiment, each lift pin 230 is included in an aperture 250. In one embodiment described above, the aperture 250 is a hole included in the conductive pedestal 212, as shown in FIG. 2A and described in more detail below in conjunction with FIG. 2C. The hole may not be coated with a ceramic material and may be a location susceptible to current leakage from the electrostatic chuck assembly. In another embodiment described above, the aperture 250 is a notch included in the peripheral edge of the conductive pedestal, as described in more detail below in conjunction with FIG. 3A-3C. The notch in the embodiment of FIG. 3A-3C may be coated with a ceramic material and may reduce current leakage from the electrostatic chuck assembly as compared to the hole in the embodiment of FIG. 2A-2C.

[0043] In an aspect of the present disclosure, thin substrates (e.g., having a thickness of about 100 microns or less) are processed in a hybrid laser ablation and plasma etch singulation process. In one embodiment of the above, the thin substrate is supported on a substrate carrier. For example, FIG. 2B is a plan view illustrating a substrate carrier suitable for supporting thin wafers during a singulation process according to an embodiment of the present disclosure.

[0044] 2B, the substrate carrier 280 includes a layer of backing tape 282 surrounded by a tape ring or frame 284. A wafer or substrate 286, such as a thin wafer or substrate, is supported by the backing tape 282 of the substrate carrier 280. In one embodiment, the wafer or substrate 286 is attached to the backing tape 282 by a die attach film. As shown by the solid line, the wafer or substrate 286 is a 300 mm wafer, i.e., the substrate carrier 280 is sized to accommodate a 300 mm wafer. However, according to one embodiment of the present disclosure, a 200 mm wafer (dotted line 287) is supported by the substrate carrier 280 even though the substrate carrier 280 is sized for a 300 mm wafer. In one embodiment, the tape ring or frame 284 is constructed of stainless steel. In an embodiment, an electrostatic chuck, such as that described in connection with FIG. 1B, 1C, 2A, 2C, or 3A-3C, accommodates an assembly such as the substrate carrier 280.

[0045] In an embodiment, the singulation process can be accommodated in a system sized to receive a substrate carrier such as substrate carrier 280. In one embodiment described above, a system such as system 400 or 500 described below can accommodate a thin wafer frame without impacting the footprint of a system otherwise sized to accommodate substrates or wafers not supported by a substrate carrier. In one embodiment, system 400 or 500 is sized to accommodate a 300 millimeter diameter wafer or substrate, although in an embodiment, 200 millimeter wafers are processed therein. The same system can accommodate a wafer carrier that is approximately 380 millimeters wide by approximately 380 millimeters long, as shown in FIG. 2B.

[0046] Figure 2C is a perspective view 290 illustrating various aspects and portions of an electrostatic chuck according to an embodiment of the present disclosure. Like numbers from Figure 2A are as described above in connection with Figure 2A. The electrostatic chuck may be paired with a shadow ring assembly as described in connection with Figures 1A, 1D, and 1E.

[0047] 2C, the electrostatic chuck includes a conductive pedestal 212 having a number of holes 294 near its peripheral edge. The electrostatic chuck may accommodate a number of lift pins that correspond to one of the number of holes 294. In an embodiment, the conductive pedestal 212 is coated with a ceramic material, such as alumina, but the inner surface of each of the number of holes is not coated with a ceramic material.

[0048] In an embodiment, the electrostatic chuck further includes an edge insulator ring 210 laterally around the conductive pedestal 212. In an embodiment, the electrostatic chuck further includes a bottom insulator ring 218 below the conductive pedestal 212, the bottom insulator ring 218 having a plurality of openings 296, FIG. 2C , corresponding to one of the lift pins.

[0049] In an embodiment, the lift pins are located outside the periphery of the processing region 292 of the conductive pedestal 212, and the lift pins are positioned to contact the substrate carrier. In an embodiment, the electrostatic chuck is included in a process chamber with a shadow ring, shadow ring assembly, or shadow ring kit positioned over the lift pins, as described in connection with Figures 1A-1F. In one such embodiment, the shadow ring, shadow ring assembly, or shadow ring kit is sized for etching a 200 mm wafer.

[0050] Figures 3A, 3B, and 3C are plan 300, cross-sectional 320, and perspective 340 views, respectively, illustrating various aspects and portions of an electrostatic chuck according to another embodiment of the present disclosure. Like numbers from Figure 2A are as described above in connection with Figure 2A. The electrostatic chuck may be paired with a shadow ring assembly as described in connection with Figures 1A, 1D, and 1E.

[0051] 3A-3C, the electrostatic chuck includes a conductive pedestal 312 having a number of notches 302 on its peripheral edge. The electrostatic chuck also includes a number of lift pins 230 that correspond to ones of the number of notches 302. In an embodiment, the surfaces of the conductive pedestal 312 and the number of notches 302 are coated with a ceramic material. In one such embodiment, the ceramic material is or includes alumina.

[0052] In an embodiment, the electrostatic chuck further includes an edge insulator ring 310 laterally circumferentially about the conductive pedestal 312. The edge insulator ring 310 has a plurality of inner protrusions 362 that correspond to one of the plurality of notches 302. Each of the plurality of inner protrusions 362 has an opening therethrough to accommodate a corresponding one of the plurality of lift pins 230.

[0053] In an embodiment, the electrostatic chuck further includes a bottom insulator ring 318 below the conductive pedestal 312. The bottom insulator ring 318 has a number of openings (322 in FIG. 3B and 346 in FIG. 3C) that correspond to one of the lift pins.

[0054] In an embodiment, the edge insulator ring 310 and the bottom insulator ring 318 are constructed of a ceramic material such as alumina, and the conductive pedestal 312 is constructed of aluminum. The conductive pedestal 312 may be electrically coupled to ground and / or a DC voltage.

[0055] In an embodiment, the plurality of lift pins 230 are positioned outside the periphery of the processing region 342 of the conductive pedestal 312. In one embodiment, the plurality of lift pins 230 are positioned to contact the substrate carrier. In an embodiment, the electrostatic chuck further includes a shadow ring or shadow ring assembly positioned over the plurality of lift pins 230, as described in connection with FIG. 2A.

[0056] In one aspect of the disclosure, the substrate carrier is housed in an etching chamber during the singulation process. In an embodiment, the assembly including the thin wafers or substrates on the substrate carrier is subjected to a plasma etcher without affecting (e.g., etching) the film frame (e.g., tape ring or frame 284) and film (e.g., backing tape 282). Additionally, aspects of the disclosure address transporting and supporting the wafer or substrate supported by the combined film and film frame (substrate carrier) during the etching process. In particular, the etcher may be configured to accommodate etching of the thin wafers or substrates supported by the substrate carrier. For example, FIG. 4 is a cross-sectional view of an etcher according to an embodiment of the disclosure.

[0057] 4, the etching apparatus 400 includes a chamber 402. An end effector 404 is included for transferring a substrate carrier 406 into and out of the chamber 402. An inductively coupled plasma (ICP) source 408 is positioned above the chamber 402. The chamber 402 is further provided with a throttle valve 410 and a turbomolecular pump 412. In an embodiment, the etching apparatus 400 also includes an electrostatic chuck assembly 414, such as the electrostatic chuck described above. In an embodiment, the etching apparatus 400 also includes a lift pin actuator 416 and / or a shadow mask or ring actuator 1418, as shown.

[0058] A single process tool may be configured to perform many or all of the steps in a hybrid laser ablation and plasma etch singulation process. For example, FIG. 5 is a block diagram illustrating a tool layout for laser and plasma dicing of a wafer or substrate according to an embodiment of the present disclosure. In light of the following disclosure, it should be understood that in other embodiments, a coat / bake / clean (CBC) processing chamber may instead be included on or as a separate tool. In other embodiments, the plasma etch chamber and the laser scribe apparatus are a single tool.

[0059] 5, a process tool 500 includes a factory interface 502 (FI) having a number of load locks 504 coupled thereto. A cluster tool 506 is coupled to the factory interface 502. The cluster tool 506 includes one or more plasma etch chambers, such as a plasma etch chamber 508. A laser scribe apparatus 510 is also coupled to the factory interface 502. The overall footprint of the process tool 500 may be, in one embodiment, about 3500 millimeters (3.5 meters) by about 3800 millimeters (3.8 meters), as shown in FIG. 5. In an embodiment, the laser scribe apparatus 510 is configured to perform laser ablation of streets between integrated circuits of a semiconductor wafer, and the plasma etch chamber 508 is configured to etch the semiconductor wafer to singulate the integrated circuits following laser ablation.

[0060] In an embodiment, the laser scribe apparatus 510 houses a laser assembly configured to provide a femtosecond-based laser beam. In one embodiment above, the femtosecond-based laser has a wavelength of about 530 nanometers or less and has a laser pulse width of about 400 femtoseconds or less. In an embodiment, the laser is suitable for performing the laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation process described below. In one embodiment, a movable stage is also included in the laser scribe apparatus 510, the movable stage configured to move the wafer or substrate (or its carrier) relative to the laser. In a specific embodiment, the laser is also movable. The overall footprint of the laser scribe apparatus 510 may be about 2240 millimeters by about 1270 millimeters, as shown in FIG. 5, in one embodiment.

[0061] In an embodiment, the one or more plasma etch chambers 508 are configured to etch the wafer or substrate through the gaps of the patterned mask to singulate the multiple integrated circuits. In one embodiment described above, the one or more plasma etch chambers 508 are configured to perform a deep silicon etch process. In a specific embodiment, the one or more plasma etch chambers 508 are Applied Centura® Silvia™ Etch systems available from Applied Materials, Inc., Sunnyvale, Calif., USA. The etch chambers may be specifically designed for deep silicon etching used to create singulated integrated circuits on or contained within single crystal silicon substrates or wafers. In an embodiment, a high density plasma source is included (or coupled) in the plasma etch chamber 508 to facilitate a high silicon etch rate. In an embodiment, multiple etch chambers are included in the cluster tool 506 portion of the process tool 500 to enable high manufacturing throughput of the singulation or dicing process.

[0062] The plasma etching chamber 508 may include an electrostatic chuck therein. In an embodiment, the electrostatic chuck includes a conductive pedestal having a plurality of notches on its peripheral edge and a plurality of lift pins corresponding to one of the plurality of notches, as described above. In one embodiment, the surfaces of the conductive pedestal and the plurality of notches of the electrostatic chuck are coated with a ceramic material. In one embodiment, the electrostatic chuck further includes an edge insulator ring (e.g., 310) lateral to the periphery of the conductive pedestal (e.g., 312), the edge insulator ring having a plurality of inner protrusions (e.g., 362) corresponding to one of the plurality of notches (e.g., 302), each of the plurality of inner protrusions having an opening therethrough to accommodate a corresponding one of the plurality of lift pins. In one embodiment, the electrostatic chuck further includes a bottom insulator ring (e.g., 318) below the conductive pedestal (e.g., 312), the bottom insulator ring having a plurality of openings (e.g., 346) corresponding to one of the plurality of lift pins. In one embodiment, the lift pins of the electrostatic chuck of the plasma etch chamber 508 are located outside the periphery of the processing region (e.g., 342) of the conductive pedestal (e.g., 312), and the lift pins are positioned to contact the substrate carrier (e.g., contact the tape ring or frame 284 of the substrate carrier assembly 280 described in connection with FIG. 2B).

[0063] Factory interface 502 may be an atmospheric port suitable for interfacing between an external manufacturing facility having a laser scribe apparatus 510 and cluster tool 506. Factory interface 502 may include a robot having an arm or blade for transferring wafers (or their carriers) from a storage unit (such as a front-opening unified pod) to either cluster tool 506 or laser scribe apparatus 510, or both.

[0064] The cluster tool 506 may include other chambers suitable for performing functions in the singulation method. For example, in one embodiment, a deposition and / or bake chamber 512 is included. The deposition and / or bake chamber 512 may be configured to deposit a mask on or over the device layer of the wafer or substrate prior to laser scribing of the wafer or substrate. The mask material may be baked prior to the dicing process, as described above. The mask material may also be water soluble, as described below.

[0065] In an embodiment, referring back to FIG. 5, a wet station 514 is included. The wet station may be suitable for cleaning following a singulation process of laser scribing and plasma etching the substrate or wafer, or following a singulation process of laser scribing only, performing a room temperature or high temperature aqueous treatment to remove the water soluble mask, as described below. In an embodiment, a metrology station, not shown, is also included as a component of the process tool 500. The cleaning chamber may include atomizing mist and / or megasonic nozzle hardware to add a physical component to the cleaning process and increase the dissolution rate of the mask.

[0066] In another aspect, FIGS. 6A-6C are cross-sectional views illustrating various steps of a method for dicing a semiconductor wafer according to an embodiment of the present disclosure.

[0067] 6A, a mask 602 is formed over a semiconductor wafer or substrate 604. The mask 602 covers and protects integrated circuits 606 formed on the surface of the semiconductor wafer 604. The mask 602 also covers the interstitial streets 607 formed between each integrated circuit 606.

[0068] In an embodiment, the semiconductor wafer or substrate 604 is supported by a substrate carrier (such as the substrate carrier described in connection with FIG. 2B ) during formation of the mask 602. In an embodiment, forming the mask 602 on the semiconductor wafer 604 includes spin-coating the mask 602 onto the semiconductor wafer 604. In a specific embodiment, prior to coating, a plasma or chemical pre-treatment is performed to enable better wetting and coating of the wafer.

[0069] In an embodiment, the mask 602 is a water-soluble mask in that it is readily soluble in an aqueous medium. For example, in one embodiment, the as-deposited water-soluble mask 602 is composed of a material that dissolves in one or more of an alkaline solution, an acidic solution, or deionized water. In a specific embodiment, the as-deposited water-soluble mask 602 has an etching or removal rate in an aqueous solution ranging from about 1 to 15 microns / minute. In one embodiment, the mask 602 is a polyvinyl alcohol (PVA)-based water-soluble mask.

[0070] In an embodiment, the semiconductor wafer or substrate 604 is composed of a material suitable for withstanding the manufacturing process, upon which the semiconductor processing layers may be suitably disposed. For example, in one embodiment, the semiconductor wafer or substrate 604 is composed of a Group IV based material, such as, but not limited to, crystalline silicon, germanium, or silicon / germanium. In a specific embodiment, providing the semiconductor wafer 604 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, the semiconductor wafer or substrate 604 is composed of a III-V material, such as, for example, a III-V material substrate used in the manufacture of light emitting diodes (LEDs).

[0071] In an embodiment, an array of semiconductor devices is disposed on or in the semiconductor wafer or substrate 604 as part of an integrated circuit 606. Examples of such semiconductor devices include, but are not limited to, memory devices or complementary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and covered with a dielectric layer. A number of metal interconnects may be formed on the devices or transistors and in the surrounding dielectric layer and may be used to electrically couple the devices or transistors to form the integrated circuit 606. The materials that make up the streets 607 may be similar or the same as the materials used to form the integrated circuit 606. For example, the streets 607 may be composed of layers of dielectric materials, semiconductor materials, and metallization. In an embodiment, one or more of the streets 607 include test devices similar to the actual devices of the integrated circuit 606.

[0072] In an optional embodiment, the mask 602 is baked prior to laser patterning of the mask. In an embodiment, the mask 602 is baked to increase the etch resistance of the mask 602. In a specific embodiment, the mask 602 is baked at a relatively high temperature in the range of about 50 to 130° C. Such high temperature baking can cause cross-linking of the mask 602, significantly increasing the etch resistance. In one embodiment, the baking is performed using a hot plate technique or thermal (light) radiation applied from the front side of the wafer (e.g., the side without tape attached, if a substrate carrier is used), or other suitable technique.

[0073] 6B, the mask 602 is patterned in a laser scribing process to produce a patterned mask 608 having gaps 610, exposing areas of the semiconductor wafer or substrate 604 between the integrated circuits 606. As such, the laser scribing process is used to remove material of the streets 607 originally formed between the integrated circuits 606. According to an embodiment of the present disclosure, patterning the mask 602 in a laser scribing process further includes forming trenches 612 partially in the areas of the semiconductor wafer 604 between the integrated circuits 606, as also shown in FIG. 6B. In an embodiment, the semiconductor wafer or substrate 604 is supported by a substrate carrier (such as the substrate carrier described in connection with FIG. 2B) during the laser scribing process.

[0074] In an embodiment, the mask 602 is patterned with a Gaussian laser beam, although non-Gaussian beams can also be used. Furthermore, the beam can be stationary or rotating. In an embodiment, femtosecond-based lasers are used as the source for the laser scribing process. For example, in an embodiment, lasers with wavelengths in the visible spectrum plus ultraviolet (UV) and infrared (IR) ranges (totaling a broadband light spectrum) are used as femtosecond-based lasers, i.e., lasers with wavelengths in the order of femtoseconds (10 -15 607, and is used to provide a laser having a pulse width of about 100 s (.times.100 s). In one embodiment, the ablation is wavelength independent or essentially wavelength independent, making it suitable for complex films such as the films of the mask 602, the streets 607, and possibly portions of the semiconductor wafer or substrate 604.

[0075] It should be appreciated that by using a laser beam profile with a contribution from the femtosecond range, the thermal damage problem is mitigated or eliminated for longer pulse widths (e.g., nanosecond processing). The elimination or mitigation of damage during laser scribing may be due to low energy recombination or lack of thermal equilibrium. It should also be appreciated that laser parameter selection, such as beam profile, may be important to develop a good laser scribing and dicing process that minimizes chips, microcracks, and delamination to achieve a clean laser scribe cut. The cleaner the laser scribe cut, the smoother the etching process that may be performed for final die singulation. In a semiconductor device wafer, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

[0076] The streets between individual integrated circuits disposed on a wafer or substrate may comprise similar or the same layers as the integrated circuits themselves. For example, Figure 7 is a cross-sectional view showing a stack of materials that may be used in the street regions of a semiconductor wafer or substrate according to embodiments of the present disclosure.

[0077] 7, street region 700 includes an upper portion 702 of a silicon substrate, a first silicon dioxide layer 704, a first etch stop layer 706, a first low-k dielectric layer 708 (e.g., having a dielectric constant less than the 4.0 dielectric constant of silicon dioxide), a second etch stop layer 710, a second low-k dielectric layer 712, a third etch stop layer 714, an undoped silica glass (USG) layer 716, a second silicon dioxide layer 718, and a scribing and / or etching mask 720 (such as the mask described above in connection with mask 602). Copper metallization 722 is disposed between the first and third etch stop layers 706 and 714 and through the second etch stop layer 710. In a particular embodiment, the first, second and third etch stop layers 706, 710 and 714 are comprised of silicon nitride, and the low-k dielectric layers 708 and 712 are comprised of a carbon doped silicon oxide material.

[0078] Under conventional laser irradiation (such as nanosecond-based irradiation), the materials of the street 700 behave quite differently in terms of light absorption and ablation mechanisms. For example, a dielectric layer such as silicon dioxide is essentially transparent to all commercially available laser wavelengths under normal conditions. In contrast, metals, organics (e.g., low-k materials) and silicon can couple photons very easily, especially in response to nanosecond-based irradiation. In an embodiment, a femtosecond-based laser scribing process is used to pattern a layer of silicon dioxide, a layer of low-k material, and a layer of copper by ablating the layer of silicon dioxide before ablating the layer of low-k material and the layer of copper.

[0079] For femtosecond-based laser beams, in embodiments, suitable femtosecond-based laser processes are typically characterized by high peak intensity (irradiance) that results in nonlinear interactions in various materials. In one embodiment above, the femtosecond laser source has a pulse width in the range of about 10 femtoseconds to 500 femtoseconds, but preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser source has a wavelength in the range of about 1570 nanometers to 200 nanometers, but preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optics provide a focal spot in the range of about 3 microns to 15 microns, but preferably in the range of about 5 microns to 10 microns or 10 to 15 microns, at the working plane.

[0080] In an embodiment, the laser source has a pulse repetition rate in the range of about 200 kHz to 10 MHz, but preferably in the range of 500 kHz to 5 MHz. In an embodiment, the laser source provides a pulse energy at the work plane in the range of about 0.5 uJ to 100 uJ, but preferably in the range of 1 uJ to 5 uJ. In an embodiment, the laser scribing process proceeds along the workpiece surface at a speed in the range of about 500 mm / sec to 5 m / sec, but preferably in the range of about 600 mm / sec to 2 m / sec.

[0081] The scribing process may be performed in only a single pass or may be performed in multiple passes, but in embodiments, preferably 1 to 2 passes. In one embodiment, the scribe depth in the workpiece is in the range of about 5 microns to 50 microns deep, preferably about 10 microns to 20 microns deep. In embodiments, the kerf width of the laser beam generated is in the range of about 2 microns to 15 microns, but preferably about 6 microns to 10 microns deep for silicon wafer scribing / dicing, as measured at the device / silicon interface.

[0082] The laser parameters may be selected taking into consideration the benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of the inorganic dielectric (e.g., silicon dioxide), minimizing spalling and swarfing caused by underlayer damage prior to direct ablation of the inorganic dielectric, etc. The parameters may also be selected to precisely control the ablation width (e.g., kerf width) and depth to provide a process throughput meaningful for industrial applications.

[0083] In an optional embodiment, an intermediate post-mask opening cleaning step is performed following the laser scribing process and prior to the plasma etch singulation process. In an embodiment, the post-mask opening cleaning step is a plasma-based cleaning process. In one example, as described below, the plasma-based cleaning process is non-reactive with the trenches 612 of the substrate 604 exposed by the gaps 610.

[0084] According to one embodiment, the plasma-based cleaning process is non-reactive to the exposed areas of the substrate 604 in that the exposed areas are not etched or are etched only negligibly during the cleaning process. In one embodiment described above, only non-reactive gas plasma cleaning is used. For example, a high-bias plasma treatment for both mask condensation and cleaning of the scribed openings is performed using Ar or another non-reactive gas (or a mixture thereof). This approach may be suitable for water-soluble masks such as mask 602. In another such embodiment, the mask condensation (densification of the surface layer) and cleaning steps of the scribed trenches are performed separately, for example, a high-bias plasma treatment of Ar or a non-reactive gas (or a mixture thereof) for the mask condensation is performed first, and then an Ar+SF6 plasma cleaning of the laser scribed trenches is performed. This embodiment may be preferred when the mask material is too thick and therefore an Ar clean is not sufficient for trench cleaning. In this case, the metal salts of the mask may provide etch resistance during the plasma cleaning step with SF6.

[0085] Referring to Figure 6C, the semiconductor wafer 604 is etched through the gaps 610 of the patterned mask 608 to singulate the integrated circuits 606. According to an embodiment of the present disclosure, etching the semiconductor wafer 604 includes finally etching completely through the semiconductor wafer 604, as shown in Figure 6C, by etching the trenches 612 that were initially formed in the laser scribing process. The patterned mask 608 protects the integrated circuits during the plasma etch.

[0086] In an embodiment, during a plasma etching process, the semiconductor wafer or substrate 602 is supported by a substrate carrier (such as the substrate carrier described in connection with FIG. 2B). In one such embodiment, the substrate carrier is supported by an electrostatic chuck having a conductive pedestal with a number of notches on its peripheral edge, as described above in connection with FIGS. 3A-3C. In one such embodiment, the surfaces of the conductive pedestal and the number of notches are coated with a ceramic material that prevents current from leaking from the electrostatic chuck during etching.

[0087] In an embodiment, patterning the mask 602 with a laser scribing process includes forming trenches in areas of the semiconductor wafer between the integrated circuits, and plasma etching the semiconductor wafer includes extending the trenches to form corresponding trench extensions. In one such embodiment, each trench has a width and each corresponding trench extension has its own width.

[0088] In an embodiment, etching the semiconductor wafer 604 includes using a plasma etch process. In one embodiment, a through-Si via type etch process is used. For example, in a specific embodiment, the etch rate of the material of the semiconductor wafer 604 is greater than 10 microns per minute. An ultra-high density plasma source may be used for the plasma etch portion of the die singulation process. One example of a suitable process chamber for performing the plasma etch process described above is the Applied Centura® Silvia™ Etch system available from Applied Materials, Inc., Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines capacitively coupled RF with inductively coupled RF, allowing for greater independent control of ion density and ion energy than was possible with capacitive coupling alone, even when improved with magnetic enhancement. This combination effectively decouples ion density from ion energy, allowing for relatively high density plasmas to be achieved even at very low pressures and without potentially harmful high DC bias levels. The result is a very wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystal silicon substrate or wafer 604 at an etch rate that is greater than about 40% of the conventional etch rate of silicon while maintaining essentially precise profile control and substantially scallop-free sidewalls. In a specific embodiment, a through-Si type etch process is used. This etch process is based on a plasma generated from a reactive gas, which is generally a fluorine-based gas such as SF6, C4F8, CHF3, XeF2, or any other reactive gas capable of etching silicon at a relatively fast etch rate. In another embodiment, the plasma etch process described in connection with FIG. 6C employs a conventional Bosch type dep / etch / dep process to etch through the substrate 604.In general, the Bosch-type process consists of three sub-steps: deposition, directional impingement etching, and isotropic chemical etching, which are carried out through many iterations (cycles) until the silicon is completely etched.

[0089] As described above, in an embodiment, the semiconductor wafer or substrate 602 is supported during the plasma etching process by a substrate carrier (such as the substrate carrier described in connection with FIG. 2B ), which is supported by an electrostatic chuck having a conductive pedestal with a plurality of notches on its peripheral edge. In the specific embodiment described above, following etching, the substrate carrier is removed from the conductive pedestal using a plurality of lift pins that correspond to one of the plurality of notches in the conductive pedestal.

[0090] In an embodiment, following the singulation process, the patterned mask 608 is removed. In an embodiment, the patterned mask 608 is a patterned water-soluble mask. In one embodiment, the patterned mask 608 is removed using an aqueous solution. In one embodiment above, the patterned mask 608 is removed by a hydrothermal treatment, such as a high temperature water treatment. In a specific embodiment, the patterned mask 608 is removed by a hydrothermal treatment at a temperature in the range of about 40 to 100° C. In a particular embodiment, the patterned mask 608 is removed by a hydrothermal treatment at a temperature in the range of about 80 to 90° C. It will be appreciated that the higher the temperature of the water, the shorter the time that may be required for the hydrothermal treatment. According to an embodiment of the present disclosure, a plasma cleaning process may be performed after etching to aid in the removal of the patterned mask 608.

[0091] It should be understood that in other situations, lower water treatment temperatures may be beneficial. For example, if the dicing wafer is supported on a dicing tape that may be affected by higher temperature water treatments (e.g., through loss of adhesion), a relatively low water treatment temperature may be employed, albeit for a longer duration than a relatively high water treatment temperature. In one embodiment described above, the water treatment is between room temperature (i.e., the water is not heated) and at a temperature below about 40° C. In the particular embodiment described above, the patterned mask 608 is removed with a warm water treatment at a temperature in the range of about 35 to 40° C.

[0092] 6A-6C, wafer dicing may be performed by first ablating through the mask, through the wafer streets (including metallization), and partially into the silicon substrate. Die singulation may then be completed by a deep through-silicon plasma etch. Specific examples of material stacks for dicing, according to embodiments of the present disclosure, are described below in conjunction with FIGS. 8A-8D.

[0093] Referring to FIG. 8A, a material stack for hybrid laser ablation and plasma etch dicing includes a mask 802, a device layer 804, and a substrate 806. The mask layer 802, the device layer 804, and the substrate 806 are disposed on a die attach film 808 that is attached to a backing tape 810. In other embodiments, direct bonding to a standard dicing tape is used. In an embodiment, the mask 802 is a mask as described above in connection with the mask 602. The device layer 804 includes an inorganic dielectric layer (such as silicon dioxide) disposed on one or more metal layers (such as a copper layer) and one or more low-k dielectric layers (such as a carbon doped oxide layer). The device layer 804 also includes streets disposed between integrated circuits, the streets including the same or similar layers as the integrated circuits. The substrate 806 is a bulk single crystal silicon substrate. In an embodiment, the mask 802 is fabricated using a thermal process or bake 899 as described above. In an embodiment, the mask 802 is a water mask.

[0094] In an embodiment, the bulk single crystal silicon substrate 806 is thinned from the backside before being attached to the die attach film 808. The thinning can be done by a backside grinding process. In one embodiment, the bulk single crystal silicon substrate 806 is thinned to a thickness in the range of about 30 to 200 microns. Note that in an embodiment, the thinning is performed before the laser ablation and plasma etching dicing process. In an embodiment, the mask 802 has a thickness in the range of about 3 to 100 microns and the device layer 804 has a thickness in the range of about 2 to 20 microns. In an embodiment, the die attach film 808 (or any suitable alternative that can bond a thinned or thin wafer or substrate to a backing tape 810, such as a dicing tape composed of a top adhesive layer and a base film) has a thickness in the range of about 10 to 200 microns.

[0095] Referring to FIG. 8B, portions of the mask 802 , device layer 804 and substrate 806 are patterned in a laser scribing process 812 to form trenches 814 in the substrate 806 .

[0096] 8C, a deep through-silicon plasma etch process 816 is used to extend trenches 814 down to the die attach film 808, exposing the top of the die attach film 808 and singulating the silicon substrate 806. The device layer 804 is protected by mask 802 during the deep through-silicon plasma etch process 816.

[0097] 8D, the singulation process may further include patterning the die attach film 808 to expose the top of the backing tape 810 to singulate the die attach film 808. In an embodiment, the die attach film is singulated by a laser process or by an etching process. Further embodiments may then include removing the singulated portion of the substrate 806 from the backing tape 810 (e.g., as individual integrated circuits). In an embodiment, the singulated die attach film 808 is retained on the backside of the singulated portion of the substrate 806. In an alternative embodiment, if the substrate 806 is thinner than about 50 microns, a laser scribing process 812 is used to completely singulate the substrate 806 without the use of an additional plasma process. An embodiment may further include removing the mask 802 from the device layer 804. Removal of the mask 802 may be performed as described above for removal of the patterned mask 608.

[0098] An embodiment of the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process according to an embodiment of the present disclosure. In one embodiment, the computer system is coupled to a process tool 500 as described in connection with FIG. 5 or an etch chamber 400 as described in connection with FIG. 4. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustic, or other form of propagated signal (e.g., infrared signal, digital signal, etc.)).

[0099] FIG. 9 is a diagrammatic representation illustrating a machine in an exemplary form of a computer system 900 upon which a set of instructions for causing the machine to perform any one or more of the methodologies described herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, although only a single machine is illustrated, the term "machine" shall be construed to include any collection of machines (e.g., computers) that individually or jointly execute a set (or sets) of instructions for performing any one or more of the methodologies described herein.

[0100] The exemplary computer system 900 includes a processor 902, a main memory 904 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 918 (such as a data storage device), which communicate with each other via a bus 930.

[0101] Processor 902 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, processor 902 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processor 902 may also be one or more special purpose processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, etc. Processor 902 is configured to execute processing logic 926 for performing the operations described herein.

[0102] The computer system 900 may further include a network interface device 908. The computer system 900 may also include a video display device 910 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), and a signal generating device 916 (e.g., a speaker).

[0103] The secondary memory 918 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 932 having stored thereon one or more sets of instructions (e.g., software 922) embodying any one or more of the methodologies or functions described herein. The software 922 may also reside, completely or at least partially, within the main memory 904 and / or within the processor 902 during its execution by the computer system 900, with the main memory 904 and the processor 902 also constituting machine-readable storage media. The software 922 may further be transmitted or received over a network 920 via a network interface device 908.

[0104] Although the machine-accessible storage medium 932 is illustrated as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium that can store or encode a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should therefore be interpreted to include, but is not limited to, solid-state memories, and optical and magnetic media.

[0105] According to an embodiment of the present disclosure, a machine-accessible storage medium has instructions stored thereon that cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits, such as one or more of the methods described herein.

[0106] Thus, a hybrid wafer dicing approach using laser scribing and plasma etching processes implemented with a shadow ring kit is disclosed.

Claims

1. An etching apparatus comprising: A chamber; a plasma source within or coupled to the chamber; an electrostatic chuck in the chamber, the electrostatic chuck including a conductive pedestal for supporting a substrate carrier sized to support a wafer having a first diameter; a shadow ring assembly between the plasma source and the electrostatic chuck, the shadow ring assembly comprising a carrier and an insert ring, the insert ring coupled to the carrier, the insert ring of the shadow ring assembly sized to process a wafer having a second diameter smaller than the first diameter, the insert ring of the shadow ring assembly having an inner diameter smaller than the second diameter; An etching apparatus comprising:

2. 2. The etching apparatus of claim 1, wherein the first diameter is about 300 mm and the second diameter is about 200 mm.

3. The etching apparatus of claim 1 , wherein the shadow ring assembly includes a heat shield.

4. The etching apparatus of claim 3 , wherein the heat shield, the insert ring, and the carrier comprise solid alumina.

5. 4. The etching apparatus of claim 3, wherein the heat shield includes a pocket therein for receiving the insert ring without contacting the insert ring.

6. the conductive pedestal having a plurality of holes therethrough, the etching apparatus further comprising: a plurality of lift pins corresponding to ones of the plurality of holes and positioned to contact the substrate carrier beneath the wafer; The etching apparatus of claim 1 .

7. the conductive pedestal having a plurality of notches on a peripheral edge thereof, the etching apparatus further comprising: a plurality of lift pins corresponding to one of the plurality of notches, the lift pins being positioned to contact a frame of the substrate carrier; The etching apparatus of claim 1 .

8. 1. A method for dicing a semiconductor wafer containing a plurality of integrated circuits, comprising: forming a mask over the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits, the semiconductor wafer being supported by a substrate carrier sized to support a wafer having a first diameter; patterning the mask with a laser scribing process to provide a patterned mask having gaps exposing areas of the semiconductor wafer between the integrated circuits; etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits while the semiconductor wafer is supported by the substrate carrier and while the substrate carrier is partially covered by a shadow ring assembly; the shadow ring assembly is between a plasma source and an electrostatic chuck and comprises a carrier and an insert ring, the insert ring coupled to the carrier, the insert ring of the shadow ring assembly is sized to process the semiconductor wafer having a second diameter smaller than the first diameter, and the insert ring of the shadow ring assembly has an inner diameter smaller than the second diameter.

9. 9. The method of claim 8, wherein the shadow ring assembly includes a heat shield, the heat shield including a pocket therein for receiving the insert ring without contacting the insert ring to avoid thermal contact during etching.

10. 9. The method of claim 8, wherein the first diameter is about 300 mm and the second diameter is about 200 mm.

11. 1. A system for dicing a semiconductor wafer containing a plurality of integrated circuits, comprising: A factory interface; a laser scribing device coupled to the factory interface and including a laser; 10. The etching apparatus of claim 1 coupled to the factory interface; A system comprising:

12. 12. The system of claim 11, wherein the first diameter is about 300 mm and the second diameter is about 200 mm.

13. The system of claim 11 , wherein the shadow ring assembly of the etching apparatus includes a heat shield.

14. The system of claim 13 , wherein the heat shield, the insert ring, and the carrier comprise solid alumina.

15. The system of claim 13 , wherein the heat shield includes a pocket therein for receiving the insert ring without contacting the insert ring.

16. 14. The system of claim 13, wherein the insert ring has an inner opening having a diameter of approximately 197 mm.

17. 12. The system of claim 11, wherein the laser scriber is configured to perform laser ablation of streets between integrated circuits of a semiconductor wafer and the etcher is configured to etch the semiconductor wafer to singulate the integrated circuits following the laser ablation.

18. The etching apparatus is housed on a cluster tool coupled to the factory interface, the cluster tool further comprising: a deposition chamber configured to form a mask layer over the integrated circuits of the semiconductor wafer; The system of claim 11 , comprising:

19. The etching equipment is housed on a cluster tool coupled to the factory interface, the cluster tool further comprising: A wet / dry station configured to clean the semiconductor wafer following laser ablation or etching. The system of claim 11 , comprising:

20. The system of claim 11 , wherein the laser scribing device comprises a femtosecond-based laser.

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