Wafer Polishing Method
The wafer polishing method addresses scratches and process-affected layers by using abrasive particles selected based on Knoop hardness, enhancing semiconductor device yield and reducing defects.
Patent Information
- Application Number
- JP2021051293
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-03-25
- Publication Date
- 2025-01-20
- Estimated Expiration
- 2041-03-25
AI Technical Summary
Conventional wafer polishing methods often result in scratches and process-affected layers, leading to low yield and potential defects in semiconductor devices, and inefficient polishing processes.
A wafer polishing method using a polishing body and liquid with abrasive particles, employing Raman spectroscopy to measure the process-affected layer and selecting abrasive particles based on Knoop hardness to effectively remove the layer, thereby reducing defects.
The method achieves a high yield in semiconductor device manufacturing by minimizing scratches and process-affected layers, ensuring the polished wafers do not cause electrical defects.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a method for polishing a wafer. [Background technology]
[0002] Patent Document 1 discloses an example of a wafer polishing method for polishing the surface of a wafer sliced from an ingot. This wafer polishing method uses a polishing body and a polishing liquid. The polishing body does not contain abrasive particles, but the polishing liquid contains abrasive particles. The wafer and the polishing body are moved relative to each other under a predetermined surface pressure in the presence of the polishing liquid, and the wafer is polished. The type, diameter, and amount of abrasive particles are empirically selected depending on the wafer material, surface pressure conditions, relative movement conditions, etc. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2015-211993 A Summary of the Invention [Problem to be solved by the invention]
[0004] However, when a wafer is polished by a conventional wafer polishing method, scratches may occur locally on the polished wafer. A scratched wafer cannot be used as it is in a post-process for manufacturing a semiconductor device, and therefore even if the scratched wafer is further polished to become a scratch-free wafer, the yield of the obtained wafer for manufacturing a semiconductor device is not sufficient.
[0005] That is, even if a scratched wafer has no scratches, a process-induced layer may be present at the location where the scratch was due to compressive or tensile stress. The process-induced layer may cause defects in electrical characteristics, etc. in semiconductor devices, so it is necessary to remove it to some extent. In the first place, a wafer inevitably has a process-induced layer on its surface when it is cut from an ingot by a wire saw or the like.
[0006] In addition, in each conventional semiconductor device processing step, the tool specifications and removal amount (polishing amount) are uniformly determined. Therefore, processing using a uniform tool may result in unnecessary polishing of the wafer, long processing time, or the wafer may still have many processing-affected layers or may develop new processing-affected layers.
[0007] The present invention has been made in consideration of the above-mentioned conventional circumstances, and an object of the present invention is to provide a wafer polishing method capable of realizing a high yield in manufacturing semiconductor devices. [Means for solving the problem]
[0008] The present invention provides a wafer polishing method using a polishing body and a polishing liquid, at least one of the polishing body and the polishing liquid having abrasive particles, and moving a wafer and the polishing body relative to each other under a predetermined surface pressure in the presence of the polishing liquid, thereby polishing the wafer, comprising: a measuring step of measuring a maximum value of a process-affected layer of the wafer by Raman spectroscopy; a selection step of selecting at least the abrasive particles according to the maximum value; a processing step of polishing the wafer with the abrasive particles selected in the selection step. 、 In the selection step, when the maximum value is A (μm), A / 2-{5×10 -8 ×Z 2 +8×10 -5 Knoop hardness Z(KH(kgf / mm × Z-0.1)≦0 2 )) to select the abrasive particles havingIt is characterized by:
[0009] According to the inventor's findings, the process-affected layer of a wafer can be detected non-destructively by Raman spectroscopy. Then, by polishing the wafer with abrasive particles selected according to the maximum value of the process-affected layer, the process-affected layer can be effectively reduced. After polishing the wafer in this way, the electrical characteristics of the semiconductor device are less likely to be defective.
[0010] Therefore, the wafer polishing method of the present invention can achieve a high yield in manufacturing semiconductor devices.
[0011] In the selection step, when the maximum value of the processing-affected layer detected in the measurement step is A (μm), A / 2-{5×10 -8 xZ 2 +8×10 -5 Knoop hardness Z(KH(kgf / mm × Z-0.1)≦0 2 It is preferable to select abrasive particles having a
[0012] The inventors used abrasive particles with various Knoop hardnesses and confirmed the depth (μm) of the process-affected layer formed on the wafer by each abrasive particle, thereby finding a relationship between the Knoop hardness of each abrasive particle and the depth of the process-affected layer formed by each abrasive particle. By polishing a wafer with the abrasive particles selected in this way, it is possible to remove at least 50% of the process-affected layer. A wafer from which at least 50% of the process-affected layer has been removed is less likely to cause defects in the electrical characteristics of a semiconductor device. Furthermore, by polishing a wafer with the abrasive particles selected in this way, the process-affected layer can be effectively removed without polishing the wafer unnecessarily or generating a new process-affected layer. The Japanese Industrial Standard JISZ2251 specifies the test method for the Knoop hardness test, and the Knoop hardness Z is specified in this standard.
[0013] The inventors have confirmed the effect of the present invention when the polishing body is made of foamed resin and the polishing liquid contains abrasive particles. The polishing body may be made of fibers. (1) The polishing body has a binder and abrasive particles held by the binder, and the polishing liquid contains abrasive particles, (2) The polishing body has a binder and abrasive particles held by the binder, and the polishing liquid does not contain abrasive particles, and (3) The polishing body is made of resin and has a base material in which a plurality of bubbles are formed and abrasive particles held in the base material or the bubbles, and the polishing liquid does not contain abrasive particles. Effect of the Invention
[0014] According to the wafer polishing method of the present invention, a high yield in manufacturing semiconductor devices can be achieved. [Brief description of the drawings]
[0015] [Figure 1] FIG. 1 is a plan view of a wafer. [Diagram 2] FIG. 2 shows the results of measurement by Raman spectroscopy. [Diagram 3] FIG. 3 is a graph showing the relationship between the Knoop hardness of each abrasive particle and the depth of the process-affected layer caused on the wafer by each abrasive particle. [Figure 4] FIG. 4 is a graph showing the relationship between the Knoop hardness and the polishing efficiency index of each abrasive particle. [Diagram 5] FIG. 5 is a schematic cross-sectional view of a wafer polishing apparatus used in the processing step. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] (Test 1) As shown in Fig. 1, a wafer 1 made of 4H-SiC single crystal with a diameter of 4 inches was prepared. For this wafer 1, coordinate axes were assumed in which the x-axis and y-axis extending from a center point O were defined on the surface of the wafer 1, and the z-axis was defined in the thickness direction of the wafer 1. A total of three regions 1a to 1c were defined, starting from region 1a closest to center point O. Each of regions 1a to 1c was defined to be in the range of -5 to 5 (μm) in the x direction and 0 to -5 (μm) in the z direction.
[0017] Then, a laser beam was sequentially irradiated onto each of the regions 1a to 1c using a Raman spectrometer, and the Raman scattered light was measured. An example of the measurement results obtained by Raman spectroscopy is shown in Fig. 2. As shown in Fig. 2, the wafer 1 has a process-affected layer 3 on the front surface side in each of the regions 1a to 1c.
[0018] However, in each of the regions 1a to 1c, the portion C designated by x = -0.5 to 0.5 (μm) and z = -4.5 to -5 (μm) is a depth region where it is generally considered that there is no process-affected layer in the wafer before polishing. Therefore, the average value of the Raman peaks in the portion C is used as the standard, and the Raman peak is located 0.15 cm away from the high wavenumber side. -1 If the Raman peak shifts by more than 0.15 cm to the low wavenumber side, it is a processing-affected layer with compressive stress. -1 If the shift is greater than this, it is defined as a process-affected layer having tensile stress.
[0019] The maximum depth a (μm) of the process-affected layer 3 in each of the regions 1a to 1c was measured. Even if damage appears to be present to a depth of, for example, 0.7 μm on the inspection screen, when the laser light penetrates inside the SiC, it actually reaches a depth multiplied by 2.65, which is the refractive index of SiC. In other words, the process-affected layer 3 exists to a depth of 0.7 × 2.65 = 1.855 μm. The maximum value of a was taken as A.
[0020] On the other hand, abrasive particles made of silica (SiO2), abrasive particles made of alumina (Al2O3), abrasive particles made of cubic boron nitride (CBN), and abrasive particles made of diamond were prepared, and the depth (μm) of the process-affected layer 3 newly formed by polishing using these abrasive particles was confirmed. The Knoop hardness of the abrasive particles made of silica (SiO2) was 937 (KH), the Knoop hardness of the abrasive particles made of alumina (Al2O3) was 2220 (KH), the Knoop hardness of the abrasive particles made of cubic boron nitride (CBN) was 4600 (KH), and the Knoop hardness of the abrasive particles made of diamond was 8000 (KH). The results are shown in Figure 3. The curve shown in Figure 3 can be expressed by the following formula 1, with the Knoop hardness on the x-axis and the depth of the process-affected layer 3 on the y-axis.
[0021] Number 1...y=5×10 -8 x 2 +8×10 -5 x-0.1
[0022] When x in this formula 1 is the Knoop hardness Z and 50% or more of the maximum value A of the processing-affected layer is removed, the following formula 2 is obtained.
[0023] Number 2…A / 2-{5×10 -8 xZ 2 +8×10 -5 ×Z-0.1}≦0
[0024] Using abrasive particles with the above four types of Knoop hardness, the relationship between the Knoop hardness of each abrasive particle and the polishing efficiency index was confirmed. The polishing efficiency index was evaluated assuming that the polishing rate of abrasive particles made of silica was 1. The results are shown in Figure 4. The curve shown in Figure 4 can be expressed by the following formula 3, with Knoop hardness on the x-axis and the polishing efficiency index on the y-axis.
[0025] Number 3...y=2×10 -10 x 3 -1×10 -6 x 2 +0.0028x-0.7611
[0026] According to this formula (3), when a polishing process is performed using abrasive particles that satisfy the formula (2), the damaged layer 3 can be effectively removed.
[0027] (Test 2) "Measurement process" Wafer 1 was prepared for Test 1. For wafer 1, maximum value A of process-affected layer 3 was measured by Raman spectroscopy in the same manner as in Test 1. As a result, maximum value A of process-affected layer 3 was 1.9 μm.
[0028] "Selection process" Substituting A=1.9 into the above formula 2 to find Z, we obtain Z≦3852 (KH). For this reason, abrasive particles made of alumina with a Knoop hardness of 2220 (KH) were used as an example. On the other hand, abrasive particles made of cubic boron nitride with a Knoop hardness of 4600 (KH) were used as a comparative example.
[0029] "Processing process" A polishing apparatus (Engis EJW-380) shown in Fig. 5 was prepared. This polishing apparatus includes a plurality of carriers 5, a surface plate 7, a driving device 9, and a polishing liquid supplying device 11.
[0030] Although only a single carrier 5 is shown in Fig. 5, the polishing apparatus has multiple carriers 5. Each carrier 5 is in the shape of a horizontal disk. A recess 5a is formed in the lower surface of each carrier 5, and a wafer 1 is fixed to the recess 5a. A carrier rotation shaft 5b protrudes vertically from the upper surface of each carrier 5. The surface to be polished 1a, which is the Si surface of the wafer 1, faces downward.
[0031] The surface plate 7 is a horizontal disk that contains all the carriers 5. A surface plate rotation shaft 7a protrudes vertically from the underside of the surface plate 7. A disk-shaped polishing pad 13 is fixed to the upper surface of the surface plate 7 with an adhesive so as to face each wafer 1. The polishing pad 13 is a urethane pad (manufactured by Nitta Haas, IC1000) with a diameter of 300 mm.
[0032] The driving device 9 has a main driving device 9a, a sub-driving device 9b, and a pressure device 9c. The main driving device 9a drives the base plate rotation shaft 7a to rotate around the first axis O1 at a predetermined speed. The sub-driving device 9b drives each carrier rotation shaft 5b to rotate around the second axis O2 at a predetermined speed. The pressure device 9c presses each carrier rotation shaft 5b and the sub-driving device 9b toward the base plate 7 with a predetermined load.
[0033] The polishing liquid supplying device 11 is provided above the platen 7. The polishing liquid supplying device 11 provides a polishing liquid 11a between each wafer 1 and the polishing pad 13. The polishing liquid 11a is a dispersion of any abrasive particles in pure water at a concentration of 5% by mass.
[0034] In this polishing apparatus, each wafer 1 was polished under the following conditions. Flow rate of polishing liquid 11a: 10 mL / min Load: 30kPa Rotation speed of surface plate 7: 60 rpm Carrier 5 rotation speed: 60 rpm Processing time: 30 minutes
[0035] The maximum value A of the process-affected layer 3 of the wafer 1 polished with the abrasive particles of the Example and the wafer 1 polished with the abrasive particles of the Comparative Example was measured by Raman spectroscopy in the same manner as in Test 1. As a result, the maximum value A of the process-affected layer 3 of the wafer 1 polished with the abrasive particles of the Example was 0.265 μm, which was 14% of the value before polishing.
[0036] On the other hand, in the wafer 1 polished with the abrasive particles of the comparative example, the maximum value A of the process-affected layer 3 was 1.5 μm, which was 79% of the value before polishing.
[0037] Therefore, by polishing the wafer 1 with the abrasive particles of the embodiment, it is possible to effectively reduce the process-affected layer 3. The wafer 1 thus polished is less likely to cause defects in the electrical characteristics of the semiconductor device.
[0038] Therefore, according to the wafer polishing method of the embodiment, a high yield in manufacturing semiconductor devices can be achieved.
[0039] Although the present invention has been described above with reference to the embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified as appropriate without departing from the spirit of the present invention.
[0040] For example, the wafer 1 is not limited to SiC, and may be a semiconductor substrate such as Si or GaN. In addition, the abrasive particles are not limited to alumina, and may be diamond, cubic boron nitride, B4C (boron carbide), CeO2, silicon carbide, silica, zirconia, titania, manganese oxide, barium carbonate, chromium oxide, iron oxide, etc., as long as they are selected according to the present invention.
[0041] In the above embodiment, the polishing body is made of foamed resin and the polishing liquid contains abrasive particles, but the polishing liquid may contain an NaOH aqueous solution, a potassium permanganate aqueous solution, an amine-based aqueous solution, or the like. [Industrial Applicability]
[0042] The present invention can be used in a method for manufacturing a semiconductor device. [Explanation of symbols]
[0043] 13...Abrasive body (abrasive pad) 11a...polishing liquid 1...Wafer 3...Process-affected layer A: Maximum value Z...Knoop hardness
Claims
1. A wafer polishing method using a polishing body and a polishing liquid, at least one of the polishing body and the polishing liquid having abrasive particles, comprising moving a wafer and the polishing body relative to each other under a predetermined surface pressure in the presence of the polishing liquid, the method comprising: a measuring step of measuring a maximum value of a process-affected layer of the wafer by Raman spectroscopy; a selection step of selecting at least the abrasive particles according to the maximum value; a processing step of polishing the wafer with the abrasive particles selected in the selection step, In the selection step, when the maximum value is A (μm), A method for polishing a wafer, comprising the step of selecting abrasive particles having a Knoop hardness Z (KH (kgf / mm 2 )) that satisfies A / 2-{5×10 -8 ×Z 2 +8×10 -5 ×Z-0.1}≦0.
2. The abrasive body is made of fiber or foamed resin, 2. The method for polishing a wafer according to claim 1, wherein the polishing liquid contains the abrasive particles.
Citation Information
Patent Citations
Manufacture of semiconductor device and abrasive device
JP1995321076A
Polishing end point detecting method and polishing end point detecting device of wafer
JP2000135673A
Method for correcting warp of ceramic plate and method for manufacturing spacer for flat panel display
JP2005193333A
Group iii nitride semiconductor substrate
JP2013126939A
Polishing pad, polishing method using the polishing pad, and using method of the polishing pad
JP2015211993A