Quantum state preparation circuit generation, quantum state preparation method, device, and quantum chip

Abstract

The present application relates to a method, an apparatus, a quantum chip, an electronic device, a storage medium, and a computer program product for generating a quantum state preparation circuit, which includes steps of determining a target qubit set under a binary tree restriction, applying a one-qubit flip gate to a first target child node qubit (702 and 704), applying a two-qubit phase shift gate between the child node qubits (706), applying a two-qubit swap gate between the first target child node qubit and a second target child node qubit (708), taking the child node qubit as a root node qubit and repeatedly executing until the child node qubit becomes a leaf node qubit (710), and applying a two-qubit phase shift gate between the leaf node qubits under a path restriction and applying a one-qubit phase shift gate to the leaf node qubit to obtain a quantum state preparation circuit (712 and 714).

Description

[Technical field]

[0001] The present application relates to the field of quantum technology, and in particular to the generation of quantum state preparation circuits, and quantum state preparation methods, apparatus, quantum chips, electronic devices, storage media, and computer program products.

[0002] This application claims priority to a Chinese patent application filed with the China Patent Office on May 18, 2022, bearing application number 202210542256X and entitled "GENERATING QUANTUM STATE PREPARATION CIRCUIT, AND QUANTUM STATE PREPARATION METHOD, APPARATUS, AND QUANTUM CHIP," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] With the development of quantum technology, quantum state preparation technology has emerged, and the process of loading classical data into a quantum state is called quantum state preparation. In quantum systems, due to quantum decoherence, if the quantum circuit is too deep, the quantum circuit may degenerate into a classical circuit. In real quantum devices, the interaction between qubits may be restricted due to the spatial arrangement of qubits or other factors. Therefore, in quantum state preparation circuits, the qubits that can be acted on by a CNOT gate (two-qubit gate) are limited by the specific physical device.

[0004] At present, direct improvement of conventional quantum state preparation circuits under circuit limitations can significantly increase the circuit depth. Summary of the Invention [Problem to be solved by the invention]

[0005] Based on this, in order to address the above technical problems, it is necessary to provide a quantum state preparation circuit generation, and a quantum state preparation method, apparatus, quantum chip, electronic device, storage medium, and computer program product that can effectively reduce the circuit depth. [Means for solving the problem]

[0006] In one aspect, the present application provides a method for generating a quantum state preparation circuit, the method comprising: Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path restriction; determining a target qubit set under the binary tree constraint, and applying a one-qubit flip gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying a two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; operating a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a phase-shift gate subcircuit; applying a two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit.

[0007] In another aspect, the present application further provides an apparatus for generating a quantum state preparation circuit, the apparatus comprising: A quantum gate acquisition module is used to acquire a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under a path restriction; an inverting gate action module adapted to determine a target qubit set under the binary tree constraint and to apply a one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; a phase-shift gate action module used to actuate a two-qubit phase-shift gate between a child node qubit corresponding to a root node qubit to obtain a phase-shift gate subcircuit; a swap gate action module used to apply a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; a repeating module adapted to operate a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit and obtain a phase-shift gate subcircuit, the child node qubit being a root node qubit, until the child node qubit becomes a leaf node qubit; a leaf node action module used to operate a two-qubit phase-shift gate under a path restriction between leaf node qubits corresponding to parent node qubits in a target qubit set to obtain a leaf phase-shift gate sub-circuit, and to operate a one-qubit phase-shift gate on the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; and a combination module that is used to combine the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit.

[0008] In another aspect, the present application further provides a quantum chip including a quantum state preparation circuit, the quantum state preparation circuit being realized by a method for generating a quantum state preparation circuit, the method for generating the quantum state preparation circuit comprising: Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path restriction; determining a target qubit set under the binary tree constraint, and applying a one-qubit flip gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying a two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; operating a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a phase-shift gate subcircuit; applying a two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; and combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit.

[0009] In another aspect, the present application further provides an electronic device, the electronic device including a memory and a processor, the memory having computer-readable instructions stored therein, the processor, when executing the computer-readable instructions, performing: Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path restriction; determining a target qubit set under the binary tree constraint, and applying a one-qubit flip gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying a two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; operating a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a phase-shift gate subcircuit; applying a two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; combining the inverting gate sub-circuit, the phase-shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase-shifting gate sub-circuit, and the one-qubit phase-shifting sub-circuit to form a quantum state preparation circuit.

[0010] In another aspect, the present application further provides a computer-readable storage medium having computer-readable instructions stored thereon, the computer-readable instructions, when executed by a processor, Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path restriction; determining a target qubit set under the binary tree constraint, and applying a one-qubit flip gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying a two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; operating a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a phase-shift gate subcircuit; applying a two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; combining the inverting gate sub-circuit, the phase-shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase-shifting gate sub-circuit, and the one-qubit phase-shifting sub-circuit to form a quantum state preparation circuit.

[0011] In another aspect, the present application further provides a computer program product, the computer program product including computer readable instructions that, when executed by a processor, Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path restriction; determining a target qubit set under the binary tree constraint, and applying a one-qubit flip gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying a two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; operating a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a phase-shift gate subcircuit; applying a two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; combining the inverting gate sub-circuit, the phase-shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase-shifting gate sub-circuit, and the one-qubit phase-shifting sub-circuit to form a quantum state preparation circuit.

[0012] The method, apparatus, quantum chip, electronic device, storage medium, and computer program product for generating a quantum state preparation circuit include determining a target qubit set under a binary tree constraint, applying a one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inversion gate subcircuit, applying a two-qubit phase shift gate between the child node qubits corresponding to the root node qubit to obtain a phase shift gate subcircuit, and applying a two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, wherein the second target child node qubit is a child node qubit of the first target child node qubit, and returning to the step of applying a two-qubit phase-shift gate between the child node qubits corresponding to the root node qubit until the child node qubit becomes a child bit, and obtaining a phase-shift gate sub-circuit; applying a two-qubit phase-shift gate under the path restriction between the leaf node qubits corresponding to the parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; and combining the inversion gate sub-circuit, the phase-shift gate sub-circuit, the swap gate sub-circuit, the leaf phase-shift gate sub-circuit, and the one-qubit phase-shift sub-circuit to form a quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit, and further effectively reducing the time for quantum state preparation, and improving the operating efficiency of quantum computing.

[0013] In one aspect, the present application provides a method for preparing a quantum state, the method comprising: obtaining a target data vector; and obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying a target one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inversion gate subcircuit; applying a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit; operating a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target 2-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying a target 1-qubit phase-shift gate to the leaf node qubit to obtain a target 1-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The method includes a step of inputting a preset initial quantum state into a target quantum state preparation circuit to perform quantum state preparation, thereby obtaining a quantum state corresponding to the target data vector.

[0014] In another aspect, the present application further provides a quantum state preparation device, the device comprising: A target quantum gate acquisition module is used for acquiring a target data vector, and acquiring a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction according to the target data vector; a target inverting gate action module adapted to determine a target qubit set under the binary tree constraint and to act a target one-qubit inverting gate on a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inverting gate subcircuit; a target phase-shift gate action module used to actuate a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate sub-circuit; a target swap gate action module used to apply a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit; a target iteration module adapted to operate a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and to execute back to the step of obtaining a target phase-shift gate sub-circuit; a target leaf node action module used for operating a target two-qubit phase-shift gate under a path restriction between leaf node qubits corresponding to parent node qubits in a target qubit set to obtain a target leaf phase-shift gate sub-circuit, and operating a target one-qubit phase-shift gate on a leaf node qubit to obtain a target one-qubit phase-shift sub-circuit; a target combination module used to combine the target inversion gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; A preparation module is used for inputting a preset initial quantum state into a target quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the target data vector.

[0015] In another aspect, the present application further provides a quantum chip including a quantum state preparation circuit, the quantum state preparation circuit being realized by a method for generating a quantum state preparation circuit, the method for generating the quantum state preparation circuit comprising: obtaining a target data vector; and obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying a target one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inversion gate subcircuit; applying a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit; operating a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target 2-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying a target 1-qubit phase-shift gate to the leaf node qubit to obtain a target 1-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The method includes a step of inputting a preset initial quantum state into a target quantum state preparation circuit to perform quantum state preparation, thereby obtaining a quantum state corresponding to the target data vector.

[0016] In another aspect, the present application further provides an electronic device, the electronic device including a memory and a processor, the memory having computer-readable instructions stored therein, the processor, when executing the computer-readable instructions, performing: obtaining a target data vector; and obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying a target one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inversion gate subcircuit; applying a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit; operating a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target 2-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying a target 1-qubit phase-shift gate to the leaf node qubit to obtain a target 1-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The step of preparing a quantum state by inputting a preset initial quantum state into a target quantum state preparation circuit to obtain a quantum state corresponding to the target data vector is realized.

[0017] In another aspect, the present application further provides a computer-readable storage medium having computer-readable instructions stored thereon, the computer-readable instructions, when executed by a processor, obtaining a target data vector; and obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying a target one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inversion gate subcircuit; applying a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit; operating a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target 2-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying a target 1-qubit phase-shift gate to the leaf node qubit to obtain a target 1-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The step of preparing a quantum state by inputting a preset initial quantum state into a target quantum state preparation circuit to obtain a quantum state corresponding to the target data vector is realized.

[0018] In another aspect, the present application further provides a computer program product, the computer program product including computer readable instructions that, when executed by a processor, obtaining a target data vector; and obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under a path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying a target one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inversion gate subcircuit; applying a target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit; operating a target two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, until the child node qubit becomes a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target 2-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying a target 1-qubit phase-shift gate to the leaf node qubit to obtain a target 1-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The step of preparing a quantum state by inputting a preset initial quantum state into a target quantum state preparation circuit to obtain a quantum state corresponding to the target data vector is realized. Effect of the Invention

[0019] The above quantum state preparation method, apparatus, quantum chip, electronic device, storage medium, and computer program product include obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under path restriction corresponding to a target data vector; then using the target 1 qubit flip gate, the target 1 qubit phase shift gate, the target 2 qubit swap gate, and the target 2 qubit phase shift gate under path restriction to generate a target quantum state preparation circuit corresponding to the target data vector with a target qubit set under binary tree restriction; and applying circuit depths of the target 1 qubit flip gate, the target 1 qubit phase shift gate, the target 2 qubit swap gate, and the target 2 qubit phase shift gate under path restriction to the target qubit under binary tree restriction, wherein the path restrictions under the binary tree restriction are not crossed, thereby significantly reducing the circuit depth of the obtained quantum state preparation circuit, and effectively reducing the circuit depth of the quantum state preparation circuit. Next, the predetermined initial quantum state is input into a target quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the target data vector, i.e., by preparing the quantum state using a target quantum state preparation circuit with reduced circuit depth, the time for quantum state preparation can be effectively reduced and the operating efficiency of quantum computing can be improved, thereby improving the efficiency of quantum state preparation.

[0020] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that need to be used in the description of the embodiments. It is obvious that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can further obtain other drawings based on these drawings under the premise of not performing creative work. [Brief description of the drawings]

[0021] [Figure 1]FIG. 1 is an application environment diagram of a method for generating a quantum state preparation circuit in one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a binary tree restriction of a quantum circuit in one embodiment. [Diagram 3] FIG. 2 is a schematic diagram of an n-path restriction for an n-qubit circuit in one embodiment. [Figure 4] FIG. 1 is a schematic diagram of a circuit implementation of a two-qubit swap gate [Equation 1] in one embodiment. [Diagram 5] FIG. 2 is a schematic diagram of a circuit implementation of a two-qubit rotate gate [Equation 2] in one embodiment. [Figure 6] FIG. 2 is a schematic diagram of a circuit implementation of a CNOT gate [Equation 3] under path constraints in one embodiment. [Figure 7] FIG. 1 is a process diagram of a method for generating a quantum state preparation circuit in one embodiment. [Figure 8] FIG. 1 is a process diagram for generating a three-qubit quantum state preparation circuit in one embodiment. [Figure 9] FIG. 2 is a process diagram for obtaining a quantum state corresponding to a target data vector in one embodiment. [Figure 10] FIG. 1 is a process diagram of quantum recommendation in one embodiment. [Figure 11] FIG. 2 is a process diagram of a quantum state preparation method in one embodiment. [Figure 12] FIG. 2 is a schematic diagram of generating a quantum state preparation circuit in one specific embodiment. [Figure 13] FIG. 2 is a structural block diagram of a generating device for a quantum state preparation circuit in one embodiment. [Figure 14] FIG. 2 is a structural block diagram of a quantum state preparation device in one embodiment. [Figure 15] FIG. 1 is a diagram showing the internal structure of an electronic device according to an embodiment.

[0022]

number

number

number

[0023] In order to make the objectives, technical solutions and advantages of the present application clearer and more obvious, the present application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely used to interpret the present application, and are not used to limit the present application.

[0024] The method for generating a quantum state preparation circuit provided by the embodiment of the present application can be applied to the application environment shown in FIG. 1. Here, the electronic device 102 communicates with the quantum chip 104 through a network. The data storage system can store data that the electronic device 102 needs to process. The data storage system can be integrated in the electronic device 102, or can be located in a cloud or in another network server. The electronic device 102 can be used to generate a quantum state preparation circuit 1042, in which the electronic device 102 obtains a one-qubit inversion gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under a path restriction. The electronic device 102 determines a target qubit set under a binary tree restriction, and applies the one-qubit inversion gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inversion gate subcircuit. The electronic device 102 applies the two-qubit phase shift gate between the child node qubits corresponding to the root node qubit to obtain a phase shift gate subcircuit. Electronic device 102 applies a two-qubit swap gate between a first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit. The second target child node qubit is a child node qubit of the first target child node qubit. Electronic device 102 returns to the step of applying a two-qubit phase-shift gate between child node qubits corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and obtaining a phase-shift gate subcircuit. Electronic device 102 applies a two-qubit phase-shift gate under a path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate subcircuit, and applies a one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift subcircuit.The electronic device 102 combines the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swapping gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit 1042. The quantum chip 104 can finally be fabricated based on the quantum state preparation circuit 1042.

[0025] Here, the electronic device 102 may be an industrialized smart device used to fabricate the quantum state preparation circuit 1042, such as a photoetching device, a robot arm, and other devices required for industrial production. After using the quantum state preparation circuit 1042 to fabricate the quantum chip 104, the quantum chip 104 may be integrated into various smart terminals, including smartphones, tablet computers, laptops, desktop computers, smart speakers, smart watches, Internet of Things devices, and portable wearable devices, and the Internet of Things devices may be smart speakers, smart TVs, smart air conditioners, and smart car-mounted devices, etc. The portable wearable devices may be smart watches, smart bands, and head-mounted devices, etc.

[0026] Before describing the embodiments of the present application in more detail, the relevant nouns, terms, symbols, relevant parameters, and basic quantum gates in the embodiments of the present application are explained. The relevant nouns and terms in the embodiments of the present application are applied to the following interpretation.

[0027] (1) Quantum Computation: A type of computing method that utilizes properties such as superposition of quantum states and entanglement to quickly complete computational tasks.

[0028] (2) Quantum bit (Qubit): A form of transport for quantum information.

[0029] (3) Quantum Circuit: A type of quantum computing model that consists of a series of quantum gate sequences and completes a calculation using quantum gates.

[0030] (4) Quantum chip: The central processor of a quantum computer. A quantum computer is a type of machine that uses the superposition principle of quantum mechanics and quantum entanglement to perform calculations. It has relatively high parallel processing capabilities and can solve some problems that are difficult to calculate with classical computers.

[0031] (5) Basic symbols related to this application: [n]0 represents the set {0,1,...,n}. F2 represents a binary field. [Number 4] represents the empty string. For any x∈{0,1} n About e x represents a vector whose element number x is 1 and the other elements are 0. For any quantum bit number i, |ψ> i denotes that the quantum state |ψ〉 is the quantum state at qubit i.

[0032]

number

[0033] (6) Basic quantum gates according to the present application: In order to better describe the structure of quantum circuits under the binary tree constraint, the present application first describes some basic quantum gates.

[0034] A one-qubit flip gate X is defined as |0>→|1>, |1>→|0>.

[0035] For any real number θ∈R, there are 1-bit quantum gates R(θ) and R y (θ) are, respectively R(θ): |0>→|0>,|1>→e iθ |1>, R y (θ): |0>→cos(θ / 2)|0>+sin(θ / 2)|1>, |1>→-sin(θ / 2)|0>+cos(θ / 2)|1>.

[0036] A two-qubit rotation (phase shift) gate [Equation 5] acting on qubits i and j (rotating around the y-axis (phase shift)) is |0> i |0> j →|0> i |0> j , |1> i |0> j →cos(θ / 2) |1> i |0> j +sin(θ / 2)|0> i |1> j , |0> i |1> j →-sin(θ / 2) |1> i |0> j +cos(θ / 2)|0> i |1> j , |1> i |1> j →|1> i |1> j It is defined as:

[0037]

number

[0038] The CNOT (controlled NOT) gate [6] acting on quantum bits i and j is |0> i |0> j →|0> i |0> j ,|0> i |1> j →|0> i |1> j ,|1> i |0> j →|1> i |1> j ,|1> i |1> j →|1> i |0> j It is defined as:

[0039]

number

[0040] The swap gate [7] acting on quantum bits i and j is |x> i |y> j →|y> i |x> j ,∀x,y∈{0,1}.

number

[0041] (7) Binary Tree Restriction: If a CNOT gate is permitted to operate only on two adjacent qubits, the circuit is said to be under the binary tree restriction. Figure 2 shows the binary tree restriction of a quantum circuit, where each vertex [8] has 2 n - represents one qubit. In a binary tree, if two qubits are connected by one edge, then a CNOT gate can operate on these two qubits.

[0042]

number

[0043] (8) n-path restriction: In an n-qubit circuit, if a CNOT gate is allowed to act only on two adjacent qubits, the circuit is said to be under the n-path restriction. Figure 3 shows the n-path restriction of an n-qubit circuit, with vertices R1, R2, ..., and R n Each of n represents a quantum bit. If two quantum bits are connected by one edge, a CNOT gate can act on these two quantum bits.

[0044] (9) This application first describes the implementation of the four sub-circuits.

[0045] A circuit implementation of the 1, 2 qubit swap gate [9] is shown in Figure 4.

[0046]

number

[0047] 2. A circuit realization of a two-qubit rotation (phase-shift) gate [Equation 10] is shown in Figure 5.

[0048]

number

[0049] 3. Circuit realization of the CNOT gate [Equation 11] under path constraints: Under path constraints, [Equation 11] can be realized by a CNOT circuit whose depth and size are both 0 (|ij|), as shown in Figure 6.

[0050]

number

[0051] 4. Circuit realization of a two-qubit rotate gate [Equation 12] under path restriction: As can be seen by combining the circuit realization of a two-qubit rotate gate [Equation 13] (Figure 5) with the circuit realization of a CNOT gate [Equation 14] under path restriction (Figure 6), under path restriction, [Equation 15] can be realized by a quantum circuit with depth 0 (|ij|).

[0052]

number

number

number

number

[0053] In one embodiment, a method for generating a quantum state preparation circuit is provided, as shown in Fig. 7. Taking the method as an example applied to the electronic device in Fig. 1, the method includes the following steps 702 to 714.

[0054] Step 702: Obtain a 1-qubit flip gate, a 1-qubit phase shift gate, a 2-qubit swap gate, and a 2-qubit phase shift gate under path restriction.

[0055] Here, the one-qubit flip gate is a quantum gate used to flip a single qubit. The one-qubit phase shift gate is a quantum gate used to perform a phase shift on a single qubit. The two-qubit swap gate is a quantum gate used to swap two qubits. The two-qubit phase shift gate is a quantum gate used to perform a phase shift on two qubits.

[0056] Specifically, the electronic device obtains an initial vector, and determines a 1-qubit flip gate, a 1-qubit phase shift gate, a 2-qubit swap gate, and a 2-qubit phase shift gate under a path restriction based on the initial vector. The initial vector is a vector of initial classical data, and may be preset. The electronic device may directly obtain the 1-qubit flip gate, the 1-qubit phase shift gate, the 2-qubit swap gate, and the 2-qubit phase shift gate under a path restriction from a database. The electronic device may further obtain the 1-qubit flip gate, the 1-qubit phase shift gate, the 2-qubit swap gate, and the 2-qubit phase shift gate under a path restriction uploaded from a terminal.

[0057] STEP 704: Determine a target qubit set under the binary tree constraint, and apply a one-qubit inverting gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit.

[0058] Here, the target qubit set under the binary tree restriction refers to a set of qubits in which the qubits in the target qubit set are arranged in the form of a binary tree and a CNOT gate is allowed to act only on two adjacent qubits. A binary tree refers to an ordered tree in which the degree of the nodes in the tree is two or less. A binary tree is an empty tree or a non-empty tree consisting of a root node and two left and right child trees that do not intersect with each other and are called the root, respectively, and the left and right child trees are also binary trees. The root node qubit refers to the qubit at the root node position in the binary tree. The first target child node qubit refers to the qubit at the target child node position corresponding to the root node qubit, which may be the left child node position or the right child node position. The inverting gate subcircuit refers to a quantum circuit obtained by applying a one-qubit inverting gate to the first target child node qubit.

[0059] Specifically, the electronic device takes each qubit and uses it to determine a target qubit set under the binary tree constraint, then applies a one-qubit flip gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain a flip gate subcircuit, i.e., realizes a one-qubit flip gate in the first target child node qubit corresponding to the root node qubit in the target qubit set, where a one-qubit flip operation can be performed on the qubit passing through the first target child node, such as flipping |0> to |1> or |1> to |0>.

[0060] STEP 706: Apply a two-qubit phase-shift gate between the child node qubits corresponding to the root node qubit to obtain a phase-shift gate sub-circuit.

[0061] Here, "between child node qubits" refers to between the qubit at the left child node position and the qubit at the right child node position. A phase-shift gate subcircuit refers to a quantum circuit obtained by applying a two-qubit phase-shift gate between the qubit at the left child node position of the root node qubit and the qubit at the right child node position.

[0062] Specifically, the electronic device operates a two-qubit phase shift gate under path restriction between child node qubits corresponding to the root node qubit to obtain a phase shift gate subcircuit, i.e., realizes a two-qubit phase shift gate between the qubit at the left child node position and the qubit at the right child node position, and at this time, can perform a phase shift operation on the qubit at the left child node position and the qubit at the right child node position.

[0063] Step 708: Operate a two-qubit swap gate between the first target child node qubit and the second target child node qubit, where the second target child node qubit is a child node qubit of the first target child node qubit, to obtain a swap gate sub-circuit.

[0064] Here, the second target child node qubit is a child node qubit of the first target child node qubit. The second target child node qubit refers to a qubit at a target child node position corresponding to the first target child node qubit as the parent node qubit, and the target child node position may be a left child node position or a right byte position. The swap gate subcircuit refers to a quantum circuit obtained by applying a two-qubit swap gate between the first target child node qubit and the second target child node qubit. The parent node qubit refers to a qubit at a parent node position, and the parent node position may be a parent node position corresponding to an intermediate node position of a binary tree or a parent node position corresponding to a leaf node position.

[0065] Specifically, the electronic device operates a two-qubit swap gate between the first target child node qubit and the second target child node qubit to obtain a swap gate subcircuit, i.e., the electronic device realizes a two-qubit swap gate between the first target child node qubit and the second target child node qubit, and is then able to perform a qubit swap operation on the qubit of the first target child node and the qubit of the second target child node.

[0066] In one embodiment, when the first target child node qubit is a qubit at a left child node position corresponding to a parent node qubit, the second target child node qubit is a qubit at a left child node position corresponding to the first target child node qubit. When the first target child node qubit is a qubit at a right child node position corresponding to a parent node qubit, the second target child node qubit is a qubit at a right child node position corresponding to the first target child node qubit. Here, the parent node qubit may be a root node qubit or a non-root node qubit, for example, the parent node qubit may be a middle node qubit.

[0067] Step 710: The child node qubit is made the root node qubit, and a two-qubit phase shift gate is applied between the child node qubit corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and the process returns to the step of obtaining a phase shift gate subcircuit.

[0068] Here, the leaf node quantum bit refers to the quantum bit at the leaf node position in the binary tree.

[0069] Specifically, after obtaining the swap gate subcircuit, the electronic device determines whether the child node qubit is a leaf node qubit, i.e., determines whether the second target child node qubit is a leaf node qubit, i.e., determines whether a child node qubit corresponding to the second target child node qubit still exists. When there is no child node qubit corresponding to the second target child node qubit, the second target child node qubit is indicated as a leaf node qubit, and when there is a child node qubit corresponding to the second target child node qubit, the second target child node qubit is indicated as not being a leaf node qubit. When the child node qubit is not a leaf node qubit, the child node qubit is set as a root node qubit and a two-qubit phase shift gate is applied between the child node qubits corresponding to the root node qubit, and the process returns to the step of obtaining a phase shift gate subcircuit. That is, the electronics performs an iteration, taking a child node qubit as a parent node qubit, then operates a two-qubit phase-shift gate between the two child node qubits of the parent node qubit to obtain a phase-shift gate sub-circuit, until the child node qubit becomes a leaf node qubit, at which point the electronics completes the iteration, obtaining each phase-shift gate sub-circuit and each swap gate sub-circuit.

[0070] Step 712: A two-qubit phase-shift gate under the path restriction is applied between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and a one-qubit phase-shift gate is applied to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit.

[0071] Here, the parent node qubit refers to the qubit at the parent node position corresponding to the leaf node position. The leaf phase-shift gate subcircuit refers to a quantum circuit obtained by applying a two-qubit phase-shift gate under a path restriction between the leaf node qubit and the corresponding parent node qubit. The one-qubit phase-shift subcircuit refers to a quantum circuit obtained by applying a one-qubit phase-shift gate to the leaf node qubit.

[0072] Specifically, the electronic device determines that the child node qubit is a leaf node qubit. At this time, the iteration is completed, and the leaf node qubit is then processed, i.e., a two-qubit phase-shift gate under the path restriction is applied between the leaf node qubits corresponding to the parent node qubits in the target qubit set, to obtain a leaf phase-shift gate subcircuit. That is, a two-qubit phase-shift gate under the path restriction is realized between the leaf node qubits where the parent node qubit exists. And a one-qubit phase-shift gate is applied to the leaf node qubit, to obtain a one-qubit phase-shift subcircuit, that is, a one-qubit phase-shift gate is realized in the leaf node qubit.

[0073] STEP 714: The inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit are combined to form a quantum state preparation circuit.

[0074] Here, the quantum state preparation circuit refers to the quantum state preparation circuit corresponding to the generated initial vector. When it is necessary to generate a quantum state preparation circuit for another classical data vector, the parameters in the quantum state preparation circuit are updated using the other classical data vector to obtain the quantum state preparation circuit corresponding to the other classical data vector.

[0075] Specifically, the electronic device combines an inverting gate sub-circuit, a phase shifting gate sub-circuit, a swap gate sub-circuit, a leaf phase shifting gate sub-circuit, and a one qubit phase shifting sub-circuit to obtain a quantum state preparation circuit.

[0076] The method for generating the quantum state preparation circuit includes determining a target qubit set under the binary tree constraint, applying a one-qubit inversion gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain an inversion gate subcircuit, applying a two-qubit phase shift gate between the child node qubit corresponding to the root node qubit to obtain a phase shift gate subcircuit, and applying a two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, where the second target child node qubit is a child node qubit of the first target child node qubit, and returning to the step of applying the two-qubit phase shift gate between the child node qubit corresponding to the root node qubit until the child node qubit becomes a leaf node qubit to obtain a phase shift gate subcircuit. operating the two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to the parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and operating the one-qubit phase-shift gate on the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; operating the circuit depths of the target one-qubit flip gate, the target one-qubit phase-shift gate, the target two-qubit swap gate, and the target two-qubit phase-shift gate under the path restriction on the target qubit under the binary tree restriction, wherein none of the path restrictions under the binary tree restriction cross; thereby significantly reducing the circuit depth of the resulting quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit; and then preparing a quantum state using the target quantum state preparation circuit with the reduced circuit depth, effectively reducing the time for quantum state preparation and improving the operation efficiency of quantum computing.

[0077] In one embodiment, step 702, i.e., obtaining a two-qubit swap gate and a two-qubit phase-shift gate under path constraints, includes the steps of: The method includes obtaining a one-qubit gate and a controlled-NOT gate under the path restriction, and combining the one-qubit gate and the controlled-NOT gate under the path restriction to form a two-qubit swap gate and a two-qubit phase shift gate under the path restriction.

[0078] Here, the one-qubit gate refers to a quantum gate that operates on one qubit, including, but not limited to, a one-bit quantum inversion gate and a one-bit quantum phase shifter. The controlled NOT gate under path restriction refers to a CNOT gate under path restriction.

[0079] Specifically, the electronic device may obtain a one-qubit gate and a controlled NOT gate under the path restriction from the database, and then combine the one-qubit gate and the controlled NOT gate under the path restriction to obtain a two-qubit swap gate and a two-qubit phase shift gate under the path restriction. Here, the combining may be connecting different quantum gates according to a connection method of the quantum circuit. In one embodiment, the electronic device may obtain a required number of one-qubit gates and a controlled NOT gate under the path restriction based on the number of one-qubit gates and controlled NOT gates under the path restriction required when establishing a two-qubit swap gate, and then combine each one-qubit gate and the controlled NOT gate under the path restriction to obtain a two-qubit swap gate. The electronic device may obtain a required number of one-qubit gates and a controlled NOT gate under the path restriction based on the number of one-qubit gates and controlled NOT gates under the path restriction required when establishing a two-qubit phase shift gate under the path restriction, and then combine each one-qubit gate and the controlled NOT gate under the path restriction to obtain a two-qubit phase shift gate under the path restriction.

[0080] In one embodiment, the number of qubits in the target qubit set is 2 n+1 −1, and n is a positive integer equal to or greater than 1. Specifically, the electronic device is n qubits, then 2 n Then, we obtain an auxiliary qubit based on the qubit of n Based on the qubits and auxiliary qubits, we can obtain 2 n+1 -Get one qubit, i.e., get a target qubit set, then get 2 generated on the target qubit set. n The quantum state preparation circuit n The quantum bit quantum state |ψ v An auxiliary qubit is a qubit that is used auxiliary when generating a target qubit set.

[0081] In one embodiment, as shown in FIG. 8, a method for generating a quantum state preparation circuit includes: determining 802 three qubits under the binary tree constraint when n is 1; applying a one-qubit inverting gate to a first target leaf node qubit corresponding to the root node qubit of the three qubits to obtain an inverting gate subcircuit; Step 806: applying a two-qubit phase-shift gate between the leaf-node qubits corresponding to the root-node qubits to obtain a phase-shift gate subcircuit; applying a one-quantum phase-shift gate to the leaf-node qubit to obtain a one-qubit phase-shift subcircuit; and step 810 of combining the inverting gate sub-circuit, the phase shift gate sub-circuit, and the one-qubit phase shift sub-circuit to form a quantum state preparation circuit corresponding to three qubits.

[0082] Specifically, when n is 1, it indicates that a two-qubit circuit is to be generated, and a two-qubit quantum state is prepared using the two-qubit circuit. At this time, the electronic device obtains one ancillary qubit and two qubits to determine three qubits under the binary tree restriction. Next, the electronic device applies a one-qubit inversion gate to a first target leaf node qubit corresponding to the root node qubit among the three qubits to obtain an inversion gate subcircuit. At this time, if it is determined that the child node qubit is already a leaf node qubit, the leaf node qubit is directly processed, that is, a two-qubit phase shift gate is applied between the leaf node qubit corresponding to the root node qubit to obtain a phase shift gate subcircuit. Furthermore, a one-qubit phase shift gate is applied to the leaf node qubit to obtain a one-qubit phase shift subcircuit. Finally, the inversion gate subcircuit, the phase shift gate subcircuit, and the one-qubit phase shift subcircuit are combined to obtain a quantum state preparation circuit when n=1. When n is greater than 1, a two-qubit swap gate is used to operate between the parent node qubit and the child node qubit, then a two-qubit phase-shift gate is operated between the two child node qubits corresponding to the parent node qubit, and further repeated continuously and cyclically, finally obtaining a quantum state preparation circuit when n is greater than 1.

[0083] In the above embodiment, three quantum bits under the binary tree restriction are determined. Then, a one-qubit inversion gate is applied to a first target leaf node quantum bit corresponding to the root node quantum bit among the three quantum bits to obtain an inversion gate subcircuit. A two-qubit phase shift gate is applied between the leaf node quantum bits corresponding to the root node quantum bit to obtain a phase shift gate subcircuit. A one-qubit phase shift gate is applied to the leaf node quantum bit to obtain a one-qubit phase shift subcircuit. The inversion gate subcircuit, the phase shift gate subcircuit, and the one-qubit phase shift subcircuit are combined to form a quantum state preparation circuit corresponding to the three quantum bits. That is, by generating a quantum state preparation circuit under the binary tree restriction, it is possible to avoid the crossing of the path restriction, thereby effectively reducing the circuit depth of the quantum state preparation circuit.

[0084] In one embodiment, the inverting gate subcircuit has a circuit depth of 1, the phase shifting gate subcircuit has a circuit depth of 0(1), the swap gate subcircuit has a circuit depth of 3, the leaf phase shifting gate subcircuit has a circuit depth of 0(1), and the one qubit phase shifting subcircuit has a circuit depth of 1, and the method comprises: The method further includes determining a circuit depth of the quantum state preparation circuit based on circuit depths corresponding to the inverting gate subcircuit, the phase shift gate subcircuit, the swap gate subcircuit, the leaf phase shift gate subcircuit, and the one qubit phase shift subcircuit, respectively, where the circuit depth is 0(n).

[0085] Specifically, when an inverting gate subcircuit contains only one 1-qubit inverting gate, the circuit depth is 1. Under a path restriction with a length of 3, the circuit depth of the phase-shifting gate subcircuit is 0 (1), which means that the length of the path formed by the root node qubit and the two child node qubits is 3. As can be seen based on the circuit realization of the swap gate [Equation 16], the circuit depth of the swap gate subcircuit is 3. Under the binary tree restriction, none of the path restrictions formed by the root node qubit and the two child node qubits cross each other, so all the 2-qubit phase-shifting gates can be realized in parallel, and the depth is still 0 (1). The 1-qubit phase-shifting subcircuit is composed of 1-qubit gates acting on different qubits, so the circuit depth is 1. In this case, we finally obtain that the circuit depth of the quantum state preparation circuit is 0 (n). That is, the depth of the unary-coded quantum state preparation circuit generated in this application under the binary tree restriction is linear in depth. This application proposes that by allowing only CNOT gates to operate on two qubits that have a connecting edge in a binary tree, any unary-encoded 2 n -qubit quantum state |ψ v > is a circuit with depth 0(n) n -qubit circuits. In this application, we only allow the use of any 1-bit quantum gates and CNOT gates in quantum circuits. That is, by only allowing CNOT gates to operate on two qubits that have a connecting edge in a binary tree, quantum circuits under the path restriction will not cross each other, thereby significantly reducing the circuit depth of the quantum state preparation circuits generated in this application.

[0086]

number

[0087] In one embodiment, the first target child node qubit includes a first left child node qubit, and the second target child node qubit includes a second left child node qubit; Applying a one-qubit inverting gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit in Step 704 includes: Applying a one-qubit inverting gate to a first left child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit.

[0088] Here, the first left child node quantum bit refers to the quantum bit at the left node position of the two child nodes corresponding to the root node quantum bit.

[0089] Specifically, the electronics can operate a one-qubit flip gate on the first left child node qubit to obtain an inverting gate subcircuit, i.e., realize a qubit flip gate at the first left child node qubit, i.e., perform a qubit flip operation at the first left child node position.

[0090] Step 708 of operating a two-qubit swap gate between the first target child node qubit and the second target child node qubit to obtain a swap gate subcircuit includes: Operating a two-qubit swap gate between the first left child node qubit and the second left child node qubit to obtain a swap gate subcircuit.

[0091] Here, the second left child node quantum bit refers to the quantum bit at the left node position of the two child nodes corresponding to the first left child node quantum bit.

[0092] Specifically, the electronic device can operate a two-qubit swap gate between the first left child node qubit and the second left child node qubit to obtain a swap gate subcircuit, i.e., realize a two-qubit swap gate between the first left child node qubit and the second left child node qubit, i.e., perform a qubit swap operation on the first left child node qubit and the second left child node qubit.

[0093] In the above embodiment, the electronic device applies a 1-qubit inversion gate to a qubit of a child node, and applies a 2-qubit swap gate between the qubits of the same node, thereby avoiding the problem of path crossing under the binary tree constraint and thereby improving the accuracy of the obtained quantum circuit.

[0094] In one embodiment, the first target child node qubit includes a first right child node qubit and the second target child node qubit includes a second right child node qubit; Applying a one-qubit inverting gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit in Step 704 includes: Applying a one-qubit inverting gate to a first right child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit.

[0095] Here, the first right child node quantum bit refers to the quantum bit at the right node position of the two child nodes corresponding to the root node quantum bit.

[0096] Specifically, the electronic device can operate a one-qubit flip gate on the first right child node qubit to obtain an inverting gate subcircuit, i.e., realize a qubit flip gate at the first right child node qubit, i.e., perform a qubit flip operation at the first right child node location.

[0097] Step 708 of operating a two-qubit swap gate between the first target child node qubit and the second target child node qubit to obtain a swap gate subcircuit includes: Operating a two-qubit swap gate between the first right child node qubit and the second right child node qubit to obtain a swap gate subcircuit.

[0098] Here, the second right child node quantum bit refers to the quantum bit at the right node position of the two child nodes corresponding to the first right child node quantum bit.

[0099] Specifically, when the electronic device applies a two-qubit swap gate to a target child node qubit, the electronic device must apply the two-qubit swap gate between the target child node qubit and a child node qubit at the same position to ensure the accuracy of the resulting swap gate subcircuit, i.e., to realize a two-qubit swap gate between the first right child node qubit and the second right child node qubit, i.e., to perform a qubit swap operation on the first right child node qubit and the second right child node qubit.

[0100] In the above embodiment, the electronic device applies a 1-qubit inversion gate to a qubit of a child node, and applies a 2-qubit swap gate between the qubits of the same node, thereby avoiding the problem of path crossing under the binary tree constraint and thereby improving the accuracy of the obtained quantum circuit.

[0101] In one specific embodiment, the specific definition of the one-ary encoded quantum state preparation problem under the binary tree restriction is as follows. Given an arbitrary complex vector [Equation 17] that satisfies ||v||2=1, and an initial state [Equation 18], we can solve the problem by dividing the vector into two parts as shown in [Equation 19]. n Prepare the quantum state of the bit.

[0102]

number

number

number

[0103] The structure of the unary-encoded quantum state preparation circuit under the binary tree restriction is described as follows.

[0104] First, 2 under the binary tree restriction n+1 -Number one qubit.

[0105] 1. The qubit at the binary tree root node is marked as [number 20], where [number 21] represents the empty string. At this time, the root node of the binary tree is at the 0th layer of the binary tree.

[0106]

number

number

[0107] 2. For any 0≦k≦n-1 and x∈{0,1} k At the kth layer of the binary tree, x The left child node of is q x0 and the right child node is marked as q x1 and is marked.

[0108] The initial state of all the above quantum bits is |0>. Any unary quantum state may be as follows [Equation 22].

[0109]

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[0110]

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[0111] Next, we generate a one-ary encoded quantum state preparation circuit under the binary tree restriction. The construction process is as follows.

[0112] Step 0: A one-bit quantum gate X is applied to the quantum bit q0.

[0113] Step 1: Step 1.1: Operate a two-qubit phase-shift gate [Equation 25] under the restriction of the path [Equation 24], where [Equation 26] and [Equation 27].

[0114]

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[0115] Step 1.2: q0 and q 00 By applying a two-qubit exchange gate [Equation 28] to q1 and q 10 An exchange gate [equation 29] is applied on the top.

[0116]

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[0117] Step 2: Step 2.1: Route q 00 -q0-q 01 A two-qubit phase-shift gate

[30] operates under the restriction of cos(2α0)=v 00 / v0 and sin(2α0)=v 01 / v0. Path q 10 -q1-q 11 A two-qubit phase-shift gate [Equation 31] is operated under the restriction of cos(2α1)=v 10 / v1 and sin(2α1)=v 11 / v1.

[0118]

number

number

[0119] Step 2.2:q 00 , and q 000 By applying a two-qubit exchange gate [Equation 32] to 01 , and q 010 By applying a two-qubit exchange gate [Equation 33] to 10 , and q 100 By applying a two-qubit exchange gate [Equation 34] to 11 , and q 110 A two-qubit exchange gate [Equation 35] is applied on the

[0120]

number

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[0121] Step j (2≦j≦n-1): Step j.1: For all z∈{0,1} j-1 For route q z0 -q z -q z1 A two-qubit phase-shift gate [Equation 36] is operated under the restriction of cos(2α z )=v z0 / v z , and sin(2α z )=v z1 / v z It is.

[0122]

number

[0123] Step j.2: For all z∈{0,1} j-1 About, Q z0 , and q z00 By applying a two-qubit exchange gate [Equation 37] to z1 , and q z10 A two-qubit exchange gate [Equation 38] is applied on the

[0124]

number

number

[0125] Step n: Step n.1: For all z∈{0,1} n-1 For route q z0 -q z -q z1 A two-qubit phase-shift gate [Equation 39] is operated under the restriction of cos(2α z )=v z0 / v z , and sin(2α z )=vz1 / v z It is.

[0126]

number

[0127] Step n.2: For all x∈{0,1} n About, Q x On the top, one quantum phase shift gate R(θ x ) is applied.

[0128] We will explain the accuracy of the unary-coded quantum state preparation circuit structure under the above binary tree restriction. According to the above structure, the following [Numerical formula 40] can be seen.

[0129]

number

[0130] Since a unary encoded quantum state is finally obtained, the accuracy of the quantum circuit is therefore ensured.

[0131] We explain the circuit depth of the unary-coded quantum state preparation circuit structure under the above binary tree restriction.

[0132] 1, Step 0: It contains only one 1-bit quantum gate, the X gate, and the circuit depth is 1.

[0133] 2. Step 1: As can be seen from the realization of a circuit under the path restriction of a 2-bit rotate gate in the realization of the four subcircuits in this application, in step 1.1, under the path restriction of length 3, [Number 41] can be realized by a circuit with a depth of 0 (1). As can be seen from the realization of a 2-qubit swap gate in the realization of the four subcircuits in this application, step 1.2 can be realized by a circuit with a depth of 3.

[0134]

number

[0135] 3. Step j (2≦j≦n-1): For all z∈{0,1} j-1 As can be seen from the circuit realization under the path restriction of the two-qubit rotation gate in the realization of the four subcircuits in this application, z0 -q z -q z1 The [Equation 42] gate under the constraint can be realized by a circuit whose depth is 0(1). And since none of these path constraints cross, all the two-qubit rotate gates in step j.1 can be realized in parallel and the depth is still 0(1). As can be seen from the realization of the two-qubit swap gate in the four subcircuit realizations in this application, step j.2 can be realized by a circuit whose depth is 3.

[0136]

number

[0137] 4. Step n: For all z∈{0,1} n-1 As can be seen from the circuit realization under the path restriction of the two-qubit rotation gate in the realization of the four subcircuits in this application, z0 -q z -q z1 The [Equation 43] gate under the constraint can be realized by a circuit whose depth is 0(1). And because none of these path constraints cross, all the 2-qubit rotate gates in step n.1 can be realized in parallel, so the depth is still 0(1). Because step n.2 consists of 1-bit quantum gates acting on different qubits, the circuit depth is 1.

[0138]

number

[0139] As can be seen, the circuit depth of the unary-encoded quantum state preparation circuit is 0(n); i.e., by allowing only CNOT gates to operate on two qubits that have a connecting edge in the binary tree, no path restrictions cross, thereby significantly reducing the circuit depth of the generated quantum state preparation circuit.

[0140] In one embodiment, as shown in FIG. 9 , after step 714, i.e., after the step of combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit, the method further includes steps 902 to 906.

[0141] Step 902: Get a target data vector.

[0142] Here, the target data vector refers to a vector corresponding to the target data, and the target data is classical data, which may be text data, image data, video data, audio data, etc. The target data is data that needs to prepare a corresponding quantum state.

[0143] Specifically, the electronic device obtains a target data vector that needs to prepare a quantum state. The electronic device may obtain the target data vector from a database. The electronic device may obtain the target data vector uploaded from a terminal. The electronic device may further obtain the target data vector from a service side.

[0144] Step 904: Determine a qubit operator based on the target data vector, and update the qubit quantum gate in the quantum state preparation circuit based on the qubit operator to obtain a target quantum state preparation circuit corresponding to the target data vector.

[0145] Here, the quantum bit operator is obtained after determining a parameter corresponding to the quantum bit gate based on the target data vector, and the quantum bit operator includes, but is not limited to, a two-qubit phase shift operator and a one-qubit phase shift operator, etc. The two-qubit phase shift operator is obtained after determining a phase shift parameter corresponding to the two-qubit phase shift gate based on the target data vector. The one-qubit phase shift operator is obtained after determining a phase shift parameter corresponding to the one-qubit phase shift gate based on the target data vector, and the phase shift parameter is a preset parameter that can be set according to needs. The target quantum state preparation circuit refers to a quantum state preparation circuit corresponding to the target data vector, and is used to prepare a quantum state corresponding to the target data vector.

[0146] Specifically, the electronics determines a qubit operator based on the target data vector, and then uses the qubit operator to update a qubit quantum gate in the quantum state preparation circuit to obtain a target quantum state preparation circuit corresponding to the target data vector, i.e., the electronics uses the qubit operator corresponding to the target data vector to replace the same qubit quantum gate in the quantum state preparation circuit, thereby obtaining a quantum state preparation circuit with an updated quantum gate, i.e., a target quantum state preparation circuit corresponding to the target data vector.

[0147] Step 906: A preset initial quantum state is input to a target quantum state preparation circuit to perform quantum state preparation, and a quantum state corresponding to the target data vector is obtained.

[0148] Here, the preset initial quantum state refers to a preset initial quantum state, and the initial quantum state may be [Mathematical Expression 44].

[0149]

number

[0150] Specifically, the electronic device inputs a preset initial quantum state to a target quantum state preparation circuit, which performs a quantum operation using a quantum bit operator, and finally obtains a quantum state corresponding to the output target data vector.

[0151] In the above embodiment, the target data vector is used to determine the quantum bit operator, and the quantum bit quantum gate in the quantum state preparation circuit is updated according to the quantum bit operator to obtain the target quantum state preparation circuit corresponding to the target data vector, and then the preset initial quantum state is input into the target quantum state preparation circuit to perform quantum state preparation and obtain the quantum state corresponding to the target data vector. That is, the quantum bit operator is used to update the quantum state preparation circuit, the target quantum state preparation circuit is obtained, and then quantum state preparation is performed, thereby improving the efficiency of obtaining the quantum state corresponding to the target data vector.

[0152] In one embodiment, as shown in FIG. 10, after the step of combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit, the method further includes steps 1002 to 1008.

[0153] Step 1002: Obtain a recommended preference data vector.

[0154] Here, the recommended preference data vector refers to a vector corresponding to the recommended preference data, which is used to characterize the preference information of the target to be recommended.

[0155] Specifically, the electronic device may obtain recommendation preference data from a recommendation service system, and then vectorize the recommendation preference data to obtain a recommendation preference data vector.

[0156] Step 1004: Determine a qubit operator based on the recommended preference data vector, and update the qubit quantum gate in the quantum state preparation circuit based on the qubit operator to obtain a recommended quantum state preparation circuit corresponding to the recommended preference data vector.

[0157] Here, the recommended quantum state preparation circuit is a quantum circuit used to prepare a quantum state corresponding to the recommended preference data vector.

[0158] Specifically, the electronic device uses the recommended preference data vector to perform calculations to obtain a qubit operator corresponding to the recommended preference data vector, including but not limited to a two-qubit phase shift operator, a one-qubit phase shift operator, etc. The qubit operator is then used to update a qubit quantum gate in the quantum state preparation circuit to obtain a recommended quantum state preparation circuit corresponding to the recommended preference data vector. That is, the electronic device uses the qubit operator corresponding to the recommended preference data vector to replace the same qubit quantum gate in the quantum state preparation circuit, thereby obtaining a quantum state preparation circuit with an updated quantum gate. That is, a recommended quantum state preparation circuit corresponding to the recommended preference data vector is obtained.

[0159] Step 1006: The preset initial quantum state is input to a recommended quantum state preparation circuit to perform quantum state preparation, and obtain a quantum state corresponding to the recommended preference data vector.

[0160] Here, the preset initial quantum state refers to a preset initial quantum state, and the initial quantum state may be [Mathematical Expression 45].

[0161]

number

[0162] Specifically, the electronic device inputs a preset initial quantum state to a recommended quantum state preparation circuit, which performs a quantum operation using a quantum bit operator, and finally obtains a quantum state corresponding to the output recommended preference data vector.

[0163] Step 1008: Perform a quantum operation based on the quantum state corresponding to the recommended preference data vector and the quantum singular value estimation algorithm circuit to obtain a target quantum state, and perform a quantum measurement based on the target quantum state to obtain a recommended result corresponding to the recommended preference data vector.

[0164] Here, the quantum singular value estimation algorithm circuit refers to a quantum circuit corresponding to the quantum singular value estimation algorithm. The target quantum state refers to a quantum state output after performing a quantum operation on a quantum state corresponding to a recommended preference data vector by the quantum singular value estimation algorithm circuit. The quantum measurement can cause a quantum collapse and change uncertainty into certainty. A definite value after collapse can be obtained by the quantum measurement. The recommendation result corresponding to the recommended preference data vector refers to a result of whether or not to make a recommendation corresponding to the recommended preference data vector, and the recommendation result includes making a recommendation and not making a recommendation.

[0165] Specifically, the electronic device inputs the quantum state corresponding to the recommended preference data vector into a quantum singular value estimation algorithm circuit to perform quantum operation, obtains an output target quantum state, and then performs quantum measurement on the target quantum state, i.e., performs a measurement operation of a square operation. When a recommendation result corresponding to the recommended preference data vector is obtained and the recommendation result is to make a recommendation, the recommendation information can be sent to the recommended target terminal corresponding to the recommended preference data. When the recommendation result is to not make a recommendation, no processing is performed, i.e., there is no need to send the recommendation information to the recommended target terminal corresponding to the recommended preference data.

[0166] In the above embodiment, the recommended preference data vector is used in a recommended quantum state preparation circuit to perform quantum state preparation, thereby obtaining a quantum state corresponding to the recommended preference data vector, and a quantum state preparation circuit with reduced circuit depth is used to perform quantum state preparation, thereby improving the efficiency of obtaining a quantum state corresponding to the recommended preference data vector. Then, a quantum singular value estimation algorithm circuit is used to perform quantum operation to obtain a target quantum state, and quantum measurement is performed according to the target quantum state to obtain a recommended result corresponding to the recommended preference data vector, and then a quantum test is performed using the quantum state corresponding to the recommended preference data vector, thereby improving the efficiency of obtaining a recommended result.

[0167] In one specific embodiment, in a quantum recommendation system, classical data is represented as a preference matrix P=[P ij ] n×m Before running the quantum recommendation system, the data P i =[P i1 ,P i2 ,…,P im ] must be loaded into the corresponding quantum state

[46] , where {|j>: j=1,...,m} represents a set of orthogonal bases. In addition to quantum recommendation systems, quantum algorithms such as quantum support vector machine solving of quantum linear simultaneous equations, quantum clustering algorithms, and Hamiltonian simulations also require the conversion of classical data into quantum data by quantum state preparation circuits.

[0168]

number

[0169] In one embodiment, a quantum state preparation method is provided, as shown in Fig. 11. Taking the method as an example applied to the electronic device in Fig. 1, the method includes the following steps:

[0170] Step 1102: Obtain a target data vector, and obtain a target 1-qubit inversion gate, a target 1-qubit phase shift gate, a target 2-qubit swap gate, and a target 2-qubit phase shift gate under path restriction based on the target data vector.

[0171] Here, the target data vector refers to a vector corresponding to the target data, and the target data is classical data. The classical data may be text data, image data, video data, and audio data, etc. The target data is data for which a corresponding quantum state needs to be prepared. The target 1 qubit flip gate refers to a 1 qubit flip gate corresponding to the target data vector. The target 1 qubit phase shift gate refers to a 1 qubit phase shift gate corresponding to the target data vector. The target 2 qubit swap gate refers to a 2 qubit swap gate corresponding to the target data vector. The target 2 qubit phase shift gate refers to a 2 qubit phase shift gate corresponding to the target data vector.

[0172] Specifically, the electronic device obtains a target data vector that needs to prepare a quantum state. The electronic device may obtain the target data vector from a database. The electronic device may obtain a target data vector uploaded from a terminal. The electronic device may further obtain the target data vector from a service side. A target 1-qubit inversion gate, a target 1-qubit phase shift gate, a target 2-qubit swap gate, and a target 2-qubit phase shift gate under a path restriction are obtained based on the target data vector.

[0173] Step 1102: Determine a target qubit set under the binary tree constraint, and apply a target one-qubit inversion gate to a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain a target inversion gate sub-circuit.

[0174] Here, the target inversion gate subcircuit refers to a quantum circuit obtained by applying a target one-qubit inversion gate to a first target child node qubit.

[0175] Specifically, the electronic device takes each qubit and uses it to determine a target qubit set under the binary tree constraint, then operates a target one-qubit flip gate on a first target child node qubit corresponding to the root node qubit in the target qubit set to obtain a target one-qubit flip gate subcircuit, i.e., realizes a target one-qubit flip gate at the first target child node qubit corresponding to the root node qubit in the target qubit set.

[0176] Step 1104: A target two-qubit phase-shift gate is applied between the child node qubits corresponding to the root node qubit to obtain a target phase-shift gate sub-circuit.

[0177] Here, the target phase shift gate subcircuit is a quantum circuit obtained by applying a target two-qubit phase shift gate between a qubit located at the left child node position and a qubit located at the right child node position of the root node qubit.

[0178] Specifically, the electronic device operates a two-qubit phase-shift gate under the path restriction between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate subcircuit, i.e., to realize a two-qubit phase-shift gate between a qubit at the left child node position and a qubit at the right child node position. Here, since the two-qubit phase-shift gate is realized by combining a one-qubit gate and a CNOT gate under the path restriction between the qubit at the left child node position and the root node qubit, the phase-shift gate subcircuit is obtained by operating a CNOT gate under the path restriction between the qubit at the left child node position and the root node qubit, and operating a CNOT gate under the path restriction between the qubit at the right child node position and the root node qubit, and then combining the one-qubit gate on the qubit at the left child node position, the qubit at the right child node position, and the root node qubit.

[0179] Step 1106: Operate a target two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a target swap gate subcircuit. The second target child node qubit is a child node qubit of the first target child node qubit.

[0180] Here, the target swap gate subcircuit refers to a quantum circuit obtained by applying a target two-qubit swap gate between a first target child node qubit and a second target child node qubit.

[0181] Specifically, the electronics operates a target two-qubit swap gate between the first target child node qubit and the second target child node qubit to obtain a target swap gate sub-circuit, i.e., the electronics realizes a target two-qubit swap gate between the first target child node qubit and the second target child node qubit.

[0182] Step 1108: The child node qubit is taken as the root node qubit, and the target 2-qubit phase shift gate is applied between the child node qubit corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and the process returns to the step of obtaining a target phase shift gate subcircuit.

[0183] Specifically, the electronics performs the step of returning to the step of obtaining a target phase-shift gate subcircuit by operating a target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit, with the child node qubit as the root node qubit, until the child node qubit becomes a leaf node qubit. At this time, the electronics completes the iteration, and continues to perform the iteration when the child node qubit is not a leaf node qubit. When completing the iteration, the electronics obtains each target phase-shift gate subcircuit and each target swap gate subcircuit.

[0184] Step 1110: A target 2-qubit phase shift gate under the path restriction is applied between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase shift gate sub-circuit, and a target 1-qubit phase shift gate is applied to the leaf node qubit to obtain a target 1-qubit phase shift sub-circuit.

[0185] Here, the term "target leaf phase-shift gate subcircuit" refers to a quantum circuit obtained by applying a targeted two-qubit phase-shift gate under a path restriction between a leaf node qubit corresponding to a parent node qubit, and the term "one-qubit phase-shift subcircuit" refers to a quantum circuit obtained by applying a targeted one-qubit phase-shift gate to a leaf node qubit.

[0186] Specifically, when the electronic device determines that the child node quantum bit is a leaf node quantum bit, it operates a target 2-qubit phase shift gate under a path restriction between the leaf node quantum bit corresponding to the parent node quantum bit in the target quantum bit set to obtain a target leaf phase shift gate subcircuit, and operates a target 1 quantum phase shift gate on the leaf node quantum bit to obtain a target 1-qubit phase shift subcircuit.

[0187] Step 1112: The target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit are combined to form a target quantum state preparation circuit corresponding to the target data vector.

[0188] Here, the target quantum state preparation circuit corresponding to the target data vector refers to the quantum state preparation circuit corresponding to the generated target data vector.

[0189] Specifically, the electronics combine a target invert gate sub-circuit, a target phase shift gate sub-circuit, a target swap gate sub-circuit, a target leaf phase shift gate sub-circuit, and a target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector.

[0190] Step 1114: A preset initial quantum state is input to a target quantum state preparation circuit to perform quantum state preparation, and a quantum state corresponding to the target data vector is obtained.

[0191] Here, the preset initial quantum state refers to a preset initial quantum state, and the initial quantum state may be [Mathematical Expression 47].

[0192]

number

[0193] Specifically, the electronic device inputs a preset initial quantum state to a target quantum state preparation circuit, which performs a quantum operation using a quantum bit operator, and finally obtains a quantum state corresponding to the output target data vector.

[0194] The quantum state preparation method includes obtaining a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under path restriction corresponding to a target data vector; then using the target 1 qubit flip gate, the target 1 qubit phase shift gate, the target 2 qubit swap gate, and the target 2 qubit phase shift gate under path restriction to generate a target quantum state preparation circuit corresponding to the target data vector with a target qubit set under binary tree restriction; and applying circuit depths of the target 1 qubit flip gate, the target 1 qubit phase shift gate, the target 2 qubit swap gate, and the target 2 qubit phase shift gate under path restriction to the target qubit under binary tree restriction, wherein none of the path restrictions under the binary tree restriction cross each other, thereby significantly reducing the circuit depth of the obtained quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit. Next, the predetermined initial quantum state is input into a target quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the target data vector, i.e., by preparing the quantum state using a target quantum state preparation circuit with reduced circuit depth, the time for quantum state preparation can be effectively reduced and the operating efficiency of quantum computing can be improved, thereby improving the efficiency of quantum state preparation.

[0195] In one specific embodiment, regarding the generation of a quantum state preparation circuit that is unary-coded under the binary tree restriction, specifically, the vector to be prepared is obtained as follows [Equation 48].

[0196]

number

[0197] Obtain the two-qubit operator corresponding to the vector v to be prepared as follows:

[0198] The quantum bit operator corresponding to [Number 49] is [Number 50], the quantum bit operator corresponding to [Number 51] is [Number 52], the quantum bit operator corresponding to [Number 53] is [Number 54], the quantum bit operator corresponding to [Number 55] is [Number 56], the quantum bit operator corresponding to [Number 57] is [Number 58], and the quantum bit operator corresponding to [Number 59] is [Number 60].

[0199]

number

number

number

number

number

number

number

number

number

number

number

number

[0200] FIG. 12 is a schematic diagram of the realization of a unary-coded quantum state preparation circuit corresponding to a vector v to be prepared, specifically as follows.

[0201] Step 0: Apply an X gate to qubit q0.

[0202] Step 1: Step 1.1: A two-qubit rotation gate [Equation 62] acting on q0 and q1 under the restriction of the path [Equation 61] To achieve this.

[0203]

number

number

[0204] Step 1.2: q0 and q 00 Applying [Number 63] to the above, q1 and q 10 Apply [number 64] on top.

[0205]

number

number

[0206] Step 2: Step 2.1: Simultaneously, route q 00 -q0-q 01 Under the restriction of q 00 , and q 01 We realize a two-qubit rotation gate

[65] that operates on the path q 10 -q1-q 11 Under the restriction of q 10 , and q11 We realize a two-qubit rotation gate

[66] that operates on

[0207]

number

number

[0208] Step 2.2: At the same time, q 00 , and q 000 Applying [Number 67] to the above, q 01 , and q 010 Applying [Number 68] to the above, q 10 , and q 100 Applying [Number 69] to the above, q 11 , and q 110 Apply [number 70] on top.

[0209]

number

number

number

number

[0210] Step 3: Step 3.1: Simultaneously route q 000 -q 00 -q 001 Under the restriction of q 000 , and q 001 We realize a two-qubit rotation gate [Eq. 71] that operates on the path q 010 -q 01 -q 011 Under the restriction of q 010 , and q 011 We realize a two-qubit rotation gate [Eq. 72] that operates on the path q 100 -q 10 -q101 Under the restriction of q 100 , and q 101 We realize a two-qubit rotation gate [Eq. 73] that operates on the path q 110 -q 11 -q 111 Under the restriction of q 110 , and q 111 We realize a two-qubit rotation gate

[74] that operates on

[0211]

number

number

number

number

[0212] Step 3.1: For all x∈{0,1} 3 At the same time, the qubit q x On the top, we have a 1-bit quantum gate R(θ x ) is applied.

[0213] In this way, a unary-coded quantum state preparation circuit corresponding to the vector v to be prepared is obtained, and the circuit depth of the unary-coded quantum state preparation circuit is 0(n), which effectively reduces the circuit depth of the quantum state preparation circuit. Next, the preset initial quantum state is input into the unary-coded quantum state preparation circuit corresponding to the vector v to be prepared to perform quantum state preparation, and a quantum state corresponding to the vector v to be prepared is obtained, which further effectively reduces the time for quantum state preparation, improves the operation efficiency of quantum calculation, and thereby improves the efficiency of quantum state preparation.

[0214] In one specific embodiment, the quantum state preparation method can be applied to a quantum state preparation scene corresponding to image data. Specifically, the electronic device obtains image data, and then performs vectorization on the image data to obtain an image vector. Then, a quantum preparation circuit generated using the quantum state preparation circuit generation method of the present application is obtained. Then, the image vector is used to calculate quantum bit operators, including a two-qubit phase shift operator and a one-qubit phase shift operator. Then, the quantum bit operators are used to update corresponding quantum gates in the quantum preparation circuit, for example, a two-qubit phase shift operator can be used to update a two-qubit phase shift gate in the quantum preparation circuit, and a one-qubit phase shift operator can be used to update a one-qubit phase shift gate in the quantum preparation circuit. After completing the update of all quantum gates that need to be updated using the quantum bit operators in the quantum preparation circuit, a target quantum state preparation circuit corresponding to the image vector is obtained. Finally, the initial quantum state is input into the target quantum state preparation circuit corresponding to the image vector to prepare a quantum state, and an output of the target quantum state preparation circuit is obtained, that is, a quantum state corresponding to the image vector is obtained. Then, a quantum operation is performed using the quantum state corresponding to the image vector to obtain a processing result of the quantum state corresponding to the image vector, thereby greatly improving the processing efficiency of image data.

[0215] It should be understood that although the steps in the flowcharts according to the above embodiments are displayed in order according to the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this specification, the execution of these steps is not limited to a strict order, and these steps may be executed in other orders. Furthermore, at least some of the steps in the flowcharts according to the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The execution order of these steps or stages is also not necessarily performed in order, and they may be executed alternately or in alternation with other steps or at least some of the steps or stages of other steps.

[0216] Based on the technical idea of ​​the same invention, the embodiment of the present application further provides a quantum state preparation circuit generation device, or a quantum state preparation method, and a quantum state preparation device, which are used to realize the above-mentioned quantum state preparation circuit generation method. The means for solving the problem provided by the device are similar to the means described in the above-mentioned method, so that the specific limitations in one or more embodiments of the quantum state preparation circuit generation device or quantum state preparation device presented below can be referred to the limitations of the above-mentioned quantum state preparation circuit generation method or quantum state preparation method, and therefore duplicated explanations will be omitted here.

[0217] In one embodiment, as shown in FIG. 13 , a quantum state preparation circuit generating apparatus 1300 includes a quantum gate acquisition module 1302, an inversion gate action module 1304, a phase shift gate action module 1306, a swap gate action module 1308, a repetition module 1310, a leaf node action module 1312, and a combination module 1314, where: The quantum gate acquisition module 1302 is used to acquire a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under a path restriction; an inverting gate action module 1304 for determining a target qubit set under the binary tree constraint, and applying a one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; the phase shift gate action module 1306 is used to apply a two-qubit phase shift gate between the child node qubit corresponding to the root node qubit to obtain a phase shift gate subcircuit; a swap gate action module 1308 is used to act a two-qubit swap gate between the first target child node qubit and the second target child node qubit to obtain a swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; the iteration module 1310 is used to return to the step of applying a two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit and obtaining a phase-shift gate subcircuit until the child node qubit becomes a root node qubit and the child node qubit becomes a leaf node qubit; the leaf node action module 1312 is used to act a two-qubit phase-shift gate under a path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and act a one-qubit phase-shift gate on the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; The combination module 1314 is used to combine the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit.

[0218] In one embodiment, the quantum gate acquisition module 1302 is further used for acquiring a one-qubit gate and a controlled-NOT gate under the path restriction, and combining based on the one-qubit gate and the controlled-NOT gate under the path restriction to form a two-qubit swap gate and a two-qubit phase shift gate under the path restriction.

[0219] In one embodiment, the number of qubits in the target qubit set is 2 n+1 −1, and n is a positive integer equal to or greater than 1.

[0220] In one embodiment, the quantum state preparation circuit generating device 1300 includes: The system further includes a generation module for determining three qubits under the binary tree constraint when n is 1, applying a one-qubit inverting gate to a first target leaf node qubit corresponding to the root node qubit of the three qubits to obtain an inverting gate subcircuit, applying a two-qubit phase shift gate between the leaf node qubits corresponding to the root node qubit to obtain a phase shift gate subcircuit, applying a one-qubit phase shift gate to the leaf node qubit to obtain a one-qubit phase shift subcircuit, and combining the inverting gate subcircuit, the phase shift gate subcircuit, and the one-qubit phase shift subcircuit to form a quantum state preparation circuit corresponding to the three qubits.

[0221] In one embodiment, the circuit depth of the inverting gate subcircuit is 1, the circuit depth of the phase shifting gate subcircuit is 0 (1), the circuit depth of the swap gate subcircuit is 3, the circuit depth of the leaf phase shifting gate subcircuit is 0 (1), and the circuit depth of the one qubit phase shifting subcircuit is 1, and the quantum state preparation circuit generating apparatus 1300 is The quantum state preparation circuit further includes a circuit depth determination module used to determine a circuit depth of the quantum state preparation circuit based on the circuit depths corresponding to the inversion gate subcircuit, the phase shift gate subcircuit, the swap gate subcircuit, the leaf phase shift gate subcircuit, and the one qubit phase shift subcircuit, respectively, where the circuit depth is 0(n).

[0222] In one embodiment, the first target child node qubit includes a first left child node qubit, and the second target child node qubit includes a second left child node qubit; The inverting gate operation module 1304 is further used to operate a one-qubit inverting gate on a first left child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit; Swap gate action module 1308 is further used to apply a two-qubit swap gate between the first left child node qubit and the second left child node qubit to obtain a swap gate subcircuit.

[0223] In one embodiment, the first target child node qubit includes a first right child node qubit and the second target child node qubit includes a second right child node qubit; The inverting gate operation module 1304 is further used to operate a one-qubit inverting gate on a first right child node qubit corresponding to the root node qubit in the target qubit set to obtain an inverting gate subcircuit; Swap gate action module 1308 is further used to apply a two-qubit swap gate between the first right child node qubit and the second right child node qubit to obtain a swap gate subcircuit.

[0224] In one embodiment, the quantum state preparation circuit generating device 1300 includes: The quantum state preparation module is used for obtaining a target data vector, determining a quantum bit operator based on the target data vector, updating a quantum bit quantum gate in the quantum state preparation circuit based on the quantum bit operator to obtain a target quantum state preparation circuit corresponding to the target data vector, and inputting a predetermined initial quantum state into the target quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the target data vector.

[0225] In one embodiment, the quantum state preparation circuit generating device 1300 includes: The present invention further includes a quantum recommendation module for obtaining a recommended preference data vector, determining a quantum bit operator based on the recommended preference data vector, updating a quantum bit quantum gate in the quantum state preparation circuit based on the quantum bit operator, and obtaining a recommended quantum state preparation circuit corresponding to the recommended preference data vector, inputting a preset initial quantum state into the recommended quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the recommended preference data vector, performing quantum operations based on the quantum state corresponding to the recommended preference data vector and the quantum singular value estimation algorithm circuit to obtain a target quantum state, and performing quantum measurement based on the target quantum state to obtain a recommended result corresponding to the recommended preference data vector.

[0226] In one embodiment, as shown in FIG. 14 , a quantum state preparation apparatus 1400 is provided, including a target quantum gate acquisition module 1402, a target inversion gate action module 1404, a target phase shift gate action module 1406, a target swap gate action module 1408, a target repetition module 1410, a target leaf node action module 1412, a target combination module 1414, and a preparation module 1416, where: The target quantum gate acquisition module 1402 is used to acquire a target data vector, and acquire a target 1 qubit flip gate, a target 1 qubit phase shift gate, a target 2 qubit swap gate, and a target 2 qubit phase shift gate under path restriction according to the target data vector; a target inverting gate operation module 1404 for determining a target qubit set under the binary tree constraint, and operating a target one-qubit inverting gate on a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inverting gate subcircuit; the target phase shift gate action module 1406 is used to act a target two-qubit phase shift gate between the child node qubit corresponding to the root node qubit to obtain a target phase shift gate subcircuit; a target swap gate action module 1408 is used to act a target two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, where the second target child node qubit is a child node qubit of the first target child node qubit; the target iteration module 1410 is used to return to the step of applying the target two-qubit phase-shift gate between the child node qubit corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and obtain a target phase-shift gate sub-circuit; the target leaf node action module 1412 is used to act a target two-qubit phase-shift gate under a path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and act a target one-qubit phase-shift gate on the leaf node qubit to obtain a target one-qubit phase-shift sub-circuit; a target combination module 1414 for combining the target inverting gate sub-circuit, the target phase shifting gate sub-circuit, the target swapping gate sub-circuit, the target leaf phase shifting gate sub-circuit, and the target one qubit phase shifting sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; The preparation module 1416 is used to input a preset initial quantum state into a target quantum state preparation circuit to perform quantum state preparation, and obtain a quantum state corresponding to the target data vector.

[0227] The quantum state preparation circuit generating device or each module in the quantum state preparation device can be realized in whole or in part by software, hardware, or a combination thereof. Each module may be built into the processor in the electronic device in the form of hardware, or may be independent therefrom, or may be stored in the memory in the electronic device in the form of software, whereby the processor calls and executes the operations corresponding to each module.

[0228] In one embodiment, an electronic device is provided, which may be an industrialized smart device, and its internal structure diagram may be shown in FIG. 15. The electronic device includes a processor, a memory, an input / output interface (abbreviated as Input / Output, I / O), and a communication interface. Here, the processor, the memory, and the input / output interface are connected by a system bus, and the communication interface is connected to the system bus by the input / output interface. Here, the processor of the electronic device is used to provide calculation and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the operation of the operating system and the computer-readable instructions in the non-volatile storage medium. The database of the electronic device is used to store target data vectors. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to connect and communicate with an external terminal through a network. The computer readable instructions when executed by a processor implement a method for generating a quantum state preparation circuit or a quantum state preparation method.

[0229] As will be understood by those skilled in the art, the structure shown in FIG. 15 is merely a block diagram of some structures related to the means of the present application, and does not constitute a limitation on electronic devices to which the means of the present application is applied; a specific electronic device may include more or fewer components than those shown, combine some components, or have a different component arrangement.

[0230] In one embodiment, a quantum chip is provided, comprising a quantum state preparation circuit, the quantum state preparation circuit being realized by the method for generating a quantum state preparation circuit in the present application. The quantum chip can be applied to various smart terminals and in-vehicle devices.

[0231] In one embodiment, an electronic device is further provided, comprising a memory and a processor, the memory having computer-readable instructions stored therein, the processor performing the steps in each of the method embodiments described above when executing the computer-readable instructions.

[0232] In one embodiment, a computer readable storage medium is provided having computer readable instructions stored thereon which, when executed by a processor, perform the steps in each of the method embodiments described above.

[0233] In one embodiment, a computer program product is provided, comprising computer readable instructions which, when executed by a processor, implement the steps in each of the method embodiments described above.

[0234] It is necessary to explain that the user information (including but not limited to user device information and user personal information, etc.) and data (including but not limited to data used for analysis, stored data, and displayed data, etc.) related to this application are all information and data authorized by the user or fully authorized by each party, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant country or region. As for pushed information, the recommended target device can reject it, and advertising push information, etc. can be easily rejected.

[0235] As can be understood by those skilled in the art, the implementation of all or part of the processes in the above embodiment methods may be completed by instructing relevant hardware by computer-readable instructions, and the above computer-readable instructions may be stored in a non-volatile computer-readable storage medium, and the above embodiment methods may include the processes when the computer-readable instructions are executed. Here, any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM (registered trademark)), phase change memory (PCM), graphene memory, etc. The volatile memory may include Random Access Memory (RAM), or an external high-speed cache memory, etc. By way of explanation and not limitation, the RAM may be in a variety of forms, such as Static Random Access Memory (SRAM), or Dynamic Random Access Memory (DRAM). The database according to the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a distributed database based on a blockchain, etc. The processor according to the embodiments provided herein may include, but is not limited to, a general-purpose processor, a central processor, a graphics processor, a digital signal processor, a programmable logic device, and a data processing logic device based on quantum computing, etc.

[0236] Although the technical features of the above embodiments can be combined in any combination, for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features are not contradictory, they should be considered to be within the scope described in this specification.

[0237] It should be understood that the above examples merely show some embodiments of the present application, and the description is relatively specific and detailed, but does not limit the scope of the patent of the present application. It should be noted that a person skilled in the art can make various modifications and improvements without departing from the idea of ​​the present application, all of which are within the scope of protection of the present application. Therefore, the scope of protection of the present application should be in accordance with the scope of the attached claims. [Explanation of symbols]

[0238] 102 Electronic equipment 104 Quantum Chip 1042 Quantum state preparation circuit 1300 generator 1302 Quantum Gate Acquisition Module 1304 Inverted Gate Action Module 1306 Phase Shift Gate Action Module 1308 Swap Gate Action Module 1310 Repetition Module 1312 Leaf Node Action Module 1400 Quantum State Preparation Device 1402 Target Quantum Gate Acquisition Module 1404 Target Inversion Gate Action Module 1406 Target Phase Shift Gating Module 1408 Target Swap Gate Action Module 1410 Target Repetition Module 1412 Target Leaf Node Action Module 1416 Preparation Module

Claims

1. An apparatus for generating a quantum state preparation circuit, the apparatus comprising: A quantum gate acquisition module is used to acquire a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under a path restriction; an inverting gate action module adapted to determine a target qubit set under a binary tree constraint and to apply the one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; a phase-shift gate action module used to apply the two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a phase-shift gate subcircuit; a swap gate action module used to apply the two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit, the second target child node qubit being a child node qubit of the first target child node qubit; a repetition module adapted to operate the two-qubit phase-shift gate between child node qubits corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and to run back and forth to obtain a phase-shift gate subcircuit; a leaf node action module used for operating the two-qubit phase shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase shift gate sub-circuit, and operating the one-qubit phase shift gate on the leaf node qubit to obtain a one-qubit phase shift sub-circuit; and a combination module used to combine the inverting gate subcircuit, the phase shift gate subcircuit, the swap gate subcircuit, the leaf phase shift gate subcircuit, and the one qubit phase shift subcircuit to form a quantum state preparation circuit.

2. 2. The apparatus of claim 1, wherein the quantum gate acquisition module is further used for acquiring a one-qubit gate and a controlled-NOT gate under a path restriction, and combining the one-qubit gate and the controlled-NOT gate under the path restriction to form the two-qubit swap gate and the two-qubit phase shift gate under the path restriction.

3. the number of qubits in the target qubit set is 2n+1−1; 2. The apparatus of claim 1, wherein n is a positive integer greater than or equal to 1.

4. The apparatus comprises:

4. The apparatus of claim 3, further comprising a generation module for: determining three qubits under the binary tree constraint when n is 1; applying the one-qubit inverting gate to a first target leaf node qubit corresponding to a root node qubit of the three qubits to obtain an inverting gate subcircuit; applying the two-qubit phase shift gate between leaf node qubits corresponding to the root node qubits to obtain a phase shift gate subcircuit; applying the one-qubit phase shift gate to the leaf node qubit to obtain a one-qubit phase shift subcircuit; and combining the inverting gate subcircuit, the phase shift gate subcircuit, and the one-qubit phase shift subcircuit to form a quantum state preparation circuit corresponding to the three qubits.

5. the inverting gate subcircuit has a circuit depth of 1, the phase shifting gate subcircuit has a circuit depth of 0 (1), the swap gate subcircuit has a circuit depth of 3, the leaf phase shifting gate subcircuit has a circuit depth of 0 (1), the one qubit phase shifting subcircuit has a circuit depth of 1, and the apparatus 4. The apparatus of claim 3, further comprising a circuit depth determination module adapted to determine a circuit depth of the quantum state preparation circuit based on circuit depths corresponding respectively to the inverting gate subcircuit, the phase shifting gate subcircuit, the swap gate subcircuit, the leaf phase shifting gate subcircuit, and the one qubit phase shifting subcircuit, where the circuit depth is 0(n).

6. the first target child node qubit comprises a first left child node qubit, and the second target child node qubit comprises a second left child node qubit; the inverting gate action module is further used to apply the one-qubit inverting gate to a first left child qubit corresponding to a root qubit in the target qubit set to obtain the inverting gate subcircuit; 2. The apparatus of claim 1 , wherein the swap gate action module is further adapted to actuate the two-qubit swap gate between the first left child node qubit and a second left child node qubit to obtain the swap gate subcircuit.

7. the first target child node qubit includes a first right child node qubit, and the second target child node qubit includes a second right child node qubit; the inverting gate action module is further used to apply the one-qubit inverting gate to a first right child qubit corresponding to a root node qubit in the target qubit set to obtain the inverting gate subcircuit; 2. The apparatus of claim 1 , wherein the swap gate action module is further adapted to actuate the two-qubit swap gate between the first right child node qubit and a second right child node qubit to obtain the swap gate subcircuit.

8. The apparatus comprises:

2. The apparatus of claim 1, further comprising a quantum state preparation module used for obtaining a target data vector, determining a quantum bit operator based on the target data vector, updating a quantum bit quantum gate in the quantum state preparation circuit based on the quantum bit operator to obtain a target quantum state preparation circuit corresponding to the target data vector, and inputting a preset initial quantum state into the target quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the target data vector.

9. The apparatus comprises:

2. The apparatus of claim 1, further comprising a quantum recommendation module for: obtaining a recommended preference data vector; determining a qubit operator based on the recommended preference data vector; updating a qubit quantum gate in the quantum state preparation circuit based on the qubit operator to obtain a recommended quantum state preparation circuit corresponding to the recommended preference data vector; inputting a preset initial quantum state into the recommended quantum state preparation circuit to perform quantum state preparation and obtain a quantum state corresponding to the recommended preference data vector; performing a quantum operation based on the quantum state corresponding to the recommended preference data vector and a quantum singular value estimation algorithm circuit to obtain a target quantum state; and performing a quantum measurement based on the target quantum state to obtain a recommended result corresponding to the recommended preference data vector.

10. 1. A quantum state preparation device, comprising: A target quantum gate acquisition module is used for acquiring a target data vector, and acquiring a target one qubit flip gate, a target one qubit phase shift gate, a target two qubit swap gate, and a target two qubit phase shift gate under a path restriction according to the target data vector; a target inverting gate action module adapted to determine a target qubit set under a binary tree constraint and to apply the target one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inverting gate sub-circuit; a target phase-shift gate action module used to actuate the target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate sub-circuit; a target swap gate action module used to operate the target two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a target swap gate subcircuit, the second target child node qubit being a child node qubit of the first target child node qubit; a target iteration module adapted to operate the target two-qubit phase-shift gate between child node qubits corresponding to the root node qubit until the child node qubit becomes a leaf node qubit, and to return to the step of obtaining a target phase-shift gate sub-circuit; a target leaf node action module used for operating a target two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and operating the target one-qubit phase-shift gate on the leaf node qubit to obtain a target one-qubit phase-shift sub-circuit; a target combination module used to combine the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; A preparation module used to input a predetermined initial quantum state into the target quantum state preparation circuit to perform quantum state preparation and obtain a unary-coded quantum state corresponding to the target data vector.

11. 1. A method for generating a quantum state preparation circuit performed by an electronic device, the method comprising: Obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path constraints; determining a target qubit set under a binary tree constraint, and applying the one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit; applying the two-qubit phase shift gate between child node qubits corresponding to the root node qubit to obtain a phase shift gate subcircuit; operating the two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate sub-circuit, the second target child node qubit being a child node qubit of the first target child node qubit; performing the two-qubit phase-shift gate between child node qubits corresponding to the root node qubit, with the child node qubit being a root node qubit, until the child node qubit becomes a leaf node qubit, returning to the step of obtaining a phase-shift gate subcircuit; applying the two-qubit phase-shift gate under the path constraint between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a leaf phase-shift gate sub-circuit, and applying the one-qubit phase-shift gate to the leaf node qubit to obtain a one-qubit phase-shift sub-circuit; and combining the inverting gate subcircuit, the phase shift gate subcircuit, the swap gate subcircuit, the leaf phase shift gate subcircuit, and the one qubit phase shift subcircuit to form a quantum state preparation circuit.

12. The steps of obtaining a one-qubit flip gate, a one-qubit phase shift gate, a two-qubit swap gate, and a two-qubit phase shift gate under path constraints include: Obtaining a one-qubit gate and a controlled-NOT gate under path constraints; and combining the one-qubit gate and the controlled-NOT gate under the path restriction to form the two-qubit swap gate and the two-qubit phase-shift gate under the path restriction.

13. 12. The method of claim 11, wherein the number of qubits in the target qubit set is 2n+1-1, where n is a positive integer greater than or equal to 1.

14. The method comprises: determining three quantum bits under a binary tree constraint when n is 1; applying the one-qubit inverting gate to a first target leaf node qubit corresponding to a root node qubit of the three qubits to obtain an inverting gate subcircuit; applying the two-qubit phase-shift gate between leaf-node qubits corresponding to the root-node qubit to obtain a phase-shift gate subcircuit; applying the one-qubit phase-shift gate to the leaf-node qubit to obtain a one-qubit phase-shift subcircuit; 14. The method of claim 13, further comprising combining the inverting gate sub-circuit, the phase shift gate sub-circuit, and the one qubit phase shift sub-circuit to form a quantum state preparation circuit corresponding to the three qubits.

15. the inverting gate subcircuit has a circuit depth of 1, the phase shifting gate subcircuit has a circuit depth of 0(1), the swap gate subcircuit has a circuit depth of 3, the leaf phase shifting gate subcircuit has a circuit depth of 0(1), and the one qubit phase shifting subcircuit has a circuit depth of 1, and the method comprises:

14. The method of claim 13, further comprising: determining a circuit depth of the quantum state preparation circuit based on circuit depths corresponding to the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit, respectively, where the circuit depth is 0(n).

16. the first target child node qubit comprises a first left child node qubit, and the second target child node qubit comprises a second left child node qubit; The step of determining a target qubit set under a binary tree constraint and applying the one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit comprises: applying the one-qubit inverting gate to a first left child qubit corresponding to a root qubit in the target qubit set to obtain the inverting gate subcircuit; said step of operating the two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit comprises:

12. The method of claim 11, comprising operating the two-qubit swap gate between the first left child node qubit and a second left child node qubit to obtain the swap gate subcircuit.

17. the first target child node qubit includes a first right child node qubit, and the second target child node qubit includes a second right child node qubit; The step of determining a target qubit set under a binary tree constraint and applying the one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain an inverting gate subcircuit comprises: applying the one-qubit inverting gate to a first right child qubit corresponding to a root qubit in the target qubit set to obtain the inverting gate subcircuit; said step of operating the two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a swap gate subcircuit comprises:

12. The method of claim 11, comprising operating the two-qubit swap gate between the first right child node qubit and a second right child node qubit to obtain the swap gate subcircuit.

18. after the step of combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit; obtaining a target data vector; determining a qubit operator based on the target data vector, and updating a qubit quantum gate in the quantum state preparation circuit based on the qubit operator to obtain a target quantum state preparation circuit corresponding to the target data vector; 12. The method of claim 11, further comprising: inputting a preset initial quantum state into the target quantum state preparation circuit to perform quantum state preparation to obtain a quantum state corresponding to the target data vector.

19. after the step of combining the inverting gate sub-circuit, the phase shifting gate sub-circuit, the swap gate sub-circuit, the leaf phase shifting gate sub-circuit, and the one qubit phase shifting sub-circuit to form a quantum state preparation circuit; obtaining a recommended preference data vector; determining a qubit operator based on the recommended preference data vector, and updating a qubit quantum gate in the quantum state preparation circuit based on the qubit operator to obtain a recommended quantum state preparation circuit corresponding to the recommended preference data vector; A step of inputting a preset initial quantum state into the recommended quantum state preparation circuit to perform quantum state preparation, and obtaining a quantum state corresponding to the recommended preference data vector; 12. The method of claim 11, further comprising: performing a quantum operation based on the quantum state corresponding to the recommended preference data vector and a quantum singular value estimation algorithm circuit to obtain a target quantum state; and performing a quantum measurement based on the target quantum state to obtain a recommended result corresponding to the recommended preference data vector.

20. 1. A quantum state preparation method, the method comprising: obtaining a target data vector; and obtaining a target one qubit flip gate, a target one qubit phase shift gate, a target two qubit swap gate, and a target two qubit phase shift gate under path restriction based on the target data vector; determining a target qubit set under the binary tree constraint, and applying the target one-qubit inverting gate to a first target child node qubit corresponding to a root node qubit in the target qubit set to obtain a target inverting gate subcircuit; applying the target two-qubit phase-shift gate between a child node qubit corresponding to the root node qubit to obtain a target phase-shift gate sub-circuit; operating the target two-qubit swap gate between the first target child node qubit and a second target child node qubit to obtain a target swap gate sub-circuit, the second target child node qubit being a child node qubit of the first target child node qubit; performing a target two-qubit phase-shift gate between child node qubits corresponding to the root node qubit, with the child node qubit being a root node qubit, until the child node qubit is a leaf node qubit, and returning to the step of obtaining a target phase-shift gate sub-circuit; applying a target two-qubit phase-shift gate under the path restriction between leaf node qubits corresponding to parent node qubits in the target qubit set to obtain a target leaf phase-shift gate sub-circuit, and applying the target one-qubit phase-shift gate to the leaf node qubit to obtain a target one-qubit phase-shift sub-circuit; combining the target invert gate sub-circuit, the target phase shift gate sub-circuit, the target swap gate sub-circuit, the target leaf phase shift gate sub-circuit, and the target one qubit phase shift sub-circuit to form a target quantum state preparation circuit corresponding to the target data vector; A quantum state preparation method comprising the steps of: inputting a predetermined initial quantum state into the target quantum state preparation circuit to perform quantum state preparation, and obtaining a quantum state corresponding to the target data vector.

21. A quantum chip including a quantum state preparation circuit, the quantum state preparation circuit being realized by the method for generating a quantum state preparation circuit according to any one of claims 11 to 20.

22. An electronic device comprising a memory and a processor, the memory storing computer readable instructions, the processor implementing a method according to any one of claims 11 to 20 when executing the computer readable instructions.

23. A computer program, characterized in that when it is executed by a processor, it implements the method according to any one of claims 11 to 20.

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